1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 34 #ifndef _DRAGONFLY_OS_H_ 35 #define _DRAGONFLY_OS_H_ 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 42 #include <bus/pci/pcivar.h> 43 #include <bus/pci/pcireg.h> 44 45 #define usec_delay(x) DELAY(x) 46 #define usec_delay_irq usec_delay 47 #define msec_delay(x) DELAY(1000*(x)) 48 /* TODO: Should we be paranoid about delaying in interrupt context? */ 49 #define msec_delay_irq(x) DELAY(1000*(x)) 50 51 extern int e1000_debug; 52 53 #define DEBUGPRINT(S, args...) \ 54 do { \ 55 if (e1000_debug) \ 56 kprintf(S, ##args); \ 57 } while (0) 58 #define DEBUGFUNC(F) DEBUGOUT(F) 59 #define DEBUGOUT(S) DEBUGPRINT(S) 60 #define DEBUGOUT1(S,A) DEBUGPRINT(S, A) 61 #define DEBUGOUT2(S,A,B) DEBUGPRINT(S, A, B) 62 #define DEBUGOUT3(S,A,B,C) DEBUGPRINT(S, A, B, C) 63 #define DEBUGOUT7(S,A,B,C,D,E,F,G) DEBUGPRINT(S, A, B, C, D, E, F, G) 64 65 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 66 #define PCI_COMMAND_REGISTER PCIR_COMMAND 67 68 /* 69 * These typedefs are necessary due to the new 70 * shared code, they are native to Linux. 71 */ 72 typedef uint64_t u64; 73 typedef uint32_t u32; 74 typedef uint16_t u16; 75 typedef uint8_t u8; 76 typedef int64_t s64; 77 typedef int32_t s32; 78 typedef int16_t s16; 79 typedef int8_t s8; 80 81 #define __le16 u16 82 #define __le32 u32 83 #define __le64 u64 84 85 struct e1000_osdep { 86 bus_space_tag_t mem_bus_space_tag; 87 bus_space_handle_t mem_bus_space_handle; 88 bus_space_tag_t io_bus_space_tag; 89 bus_space_handle_t io_bus_space_handle; 90 bus_space_tag_t flash_bus_space_tag; 91 bus_space_handle_t flash_bus_space_handle; 92 device_t dev; 93 }; 94 95 #define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \ 96 ? reg : e1000_translate_register_82542(reg)) 97 98 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) 99 100 /* Read from an absolute offset in the adapter's memory space */ 101 #define E1000_READ_OFFSET(hw, offset) \ 102 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 103 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset) 104 105 /* Write to an absolute offset in the adapter's memory space */ 106 #define E1000_WRITE_OFFSET(hw, offset, value) \ 107 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 108 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset, value) 109 110 /* Register READ/WRITE macros */ 111 112 #define E1000_READ_REG(hw, reg) \ 113 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 114 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 115 E1000_REGISTER(hw, reg)) 116 117 #define E1000_READ_REG16(hw, reg) \ 118 bus_space_read_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 119 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 120 E1000_REGISTER(hw, reg)) 121 122 #define E1000_WRITE_REG(hw, reg, value) \ 123 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 124 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 125 E1000_REGISTER(hw, reg), value) 126 127 #define E1000_WRITE_REG16(hw, reg, value) \ 128 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 129 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 130 E1000_REGISTER(hw, reg), value) 131 132 #define E1000_READ_REG_ARRAY(hw, reg, index) \ 133 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 134 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 135 E1000_REGISTER(hw, reg) + ((index)<< 2)) 136 137 #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \ 138 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 139 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 140 E1000_REGISTER(hw, reg) + ((index)<< 2), value) 141 142 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY 143 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY 144 145 #define E1000_READ_REG_ARRAY_BYTE(hw, reg, index) \ 146 bus_space_read_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 147 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 148 E1000_REGISTER(hw, reg) + index) 149 150 #define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \ 151 bus_space_write_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 152 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 153 E1000_REGISTER(hw, reg) + index, value) 154 155 #define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \ 156 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \ 157 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \ 158 E1000_REGISTER(hw, reg) + (index << 1), value) 159 160 #define E1000_WRITE_REG_IO(hw, reg, value) do {\ 161 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \ 162 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \ 163 (hw)->io_base, reg); \ 164 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \ 165 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \ 166 (hw)->io_base + 4, value); } while (0) 167 168 #define E1000_READ_FLASH_REG(hw, reg) \ 169 (((hw)->mac.type == e1000_pch_spt) ? E1000_READ_REG(hw, (reg) + 0xE000): \ 170 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 171 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)) 172 173 #define E1000_READ_FLASH_REG16(hw, reg) \ 174 (((hw)->mac.type == e1000_pch_spt) ? E1000_READ_REG16(hw, (reg) + 0xE000): \ 175 bus_space_read_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 176 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)) 177 178 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ 179 (((hw)->mac.type == e1000_pch_spt) ? E1000_WRITE_REG(hw, (reg) + 0xE000, value): \ 180 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 181 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)) 182 183 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ 184 (((hw)->mac.type == e1000_pch_spt) ? E1000_WRITE_REG16(hw, (reg) + 0xE000, value): \ 185 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \ 186 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)) 187 188 #endif /* _DRAGONFLY_OS_H_ */ 189