1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read, bool page_set); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51 static const u16 e1000_igp_2_cable_length_table[] = { 52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 59 124}; 60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64 /** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.set_page = e1000_null_set_page; 86 phy->ops.read_reg = e1000_null_read_reg; 87 phy->ops.read_reg_locked = e1000_null_read_reg; 88 phy->ops.read_reg_page = e1000_null_read_reg; 89 phy->ops.release = e1000_null_phy_generic; 90 phy->ops.reset = e1000_null_ops_generic; 91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 93 phy->ops.write_reg = e1000_null_write_reg; 94 phy->ops.write_reg_locked = e1000_null_write_reg; 95 phy->ops.write_reg_page = e1000_null_write_reg; 96 phy->ops.power_up = e1000_null_phy_generic; 97 phy->ops.power_down = e1000_null_phy_generic; 98 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 99 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null; 100 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null; 101 } 102 103 /** 104 * e1000_null_set_page - No-op function, return 0 105 * @hw: pointer to the HW structure 106 **/ 107 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw, 108 u16 E1000_UNUSEDARG data) 109 { 110 DEBUGFUNC("e1000_null_set_page"); 111 return E1000_SUCCESS; 112 } 113 114 /** 115 * e1000_null_read_reg - No-op function, return 0 116 * @hw: pointer to the HW structure 117 **/ 118 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw, 119 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data) 120 { 121 DEBUGFUNC("e1000_null_read_reg"); 122 return E1000_SUCCESS; 123 } 124 125 /** 126 * e1000_null_phy_generic - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw) 130 { 131 DEBUGFUNC("e1000_null_phy_generic"); 132 return; 133 } 134 135 /** 136 * e1000_null_lplu_state - No-op function, return 0 137 * @hw: pointer to the HW structure 138 **/ 139 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw, 140 bool E1000_UNUSEDARG active) 141 { 142 DEBUGFUNC("e1000_null_lplu_state"); 143 return E1000_SUCCESS; 144 } 145 146 /** 147 * e1000_null_write_reg - No-op function, return 0 148 * @hw: pointer to the HW structure 149 **/ 150 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw, 151 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data) 152 { 153 DEBUGFUNC("e1000_null_write_reg"); 154 return E1000_SUCCESS; 155 } 156 157 /** 158 * e1000_read_i2c_byte_null - No-op function, return 0 159 * @hw: pointer to hardware structure 160 * @byte_offset: byte offset to write 161 * @dev_addr: device address 162 * @data: data value read 163 * 164 **/ 165 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 166 u8 E1000_UNUSEDARG byte_offset, 167 u8 E1000_UNUSEDARG dev_addr, 168 u8 E1000_UNUSEDARG *data) 169 { 170 DEBUGFUNC("e1000_read_i2c_byte_null"); 171 return E1000_SUCCESS; 172 } 173 174 /** 175 * e1000_write_i2c_byte_null - No-op function, return 0 176 * @hw: pointer to hardware structure 177 * @byte_offset: byte offset to write 178 * @dev_addr: device address 179 * @data: data value to write 180 * 181 **/ 182 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 183 u8 E1000_UNUSEDARG byte_offset, 184 u8 E1000_UNUSEDARG dev_addr, 185 u8 E1000_UNUSEDARG data) 186 { 187 DEBUGFUNC("e1000_write_i2c_byte_null"); 188 return E1000_SUCCESS; 189 } 190 191 /** 192 * e1000_check_reset_block_generic - Check if PHY reset is blocked 193 * @hw: pointer to the HW structure 194 * 195 * Read the PHY management control register and check whether a PHY reset 196 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 197 * return E1000_BLK_PHY_RESET (12). 198 **/ 199 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 200 { 201 u32 manc; 202 203 DEBUGFUNC("e1000_check_reset_block"); 204 205 manc = E1000_READ_REG(hw, E1000_MANC); 206 207 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 208 E1000_BLK_PHY_RESET : E1000_SUCCESS; 209 } 210 211 /** 212 * e1000_get_phy_id - Retrieve the PHY ID and revision 213 * @hw: pointer to the HW structure 214 * 215 * Reads the PHY registers and stores the PHY ID and possibly the PHY 216 * revision in the hardware structure. 217 **/ 218 s32 e1000_get_phy_id(struct e1000_hw *hw) 219 { 220 struct e1000_phy_info *phy = &hw->phy; 221 s32 ret_val = E1000_SUCCESS; 222 u16 phy_id; 223 u16 retry_count = 0; 224 225 DEBUGFUNC("e1000_get_phy_id"); 226 227 if (!phy->ops.read_reg) 228 return E1000_SUCCESS; 229 230 while (retry_count < 2) { 231 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 232 if (ret_val) 233 return ret_val; 234 235 phy->id = (u32)(phy_id << 16); 236 usec_delay(20); 237 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 238 if (ret_val) 239 return ret_val; 240 241 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 242 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 243 244 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 245 return E1000_SUCCESS; 246 247 retry_count++; 248 } 249 250 return E1000_SUCCESS; 251 } 252 253 /** 254 * e1000_phy_reset_dsp_generic - Reset PHY DSP 255 * @hw: pointer to the HW structure 256 * 257 * Reset the digital signal processor. 258 **/ 259 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 260 { 261 s32 ret_val; 262 263 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 264 265 if (!hw->phy.ops.write_reg) 266 return E1000_SUCCESS; 267 268 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 269 if (ret_val) 270 return ret_val; 271 272 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 273 } 274 275 /** 276 * e1000_read_phy_reg_mdic - Read MDI control register 277 * @hw: pointer to the HW structure 278 * @offset: register offset to be read 279 * @data: pointer to the read data 280 * 281 * Reads the MDI control register in the PHY at offset and stores the 282 * information read to data. 283 **/ 284 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 285 { 286 struct e1000_phy_info *phy = &hw->phy; 287 u32 i, mdic = 0; 288 289 DEBUGFUNC("e1000_read_phy_reg_mdic"); 290 291 if (offset > MAX_PHY_REG_ADDRESS) { 292 DEBUGOUT1("PHY Address %d is out of range\n", offset); 293 return -E1000_ERR_PARAM; 294 } 295 296 /* Set up Op-code, Phy Address, and register offset in the MDI 297 * Control register. The MAC will take care of interfacing with the 298 * PHY to retrieve the desired data. 299 */ 300 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 301 (phy->addr << E1000_MDIC_PHY_SHIFT) | 302 (E1000_MDIC_OP_READ)); 303 304 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 305 306 /* Poll the ready bit to see if the MDI read completed 307 * Increasing the time out as testing showed failures with 308 * the lower time out 309 */ 310 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 311 usec_delay(50); 312 mdic = E1000_READ_REG(hw, E1000_MDIC); 313 if (mdic & E1000_MDIC_READY) 314 break; 315 } 316 if (!(mdic & E1000_MDIC_READY)) { 317 DEBUGOUT("MDI Read did not complete\n"); 318 return -E1000_ERR_PHY; 319 } 320 if (mdic & E1000_MDIC_ERROR) { 321 DEBUGOUT("MDI Error\n"); 322 return -E1000_ERR_PHY; 323 } 324 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 325 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 326 offset, 327 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 328 return -E1000_ERR_PHY; 329 } 330 *data = (u16) mdic; 331 332 /* Allow some time after each MDIC transaction to avoid 333 * reading duplicate data in the next MDIC transaction. 334 */ 335 if (hw->mac.type == e1000_pch2lan) 336 usec_delay(100); 337 338 return E1000_SUCCESS; 339 } 340 341 /** 342 * e1000_write_phy_reg_mdic - Write MDI control register 343 * @hw: pointer to the HW structure 344 * @offset: register offset to write to 345 * @data: data to write to register at offset 346 * 347 * Writes data to MDI control register in the PHY at offset. 348 **/ 349 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 350 { 351 struct e1000_phy_info *phy = &hw->phy; 352 u32 i, mdic = 0; 353 354 DEBUGFUNC("e1000_write_phy_reg_mdic"); 355 356 if (offset > MAX_PHY_REG_ADDRESS) { 357 DEBUGOUT1("PHY Address %d is out of range\n", offset); 358 return -E1000_ERR_PARAM; 359 } 360 361 /* Set up Op-code, Phy Address, and register offset in the MDI 362 * Control register. The MAC will take care of interfacing with the 363 * PHY to retrieve the desired data. 364 */ 365 mdic = (((u32)data) | 366 (offset << E1000_MDIC_REG_SHIFT) | 367 (phy->addr << E1000_MDIC_PHY_SHIFT) | 368 (E1000_MDIC_OP_WRITE)); 369 370 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 371 372 /* Poll the ready bit to see if the MDI read completed 373 * Increasing the time out as testing showed failures with 374 * the lower time out 375 */ 376 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 377 usec_delay(50); 378 mdic = E1000_READ_REG(hw, E1000_MDIC); 379 if (mdic & E1000_MDIC_READY) 380 break; 381 } 382 if (!(mdic & E1000_MDIC_READY)) { 383 DEBUGOUT("MDI Write did not complete\n"); 384 return -E1000_ERR_PHY; 385 } 386 if (mdic & E1000_MDIC_ERROR) { 387 DEBUGOUT("MDI Error\n"); 388 return -E1000_ERR_PHY; 389 } 390 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 391 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", 392 offset, 393 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 394 return -E1000_ERR_PHY; 395 } 396 397 /* Allow some time after each MDIC transaction to avoid 398 * reading duplicate data in the next MDIC transaction. 399 */ 400 if (hw->mac.type == e1000_pch2lan) 401 usec_delay(100); 402 403 return E1000_SUCCESS; 404 } 405 406 /** 407 * e1000_read_phy_reg_i2c - Read PHY register using i2c 408 * @hw: pointer to the HW structure 409 * @offset: register offset to be read 410 * @data: pointer to the read data 411 * 412 * Reads the PHY register at offset using the i2c interface and stores the 413 * retrieved information in data. 414 **/ 415 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 416 { 417 struct e1000_phy_info *phy = &hw->phy; 418 u32 i, i2ccmd = 0; 419 420 DEBUGFUNC("e1000_read_phy_reg_i2c"); 421 422 /* Set up Op-code, Phy Address, and register address in the I2CCMD 423 * register. The MAC will take care of interfacing with the 424 * PHY to retrieve the desired data. 425 */ 426 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 427 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 428 (E1000_I2CCMD_OPCODE_READ)); 429 430 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 431 432 /* Poll the ready bit to see if the I2C read completed */ 433 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 434 usec_delay(50); 435 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 436 if (i2ccmd & E1000_I2CCMD_READY) 437 break; 438 } 439 if (!(i2ccmd & E1000_I2CCMD_READY)) { 440 DEBUGOUT("I2CCMD Read did not complete\n"); 441 return -E1000_ERR_PHY; 442 } 443 if (i2ccmd & E1000_I2CCMD_ERROR) { 444 DEBUGOUT("I2CCMD Error bit set\n"); 445 return -E1000_ERR_PHY; 446 } 447 448 /* Need to byte-swap the 16-bit value. */ 449 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 450 451 return E1000_SUCCESS; 452 } 453 454 /** 455 * e1000_write_phy_reg_i2c - Write PHY register using i2c 456 * @hw: pointer to the HW structure 457 * @offset: register offset to write to 458 * @data: data to write at register offset 459 * 460 * Writes the data to PHY register at the offset using the i2c interface. 461 **/ 462 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 463 { 464 struct e1000_phy_info *phy = &hw->phy; 465 u32 i, i2ccmd = 0; 466 u16 phy_data_swapped; 467 468 DEBUGFUNC("e1000_write_phy_reg_i2c"); 469 470 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 471 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 472 DEBUGOUT1("PHY I2C Address %d is out of range.\n", 473 hw->phy.addr); 474 return -E1000_ERR_CONFIG; 475 } 476 477 /* Swap the data bytes for the I2C interface */ 478 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 479 480 /* Set up Op-code, Phy Address, and register address in the I2CCMD 481 * register. The MAC will take care of interfacing with the 482 * PHY to retrieve the desired data. 483 */ 484 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 485 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 486 E1000_I2CCMD_OPCODE_WRITE | 487 phy_data_swapped); 488 489 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 490 491 /* Poll the ready bit to see if the I2C read completed */ 492 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 493 usec_delay(50); 494 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 495 if (i2ccmd & E1000_I2CCMD_READY) 496 break; 497 } 498 if (!(i2ccmd & E1000_I2CCMD_READY)) { 499 DEBUGOUT("I2CCMD Write did not complete\n"); 500 return -E1000_ERR_PHY; 501 } 502 if (i2ccmd & E1000_I2CCMD_ERROR) { 503 DEBUGOUT("I2CCMD Error bit set\n"); 504 return -E1000_ERR_PHY; 505 } 506 507 return E1000_SUCCESS; 508 } 509 510 /** 511 * e1000_read_sfp_data_byte - Reads SFP module data. 512 * @hw: pointer to the HW structure 513 * @offset: byte location offset to be read 514 * @data: read data buffer pointer 515 * 516 * Reads one byte from SFP module data stored 517 * in SFP resided EEPROM memory or SFP diagnostic area. 518 * Function should be called with 519 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 520 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 521 * access 522 **/ 523 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 524 { 525 u32 i = 0; 526 u32 i2ccmd = 0; 527 u32 data_local = 0; 528 529 DEBUGFUNC("e1000_read_sfp_data_byte"); 530 531 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 532 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 533 return -E1000_ERR_PHY; 534 } 535 536 /* Set up Op-code, EEPROM Address,in the I2CCMD 537 * register. The MAC will take care of interfacing with the 538 * EEPROM to retrieve the desired data. 539 */ 540 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 541 E1000_I2CCMD_OPCODE_READ); 542 543 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 544 545 /* Poll the ready bit to see if the I2C read completed */ 546 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 547 usec_delay(50); 548 data_local = E1000_READ_REG(hw, E1000_I2CCMD); 549 if (data_local & E1000_I2CCMD_READY) 550 break; 551 } 552 if (!(data_local & E1000_I2CCMD_READY)) { 553 DEBUGOUT("I2CCMD Read did not complete\n"); 554 return -E1000_ERR_PHY; 555 } 556 if (data_local & E1000_I2CCMD_ERROR) { 557 DEBUGOUT("I2CCMD Error bit set\n"); 558 return -E1000_ERR_PHY; 559 } 560 *data = (u8) data_local & 0xFF; 561 562 return E1000_SUCCESS; 563 } 564 565 /** 566 * e1000_write_sfp_data_byte - Writes SFP module data. 567 * @hw: pointer to the HW structure 568 * @offset: byte location offset to write to 569 * @data: data to write 570 * 571 * Writes one byte to SFP module data stored 572 * in SFP resided EEPROM memory or SFP diagnostic area. 573 * Function should be called with 574 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 575 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 576 * access 577 **/ 578 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 579 { 580 u32 i = 0; 581 u32 i2ccmd = 0; 582 u32 data_local = 0; 583 584 DEBUGFUNC("e1000_write_sfp_data_byte"); 585 586 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 587 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 588 return -E1000_ERR_PHY; 589 } 590 /* The programming interface is 16 bits wide 591 * so we need to read the whole word first 592 * then update appropriate byte lane and write 593 * the updated word back. 594 */ 595 /* Set up Op-code, EEPROM Address,in the I2CCMD 596 * register. The MAC will take care of interfacing 597 * with an EEPROM to write the data given. 598 */ 599 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 600 E1000_I2CCMD_OPCODE_READ); 601 /* Set a command to read single word */ 602 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 603 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 604 usec_delay(50); 605 /* Poll the ready bit to see if lastly 606 * launched I2C operation completed 607 */ 608 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 609 if (i2ccmd & E1000_I2CCMD_READY) { 610 /* Check if this is READ or WRITE phase */ 611 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 612 E1000_I2CCMD_OPCODE_READ) { 613 /* Write the selected byte 614 * lane and update whole word 615 */ 616 data_local = i2ccmd & 0xFF00; 617 data_local |= data; 618 i2ccmd = ((offset << 619 E1000_I2CCMD_REG_ADDR_SHIFT) | 620 E1000_I2CCMD_OPCODE_WRITE | data_local); 621 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 622 } else { 623 break; 624 } 625 } 626 } 627 if (!(i2ccmd & E1000_I2CCMD_READY)) { 628 DEBUGOUT("I2CCMD Write did not complete\n"); 629 return -E1000_ERR_PHY; 630 } 631 if (i2ccmd & E1000_I2CCMD_ERROR) { 632 DEBUGOUT("I2CCMD Error bit set\n"); 633 return -E1000_ERR_PHY; 634 } 635 return E1000_SUCCESS; 636 } 637 638 /** 639 * e1000_read_phy_reg_m88 - Read m88 PHY register 640 * @hw: pointer to the HW structure 641 * @offset: register offset to be read 642 * @data: pointer to the read data 643 * 644 * Acquires semaphore, if necessary, then reads the PHY register at offset 645 * and storing the retrieved information in data. Release any acquired 646 * semaphores before exiting. 647 **/ 648 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 649 { 650 s32 ret_val; 651 652 DEBUGFUNC("e1000_read_phy_reg_m88"); 653 654 if (!hw->phy.ops.acquire) 655 return E1000_SUCCESS; 656 657 ret_val = hw->phy.ops.acquire(hw); 658 if (ret_val) 659 return ret_val; 660 661 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 662 data); 663 664 hw->phy.ops.release(hw); 665 666 return ret_val; 667 } 668 669 /** 670 * e1000_write_phy_reg_m88 - Write m88 PHY register 671 * @hw: pointer to the HW structure 672 * @offset: register offset to write to 673 * @data: data to write at register offset 674 * 675 * Acquires semaphore, if necessary, then writes the data to PHY register 676 * at the offset. Release any acquired semaphores before exiting. 677 **/ 678 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 679 { 680 s32 ret_val; 681 682 DEBUGFUNC("e1000_write_phy_reg_m88"); 683 684 if (!hw->phy.ops.acquire) 685 return E1000_SUCCESS; 686 687 ret_val = hw->phy.ops.acquire(hw); 688 if (ret_val) 689 return ret_val; 690 691 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 692 data); 693 694 hw->phy.ops.release(hw); 695 696 return ret_val; 697 } 698 699 /** 700 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 701 * @hw: pointer to the HW structure 702 * @page: page to set (shifted left when necessary) 703 * 704 * Sets PHY page required for PHY register access. Assumes semaphore is 705 * already acquired. Note, this function sets phy.addr to 1 so the caller 706 * must set it appropriately (if necessary) after this function returns. 707 **/ 708 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 709 { 710 DEBUGFUNC("e1000_set_page_igp"); 711 712 DEBUGOUT1("Setting page 0x%x\n", page); 713 714 hw->phy.addr = 1; 715 716 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 717 } 718 719 /** 720 * __e1000_read_phy_reg_igp - Read igp PHY register 721 * @hw: pointer to the HW structure 722 * @offset: register offset to be read 723 * @data: pointer to the read data 724 * @locked: semaphore has already been acquired or not 725 * 726 * Acquires semaphore, if necessary, then reads the PHY register at offset 727 * and stores the retrieved information in data. Release any acquired 728 * semaphores before exiting. 729 **/ 730 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 731 bool locked) 732 { 733 s32 ret_val = E1000_SUCCESS; 734 735 DEBUGFUNC("__e1000_read_phy_reg_igp"); 736 737 if (!locked) { 738 if (!hw->phy.ops.acquire) 739 return E1000_SUCCESS; 740 741 ret_val = hw->phy.ops.acquire(hw); 742 if (ret_val) 743 return ret_val; 744 } 745 746 if (offset > MAX_PHY_MULTI_PAGE_REG) 747 ret_val = e1000_write_phy_reg_mdic(hw, 748 IGP01E1000_PHY_PAGE_SELECT, 749 (u16)offset); 750 if (!ret_val) 751 ret_val = e1000_read_phy_reg_mdic(hw, 752 MAX_PHY_REG_ADDRESS & offset, 753 data); 754 if (!locked) 755 hw->phy.ops.release(hw); 756 757 return ret_val; 758 } 759 760 /** 761 * e1000_read_phy_reg_igp - Read igp PHY register 762 * @hw: pointer to the HW structure 763 * @offset: register offset to be read 764 * @data: pointer to the read data 765 * 766 * Acquires semaphore then reads the PHY register at offset and stores the 767 * retrieved information in data. 768 * Release the acquired semaphore before exiting. 769 **/ 770 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 771 { 772 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 773 } 774 775 /** 776 * e1000_read_phy_reg_igp_locked - Read igp PHY register 777 * @hw: pointer to the HW structure 778 * @offset: register offset to be read 779 * @data: pointer to the read data 780 * 781 * Reads the PHY register at offset and stores the retrieved information 782 * in data. Assumes semaphore already acquired. 783 **/ 784 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 785 { 786 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 787 } 788 789 /** 790 * e1000_write_phy_reg_igp - Write igp PHY register 791 * @hw: pointer to the HW structure 792 * @offset: register offset to write to 793 * @data: data to write at register offset 794 * @locked: semaphore has already been acquired or not 795 * 796 * Acquires semaphore, if necessary, then writes the data to PHY register 797 * at the offset. Release any acquired semaphores before exiting. 798 **/ 799 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 800 bool locked) 801 { 802 s32 ret_val = E1000_SUCCESS; 803 804 DEBUGFUNC("e1000_write_phy_reg_igp"); 805 806 if (!locked) { 807 if (!hw->phy.ops.acquire) 808 return E1000_SUCCESS; 809 810 ret_val = hw->phy.ops.acquire(hw); 811 if (ret_val) 812 return ret_val; 813 } 814 815 if (offset > MAX_PHY_MULTI_PAGE_REG) 816 ret_val = e1000_write_phy_reg_mdic(hw, 817 IGP01E1000_PHY_PAGE_SELECT, 818 (u16)offset); 819 if (!ret_val) 820 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 821 offset, 822 data); 823 if (!locked) 824 hw->phy.ops.release(hw); 825 826 return ret_val; 827 } 828 829 /** 830 * e1000_write_phy_reg_igp - Write igp PHY register 831 * @hw: pointer to the HW structure 832 * @offset: register offset to write to 833 * @data: data to write at register offset 834 * 835 * Acquires semaphore then writes the data to PHY register 836 * at the offset. Release any acquired semaphores before exiting. 837 **/ 838 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 839 { 840 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 841 } 842 843 /** 844 * e1000_write_phy_reg_igp_locked - Write igp PHY register 845 * @hw: pointer to the HW structure 846 * @offset: register offset to write to 847 * @data: data to write at register offset 848 * 849 * Writes the data to PHY register at the offset. 850 * Assumes semaphore already acquired. 851 **/ 852 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 853 { 854 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 855 } 856 857 /** 858 * __e1000_read_kmrn_reg - Read kumeran register 859 * @hw: pointer to the HW structure 860 * @offset: register offset to be read 861 * @data: pointer to the read data 862 * @locked: semaphore has already been acquired or not 863 * 864 * Acquires semaphore, if necessary. Then reads the PHY register at offset 865 * using the kumeran interface. The information retrieved is stored in data. 866 * Release any acquired semaphores before exiting. 867 **/ 868 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 869 bool locked) 870 { 871 u32 kmrnctrlsta; 872 873 DEBUGFUNC("__e1000_read_kmrn_reg"); 874 875 if (!locked) { 876 s32 ret_val = E1000_SUCCESS; 877 878 if (!hw->phy.ops.acquire) 879 return E1000_SUCCESS; 880 881 ret_val = hw->phy.ops.acquire(hw); 882 if (ret_val) 883 return ret_val; 884 } 885 886 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 887 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 888 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 889 E1000_WRITE_FLUSH(hw); 890 891 usec_delay(2); 892 893 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 894 *data = (u16)kmrnctrlsta; 895 896 if (!locked) 897 hw->phy.ops.release(hw); 898 899 return E1000_SUCCESS; 900 } 901 902 /** 903 * e1000_read_kmrn_reg_generic - Read kumeran register 904 * @hw: pointer to the HW structure 905 * @offset: register offset to be read 906 * @data: pointer to the read data 907 * 908 * Acquires semaphore then reads the PHY register at offset using the 909 * kumeran interface. The information retrieved is stored in data. 910 * Release the acquired semaphore before exiting. 911 **/ 912 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 913 { 914 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 915 } 916 917 /** 918 * e1000_read_kmrn_reg_locked - Read kumeran register 919 * @hw: pointer to the HW structure 920 * @offset: register offset to be read 921 * @data: pointer to the read data 922 * 923 * Reads the PHY register at offset using the kumeran interface. The 924 * information retrieved is stored in data. 925 * Assumes semaphore already acquired. 926 **/ 927 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 928 { 929 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 930 } 931 932 /** 933 * __e1000_write_kmrn_reg - Write kumeran register 934 * @hw: pointer to the HW structure 935 * @offset: register offset to write to 936 * @data: data to write at register offset 937 * @locked: semaphore has already been acquired or not 938 * 939 * Acquires semaphore, if necessary. Then write the data to PHY register 940 * at the offset using the kumeran interface. Release any acquired semaphores 941 * before exiting. 942 **/ 943 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 944 bool locked) 945 { 946 u32 kmrnctrlsta; 947 948 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 949 950 if (!locked) { 951 s32 ret_val = E1000_SUCCESS; 952 953 if (!hw->phy.ops.acquire) 954 return E1000_SUCCESS; 955 956 ret_val = hw->phy.ops.acquire(hw); 957 if (ret_val) 958 return ret_val; 959 } 960 961 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 962 E1000_KMRNCTRLSTA_OFFSET) | data; 963 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 964 E1000_WRITE_FLUSH(hw); 965 966 usec_delay(2); 967 968 if (!locked) 969 hw->phy.ops.release(hw); 970 971 return E1000_SUCCESS; 972 } 973 974 /** 975 * e1000_write_kmrn_reg_generic - Write kumeran register 976 * @hw: pointer to the HW structure 977 * @offset: register offset to write to 978 * @data: data to write at register offset 979 * 980 * Acquires semaphore then writes the data to the PHY register at the offset 981 * using the kumeran interface. Release the acquired semaphore before exiting. 982 **/ 983 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 984 { 985 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 986 } 987 988 /** 989 * e1000_write_kmrn_reg_locked - Write kumeran register 990 * @hw: pointer to the HW structure 991 * @offset: register offset to write to 992 * @data: data to write at register offset 993 * 994 * Write the data to PHY register at the offset using the kumeran interface. 995 * Assumes semaphore already acquired. 996 **/ 997 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 998 { 999 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 1000 } 1001 1002 /** 1003 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 1004 * @hw: pointer to the HW structure 1005 * 1006 * Sets up Master/slave mode 1007 **/ 1008 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 1009 { 1010 s32 ret_val; 1011 u16 phy_data; 1012 1013 /* Resolve Master/Slave mode */ 1014 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 1015 if (ret_val) 1016 return ret_val; 1017 1018 /* load defaults for future use */ 1019 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 1020 ((phy_data & CR_1000T_MS_VALUE) ? 1021 e1000_ms_force_master : 1022 e1000_ms_force_slave) : e1000_ms_auto; 1023 1024 switch (hw->phy.ms_type) { 1025 case e1000_ms_force_master: 1026 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1027 break; 1028 case e1000_ms_force_slave: 1029 phy_data |= CR_1000T_MS_ENABLE; 1030 phy_data &= ~(CR_1000T_MS_VALUE); 1031 break; 1032 case e1000_ms_auto: 1033 phy_data &= ~CR_1000T_MS_ENABLE; 1034 /* fall-through */ 1035 default: 1036 break; 1037 } 1038 1039 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 1040 } 1041 1042 /** 1043 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 1044 * @hw: pointer to the HW structure 1045 * 1046 * Sets up Carrier-sense on Transmit and downshift values. 1047 **/ 1048 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 1049 { 1050 s32 ret_val; 1051 u16 phy_data; 1052 1053 DEBUGFUNC("e1000_copper_link_setup_82577"); 1054 1055 if (hw->phy.type == e1000_phy_82580) { 1056 ret_val = hw->phy.ops.reset(hw); 1057 if (ret_val) { 1058 DEBUGOUT("Error resetting the PHY.\n"); 1059 return ret_val; 1060 } 1061 } 1062 1063 /* Enable CRS on Tx. This must be set for half-duplex operation. 1064 * Not required on some PHYs. 1065 */ 1066 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 1067 if (ret_val) 1068 return ret_val; 1069 1070 if ((hw->phy.type != e1000_phy_82579) && 1071 (hw->phy.type != e1000_phy_i217)) 1072 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 1073 1074 /* Enable downshift */ 1075 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 1076 1077 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 1078 if (ret_val) 1079 return ret_val; 1080 1081 /* Set MDI/MDIX mode */ 1082 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 1083 if (ret_val) 1084 return ret_val; 1085 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 1086 /* Options: 1087 * 0 - Auto (default) 1088 * 1 - MDI mode 1089 * 2 - MDI-X mode 1090 */ 1091 switch (hw->phy.mdix) { 1092 case 1: 1093 break; 1094 case 2: 1095 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 1096 break; 1097 case 0: 1098 default: 1099 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 1100 break; 1101 } 1102 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 1103 if (ret_val) 1104 return ret_val; 1105 1106 return e1000_set_master_slave_mode(hw); 1107 } 1108 1109 /** 1110 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 1111 * @hw: pointer to the HW structure 1112 * 1113 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 1114 * and downshift values are set also. 1115 **/ 1116 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 1117 { 1118 struct e1000_phy_info *phy = &hw->phy; 1119 s32 ret_val; 1120 u16 phy_data; 1121 1122 DEBUGFUNC("e1000_copper_link_setup_m88"); 1123 1124 1125 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1126 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1127 if (ret_val) 1128 return ret_val; 1129 1130 /* For BM PHY this bit is downshift enable */ 1131 if (phy->type != e1000_phy_bm) 1132 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1133 1134 /* Options: 1135 * MDI/MDI-X = 0 (default) 1136 * 0 - Auto for all speeds 1137 * 1 - MDI mode 1138 * 2 - MDI-X mode 1139 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1140 */ 1141 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1142 1143 switch (phy->mdix) { 1144 case 1: 1145 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1146 break; 1147 case 2: 1148 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1149 break; 1150 case 3: 1151 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1152 break; 1153 case 0: 1154 default: 1155 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1156 break; 1157 } 1158 1159 /* Options: 1160 * disable_polarity_correction = 0 (default) 1161 * Automatic Correction for Reversed Cable Polarity 1162 * 0 - Disabled 1163 * 1 - Enabled 1164 */ 1165 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1166 if (phy->disable_polarity_correction) 1167 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1168 1169 /* Enable downshift on BM (disabled by default) */ 1170 if (phy->type == e1000_phy_bm) { 1171 /* For 82574/82583, first disable then enable downshift */ 1172 if (phy->id == BME1000_E_PHY_ID_R2) { 1173 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 1174 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1175 phy_data); 1176 if (ret_val) 1177 return ret_val; 1178 /* Commit the changes. */ 1179 ret_val = phy->ops.commit(hw); 1180 if (ret_val) { 1181 DEBUGOUT("Error committing the PHY changes\n"); 1182 return ret_val; 1183 } 1184 } 1185 1186 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 1187 } 1188 1189 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1190 if (ret_val) 1191 return ret_val; 1192 1193 if ((phy->type == e1000_phy_m88) && 1194 (phy->revision < E1000_REVISION_4) && 1195 (phy->id != BME1000_E_PHY_ID_R2)) { 1196 /* Force TX_CLK in the Extended PHY Specific Control Register 1197 * to 25MHz clock. 1198 */ 1199 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1200 &phy_data); 1201 if (ret_val) 1202 return ret_val; 1203 1204 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1205 1206 if ((phy->revision == E1000_REVISION_2) && 1207 (phy->id == M88E1111_I_PHY_ID)) { 1208 /* 82573L PHY - set the downshift counter to 5x. */ 1209 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 1210 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1211 } else { 1212 /* Configure Master and Slave downshift values */ 1213 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1214 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1215 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1216 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1217 } 1218 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1219 phy_data); 1220 if (ret_val) 1221 return ret_val; 1222 } 1223 1224 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 1225 /* Set PHY page 0, register 29 to 0x0003 */ 1226 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 1227 if (ret_val) 1228 return ret_val; 1229 1230 /* Set PHY page 0, register 30 to 0x0000 */ 1231 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 1232 if (ret_val) 1233 return ret_val; 1234 } 1235 1236 /* Commit the changes. */ 1237 ret_val = phy->ops.commit(hw); 1238 if (ret_val) { 1239 DEBUGOUT("Error committing the PHY changes\n"); 1240 return ret_val; 1241 } 1242 1243 if (phy->type == e1000_phy_82578) { 1244 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1245 &phy_data); 1246 if (ret_val) 1247 return ret_val; 1248 1249 /* 82578 PHY - set the downshift count to 1x. */ 1250 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 1251 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 1252 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1253 phy_data); 1254 if (ret_val) 1255 return ret_val; 1256 } 1257 1258 if (phy->type == e1000_phy_i210) { 1259 ret_val = e1000_set_master_slave_mode(hw); 1260 if (ret_val) 1261 return ret_val; 1262 } 1263 1264 return E1000_SUCCESS; 1265 } 1266 1267 /** 1268 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 1269 * @hw: pointer to the HW structure 1270 * 1271 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1272 * Also enables and sets the downshift parameters. 1273 **/ 1274 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1275 { 1276 struct e1000_phy_info *phy = &hw->phy; 1277 s32 ret_val; 1278 u16 phy_data; 1279 1280 DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1281 1282 1283 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1284 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1285 if (ret_val) 1286 return ret_val; 1287 1288 /* Options: 1289 * MDI/MDI-X = 0 (default) 1290 * 0 - Auto for all speeds 1291 * 1 - MDI mode 1292 * 2 - MDI-X mode 1293 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1294 */ 1295 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1296 1297 switch (phy->mdix) { 1298 case 1: 1299 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1300 break; 1301 case 2: 1302 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1303 break; 1304 case 3: 1305 /* M88E1112 does not support this mode) */ 1306 if (phy->id != M88E1112_E_PHY_ID) { 1307 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1308 break; 1309 } 1310 case 0: 1311 default: 1312 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1313 break; 1314 } 1315 1316 /* Options: 1317 * disable_polarity_correction = 0 (default) 1318 * Automatic Correction for Reversed Cable Polarity 1319 * 0 - Disabled 1320 * 1 - Enabled 1321 */ 1322 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1323 if (phy->disable_polarity_correction) 1324 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1325 1326 /* Enable downshift and setting it to X6 */ 1327 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1328 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1329 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1330 1331 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1332 if (ret_val) 1333 return ret_val; 1334 1335 /* Commit the changes. */ 1336 ret_val = phy->ops.commit(hw); 1337 if (ret_val) { 1338 DEBUGOUT("Error committing the PHY changes\n"); 1339 return ret_val; 1340 } 1341 1342 return E1000_SUCCESS; 1343 } 1344 1345 /** 1346 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1347 * @hw: pointer to the HW structure 1348 * 1349 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1350 * igp PHY's. 1351 **/ 1352 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1353 { 1354 struct e1000_phy_info *phy = &hw->phy; 1355 s32 ret_val; 1356 u16 data; 1357 1358 DEBUGFUNC("e1000_copper_link_setup_igp"); 1359 1360 1361 ret_val = hw->phy.ops.reset(hw); 1362 if (ret_val) { 1363 DEBUGOUT("Error resetting the PHY.\n"); 1364 return ret_val; 1365 } 1366 1367 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1368 * timeout issues when LFS is enabled. 1369 */ 1370 msec_delay(100); 1371 1372 /* The NVM settings will configure LPLU in D3 for 1373 * non-IGP1 PHYs. 1374 */ 1375 if (phy->type == e1000_phy_igp) { 1376 /* disable lplu d3 during driver init */ 1377 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1378 if (ret_val) { 1379 DEBUGOUT("Error Disabling LPLU D3\n"); 1380 return ret_val; 1381 } 1382 } 1383 1384 /* disable lplu d0 during driver init */ 1385 if (hw->phy.ops.set_d0_lplu_state) { 1386 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1387 if (ret_val) { 1388 DEBUGOUT("Error Disabling LPLU D0\n"); 1389 return ret_val; 1390 } 1391 } 1392 /* Configure mdi-mdix settings */ 1393 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1394 if (ret_val) 1395 return ret_val; 1396 1397 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1398 1399 switch (phy->mdix) { 1400 case 1: 1401 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1402 break; 1403 case 2: 1404 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1405 break; 1406 case 0: 1407 default: 1408 data |= IGP01E1000_PSCR_AUTO_MDIX; 1409 break; 1410 } 1411 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1412 if (ret_val) 1413 return ret_val; 1414 1415 /* set auto-master slave resolution settings */ 1416 if (hw->mac.autoneg) { 1417 /* when autonegotiation advertisement is only 1000Mbps then we 1418 * should disable SmartSpeed and enable Auto MasterSlave 1419 * resolution as hardware default. 1420 */ 1421 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1422 /* Disable SmartSpeed */ 1423 ret_val = phy->ops.read_reg(hw, 1424 IGP01E1000_PHY_PORT_CONFIG, 1425 &data); 1426 if (ret_val) 1427 return ret_val; 1428 1429 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1430 ret_val = phy->ops.write_reg(hw, 1431 IGP01E1000_PHY_PORT_CONFIG, 1432 data); 1433 if (ret_val) 1434 return ret_val; 1435 1436 /* Set auto Master/Slave resolution process */ 1437 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1438 if (ret_val) 1439 return ret_val; 1440 1441 data &= ~CR_1000T_MS_ENABLE; 1442 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1443 if (ret_val) 1444 return ret_val; 1445 } 1446 1447 ret_val = e1000_set_master_slave_mode(hw); 1448 } 1449 1450 return ret_val; 1451 } 1452 1453 /** 1454 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1455 * @hw: pointer to the HW structure 1456 * 1457 * Reads the MII auto-neg advertisement register and/or the 1000T control 1458 * register and if the PHY is already setup for auto-negotiation, then 1459 * return successful. Otherwise, setup advertisement and flow control to 1460 * the appropriate values for the wanted auto-negotiation. 1461 **/ 1462 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1463 { 1464 struct e1000_phy_info *phy = &hw->phy; 1465 s32 ret_val; 1466 u16 mii_autoneg_adv_reg; 1467 u16 mii_1000t_ctrl_reg = 0; 1468 1469 DEBUGFUNC("e1000_phy_setup_autoneg"); 1470 1471 phy->autoneg_advertised &= phy->autoneg_mask; 1472 1473 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1474 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1475 if (ret_val) 1476 return ret_val; 1477 1478 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1479 /* Read the MII 1000Base-T Control Register (Address 9). */ 1480 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1481 &mii_1000t_ctrl_reg); 1482 if (ret_val) 1483 return ret_val; 1484 } 1485 1486 /* Need to parse both autoneg_advertised and fc and set up 1487 * the appropriate PHY registers. First we will parse for 1488 * autoneg_advertised software override. Since we can advertise 1489 * a plethora of combinations, we need to check each bit 1490 * individually. 1491 */ 1492 1493 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1494 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1495 * the 1000Base-T Control Register (Address 9). 1496 */ 1497 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1498 NWAY_AR_100TX_HD_CAPS | 1499 NWAY_AR_10T_FD_CAPS | 1500 NWAY_AR_10T_HD_CAPS); 1501 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1502 1503 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1504 1505 /* Do we want to advertise 10 Mb Half Duplex? */ 1506 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1507 DEBUGOUT("Advertise 10mb Half duplex\n"); 1508 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1509 } 1510 1511 /* Do we want to advertise 10 Mb Full Duplex? */ 1512 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1513 DEBUGOUT("Advertise 10mb Full duplex\n"); 1514 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1515 } 1516 1517 /* Do we want to advertise 100 Mb Half Duplex? */ 1518 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1519 DEBUGOUT("Advertise 100mb Half duplex\n"); 1520 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1521 } 1522 1523 /* Do we want to advertise 100 Mb Full Duplex? */ 1524 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1525 DEBUGOUT("Advertise 100mb Full duplex\n"); 1526 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1527 } 1528 1529 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1530 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1531 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1532 1533 /* Do we want to advertise 1000 Mb Full Duplex? */ 1534 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1535 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1536 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1537 } 1538 1539 /* Check for a software override of the flow control settings, and 1540 * setup the PHY advertisement registers accordingly. If 1541 * auto-negotiation is enabled, then software will have to set the 1542 * "PAUSE" bits to the correct value in the Auto-Negotiation 1543 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1544 * negotiation. 1545 * 1546 * The possible values of the "fc" parameter are: 1547 * 0: Flow control is completely disabled 1548 * 1: Rx flow control is enabled (we can receive pause frames 1549 * but not send pause frames). 1550 * 2: Tx flow control is enabled (we can send pause frames 1551 * but we do not support receiving pause frames). 1552 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1553 * other: No software override. The flow control configuration 1554 * in the EEPROM is used. 1555 */ 1556 switch (hw->fc.current_mode) { 1557 case e1000_fc_none: 1558 /* Flow control (Rx & Tx) is completely disabled by a 1559 * software over-ride. 1560 */ 1561 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1562 break; 1563 case e1000_fc_rx_pause: 1564 /* Rx Flow control is enabled, and Tx Flow control is 1565 * disabled, by a software over-ride. 1566 * 1567 * Since there really isn't a way to advertise that we are 1568 * capable of Rx Pause ONLY, we will advertise that we 1569 * support both symmetric and asymmetric Rx PAUSE. Later 1570 * (in e1000_config_fc_after_link_up) we will disable the 1571 * hw's ability to send PAUSE frames. 1572 */ 1573 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1574 break; 1575 case e1000_fc_tx_pause: 1576 /* Tx Flow control is enabled, and Rx Flow control is 1577 * disabled, by a software over-ride. 1578 */ 1579 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1580 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1581 break; 1582 case e1000_fc_full: 1583 /* Flow control (both Rx and Tx) is enabled by a software 1584 * over-ride. 1585 */ 1586 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1587 break; 1588 default: 1589 DEBUGOUT("Flow control param set incorrectly\n"); 1590 return -E1000_ERR_CONFIG; 1591 } 1592 1593 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1594 if (ret_val) 1595 return ret_val; 1596 1597 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1598 1599 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1600 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 1601 mii_1000t_ctrl_reg); 1602 1603 return ret_val; 1604 } 1605 1606 /** 1607 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1608 * @hw: pointer to the HW structure 1609 * 1610 * Performs initial bounds checking on autoneg advertisement parameter, then 1611 * configure to advertise the full capability. Setup the PHY to autoneg 1612 * and restart the negotiation process between the link partner. If 1613 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1614 **/ 1615 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1616 { 1617 struct e1000_phy_info *phy = &hw->phy; 1618 s32 ret_val; 1619 u16 phy_ctrl; 1620 1621 DEBUGFUNC("e1000_copper_link_autoneg"); 1622 1623 /* Perform some bounds checking on the autoneg advertisement 1624 * parameter. 1625 */ 1626 phy->autoneg_advertised &= phy->autoneg_mask; 1627 1628 /* If autoneg_advertised is zero, we assume it was not defaulted 1629 * by the calling code so we set to advertise full capability. 1630 */ 1631 if (!phy->autoneg_advertised) 1632 phy->autoneg_advertised = phy->autoneg_mask; 1633 1634 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1635 ret_val = e1000_phy_setup_autoneg(hw); 1636 if (ret_val) { 1637 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1638 return ret_val; 1639 } 1640 DEBUGOUT("Restarting Auto-Neg\n"); 1641 1642 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1643 * the Auto Neg Restart bit in the PHY control register. 1644 */ 1645 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1646 if (ret_val) 1647 return ret_val; 1648 1649 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1650 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1651 if (ret_val) 1652 return ret_val; 1653 1654 /* Does the user want to wait for Auto-Neg to complete here, or 1655 * check at a later time (for example, callback routine). 1656 */ 1657 if (phy->autoneg_wait_to_complete) { 1658 ret_val = e1000_wait_autoneg(hw); 1659 if (ret_val) { 1660 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1661 return ret_val; 1662 } 1663 } 1664 1665 hw->mac.get_link_status = TRUE; 1666 1667 return ret_val; 1668 } 1669 1670 /** 1671 * e1000_setup_copper_link_generic - Configure copper link settings 1672 * @hw: pointer to the HW structure 1673 * 1674 * Calls the appropriate function to configure the link for auto-neg or forced 1675 * speed and duplex. Then we check for link, once link is established calls 1676 * to configure collision distance and flow control are called. If link is 1677 * not established, we return -E1000_ERR_PHY (-2). 1678 **/ 1679 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1680 { 1681 s32 ret_val; 1682 bool link; 1683 1684 DEBUGFUNC("e1000_setup_copper_link_generic"); 1685 1686 if (hw->mac.autoneg) { 1687 /* Setup autoneg and flow control advertisement and perform 1688 * autonegotiation. 1689 */ 1690 ret_val = e1000_copper_link_autoneg(hw); 1691 if (ret_val) 1692 return ret_val; 1693 } else { 1694 /* PHY will be set to 10H, 10F, 100H or 100F 1695 * depending on user settings. 1696 */ 1697 DEBUGOUT("Forcing Speed and Duplex\n"); 1698 ret_val = hw->phy.ops.force_speed_duplex(hw); 1699 if (ret_val) { 1700 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1701 return ret_val; 1702 } 1703 } 1704 1705 /* Check link status. Wait up to 100 microseconds for link to become 1706 * valid. 1707 */ 1708 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1709 &link); 1710 if (ret_val) 1711 return ret_val; 1712 1713 if (link) { 1714 DEBUGOUT("Valid link established!!!\n"); 1715 hw->mac.ops.config_collision_dist(hw); 1716 ret_val = e1000_config_fc_after_link_up_generic(hw); 1717 } else { 1718 DEBUGOUT("Unable to establish link!!!\n"); 1719 } 1720 1721 return ret_val; 1722 } 1723 1724 /** 1725 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1726 * @hw: pointer to the HW structure 1727 * 1728 * Calls the PHY setup function to force speed and duplex. Clears the 1729 * auto-crossover to force MDI manually. Waits for link and returns 1730 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1731 **/ 1732 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1733 { 1734 struct e1000_phy_info *phy = &hw->phy; 1735 s32 ret_val; 1736 u16 phy_data; 1737 bool link; 1738 1739 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1740 1741 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1742 if (ret_val) 1743 return ret_val; 1744 1745 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1746 1747 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1748 if (ret_val) 1749 return ret_val; 1750 1751 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1752 * forced whenever speed and duplex are forced. 1753 */ 1754 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1755 if (ret_val) 1756 return ret_val; 1757 1758 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1759 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1760 1761 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1762 if (ret_val) 1763 return ret_val; 1764 1765 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1766 1767 usec_delay(1); 1768 1769 if (phy->autoneg_wait_to_complete) { 1770 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1771 1772 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1773 100000, &link); 1774 if (ret_val) 1775 return ret_val; 1776 1777 if (!link) 1778 DEBUGOUT("Link taking longer than expected.\n"); 1779 1780 /* Try once more */ 1781 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1782 100000, &link); 1783 } 1784 1785 return ret_val; 1786 } 1787 1788 /** 1789 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1790 * @hw: pointer to the HW structure 1791 * 1792 * Calls the PHY setup function to force speed and duplex. Clears the 1793 * auto-crossover to force MDI manually. Resets the PHY to commit the 1794 * changes. If time expires while waiting for link up, we reset the DSP. 1795 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1796 * successful completion, else return corresponding error code. 1797 **/ 1798 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1799 { 1800 struct e1000_phy_info *phy = &hw->phy; 1801 s32 ret_val; 1802 u16 phy_data; 1803 bool link; 1804 1805 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1806 1807 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1808 if (phy->type != e1000_phy_i210) { 1809 /* Clear Auto-Crossover to force MDI manually. M88E1000 1810 * requires MDI forced whenever speed and duplex are forced. 1811 */ 1812 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1813 &phy_data); 1814 if (ret_val) 1815 return ret_val; 1816 1817 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1818 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1819 phy_data); 1820 if (ret_val) 1821 return ret_val; 1822 } 1823 1824 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1825 1826 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1827 if (ret_val) 1828 return ret_val; 1829 1830 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1831 1832 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1833 if (ret_val) 1834 return ret_val; 1835 1836 /* Reset the phy to commit changes. */ 1837 ret_val = hw->phy.ops.commit(hw); 1838 if (ret_val) 1839 return ret_val; 1840 1841 if (phy->autoneg_wait_to_complete) { 1842 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1843 1844 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1845 100000, &link); 1846 if (ret_val) 1847 return ret_val; 1848 1849 if (!link) { 1850 bool reset_dsp = TRUE; 1851 1852 switch (hw->phy.id) { 1853 case I347AT4_E_PHY_ID: 1854 case M88E1340M_E_PHY_ID: 1855 case M88E1112_E_PHY_ID: 1856 case M88E1545_E_PHY_ID: 1857 case I210_I_PHY_ID: 1858 reset_dsp = FALSE; 1859 break; 1860 default: 1861 if (hw->phy.type != e1000_phy_m88) 1862 reset_dsp = FALSE; 1863 break; 1864 } 1865 1866 if (!reset_dsp) { 1867 DEBUGOUT("Link taking longer than expected.\n"); 1868 } else { 1869 /* We didn't get link. 1870 * Reset the DSP and cross our fingers. 1871 */ 1872 ret_val = phy->ops.write_reg(hw, 1873 M88E1000_PHY_PAGE_SELECT, 1874 0x001d); 1875 if (ret_val) 1876 return ret_val; 1877 ret_val = e1000_phy_reset_dsp_generic(hw); 1878 if (ret_val) 1879 return ret_val; 1880 } 1881 } 1882 1883 /* Try once more */ 1884 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1885 100000, &link); 1886 if (ret_val) 1887 return ret_val; 1888 } 1889 1890 if (hw->phy.type != e1000_phy_m88) 1891 return E1000_SUCCESS; 1892 1893 if (hw->phy.id == I347AT4_E_PHY_ID || 1894 hw->phy.id == M88E1340M_E_PHY_ID || 1895 hw->phy.id == M88E1112_E_PHY_ID) 1896 return E1000_SUCCESS; 1897 if (hw->phy.id == I210_I_PHY_ID) 1898 return E1000_SUCCESS; 1899 if (hw->phy.id == M88E1545_E_PHY_ID) 1900 return E1000_SUCCESS; 1901 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1902 if (ret_val) 1903 return ret_val; 1904 1905 /* Resetting the phy means we need to re-force TX_CLK in the 1906 * Extended PHY Specific Control Register to 25MHz clock from 1907 * the reset value of 2.5MHz. 1908 */ 1909 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1910 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1911 if (ret_val) 1912 return ret_val; 1913 1914 /* In addition, we must re-enable CRS on Tx for both half and full 1915 * duplex. 1916 */ 1917 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1918 if (ret_val) 1919 return ret_val; 1920 1921 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1922 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1923 1924 return ret_val; 1925 } 1926 1927 /** 1928 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1929 * @hw: pointer to the HW structure 1930 * 1931 * Forces the speed and duplex settings of the PHY. 1932 * This is a function pointer entry point only called by 1933 * PHY setup routines. 1934 **/ 1935 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1936 { 1937 struct e1000_phy_info *phy = &hw->phy; 1938 s32 ret_val; 1939 u16 data; 1940 bool link; 1941 1942 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1943 1944 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1945 if (ret_val) 1946 return ret_val; 1947 1948 e1000_phy_force_speed_duplex_setup(hw, &data); 1949 1950 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1951 if (ret_val) 1952 return ret_val; 1953 1954 /* Disable MDI-X support for 10/100 */ 1955 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1956 if (ret_val) 1957 return ret_val; 1958 1959 data &= ~IFE_PMC_AUTO_MDIX; 1960 data &= ~IFE_PMC_FORCE_MDIX; 1961 1962 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1963 if (ret_val) 1964 return ret_val; 1965 1966 DEBUGOUT1("IFE PMC: %X\n", data); 1967 1968 usec_delay(1); 1969 1970 if (phy->autoneg_wait_to_complete) { 1971 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1972 1973 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1974 100000, &link); 1975 if (ret_val) 1976 return ret_val; 1977 1978 if (!link) 1979 DEBUGOUT("Link taking longer than expected.\n"); 1980 1981 /* Try once more */ 1982 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1983 100000, &link); 1984 if (ret_val) 1985 return ret_val; 1986 } 1987 1988 return E1000_SUCCESS; 1989 } 1990 1991 /** 1992 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1993 * @hw: pointer to the HW structure 1994 * @phy_ctrl: pointer to current value of PHY_CONTROL 1995 * 1996 * Forces speed and duplex on the PHY by doing the following: disable flow 1997 * control, force speed/duplex on the MAC, disable auto speed detection, 1998 * disable auto-negotiation, configure duplex, configure speed, configure 1999 * the collision distance, write configuration to CTRL register. The 2000 * caller must write to the PHY_CONTROL register for these settings to 2001 * take affect. 2002 **/ 2003 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 2004 { 2005 struct e1000_mac_info *mac = &hw->mac; 2006 u32 ctrl; 2007 2008 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 2009 2010 /* Turn off flow control when forcing speed/duplex */ 2011 hw->fc.current_mode = e1000_fc_none; 2012 2013 /* Force speed/duplex on the mac */ 2014 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2015 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2016 ctrl &= ~E1000_CTRL_SPD_SEL; 2017 2018 /* Disable Auto Speed Detection */ 2019 ctrl &= ~E1000_CTRL_ASDE; 2020 2021 /* Disable autoneg on the phy */ 2022 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 2023 2024 /* Forcing Full or Half Duplex? */ 2025 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 2026 ctrl &= ~E1000_CTRL_FD; 2027 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 2028 DEBUGOUT("Half Duplex\n"); 2029 } else { 2030 ctrl |= E1000_CTRL_FD; 2031 *phy_ctrl |= MII_CR_FULL_DUPLEX; 2032 DEBUGOUT("Full Duplex\n"); 2033 } 2034 2035 /* Forcing 10mb or 100mb? */ 2036 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 2037 ctrl |= E1000_CTRL_SPD_100; 2038 *phy_ctrl |= MII_CR_SPEED_100; 2039 *phy_ctrl &= ~MII_CR_SPEED_1000; 2040 DEBUGOUT("Forcing 100mb\n"); 2041 } else { 2042 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2043 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2044 DEBUGOUT("Forcing 10mb\n"); 2045 } 2046 2047 hw->mac.ops.config_collision_dist(hw); 2048 2049 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2050 } 2051 2052 /** 2053 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 2054 * @hw: pointer to the HW structure 2055 * @active: boolean used to enable/disable lplu 2056 * 2057 * Success returns 0, Failure returns 1 2058 * 2059 * The low power link up (lplu) state is set to the power management level D3 2060 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 2061 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2062 * is used during Dx states where the power conservation is most important. 2063 * During driver activity, SmartSpeed should be enabled so performance is 2064 * maintained. 2065 **/ 2066 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 2067 { 2068 struct e1000_phy_info *phy = &hw->phy; 2069 s32 ret_val; 2070 u16 data; 2071 2072 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 2073 2074 if (!hw->phy.ops.read_reg) 2075 return E1000_SUCCESS; 2076 2077 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 2078 if (ret_val) 2079 return ret_val; 2080 2081 if (!active) { 2082 data &= ~IGP02E1000_PM_D3_LPLU; 2083 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2084 data); 2085 if (ret_val) 2086 return ret_val; 2087 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2088 * during Dx states where the power conservation is most 2089 * important. During driver activity we should enable 2090 * SmartSpeed, so performance is maintained. 2091 */ 2092 if (phy->smart_speed == e1000_smart_speed_on) { 2093 ret_val = phy->ops.read_reg(hw, 2094 IGP01E1000_PHY_PORT_CONFIG, 2095 &data); 2096 if (ret_val) 2097 return ret_val; 2098 2099 data |= IGP01E1000_PSCFR_SMART_SPEED; 2100 ret_val = phy->ops.write_reg(hw, 2101 IGP01E1000_PHY_PORT_CONFIG, 2102 data); 2103 if (ret_val) 2104 return ret_val; 2105 } else if (phy->smart_speed == e1000_smart_speed_off) { 2106 ret_val = phy->ops.read_reg(hw, 2107 IGP01E1000_PHY_PORT_CONFIG, 2108 &data); 2109 if (ret_val) 2110 return ret_val; 2111 2112 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2113 ret_val = phy->ops.write_reg(hw, 2114 IGP01E1000_PHY_PORT_CONFIG, 2115 data); 2116 if (ret_val) 2117 return ret_val; 2118 } 2119 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2120 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2121 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2122 data |= IGP02E1000_PM_D3_LPLU; 2123 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2124 data); 2125 if (ret_val) 2126 return ret_val; 2127 2128 /* When LPLU is enabled, we should disable SmartSpeed */ 2129 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2130 &data); 2131 if (ret_val) 2132 return ret_val; 2133 2134 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2135 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2136 data); 2137 } 2138 2139 return ret_val; 2140 } 2141 2142 /** 2143 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 2144 * @hw: pointer to the HW structure 2145 * 2146 * Success returns 0, Failure returns 1 2147 * 2148 * A downshift is detected by querying the PHY link health. 2149 **/ 2150 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 2151 { 2152 struct e1000_phy_info *phy = &hw->phy; 2153 s32 ret_val; 2154 u16 phy_data, offset, mask; 2155 2156 DEBUGFUNC("e1000_check_downshift_generic"); 2157 2158 switch (phy->type) { 2159 case e1000_phy_i210: 2160 case e1000_phy_m88: 2161 case e1000_phy_gg82563: 2162 case e1000_phy_bm: 2163 case e1000_phy_82578: 2164 offset = M88E1000_PHY_SPEC_STATUS; 2165 mask = M88E1000_PSSR_DOWNSHIFT; 2166 break; 2167 case e1000_phy_igp: 2168 case e1000_phy_igp_2: 2169 case e1000_phy_igp_3: 2170 offset = IGP01E1000_PHY_LINK_HEALTH; 2171 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 2172 break; 2173 default: 2174 /* speed downshift not supported */ 2175 phy->speed_downgraded = FALSE; 2176 return E1000_SUCCESS; 2177 } 2178 2179 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2180 2181 if (!ret_val) 2182 phy->speed_downgraded = !!(phy_data & mask); 2183 2184 return ret_val; 2185 } 2186 2187 /** 2188 * e1000_check_polarity_m88 - Checks the polarity. 2189 * @hw: pointer to the HW structure 2190 * 2191 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2192 * 2193 * Polarity is determined based on the PHY specific status register. 2194 **/ 2195 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 2196 { 2197 struct e1000_phy_info *phy = &hw->phy; 2198 s32 ret_val; 2199 u16 data; 2200 2201 DEBUGFUNC("e1000_check_polarity_m88"); 2202 2203 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 2204 2205 if (!ret_val) 2206 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) 2207 ? e1000_rev_polarity_reversed 2208 : e1000_rev_polarity_normal); 2209 2210 return ret_val; 2211 } 2212 2213 /** 2214 * e1000_check_polarity_igp - Checks the polarity. 2215 * @hw: pointer to the HW structure 2216 * 2217 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2218 * 2219 * Polarity is determined based on the PHY port status register, and the 2220 * current speed (since there is no polarity at 100Mbps). 2221 **/ 2222 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 2223 { 2224 struct e1000_phy_info *phy = &hw->phy; 2225 s32 ret_val; 2226 u16 data, offset, mask; 2227 2228 DEBUGFUNC("e1000_check_polarity_igp"); 2229 2230 /* Polarity is determined based on the speed of 2231 * our connection. 2232 */ 2233 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2234 if (ret_val) 2235 return ret_val; 2236 2237 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2238 IGP01E1000_PSSR_SPEED_1000MBPS) { 2239 offset = IGP01E1000_PHY_PCS_INIT_REG; 2240 mask = IGP01E1000_PHY_POLARITY_MASK; 2241 } else { 2242 /* This really only applies to 10Mbps since 2243 * there is no polarity for 100Mbps (always 0). 2244 */ 2245 offset = IGP01E1000_PHY_PORT_STATUS; 2246 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2247 } 2248 2249 ret_val = phy->ops.read_reg(hw, offset, &data); 2250 2251 if (!ret_val) 2252 phy->cable_polarity = ((data & mask) 2253 ? e1000_rev_polarity_reversed 2254 : e1000_rev_polarity_normal); 2255 2256 return ret_val; 2257 } 2258 2259 /** 2260 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2261 * @hw: pointer to the HW structure 2262 * 2263 * Polarity is determined on the polarity reversal feature being enabled. 2264 **/ 2265 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 2266 { 2267 struct e1000_phy_info *phy = &hw->phy; 2268 s32 ret_val; 2269 u16 phy_data, offset, mask; 2270 2271 DEBUGFUNC("e1000_check_polarity_ife"); 2272 2273 /* Polarity is determined based on the reversal feature being enabled. 2274 */ 2275 if (phy->polarity_correction) { 2276 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2277 mask = IFE_PESC_POLARITY_REVERSED; 2278 } else { 2279 offset = IFE_PHY_SPECIAL_CONTROL; 2280 mask = IFE_PSC_FORCE_POLARITY; 2281 } 2282 2283 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2284 2285 if (!ret_val) 2286 phy->cable_polarity = ((phy_data & mask) 2287 ? e1000_rev_polarity_reversed 2288 : e1000_rev_polarity_normal); 2289 2290 return ret_val; 2291 } 2292 2293 /** 2294 * e1000_wait_autoneg - Wait for auto-neg completion 2295 * @hw: pointer to the HW structure 2296 * 2297 * Waits for auto-negotiation to complete or for the auto-negotiation time 2298 * limit to expire, which ever happens first. 2299 **/ 2300 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2301 { 2302 s32 ret_val = E1000_SUCCESS; 2303 u16 i, phy_status; 2304 2305 DEBUGFUNC("e1000_wait_autoneg"); 2306 2307 if (!hw->phy.ops.read_reg) 2308 return E1000_SUCCESS; 2309 2310 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2311 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2312 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2313 if (ret_val) 2314 break; 2315 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2316 if (ret_val) 2317 break; 2318 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2319 break; 2320 msec_delay(100); 2321 } 2322 2323 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2324 * has completed. 2325 */ 2326 return ret_val; 2327 } 2328 2329 /** 2330 * e1000_phy_has_link_generic - Polls PHY for link 2331 * @hw: pointer to the HW structure 2332 * @iterations: number of times to poll for link 2333 * @usec_interval: delay between polling attempts 2334 * @success: pointer to whether polling was successful or not 2335 * 2336 * Polls the PHY status register for link, 'iterations' number of times. 2337 **/ 2338 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2339 u32 usec_interval, bool *success) 2340 { 2341 s32 ret_val = E1000_SUCCESS; 2342 u16 i, phy_status; 2343 2344 DEBUGFUNC("e1000_phy_has_link_generic"); 2345 2346 if (!hw->phy.ops.read_reg) 2347 return E1000_SUCCESS; 2348 2349 for (i = 0; i < iterations; i++) { 2350 /* Some PHYs require the PHY_STATUS register to be read 2351 * twice due to the link bit being sticky. No harm doing 2352 * it across the board. 2353 */ 2354 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2355 if (ret_val) 2356 /* If the first read fails, another entity may have 2357 * ownership of the resources, wait and try again to 2358 * see if they have relinquished the resources yet. 2359 */ 2360 usec_delay(usec_interval); 2361 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2362 if (ret_val) 2363 break; 2364 if (phy_status & MII_SR_LINK_STATUS) 2365 break; 2366 if (usec_interval >= 1000) 2367 msec_delay_irq(usec_interval/1000); 2368 else 2369 usec_delay(usec_interval); 2370 } 2371 2372 *success = (i < iterations); 2373 2374 return ret_val; 2375 } 2376 2377 /** 2378 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2379 * @hw: pointer to the HW structure 2380 * 2381 * Reads the PHY specific status register to retrieve the cable length 2382 * information. The cable length is determined by averaging the minimum and 2383 * maximum values to get the "average" cable length. The m88 PHY has four 2384 * possible cable length values, which are: 2385 * Register Value Cable Length 2386 * 0 < 50 meters 2387 * 1 50 - 80 meters 2388 * 2 80 - 110 meters 2389 * 3 110 - 140 meters 2390 * 4 > 140 meters 2391 **/ 2392 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2393 { 2394 struct e1000_phy_info *phy = &hw->phy; 2395 s32 ret_val; 2396 u16 phy_data, index; 2397 2398 DEBUGFUNC("e1000_get_cable_length_m88"); 2399 2400 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2401 if (ret_val) 2402 return ret_val; 2403 2404 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2405 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 2406 2407 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2408 return -E1000_ERR_PHY; 2409 2410 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2411 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2412 2413 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2414 2415 return E1000_SUCCESS; 2416 } 2417 2418 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2419 { 2420 struct e1000_phy_info *phy = &hw->phy; 2421 s32 ret_val; 2422 u16 phy_data, phy_data2, is_cm; 2423 u16 index, default_page; 2424 2425 DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2426 2427 switch (hw->phy.id) { 2428 case I210_I_PHY_ID: 2429 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2430 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2431 (I347AT4_PCDL + phy->addr), 2432 &phy_data); 2433 if (ret_val) 2434 return ret_val; 2435 2436 /* Check if the unit of cable length is meters or cm */ 2437 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2438 I347AT4_PCDC, &phy_data2); 2439 if (ret_val) 2440 return ret_val; 2441 2442 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2443 2444 /* Populate the phy structure with cable length in meters */ 2445 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2446 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2447 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2448 break; 2449 case M88E1545_E_PHY_ID: 2450 case M88E1340M_E_PHY_ID: 2451 case I347AT4_E_PHY_ID: 2452 /* Remember the original page select and set it to 7 */ 2453 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2454 &default_page); 2455 if (ret_val) 2456 return ret_val; 2457 2458 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2459 if (ret_val) 2460 return ret_val; 2461 2462 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2463 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2464 &phy_data); 2465 if (ret_val) 2466 return ret_val; 2467 2468 /* Check if the unit of cable length is meters or cm */ 2469 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2470 if (ret_val) 2471 return ret_val; 2472 2473 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2474 2475 /* Populate the phy structure with cable length in meters */ 2476 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2477 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2478 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2479 2480 /* Reset the page select to its original value */ 2481 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2482 default_page); 2483 if (ret_val) 2484 return ret_val; 2485 break; 2486 2487 case M88E1112_E_PHY_ID: 2488 /* Remember the original page select and set it to 5 */ 2489 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2490 &default_page); 2491 if (ret_val) 2492 return ret_val; 2493 2494 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2495 if (ret_val) 2496 return ret_val; 2497 2498 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2499 &phy_data); 2500 if (ret_val) 2501 return ret_val; 2502 2503 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2504 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2505 2506 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2507 return -E1000_ERR_PHY; 2508 2509 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2510 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2511 2512 phy->cable_length = (phy->min_cable_length + 2513 phy->max_cable_length) / 2; 2514 2515 /* Reset the page select to its original value */ 2516 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2517 default_page); 2518 if (ret_val) 2519 return ret_val; 2520 2521 break; 2522 default: 2523 return -E1000_ERR_PHY; 2524 } 2525 2526 return ret_val; 2527 } 2528 2529 /** 2530 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2531 * @hw: pointer to the HW structure 2532 * 2533 * The automatic gain control (agc) normalizes the amplitude of the 2534 * received signal, adjusting for the attenuation produced by the 2535 * cable. By reading the AGC registers, which represent the 2536 * combination of coarse and fine gain value, the value can be put 2537 * into a lookup table to obtain the approximate cable length 2538 * for each channel. 2539 **/ 2540 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2541 { 2542 struct e1000_phy_info *phy = &hw->phy; 2543 s32 ret_val; 2544 u16 phy_data, i, agc_value = 0; 2545 u16 cur_agc_index, max_agc_index = 0; 2546 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2547 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2548 IGP02E1000_PHY_AGC_A, 2549 IGP02E1000_PHY_AGC_B, 2550 IGP02E1000_PHY_AGC_C, 2551 IGP02E1000_PHY_AGC_D 2552 }; 2553 2554 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2555 2556 /* Read the AGC registers for all channels */ 2557 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2558 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2559 if (ret_val) 2560 return ret_val; 2561 2562 /* Getting bits 15:9, which represent the combination of 2563 * coarse and fine gain values. The result is a number 2564 * that can be put into the lookup table to obtain the 2565 * approximate cable length. 2566 */ 2567 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2568 IGP02E1000_AGC_LENGTH_MASK); 2569 2570 /* Array index bound check. */ 2571 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2572 (cur_agc_index == 0)) 2573 return -E1000_ERR_PHY; 2574 2575 /* Remove min & max AGC values from calculation. */ 2576 if (e1000_igp_2_cable_length_table[min_agc_index] > 2577 e1000_igp_2_cable_length_table[cur_agc_index]) 2578 min_agc_index = cur_agc_index; 2579 if (e1000_igp_2_cable_length_table[max_agc_index] < 2580 e1000_igp_2_cable_length_table[cur_agc_index]) 2581 max_agc_index = cur_agc_index; 2582 2583 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2584 } 2585 2586 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2587 e1000_igp_2_cable_length_table[max_agc_index]); 2588 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2589 2590 /* Calculate cable length with the error range of +/- 10 meters. */ 2591 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2592 (agc_value - IGP02E1000_AGC_RANGE) : 0); 2593 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2594 2595 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2596 2597 return E1000_SUCCESS; 2598 } 2599 2600 /** 2601 * e1000_get_phy_info_m88 - Retrieve PHY information 2602 * @hw: pointer to the HW structure 2603 * 2604 * Valid for only copper links. Read the PHY status register (sticky read) 2605 * to verify that link is up. Read the PHY special control register to 2606 * determine the polarity and 10base-T extended distance. Read the PHY 2607 * special status register to determine MDI/MDIx and current speed. If 2608 * speed is 1000, then determine cable length, local and remote receiver. 2609 **/ 2610 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2611 { 2612 struct e1000_phy_info *phy = &hw->phy; 2613 s32 ret_val; 2614 u16 phy_data; 2615 bool link; 2616 2617 DEBUGFUNC("e1000_get_phy_info_m88"); 2618 2619 if (phy->media_type != e1000_media_type_copper) { 2620 DEBUGOUT("Phy info is only valid for copper media\n"); 2621 return -E1000_ERR_CONFIG; 2622 } 2623 2624 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2625 if (ret_val) 2626 return ret_val; 2627 2628 if (!link) { 2629 DEBUGOUT("Phy info is only valid if link is up\n"); 2630 return -E1000_ERR_CONFIG; 2631 } 2632 2633 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2634 if (ret_val) 2635 return ret_val; 2636 2637 phy->polarity_correction = !!(phy_data & 2638 M88E1000_PSCR_POLARITY_REVERSAL); 2639 2640 ret_val = e1000_check_polarity_m88(hw); 2641 if (ret_val) 2642 return ret_val; 2643 2644 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2645 if (ret_val) 2646 return ret_val; 2647 2648 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 2649 2650 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2651 ret_val = hw->phy.ops.get_cable_length(hw); 2652 if (ret_val) 2653 return ret_val; 2654 2655 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2656 if (ret_val) 2657 return ret_val; 2658 2659 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2660 ? e1000_1000t_rx_status_ok 2661 : e1000_1000t_rx_status_not_ok; 2662 2663 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2664 ? e1000_1000t_rx_status_ok 2665 : e1000_1000t_rx_status_not_ok; 2666 } else { 2667 /* Set values to "undefined" */ 2668 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2669 phy->local_rx = e1000_1000t_rx_status_undefined; 2670 phy->remote_rx = e1000_1000t_rx_status_undefined; 2671 } 2672 2673 return ret_val; 2674 } 2675 2676 /** 2677 * e1000_get_phy_info_igp - Retrieve igp PHY information 2678 * @hw: pointer to the HW structure 2679 * 2680 * Read PHY status to determine if link is up. If link is up, then 2681 * set/determine 10base-T extended distance and polarity correction. Read 2682 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2683 * determine on the cable length, local and remote receiver. 2684 **/ 2685 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2686 { 2687 struct e1000_phy_info *phy = &hw->phy; 2688 s32 ret_val; 2689 u16 data; 2690 bool link; 2691 2692 DEBUGFUNC("e1000_get_phy_info_igp"); 2693 2694 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2695 if (ret_val) 2696 return ret_val; 2697 2698 if (!link) { 2699 DEBUGOUT("Phy info is only valid if link is up\n"); 2700 return -E1000_ERR_CONFIG; 2701 } 2702 2703 phy->polarity_correction = TRUE; 2704 2705 ret_val = e1000_check_polarity_igp(hw); 2706 if (ret_val) 2707 return ret_val; 2708 2709 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2710 if (ret_val) 2711 return ret_val; 2712 2713 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 2714 2715 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2716 IGP01E1000_PSSR_SPEED_1000MBPS) { 2717 ret_val = phy->ops.get_cable_length(hw); 2718 if (ret_val) 2719 return ret_val; 2720 2721 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2722 if (ret_val) 2723 return ret_val; 2724 2725 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2726 ? e1000_1000t_rx_status_ok 2727 : e1000_1000t_rx_status_not_ok; 2728 2729 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2730 ? e1000_1000t_rx_status_ok 2731 : e1000_1000t_rx_status_not_ok; 2732 } else { 2733 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2734 phy->local_rx = e1000_1000t_rx_status_undefined; 2735 phy->remote_rx = e1000_1000t_rx_status_undefined; 2736 } 2737 2738 return ret_val; 2739 } 2740 2741 /** 2742 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2743 * @hw: pointer to the HW structure 2744 * 2745 * Populates "phy" structure with various feature states. 2746 **/ 2747 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2748 { 2749 struct e1000_phy_info *phy = &hw->phy; 2750 s32 ret_val; 2751 u16 data; 2752 bool link; 2753 2754 DEBUGFUNC("e1000_get_phy_info_ife"); 2755 2756 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2757 if (ret_val) 2758 return ret_val; 2759 2760 if (!link) { 2761 DEBUGOUT("Phy info is only valid if link is up\n"); 2762 return -E1000_ERR_CONFIG; 2763 } 2764 2765 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2766 if (ret_val) 2767 return ret_val; 2768 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2769 2770 if (phy->polarity_correction) { 2771 ret_val = e1000_check_polarity_ife(hw); 2772 if (ret_val) 2773 return ret_val; 2774 } else { 2775 /* Polarity is forced */ 2776 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) 2777 ? e1000_rev_polarity_reversed 2778 : e1000_rev_polarity_normal); 2779 } 2780 2781 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2782 if (ret_val) 2783 return ret_val; 2784 2785 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2786 2787 /* The following parameters are undefined for 10/100 operation. */ 2788 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2789 phy->local_rx = e1000_1000t_rx_status_undefined; 2790 phy->remote_rx = e1000_1000t_rx_status_undefined; 2791 2792 return E1000_SUCCESS; 2793 } 2794 2795 /** 2796 * e1000_phy_sw_reset_generic - PHY software reset 2797 * @hw: pointer to the HW structure 2798 * 2799 * Does a software reset of the PHY by reading the PHY control register and 2800 * setting/write the control register reset bit to the PHY. 2801 **/ 2802 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2803 { 2804 s32 ret_val; 2805 u16 phy_ctrl; 2806 2807 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2808 2809 if (!hw->phy.ops.read_reg) 2810 return E1000_SUCCESS; 2811 2812 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2813 if (ret_val) 2814 return ret_val; 2815 2816 phy_ctrl |= MII_CR_RESET; 2817 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2818 if (ret_val) 2819 return ret_val; 2820 2821 usec_delay(1); 2822 2823 return ret_val; 2824 } 2825 2826 /** 2827 * e1000_phy_hw_reset_generic - PHY hardware reset 2828 * @hw: pointer to the HW structure 2829 * 2830 * Verify the reset block is not blocking us from resetting. Acquire 2831 * semaphore (if necessary) and read/set/write the device control reset 2832 * bit in the PHY. Wait the appropriate delay time for the device to 2833 * reset and release the semaphore (if necessary). 2834 **/ 2835 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2836 { 2837 struct e1000_phy_info *phy = &hw->phy; 2838 s32 ret_val; 2839 u32 ctrl; 2840 2841 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2842 2843 if (phy->ops.check_reset_block) { 2844 ret_val = phy->ops.check_reset_block(hw); 2845 if (ret_val) 2846 return E1000_SUCCESS; 2847 } 2848 2849 ret_val = phy->ops.acquire(hw); 2850 if (ret_val) 2851 return ret_val; 2852 2853 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2854 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2855 E1000_WRITE_FLUSH(hw); 2856 2857 usec_delay(phy->reset_delay_us); 2858 2859 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2860 E1000_WRITE_FLUSH(hw); 2861 2862 usec_delay(150); 2863 2864 phy->ops.release(hw); 2865 2866 return phy->ops.get_cfg_done(hw); 2867 } 2868 2869 /** 2870 * e1000_get_cfg_done_generic - Generic configuration done 2871 * @hw: pointer to the HW structure 2872 * 2873 * Generic function to wait 10 milli-seconds for configuration to complete 2874 * and return success. 2875 **/ 2876 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2877 { 2878 DEBUGFUNC("e1000_get_cfg_done_generic"); 2879 2880 msec_delay_irq(10); 2881 2882 return E1000_SUCCESS; 2883 } 2884 2885 /** 2886 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2887 * @hw: pointer to the HW structure 2888 * 2889 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2890 **/ 2891 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2892 { 2893 DEBUGOUT("Running IGP 3 PHY init script\n"); 2894 2895 /* PHY init IGP 3 */ 2896 /* Enable rise/fall, 10-mode work in class-A */ 2897 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2898 /* Remove all caps from Replica path filter */ 2899 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2900 /* Bias trimming for ADC, AFE and Driver (Default) */ 2901 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2902 /* Increase Hybrid poly bias */ 2903 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2904 /* Add 4% to Tx amplitude in Gig mode */ 2905 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2906 /* Disable trimming (TTT) */ 2907 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2908 /* Poly DC correction to 94.6% + 2% for all channels */ 2909 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2910 /* ABS DC correction to 95.9% */ 2911 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2912 /* BG temp curve trim */ 2913 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2914 /* Increasing ADC OPAMP stage 1 currents to max */ 2915 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2916 /* Force 1000 ( required for enabling PHY regs configuration) */ 2917 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2918 /* Set upd_freq to 6 */ 2919 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2920 /* Disable NPDFE */ 2921 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2922 /* Disable adaptive fixed FFE (Default) */ 2923 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2924 /* Enable FFE hysteresis */ 2925 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2926 /* Fixed FFE for short cable lengths */ 2927 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2928 /* Fixed FFE for medium cable lengths */ 2929 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2930 /* Fixed FFE for long cable lengths */ 2931 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2932 /* Enable Adaptive Clip Threshold */ 2933 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2934 /* AHT reset limit to 1 */ 2935 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2936 /* Set AHT master delay to 127 msec */ 2937 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2938 /* Set scan bits for AHT */ 2939 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2940 /* Set AHT Preset bits */ 2941 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2942 /* Change integ_factor of channel A to 3 */ 2943 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2944 /* Change prop_factor of channels BCD to 8 */ 2945 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2946 /* Change cg_icount + enable integbp for channels BCD */ 2947 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2948 /* Change cg_icount + enable integbp + change prop_factor_master 2949 * to 8 for channel A 2950 */ 2951 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2952 /* Disable AHT in Slave mode on channel A */ 2953 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2954 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2955 * Enable SPD+B2B 2956 */ 2957 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2958 /* Enable restart AN on an1000_dis change */ 2959 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2960 /* Enable wh_fifo read clock in 10/100 modes */ 2961 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2962 /* Restart AN, Speed selection is 1000 */ 2963 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2964 2965 return E1000_SUCCESS; 2966 } 2967 2968 /** 2969 * e1000_get_phy_type_from_id - Get PHY type from id 2970 * @phy_id: phy_id read from the phy 2971 * 2972 * Returns the phy type from the id. 2973 **/ 2974 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2975 { 2976 enum e1000_phy_type phy_type = e1000_phy_unknown; 2977 2978 switch (phy_id) { 2979 case M88E1000_I_PHY_ID: 2980 case M88E1000_E_PHY_ID: 2981 case M88E1111_I_PHY_ID: 2982 case M88E1011_I_PHY_ID: 2983 case M88E1545_E_PHY_ID: 2984 case I347AT4_E_PHY_ID: 2985 case M88E1112_E_PHY_ID: 2986 case M88E1340M_E_PHY_ID: 2987 phy_type = e1000_phy_m88; 2988 break; 2989 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2990 phy_type = e1000_phy_igp_2; 2991 break; 2992 case GG82563_E_PHY_ID: 2993 phy_type = e1000_phy_gg82563; 2994 break; 2995 case IGP03E1000_E_PHY_ID: 2996 phy_type = e1000_phy_igp_3; 2997 break; 2998 case IFE_E_PHY_ID: 2999 case IFE_PLUS_E_PHY_ID: 3000 case IFE_C_E_PHY_ID: 3001 phy_type = e1000_phy_ife; 3002 break; 3003 case BME1000_E_PHY_ID: 3004 case BME1000_E_PHY_ID_R2: 3005 phy_type = e1000_phy_bm; 3006 break; 3007 case I82578_E_PHY_ID: 3008 phy_type = e1000_phy_82578; 3009 break; 3010 case I82577_E_PHY_ID: 3011 phy_type = e1000_phy_82577; 3012 break; 3013 case I82579_E_PHY_ID: 3014 phy_type = e1000_phy_82579; 3015 break; 3016 case I82580_I_PHY_ID: 3017 phy_type = e1000_phy_82580; 3018 break; 3019 case I210_I_PHY_ID: 3020 phy_type = e1000_phy_i210; 3021 break; 3022 case I217_E_PHY_ID: 3023 phy_type = e1000_phy_i217; 3024 break; 3025 default: 3026 phy_type = e1000_phy_unknown; 3027 break; 3028 } 3029 return phy_type; 3030 } 3031 3032 /** 3033 * e1000_determine_phy_address - Determines PHY address. 3034 * @hw: pointer to the HW structure 3035 * 3036 * This uses a trial and error method to loop through possible PHY 3037 * addresses. It tests each by reading the PHY ID registers and 3038 * checking for a match. 3039 **/ 3040 s32 e1000_determine_phy_address(struct e1000_hw *hw) 3041 { 3042 u32 phy_addr = 0; 3043 u32 i; 3044 enum e1000_phy_type phy_type = e1000_phy_unknown; 3045 3046 hw->phy.id = phy_type; 3047 3048 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 3049 hw->phy.addr = phy_addr; 3050 i = 0; 3051 3052 do { 3053 e1000_get_phy_id(hw); 3054 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 3055 3056 /* If phy_type is valid, break - we found our 3057 * PHY address 3058 */ 3059 if (phy_type != e1000_phy_unknown) 3060 return E1000_SUCCESS; 3061 3062 msec_delay(1); 3063 i++; 3064 } while (i < 10); 3065 } 3066 3067 return -E1000_ERR_PHY_TYPE; 3068 } 3069 3070 /** 3071 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 3072 * @page: page to access 3073 * 3074 * Returns the phy address for the page requested. 3075 **/ 3076 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 3077 { 3078 u32 phy_addr = 2; 3079 3080 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 3081 phy_addr = 1; 3082 3083 return phy_addr; 3084 } 3085 3086 /** 3087 * e1000_write_phy_reg_bm - Write BM PHY register 3088 * @hw: pointer to the HW structure 3089 * @offset: register offset to write to 3090 * @data: data to write at register offset 3091 * 3092 * Acquires semaphore, if necessary, then writes the data to PHY register 3093 * at the offset. Release any acquired semaphores before exiting. 3094 **/ 3095 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 3096 { 3097 s32 ret_val; 3098 u32 page = offset >> IGP_PAGE_SHIFT; 3099 3100 DEBUGFUNC("e1000_write_phy_reg_bm"); 3101 3102 ret_val = hw->phy.ops.acquire(hw); 3103 if (ret_val) 3104 return ret_val; 3105 3106 /* Page 800 works differently than the rest so it has its own func */ 3107 if (page == BM_WUC_PAGE) { 3108 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3109 FALSE, FALSE); 3110 goto release; 3111 } 3112 3113 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3114 3115 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3116 u32 page_shift, page_select; 3117 3118 /* Page select is register 31 for phy address 1 and 22 for 3119 * phy address 2 and 3. Page select is shifted only for 3120 * phy address 1. 3121 */ 3122 if (hw->phy.addr == 1) { 3123 page_shift = IGP_PAGE_SHIFT; 3124 page_select = IGP01E1000_PHY_PAGE_SELECT; 3125 } else { 3126 page_shift = 0; 3127 page_select = BM_PHY_PAGE_SELECT; 3128 } 3129 3130 /* Page is shifted left, PHY expects (page x 32) */ 3131 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3132 (page << page_shift)); 3133 if (ret_val) 3134 goto release; 3135 } 3136 3137 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3138 data); 3139 3140 release: 3141 hw->phy.ops.release(hw); 3142 return ret_val; 3143 } 3144 3145 /** 3146 * e1000_read_phy_reg_bm - Read BM PHY register 3147 * @hw: pointer to the HW structure 3148 * @offset: register offset to be read 3149 * @data: pointer to the read data 3150 * 3151 * Acquires semaphore, if necessary, then reads the PHY register at offset 3152 * and storing the retrieved information in data. Release any acquired 3153 * semaphores before exiting. 3154 **/ 3155 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 3156 { 3157 s32 ret_val; 3158 u32 page = offset >> IGP_PAGE_SHIFT; 3159 3160 DEBUGFUNC("e1000_read_phy_reg_bm"); 3161 3162 ret_val = hw->phy.ops.acquire(hw); 3163 if (ret_val) 3164 return ret_val; 3165 3166 /* Page 800 works differently than the rest so it has its own func */ 3167 if (page == BM_WUC_PAGE) { 3168 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3169 TRUE, FALSE); 3170 goto release; 3171 } 3172 3173 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3174 3175 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3176 u32 page_shift, page_select; 3177 3178 /* Page select is register 31 for phy address 1 and 22 for 3179 * phy address 2 and 3. Page select is shifted only for 3180 * phy address 1. 3181 */ 3182 if (hw->phy.addr == 1) { 3183 page_shift = IGP_PAGE_SHIFT; 3184 page_select = IGP01E1000_PHY_PAGE_SELECT; 3185 } else { 3186 page_shift = 0; 3187 page_select = BM_PHY_PAGE_SELECT; 3188 } 3189 3190 /* Page is shifted left, PHY expects (page x 32) */ 3191 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3192 (page << page_shift)); 3193 if (ret_val) 3194 goto release; 3195 } 3196 3197 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3198 data); 3199 release: 3200 hw->phy.ops.release(hw); 3201 return ret_val; 3202 } 3203 3204 /** 3205 * e1000_read_phy_reg_bm2 - Read BM PHY register 3206 * @hw: pointer to the HW structure 3207 * @offset: register offset to be read 3208 * @data: pointer to the read data 3209 * 3210 * Acquires semaphore, if necessary, then reads the PHY register at offset 3211 * and storing the retrieved information in data. Release any acquired 3212 * semaphores before exiting. 3213 **/ 3214 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3215 { 3216 s32 ret_val; 3217 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3218 3219 DEBUGFUNC("e1000_read_phy_reg_bm2"); 3220 3221 ret_val = hw->phy.ops.acquire(hw); 3222 if (ret_val) 3223 return ret_val; 3224 3225 /* Page 800 works differently than the rest so it has its own func */ 3226 if (page == BM_WUC_PAGE) { 3227 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3228 TRUE, FALSE); 3229 goto release; 3230 } 3231 3232 hw->phy.addr = 1; 3233 3234 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3235 /* Page is shifted left, PHY expects (page x 32) */ 3236 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3237 page); 3238 3239 if (ret_val) 3240 goto release; 3241 } 3242 3243 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3244 data); 3245 release: 3246 hw->phy.ops.release(hw); 3247 return ret_val; 3248 } 3249 3250 /** 3251 * e1000_write_phy_reg_bm2 - Write BM PHY register 3252 * @hw: pointer to the HW structure 3253 * @offset: register offset to write to 3254 * @data: data to write at register offset 3255 * 3256 * Acquires semaphore, if necessary, then writes the data to PHY register 3257 * at the offset. Release any acquired semaphores before exiting. 3258 **/ 3259 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3260 { 3261 s32 ret_val; 3262 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3263 3264 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3265 3266 ret_val = hw->phy.ops.acquire(hw); 3267 if (ret_val) 3268 return ret_val; 3269 3270 /* Page 800 works differently than the rest so it has its own func */ 3271 if (page == BM_WUC_PAGE) { 3272 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3273 FALSE, FALSE); 3274 goto release; 3275 } 3276 3277 hw->phy.addr = 1; 3278 3279 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3280 /* Page is shifted left, PHY expects (page x 32) */ 3281 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3282 page); 3283 3284 if (ret_val) 3285 goto release; 3286 } 3287 3288 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3289 data); 3290 3291 release: 3292 hw->phy.ops.release(hw); 3293 return ret_val; 3294 } 3295 3296 /** 3297 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 3298 * @hw: pointer to the HW structure 3299 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 3300 * 3301 * Assumes semaphore already acquired and phy_reg points to a valid memory 3302 * address to store contents of the BM_WUC_ENABLE_REG register. 3303 **/ 3304 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3305 { 3306 s32 ret_val; 3307 u16 temp; 3308 3309 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm"); 3310 3311 if (!phy_reg) 3312 return -E1000_ERR_PARAM; 3313 3314 /* All page select, port ctrl and wakeup registers use phy address 1 */ 3315 hw->phy.addr = 1; 3316 3317 /* Select Port Control Registers page */ 3318 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3319 if (ret_val) { 3320 DEBUGOUT("Could not set Port Control page\n"); 3321 return ret_val; 3322 } 3323 3324 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3325 if (ret_val) { 3326 DEBUGOUT2("Could not read PHY register %d.%d\n", 3327 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3328 return ret_val; 3329 } 3330 3331 /* Enable both PHY wakeup mode and Wakeup register page writes. 3332 * Prevent a power state change by disabling ME and Host PHY wakeup. 3333 */ 3334 temp = *phy_reg; 3335 temp |= BM_WUC_ENABLE_BIT; 3336 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 3337 3338 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 3339 if (ret_val) { 3340 DEBUGOUT2("Could not write PHY register %d.%d\n", 3341 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3342 return ret_val; 3343 } 3344 3345 /* Select Host Wakeup Registers page - caller now able to write 3346 * registers on the Wakeup registers page 3347 */ 3348 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3349 } 3350 3351 /** 3352 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 3353 * @hw: pointer to the HW structure 3354 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 3355 * 3356 * Restore BM_WUC_ENABLE_REG to its original value. 3357 * 3358 * Assumes semaphore already acquired and *phy_reg is the contents of the 3359 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 3360 * caller. 3361 **/ 3362 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3363 { 3364 s32 ret_val; 3365 3366 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); 3367 3368 if (!phy_reg) 3369 return -E1000_ERR_PARAM; 3370 3371 /* Select Port Control Registers page */ 3372 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3373 if (ret_val) { 3374 DEBUGOUT("Could not set Port Control page\n"); 3375 return ret_val; 3376 } 3377 3378 /* Restore 769.17 to its original value */ 3379 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 3380 if (ret_val) 3381 DEBUGOUT2("Could not restore PHY register %d.%d\n", 3382 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3383 3384 return ret_val; 3385 } 3386 3387 /** 3388 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 3389 * @hw: pointer to the HW structure 3390 * @offset: register offset to be read or written 3391 * @data: pointer to the data to read or write 3392 * @read: determines if operation is read or write 3393 * @page_set: BM_WUC_PAGE already set and access enabled 3394 * 3395 * Read the PHY register at offset and store the retrieved information in 3396 * data, or write data to PHY register at offset. Note the procedure to 3397 * access the PHY wakeup registers is different than reading the other PHY 3398 * registers. It works as such: 3399 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 3400 * 2) Set page to 800 for host (801 if we were manageability) 3401 * 3) Write the address using the address opcode (0x11) 3402 * 4) Read or write the data using the data opcode (0x12) 3403 * 5) Restore 769.17.2 to its original value 3404 * 3405 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 3406 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 3407 * 3408 * Assumes semaphore is already acquired. When page_set==TRUE, assumes 3409 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 3410 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 3411 **/ 3412 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3413 u16 *data, bool read, bool page_set) 3414 { 3415 s32 ret_val; 3416 u16 reg = BM_PHY_REG_NUM(offset); 3417 u16 page __unused = BM_PHY_REG_PAGE(offset); 3418 u16 phy_reg = 0; 3419 3420 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3421 3422 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 3423 if ((hw->mac.type == e1000_pchlan) && 3424 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3425 DEBUGOUT1("Attempting to access page %d while gig enabled.\n", 3426 page); 3427 3428 if (!page_set) { 3429 /* Enable access to PHY wakeup registers */ 3430 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3431 if (ret_val) { 3432 DEBUGOUT("Could not enable PHY wakeup reg access\n"); 3433 return ret_val; 3434 } 3435 } 3436 3437 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg); 3438 3439 /* Write the Wakeup register page offset value using opcode 0x11 */ 3440 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3441 if (ret_val) { 3442 DEBUGOUT1("Could not write address opcode to page %d\n", page); 3443 return ret_val; 3444 } 3445 3446 if (read) { 3447 /* Read the Wakeup register page value using opcode 0x12 */ 3448 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3449 data); 3450 } else { 3451 /* Write the Wakeup register page value using opcode 0x12 */ 3452 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3453 *data); 3454 } 3455 3456 if (ret_val) { 3457 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg); 3458 return ret_val; 3459 } 3460 3461 if (!page_set) 3462 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3463 3464 return ret_val; 3465 } 3466 3467 /** 3468 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3469 * @hw: pointer to the HW structure 3470 * 3471 * In the case of a PHY power down to save power, or to turn off link during a 3472 * driver unload, or wake on lan is not enabled, restore the link to previous 3473 * settings. 3474 **/ 3475 void e1000_power_up_phy_copper(struct e1000_hw *hw) 3476 { 3477 u16 mii_reg = 0; 3478 u16 power_reg = 0; 3479 3480 /* The PHY will retain its settings across a power down/up cycle */ 3481 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3482 mii_reg &= ~MII_CR_POWER_DOWN; 3483 if (hw->phy.type == e1000_phy_i210) { 3484 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3485 power_reg &= ~GS40G_CS_POWER_DOWN; 3486 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3487 } 3488 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3489 } 3490 3491 /** 3492 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3493 * @hw: pointer to the HW structure 3494 * 3495 * In the case of a PHY power down to save power, or to turn off link during a 3496 * driver unload, or wake on lan is not enabled, restore the link to previous 3497 * settings. 3498 **/ 3499 void e1000_power_down_phy_copper(struct e1000_hw *hw) 3500 { 3501 u16 mii_reg = 0; 3502 u16 power_reg = 0; 3503 3504 /* The PHY will retain its settings across a power down/up cycle */ 3505 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3506 mii_reg |= MII_CR_POWER_DOWN; 3507 /* i210 Phy requires an additional bit for power up/down */ 3508 if (hw->phy.type == e1000_phy_i210) { 3509 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3510 power_reg |= GS40G_CS_POWER_DOWN; 3511 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3512 } 3513 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3514 msec_delay(1); 3515 } 3516 3517 /** 3518 * __e1000_read_phy_reg_hv - Read HV PHY register 3519 * @hw: pointer to the HW structure 3520 * @offset: register offset to be read 3521 * @data: pointer to the read data 3522 * @locked: semaphore has already been acquired or not 3523 * 3524 * Acquires semaphore, if necessary, then reads the PHY register at offset 3525 * and stores the retrieved information in data. Release any acquired 3526 * semaphore before exiting. 3527 **/ 3528 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3529 bool locked, bool page_set) 3530 { 3531 s32 ret_val; 3532 u16 page = BM_PHY_REG_PAGE(offset); 3533 u16 reg = BM_PHY_REG_NUM(offset); 3534 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3535 3536 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3537 3538 if (!locked) { 3539 ret_val = hw->phy.ops.acquire(hw); 3540 if (ret_val) 3541 return ret_val; 3542 } 3543 3544 /* Page 800 works differently than the rest so it has its own func */ 3545 if (page == BM_WUC_PAGE) { 3546 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3547 TRUE, page_set); 3548 goto out; 3549 } 3550 3551 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3552 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3553 data, TRUE); 3554 goto out; 3555 } 3556 3557 if (!page_set) { 3558 if (page == HV_INTC_FC_PAGE_START) 3559 page = 0; 3560 3561 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3562 /* Page is shifted left, PHY expects (page x 32) */ 3563 ret_val = e1000_set_page_igp(hw, 3564 (page << IGP_PAGE_SHIFT)); 3565 3566 hw->phy.addr = phy_addr; 3567 3568 if (ret_val) 3569 goto out; 3570 } 3571 } 3572 3573 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3574 page << IGP_PAGE_SHIFT, reg); 3575 3576 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3577 data); 3578 out: 3579 if (!locked) 3580 hw->phy.ops.release(hw); 3581 3582 return ret_val; 3583 } 3584 3585 /** 3586 * e1000_read_phy_reg_hv - Read HV PHY register 3587 * @hw: pointer to the HW structure 3588 * @offset: register offset to be read 3589 * @data: pointer to the read data 3590 * 3591 * Acquires semaphore then reads the PHY register at offset and stores 3592 * the retrieved information in data. Release the acquired semaphore 3593 * before exiting. 3594 **/ 3595 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3596 { 3597 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3598 } 3599 3600 /** 3601 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3602 * @hw: pointer to the HW structure 3603 * @offset: register offset to be read 3604 * @data: pointer to the read data 3605 * 3606 * Reads the PHY register at offset and stores the retrieved information 3607 * in data. Assumes semaphore already acquired. 3608 **/ 3609 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3610 { 3611 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3612 } 3613 3614 /** 3615 * e1000_read_phy_reg_page_hv - Read HV PHY register 3616 * @hw: pointer to the HW structure 3617 * @offset: register offset to write to 3618 * @data: data to write at register offset 3619 * 3620 * Reads the PHY register at offset and stores the retrieved information 3621 * in data. Assumes semaphore already acquired and page already set. 3622 **/ 3623 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3624 { 3625 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, TRUE); 3626 } 3627 3628 /** 3629 * __e1000_write_phy_reg_hv - Write HV PHY register 3630 * @hw: pointer to the HW structure 3631 * @offset: register offset to write to 3632 * @data: data to write at register offset 3633 * @locked: semaphore has already been acquired or not 3634 * 3635 * Acquires semaphore, if necessary, then writes the data to PHY register 3636 * at the offset. Release any acquired semaphores before exiting. 3637 **/ 3638 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3639 bool locked, bool page_set) 3640 { 3641 s32 ret_val; 3642 u16 page = BM_PHY_REG_PAGE(offset); 3643 u16 reg = BM_PHY_REG_NUM(offset); 3644 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3645 3646 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3647 3648 if (!locked) { 3649 ret_val = hw->phy.ops.acquire(hw); 3650 if (ret_val) 3651 return ret_val; 3652 } 3653 3654 /* Page 800 works differently than the rest so it has its own func */ 3655 if (page == BM_WUC_PAGE) { 3656 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3657 FALSE, page_set); 3658 goto out; 3659 } 3660 3661 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3662 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3663 &data, FALSE); 3664 goto out; 3665 } 3666 3667 if (!page_set) { 3668 if (page == HV_INTC_FC_PAGE_START) 3669 page = 0; 3670 3671 /* Workaround MDIO accesses being disabled after entering IEEE 3672 * Power Down (when bit 11 of the PHY Control register is set) 3673 */ 3674 if ((hw->phy.type == e1000_phy_82578) && 3675 (hw->phy.revision >= 1) && 3676 (hw->phy.addr == 2) && 3677 !(MAX_PHY_REG_ADDRESS & reg) && 3678 (data & (1 << 11))) { 3679 u16 data2 = 0x7EFF; 3680 ret_val = e1000_access_phy_debug_regs_hv(hw, 3681 (1 << 6) | 0x3, 3682 &data2, FALSE); 3683 if (ret_val) 3684 goto out; 3685 } 3686 3687 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3688 /* Page is shifted left, PHY expects (page x 32) */ 3689 ret_val = e1000_set_page_igp(hw, 3690 (page << IGP_PAGE_SHIFT)); 3691 3692 hw->phy.addr = phy_addr; 3693 3694 if (ret_val) 3695 goto out; 3696 } 3697 } 3698 3699 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3700 page << IGP_PAGE_SHIFT, reg); 3701 3702 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3703 data); 3704 3705 out: 3706 if (!locked) 3707 hw->phy.ops.release(hw); 3708 3709 return ret_val; 3710 } 3711 3712 /** 3713 * e1000_write_phy_reg_hv - Write HV PHY register 3714 * @hw: pointer to the HW structure 3715 * @offset: register offset to write to 3716 * @data: data to write at register offset 3717 * 3718 * Acquires semaphore then writes the data to PHY register at the offset. 3719 * Release the acquired semaphores before exiting. 3720 **/ 3721 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3722 { 3723 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3724 } 3725 3726 /** 3727 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3728 * @hw: pointer to the HW structure 3729 * @offset: register offset to write to 3730 * @data: data to write at register offset 3731 * 3732 * Writes the data to PHY register at the offset. Assumes semaphore 3733 * already acquired. 3734 **/ 3735 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3736 { 3737 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3738 } 3739 3740 /** 3741 * e1000_write_phy_reg_page_hv - Write HV PHY register 3742 * @hw: pointer to the HW structure 3743 * @offset: register offset to write to 3744 * @data: data to write at register offset 3745 * 3746 * Writes the data to PHY register at the offset. Assumes semaphore 3747 * already acquired and page already set. 3748 **/ 3749 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3750 { 3751 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, TRUE); 3752 } 3753 3754 /** 3755 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3756 * @page: page to be accessed 3757 **/ 3758 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3759 { 3760 u32 phy_addr = 2; 3761 3762 if (page >= HV_INTC_FC_PAGE_START) 3763 phy_addr = 1; 3764 3765 return phy_addr; 3766 } 3767 3768 /** 3769 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3770 * @hw: pointer to the HW structure 3771 * @offset: register offset to be read or written 3772 * @data: pointer to the data to be read or written 3773 * @read: determines if operation is read or write 3774 * 3775 * Reads the PHY register at offset and stores the retreived information 3776 * in data. Assumes semaphore already acquired. Note that the procedure 3777 * to access these regs uses the address port and data port to read/write. 3778 * These accesses done with PHY address 2 and without using pages. 3779 **/ 3780 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3781 u16 *data, bool read) 3782 { 3783 s32 ret_val; 3784 u32 addr_reg; 3785 u32 data_reg; 3786 3787 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3788 3789 /* This takes care of the difference with desktop vs mobile phy */ 3790 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3791 I82578_ADDR_REG : I82577_ADDR_REG; 3792 data_reg = addr_reg + 1; 3793 3794 /* All operations in this function are phy address 2 */ 3795 hw->phy.addr = 2; 3796 3797 /* masking with 0x3F to remove the page from offset */ 3798 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3799 if (ret_val) { 3800 DEBUGOUT("Could not write the Address Offset port register\n"); 3801 return ret_val; 3802 } 3803 3804 /* Read or write the data value next */ 3805 if (read) 3806 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3807 else 3808 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3809 3810 if (ret_val) 3811 DEBUGOUT("Could not access the Data port register\n"); 3812 3813 return ret_val; 3814 } 3815 3816 /** 3817 * e1000_link_stall_workaround_hv - Si workaround 3818 * @hw: pointer to the HW structure 3819 * 3820 * This function works around a Si bug where the link partner can get 3821 * a link up indication before the PHY does. If small packets are sent 3822 * by the link partner they can be placed in the packet buffer without 3823 * being properly accounted for by the PHY and will stall preventing 3824 * further packets from being received. The workaround is to clear the 3825 * packet buffer after the PHY detects link up. 3826 **/ 3827 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3828 { 3829 s32 ret_val = E1000_SUCCESS; 3830 u16 data; 3831 3832 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3833 3834 if (hw->phy.type != e1000_phy_82578) 3835 return E1000_SUCCESS; 3836 3837 /* Do not apply workaround if in PHY loopback bit 14 set */ 3838 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3839 if (data & PHY_CONTROL_LB) 3840 return E1000_SUCCESS; 3841 3842 /* check if link is up and at 1Gbps */ 3843 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3844 if (ret_val) 3845 return ret_val; 3846 3847 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3848 BM_CS_STATUS_SPEED_MASK; 3849 3850 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3851 BM_CS_STATUS_SPEED_1000)) 3852 return E1000_SUCCESS; 3853 3854 msec_delay(200); 3855 3856 /* flush the packets in the fifo buffer */ 3857 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3858 (HV_MUX_DATA_CTRL_GEN_TO_MAC | 3859 HV_MUX_DATA_CTRL_FORCE_SPEED)); 3860 if (ret_val) 3861 return ret_val; 3862 3863 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3864 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3865 } 3866 3867 /** 3868 * e1000_check_polarity_82577 - Checks the polarity. 3869 * @hw: pointer to the HW structure 3870 * 3871 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3872 * 3873 * Polarity is determined based on the PHY specific status register. 3874 **/ 3875 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3876 { 3877 struct e1000_phy_info *phy = &hw->phy; 3878 s32 ret_val; 3879 u16 data; 3880 3881 DEBUGFUNC("e1000_check_polarity_82577"); 3882 3883 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3884 3885 if (!ret_val) 3886 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) 3887 ? e1000_rev_polarity_reversed 3888 : e1000_rev_polarity_normal); 3889 3890 return ret_val; 3891 } 3892 3893 /** 3894 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3895 * @hw: pointer to the HW structure 3896 * 3897 * Calls the PHY setup function to force speed and duplex. 3898 **/ 3899 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3900 { 3901 struct e1000_phy_info *phy = &hw->phy; 3902 s32 ret_val; 3903 u16 phy_data; 3904 bool link; 3905 3906 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3907 3908 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3909 if (ret_val) 3910 return ret_val; 3911 3912 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3913 3914 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3915 if (ret_val) 3916 return ret_val; 3917 3918 usec_delay(1); 3919 3920 if (phy->autoneg_wait_to_complete) { 3921 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3922 3923 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3924 100000, &link); 3925 if (ret_val) 3926 return ret_val; 3927 3928 if (!link) 3929 DEBUGOUT("Link taking longer than expected.\n"); 3930 3931 /* Try once more */ 3932 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3933 100000, &link); 3934 } 3935 3936 return ret_val; 3937 } 3938 3939 /** 3940 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3941 * @hw: pointer to the HW structure 3942 * 3943 * Read PHY status to determine if link is up. If link is up, then 3944 * set/determine 10base-T extended distance and polarity correction. Read 3945 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3946 * determine on the cable length, local and remote receiver. 3947 **/ 3948 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3949 { 3950 struct e1000_phy_info *phy = &hw->phy; 3951 s32 ret_val; 3952 u16 data; 3953 bool link; 3954 3955 DEBUGFUNC("e1000_get_phy_info_82577"); 3956 3957 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3958 if (ret_val) 3959 return ret_val; 3960 3961 if (!link) { 3962 DEBUGOUT("Phy info is only valid if link is up\n"); 3963 return -E1000_ERR_CONFIG; 3964 } 3965 3966 phy->polarity_correction = TRUE; 3967 3968 ret_val = e1000_check_polarity_82577(hw); 3969 if (ret_val) 3970 return ret_val; 3971 3972 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3973 if (ret_val) 3974 return ret_val; 3975 3976 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3977 3978 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3979 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3980 ret_val = hw->phy.ops.get_cable_length(hw); 3981 if (ret_val) 3982 return ret_val; 3983 3984 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3985 if (ret_val) 3986 return ret_val; 3987 3988 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3989 ? e1000_1000t_rx_status_ok 3990 : e1000_1000t_rx_status_not_ok; 3991 3992 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3993 ? e1000_1000t_rx_status_ok 3994 : e1000_1000t_rx_status_not_ok; 3995 } else { 3996 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3997 phy->local_rx = e1000_1000t_rx_status_undefined; 3998 phy->remote_rx = e1000_1000t_rx_status_undefined; 3999 } 4000 4001 return E1000_SUCCESS; 4002 } 4003 4004 /** 4005 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 4006 * @hw: pointer to the HW structure 4007 * 4008 * Reads the diagnostic status register and verifies result is valid before 4009 * placing it in the phy_cable_length field. 4010 **/ 4011 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 4012 { 4013 struct e1000_phy_info *phy = &hw->phy; 4014 s32 ret_val; 4015 u16 phy_data, length; 4016 4017 DEBUGFUNC("e1000_get_cable_length_82577"); 4018 4019 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 4020 if (ret_val) 4021 return ret_val; 4022 4023 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 4024 I82577_DSTATUS_CABLE_LENGTH_SHIFT); 4025 4026 if (length == E1000_CABLE_LENGTH_UNDEFINED) 4027 return -E1000_ERR_PHY; 4028 4029 phy->cable_length = length; 4030 4031 return E1000_SUCCESS; 4032 } 4033 4034 /** 4035 * e1000_write_phy_reg_gs40g - Write GS40G PHY register 4036 * @hw: pointer to the HW structure 4037 * @offset: register offset to write to 4038 * @data: data to write at register offset 4039 * 4040 * Acquires semaphore, if necessary, then writes the data to PHY register 4041 * at the offset. Release any acquired semaphores before exiting. 4042 **/ 4043 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 4044 { 4045 s32 ret_val; 4046 u16 page = offset >> GS40G_PAGE_SHIFT; 4047 4048 DEBUGFUNC("e1000_write_phy_reg_gs40g"); 4049 4050 offset = offset & GS40G_OFFSET_MASK; 4051 ret_val = hw->phy.ops.acquire(hw); 4052 if (ret_val) 4053 return ret_val; 4054 4055 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4056 if (ret_val) 4057 goto release; 4058 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 4059 4060 release: 4061 hw->phy.ops.release(hw); 4062 return ret_val; 4063 } 4064 4065 /** 4066 * e1000_read_phy_reg_gs40g - Read GS40G PHY register 4067 * @hw: pointer to the HW structure 4068 * @offset: lower half is register offset to read to 4069 * upper half is page to use. 4070 * @data: data to read at register offset 4071 * 4072 * Acquires semaphore, if necessary, then reads the data in the PHY register 4073 * at the offset. Release any acquired semaphores before exiting. 4074 **/ 4075 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 4076 { 4077 s32 ret_val; 4078 u16 page = offset >> GS40G_PAGE_SHIFT; 4079 4080 DEBUGFUNC("e1000_read_phy_reg_gs40g"); 4081 4082 offset = offset & GS40G_OFFSET_MASK; 4083 ret_val = hw->phy.ops.acquire(hw); 4084 if (ret_val) 4085 return ret_val; 4086 4087 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4088 if (ret_val) 4089 goto release; 4090 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 4091 4092 release: 4093 hw->phy.ops.release(hw); 4094 return ret_val; 4095 } 4096 4097 /** 4098 * e1000_read_phy_reg_mphy - Read mPHY control register 4099 * @hw: pointer to the HW structure 4100 * @address: address to be read 4101 * @data: pointer to the read data 4102 * 4103 * Reads the mPHY control register in the PHY at offset and stores the 4104 * information read to data. 4105 **/ 4106 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data) 4107 { 4108 u32 mphy_ctrl = 0; 4109 bool locked = FALSE; 4110 bool ready = FALSE; 4111 4112 DEBUGFUNC("e1000_read_phy_reg_mphy"); 4113 4114 /* Check if mPHY is ready to read/write operations */ 4115 ready = e1000_is_mphy_ready(hw); 4116 if (!ready) 4117 return -E1000_ERR_PHY; 4118 4119 /* Check if mPHY access is disabled and enable it if so */ 4120 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4121 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4122 locked = TRUE; 4123 ready = e1000_is_mphy_ready(hw); 4124 if (!ready) 4125 return -E1000_ERR_PHY; 4126 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4127 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4128 } 4129 4130 /* Set the address that we want to read */ 4131 ready = e1000_is_mphy_ready(hw); 4132 if (!ready) 4133 return -E1000_ERR_PHY; 4134 mphy_ctrl |= (address & E1000_MPHY_ADDRESS_MASK); 4135 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4136 4137 /* Read data from the address */ 4138 ready = e1000_is_mphy_ready(hw); 4139 if (!ready) 4140 return -E1000_ERR_PHY; 4141 *data = E1000_READ_REG(hw, E1000_MPHY_DATA); 4142 4143 /* Disable access to mPHY if it was originally disabled */ 4144 if (locked) { 4145 ready = e1000_is_mphy_ready(hw); 4146 if (!ready) 4147 return -E1000_ERR_PHY; 4148 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4149 E1000_MPHY_DIS_ACCESS); 4150 } 4151 4152 return E1000_SUCCESS; 4153 } 4154 4155 /** 4156 * e1000_write_phy_reg_mphy - Write mPHY control register 4157 * @hw: pointer to the HW structure 4158 * @address: address to write to 4159 * @data: data to write to register at offset 4160 * 4161 * Writes data to mPHY control register. 4162 **/ 4163 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data) 4164 { 4165 u32 mphy_ctrl = 0; 4166 bool locked = FALSE; 4167 bool ready = FALSE; 4168 4169 DEBUGFUNC("e1000_write_phy_reg_mphy"); 4170 4171 /* Check if mPHY is ready to read/write operations */ 4172 ready = e1000_is_mphy_ready(hw); 4173 if (!ready) 4174 return -E1000_ERR_PHY; 4175 4176 /* Check if mPHY access is disabled and enable it if so */ 4177 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4178 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4179 locked = TRUE; 4180 ready = e1000_is_mphy_ready(hw); 4181 if (!ready) 4182 return -E1000_ERR_PHY; 4183 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4184 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4185 } 4186 4187 /* Set the address that we want to read */ 4188 ready = e1000_is_mphy_ready(hw); 4189 if (!ready) 4190 return -E1000_ERR_PHY; 4191 mphy_ctrl |= (address & E1000_MPHY_ADDRESS_MASK); 4192 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4193 4194 /* Read data from the address */ 4195 ready = e1000_is_mphy_ready(hw); 4196 if (!ready) 4197 return -E1000_ERR_PHY; 4198 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data); 4199 4200 /* Disable access to mPHY if it was originally disabled */ 4201 if (locked) { 4202 ready = e1000_is_mphy_ready(hw); 4203 if (!ready) 4204 return -E1000_ERR_PHY; 4205 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4206 E1000_MPHY_DIS_ACCESS); 4207 } 4208 4209 return E1000_SUCCESS; 4210 } 4211 4212 /** 4213 * e1000_is_mphy_ready - Check if mPHY control register is not busy 4214 * @hw: pointer to the HW structure 4215 * 4216 * Returns mPHY control register status. 4217 **/ 4218 bool e1000_is_mphy_ready(struct e1000_hw *hw) 4219 { 4220 u16 retry_count = 0; 4221 u32 mphy_ctrl = 0; 4222 bool ready = FALSE; 4223 4224 while (retry_count < 2) { 4225 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4226 if (mphy_ctrl & E1000_MPHY_BUSY) { 4227 usec_delay(20); 4228 retry_count++; 4229 continue; 4230 } 4231 ready = TRUE; 4232 break; 4233 } 4234 4235 if (!ready) 4236 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n"); 4237 4238 return ready; 4239 } 4240