1 /****************************************************************************** 2 3 Copyright (c) 2001-2019, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static s32 e1000_wait_autoneg(struct e1000_hw *hw); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read, bool page_set); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51 static const u16 e1000_igp_2_cable_length_table[] = { 52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 59 124}; 60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64 /** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.set_page = e1000_null_set_page; 86 phy->ops.read_reg = e1000_null_read_reg; 87 phy->ops.read_reg_locked = e1000_null_read_reg; 88 phy->ops.read_reg_page = e1000_null_read_reg; 89 phy->ops.release = e1000_null_phy_generic; 90 phy->ops.reset = e1000_null_ops_generic; 91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 93 phy->ops.write_reg = e1000_null_write_reg; 94 phy->ops.write_reg_locked = e1000_null_write_reg; 95 phy->ops.write_reg_page = e1000_null_write_reg; 96 phy->ops.power_up = e1000_null_phy_generic; 97 phy->ops.power_down = e1000_null_phy_generic; 98 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 99 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null; 100 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null; 101 } 102 103 /** 104 * e1000_null_set_page - No-op function, return 0 105 * @hw: pointer to the HW structure 106 * @data: dummy variable 107 **/ 108 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw, 109 u16 E1000_UNUSEDARG data) 110 { 111 DEBUGFUNC("e1000_null_set_page"); 112 return E1000_SUCCESS; 113 } 114 115 /** 116 * e1000_null_read_reg - No-op function, return 0 117 * @hw: pointer to the HW structure 118 * @offset: dummy variable 119 * @data: dummy variable 120 **/ 121 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw, 122 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data) 123 { 124 DEBUGFUNC("e1000_null_read_reg"); 125 return E1000_SUCCESS; 126 } 127 128 /** 129 * e1000_null_phy_generic - No-op function, return void 130 * @hw: pointer to the HW structure 131 **/ 132 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw) 133 { 134 DEBUGFUNC("e1000_null_phy_generic"); 135 return; 136 } 137 138 /** 139 * e1000_null_lplu_state - No-op function, return 0 140 * @hw: pointer to the HW structure 141 * @active: dummy variable 142 **/ 143 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw, 144 bool E1000_UNUSEDARG active) 145 { 146 DEBUGFUNC("e1000_null_lplu_state"); 147 return E1000_SUCCESS; 148 } 149 150 /** 151 * e1000_null_write_reg - No-op function, return 0 152 * @hw: pointer to the HW structure 153 * @offset: dummy variable 154 * @data: dummy variable 155 **/ 156 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw, 157 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data) 158 { 159 DEBUGFUNC("e1000_null_write_reg"); 160 return E1000_SUCCESS; 161 } 162 163 /** 164 * e1000_read_i2c_byte_null - No-op function, return 0 165 * @hw: pointer to hardware structure 166 * @byte_offset: byte offset to write 167 * @dev_addr: device address 168 * @data: data value read 169 * 170 **/ 171 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 172 u8 E1000_UNUSEDARG byte_offset, 173 u8 E1000_UNUSEDARG dev_addr, 174 u8 E1000_UNUSEDARG *data) 175 { 176 DEBUGFUNC("e1000_read_i2c_byte_null"); 177 return E1000_SUCCESS; 178 } 179 180 /** 181 * e1000_write_i2c_byte_null - No-op function, return 0 182 * @hw: pointer to hardware structure 183 * @byte_offset: byte offset to write 184 * @dev_addr: device address 185 * @data: data value to write 186 * 187 **/ 188 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 189 u8 E1000_UNUSEDARG byte_offset, 190 u8 E1000_UNUSEDARG dev_addr, 191 u8 E1000_UNUSEDARG data) 192 { 193 DEBUGFUNC("e1000_write_i2c_byte_null"); 194 return E1000_SUCCESS; 195 } 196 197 /** 198 * e1000_check_reset_block_generic - Check if PHY reset is blocked 199 * @hw: pointer to the HW structure 200 * 201 * Read the PHY management control register and check whether a PHY reset 202 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 203 * return E1000_BLK_PHY_RESET (12). 204 **/ 205 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 206 { 207 u32 manc; 208 209 DEBUGFUNC("e1000_check_reset_block"); 210 211 manc = E1000_READ_REG(hw, E1000_MANC); 212 213 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 214 E1000_BLK_PHY_RESET : E1000_SUCCESS; 215 } 216 217 /** 218 * e1000_get_phy_id - Retrieve the PHY ID and revision 219 * @hw: pointer to the HW structure 220 * 221 * Reads the PHY registers and stores the PHY ID and possibly the PHY 222 * revision in the hardware structure. 223 **/ 224 s32 e1000_get_phy_id(struct e1000_hw *hw) 225 { 226 struct e1000_phy_info *phy = &hw->phy; 227 s32 ret_val = E1000_SUCCESS; 228 u16 phy_id; 229 u16 retry_count = 0; 230 231 DEBUGFUNC("e1000_get_phy_id"); 232 233 if (!phy->ops.read_reg) 234 return E1000_SUCCESS; 235 236 while (retry_count < 2) { 237 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 238 if (ret_val) 239 return ret_val; 240 241 phy->id = (u32)(phy_id << 16); 242 usec_delay(20); 243 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 244 if (ret_val) 245 return ret_val; 246 247 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 248 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 249 250 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 251 return E1000_SUCCESS; 252 253 retry_count++; 254 } 255 256 return E1000_SUCCESS; 257 } 258 259 /** 260 * e1000_phy_reset_dsp_generic - Reset PHY DSP 261 * @hw: pointer to the HW structure 262 * 263 * Reset the digital signal processor. 264 **/ 265 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 266 { 267 s32 ret_val; 268 269 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 270 271 if (!hw->phy.ops.write_reg) 272 return E1000_SUCCESS; 273 274 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 275 if (ret_val) 276 return ret_val; 277 278 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 279 } 280 281 /** 282 * e1000_read_phy_reg_mdic - Read MDI control register 283 * @hw: pointer to the HW structure 284 * @offset: register offset to be read 285 * @data: pointer to the read data 286 * 287 * Reads the MDI control register in the PHY at offset and stores the 288 * information read to data. 289 **/ 290 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 291 { 292 struct e1000_phy_info *phy = &hw->phy; 293 u32 i, mdic = 0; 294 295 DEBUGFUNC("e1000_read_phy_reg_mdic"); 296 297 if (offset > MAX_PHY_REG_ADDRESS) { 298 DEBUGOUT1("PHY Address %d is out of range\n", offset); 299 return -E1000_ERR_PARAM; 300 } 301 302 /* Set up Op-code, Phy Address, and register offset in the MDI 303 * Control register. The MAC will take care of interfacing with the 304 * PHY to retrieve the desired data. 305 */ 306 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 307 (phy->addr << E1000_MDIC_PHY_SHIFT) | 308 (E1000_MDIC_OP_READ)); 309 310 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 311 312 /* Poll the ready bit to see if the MDI read completed 313 * Increasing the time out as testing showed failures with 314 * the lower time out 315 */ 316 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 317 usec_delay_irq(50); 318 mdic = E1000_READ_REG(hw, E1000_MDIC); 319 if (mdic & E1000_MDIC_READY) 320 break; 321 } 322 if (!(mdic & E1000_MDIC_READY)) { 323 DEBUGOUT("MDI Read did not complete\n"); 324 return -E1000_ERR_PHY; 325 } 326 if (mdic & E1000_MDIC_ERROR) { 327 DEBUGOUT("MDI Error\n"); 328 return -E1000_ERR_PHY; 329 } 330 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 331 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 332 offset, 333 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 334 return -E1000_ERR_PHY; 335 } 336 *data = (u16) mdic; 337 338 /* Allow some time after each MDIC transaction to avoid 339 * reading duplicate data in the next MDIC transaction. 340 */ 341 if (hw->mac.type == e1000_pch2lan) 342 usec_delay_irq(100); 343 344 return E1000_SUCCESS; 345 } 346 347 /** 348 * e1000_write_phy_reg_mdic - Write MDI control register 349 * @hw: pointer to the HW structure 350 * @offset: register offset to write to 351 * @data: data to write to register at offset 352 * 353 * Writes data to MDI control register in the PHY at offset. 354 **/ 355 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 356 { 357 struct e1000_phy_info *phy = &hw->phy; 358 u32 i, mdic = 0; 359 360 DEBUGFUNC("e1000_write_phy_reg_mdic"); 361 362 if (offset > MAX_PHY_REG_ADDRESS) { 363 DEBUGOUT1("PHY Address %d is out of range\n", offset); 364 return -E1000_ERR_PARAM; 365 } 366 367 /* Set up Op-code, Phy Address, and register offset in the MDI 368 * Control register. The MAC will take care of interfacing with the 369 * PHY to retrieve the desired data. 370 */ 371 mdic = (((u32)data) | 372 (offset << E1000_MDIC_REG_SHIFT) | 373 (phy->addr << E1000_MDIC_PHY_SHIFT) | 374 (E1000_MDIC_OP_WRITE)); 375 376 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 377 378 /* Poll the ready bit to see if the MDI read completed 379 * Increasing the time out as testing showed failures with 380 * the lower time out 381 */ 382 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 383 usec_delay_irq(50); 384 mdic = E1000_READ_REG(hw, E1000_MDIC); 385 if (mdic & E1000_MDIC_READY) 386 break; 387 } 388 if (!(mdic & E1000_MDIC_READY)) { 389 DEBUGOUT("MDI Write did not complete\n"); 390 return -E1000_ERR_PHY; 391 } 392 if (mdic & E1000_MDIC_ERROR) { 393 DEBUGOUT("MDI Error\n"); 394 return -E1000_ERR_PHY; 395 } 396 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 397 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", 398 offset, 399 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 400 return -E1000_ERR_PHY; 401 } 402 403 /* Allow some time after each MDIC transaction to avoid 404 * reading duplicate data in the next MDIC transaction. 405 */ 406 if (hw->mac.type == e1000_pch2lan) 407 usec_delay_irq(100); 408 409 return E1000_SUCCESS; 410 } 411 412 /** 413 * e1000_read_phy_reg_i2c - Read PHY register using i2c 414 * @hw: pointer to the HW structure 415 * @offset: register offset to be read 416 * @data: pointer to the read data 417 * 418 * Reads the PHY register at offset using the i2c interface and stores the 419 * retrieved information in data. 420 **/ 421 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 422 { 423 struct e1000_phy_info *phy = &hw->phy; 424 u32 i, i2ccmd = 0; 425 426 DEBUGFUNC("e1000_read_phy_reg_i2c"); 427 428 /* Set up Op-code, Phy Address, and register address in the I2CCMD 429 * register. The MAC will take care of interfacing with the 430 * PHY to retrieve the desired data. 431 */ 432 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 433 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 434 (E1000_I2CCMD_OPCODE_READ)); 435 436 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 437 438 /* Poll the ready bit to see if the I2C read completed */ 439 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 440 usec_delay(50); 441 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 442 if (i2ccmd & E1000_I2CCMD_READY) 443 break; 444 } 445 if (!(i2ccmd & E1000_I2CCMD_READY)) { 446 DEBUGOUT("I2CCMD Read did not complete\n"); 447 return -E1000_ERR_PHY; 448 } 449 if (i2ccmd & E1000_I2CCMD_ERROR) { 450 DEBUGOUT("I2CCMD Error bit set\n"); 451 return -E1000_ERR_PHY; 452 } 453 454 /* Need to byte-swap the 16-bit value. */ 455 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 456 457 return E1000_SUCCESS; 458 } 459 460 /** 461 * e1000_write_phy_reg_i2c - Write PHY register using i2c 462 * @hw: pointer to the HW structure 463 * @offset: register offset to write to 464 * @data: data to write at register offset 465 * 466 * Writes the data to PHY register at the offset using the i2c interface. 467 **/ 468 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 469 { 470 struct e1000_phy_info *phy = &hw->phy; 471 u32 i, i2ccmd = 0; 472 u16 phy_data_swapped; 473 474 DEBUGFUNC("e1000_write_phy_reg_i2c"); 475 476 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 477 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 478 DEBUGOUT1("PHY I2C Address %d is out of range.\n", 479 hw->phy.addr); 480 return -E1000_ERR_CONFIG; 481 } 482 483 /* Swap the data bytes for the I2C interface */ 484 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 485 486 /* Set up Op-code, Phy Address, and register address in the I2CCMD 487 * register. The MAC will take care of interfacing with the 488 * PHY to retrieve the desired data. 489 */ 490 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 491 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 492 E1000_I2CCMD_OPCODE_WRITE | 493 phy_data_swapped); 494 495 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 496 497 /* Poll the ready bit to see if the I2C read completed */ 498 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 499 usec_delay(50); 500 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 501 if (i2ccmd & E1000_I2CCMD_READY) 502 break; 503 } 504 if (!(i2ccmd & E1000_I2CCMD_READY)) { 505 DEBUGOUT("I2CCMD Write did not complete\n"); 506 return -E1000_ERR_PHY; 507 } 508 if (i2ccmd & E1000_I2CCMD_ERROR) { 509 DEBUGOUT("I2CCMD Error bit set\n"); 510 return -E1000_ERR_PHY; 511 } 512 513 return E1000_SUCCESS; 514 } 515 516 /** 517 * e1000_read_sfp_data_byte - Reads SFP module data. 518 * @hw: pointer to the HW structure 519 * @offset: byte location offset to be read 520 * @data: read data buffer pointer 521 * 522 * Reads one byte from SFP module data stored 523 * in SFP resided EEPROM memory or SFP diagnostic area. 524 * Function should be called with 525 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 526 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 527 * access 528 **/ 529 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 530 { 531 u32 i = 0; 532 u32 i2ccmd = 0; 533 u32 data_local = 0; 534 535 DEBUGFUNC("e1000_read_sfp_data_byte"); 536 537 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 538 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 539 return -E1000_ERR_PHY; 540 } 541 542 /* Set up Op-code, EEPROM Address,in the I2CCMD 543 * register. The MAC will take care of interfacing with the 544 * EEPROM to retrieve the desired data. 545 */ 546 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 547 E1000_I2CCMD_OPCODE_READ); 548 549 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 550 551 /* Poll the ready bit to see if the I2C read completed */ 552 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 553 usec_delay(50); 554 data_local = E1000_READ_REG(hw, E1000_I2CCMD); 555 if (data_local & E1000_I2CCMD_READY) 556 break; 557 } 558 if (!(data_local & E1000_I2CCMD_READY)) { 559 DEBUGOUT("I2CCMD Read did not complete\n"); 560 return -E1000_ERR_PHY; 561 } 562 if (data_local & E1000_I2CCMD_ERROR) { 563 DEBUGOUT("I2CCMD Error bit set\n"); 564 return -E1000_ERR_PHY; 565 } 566 *data = (u8) data_local & 0xFF; 567 568 return E1000_SUCCESS; 569 } 570 571 /** 572 * e1000_write_sfp_data_byte - Writes SFP module data. 573 * @hw: pointer to the HW structure 574 * @offset: byte location offset to write to 575 * @data: data to write 576 * 577 * Writes one byte to SFP module data stored 578 * in SFP resided EEPROM memory or SFP diagnostic area. 579 * Function should be called with 580 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 581 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 582 * access 583 **/ 584 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 585 { 586 u32 i = 0; 587 u32 i2ccmd = 0; 588 u32 data_local = 0; 589 590 DEBUGFUNC("e1000_write_sfp_data_byte"); 591 592 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 593 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 594 return -E1000_ERR_PHY; 595 } 596 /* The programming interface is 16 bits wide 597 * so we need to read the whole word first 598 * then update appropriate byte lane and write 599 * the updated word back. 600 */ 601 /* Set up Op-code, EEPROM Address,in the I2CCMD 602 * register. The MAC will take care of interfacing 603 * with an EEPROM to write the data given. 604 */ 605 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 606 E1000_I2CCMD_OPCODE_READ); 607 /* Set a command to read single word */ 608 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 609 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 610 usec_delay(50); 611 /* Poll the ready bit to see if lastly 612 * launched I2C operation completed 613 */ 614 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 615 if (i2ccmd & E1000_I2CCMD_READY) { 616 /* Check if this is READ or WRITE phase */ 617 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 618 E1000_I2CCMD_OPCODE_READ) { 619 /* Write the selected byte 620 * lane and update whole word 621 */ 622 data_local = i2ccmd & 0xFF00; 623 data_local |= data; 624 i2ccmd = ((offset << 625 E1000_I2CCMD_REG_ADDR_SHIFT) | 626 E1000_I2CCMD_OPCODE_WRITE | data_local); 627 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 628 } else { 629 break; 630 } 631 } 632 } 633 if (!(i2ccmd & E1000_I2CCMD_READY)) { 634 DEBUGOUT("I2CCMD Write did not complete\n"); 635 return -E1000_ERR_PHY; 636 } 637 if (i2ccmd & E1000_I2CCMD_ERROR) { 638 DEBUGOUT("I2CCMD Error bit set\n"); 639 return -E1000_ERR_PHY; 640 } 641 return E1000_SUCCESS; 642 } 643 644 /** 645 * e1000_read_phy_reg_m88 - Read m88 PHY register 646 * @hw: pointer to the HW structure 647 * @offset: register offset to be read 648 * @data: pointer to the read data 649 * 650 * Acquires semaphore, if necessary, then reads the PHY register at offset 651 * and storing the retrieved information in data. Release any acquired 652 * semaphores before exiting. 653 **/ 654 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 655 { 656 s32 ret_val; 657 658 DEBUGFUNC("e1000_read_phy_reg_m88"); 659 660 if (!hw->phy.ops.acquire) 661 return E1000_SUCCESS; 662 663 ret_val = hw->phy.ops.acquire(hw); 664 if (ret_val) 665 return ret_val; 666 667 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 668 data); 669 670 hw->phy.ops.release(hw); 671 672 return ret_val; 673 } 674 675 /** 676 * e1000_write_phy_reg_m88 - Write m88 PHY register 677 * @hw: pointer to the HW structure 678 * @offset: register offset to write to 679 * @data: data to write at register offset 680 * 681 * Acquires semaphore, if necessary, then writes the data to PHY register 682 * at the offset. Release any acquired semaphores before exiting. 683 **/ 684 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 685 { 686 s32 ret_val; 687 688 DEBUGFUNC("e1000_write_phy_reg_m88"); 689 690 if (!hw->phy.ops.acquire) 691 return E1000_SUCCESS; 692 693 ret_val = hw->phy.ops.acquire(hw); 694 if (ret_val) 695 return ret_val; 696 697 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 698 data); 699 700 hw->phy.ops.release(hw); 701 702 return ret_val; 703 } 704 705 /** 706 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 707 * @hw: pointer to the HW structure 708 * @page: page to set (shifted left when necessary) 709 * 710 * Sets PHY page required for PHY register access. Assumes semaphore is 711 * already acquired. Note, this function sets phy.addr to 1 so the caller 712 * must set it appropriately (if necessary) after this function returns. 713 **/ 714 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 715 { 716 DEBUGFUNC("e1000_set_page_igp"); 717 718 DEBUGOUT1("Setting page 0x%x\n", page); 719 720 hw->phy.addr = 1; 721 722 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 723 } 724 725 /** 726 * __e1000_read_phy_reg_igp - Read igp PHY register 727 * @hw: pointer to the HW structure 728 * @offset: register offset to be read 729 * @data: pointer to the read data 730 * @locked: semaphore has already been acquired or not 731 * 732 * Acquires semaphore, if necessary, then reads the PHY register at offset 733 * and stores the retrieved information in data. Release any acquired 734 * semaphores before exiting. 735 **/ 736 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 737 bool locked) 738 { 739 s32 ret_val = E1000_SUCCESS; 740 741 DEBUGFUNC("__e1000_read_phy_reg_igp"); 742 743 if (!locked) { 744 if (!hw->phy.ops.acquire) 745 return E1000_SUCCESS; 746 747 ret_val = hw->phy.ops.acquire(hw); 748 if (ret_val) 749 return ret_val; 750 } 751 752 if (offset > MAX_PHY_MULTI_PAGE_REG) 753 ret_val = e1000_write_phy_reg_mdic(hw, 754 IGP01E1000_PHY_PAGE_SELECT, 755 (u16)offset); 756 if (!ret_val) 757 ret_val = e1000_read_phy_reg_mdic(hw, 758 MAX_PHY_REG_ADDRESS & offset, 759 data); 760 if (!locked) 761 hw->phy.ops.release(hw); 762 763 return ret_val; 764 } 765 766 /** 767 * e1000_read_phy_reg_igp - Read igp PHY register 768 * @hw: pointer to the HW structure 769 * @offset: register offset to be read 770 * @data: pointer to the read data 771 * 772 * Acquires semaphore then reads the PHY register at offset and stores the 773 * retrieved information in data. 774 * Release the acquired semaphore before exiting. 775 **/ 776 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 777 { 778 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 779 } 780 781 /** 782 * e1000_read_phy_reg_igp_locked - Read igp PHY register 783 * @hw: pointer to the HW structure 784 * @offset: register offset to be read 785 * @data: pointer to the read data 786 * 787 * Reads the PHY register at offset and stores the retrieved information 788 * in data. Assumes semaphore already acquired. 789 **/ 790 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 791 { 792 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 793 } 794 795 /** 796 * e1000_write_phy_reg_igp - Write igp PHY register 797 * @hw: pointer to the HW structure 798 * @offset: register offset to write to 799 * @data: data to write at register offset 800 * @locked: semaphore has already been acquired or not 801 * 802 * Acquires semaphore, if necessary, then writes the data to PHY register 803 * at the offset. Release any acquired semaphores before exiting. 804 **/ 805 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 806 bool locked) 807 { 808 s32 ret_val = E1000_SUCCESS; 809 810 DEBUGFUNC("e1000_write_phy_reg_igp"); 811 812 if (!locked) { 813 if (!hw->phy.ops.acquire) 814 return E1000_SUCCESS; 815 816 ret_val = hw->phy.ops.acquire(hw); 817 if (ret_val) 818 return ret_val; 819 } 820 821 if (offset > MAX_PHY_MULTI_PAGE_REG) 822 ret_val = e1000_write_phy_reg_mdic(hw, 823 IGP01E1000_PHY_PAGE_SELECT, 824 (u16)offset); 825 if (!ret_val) 826 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 827 offset, 828 data); 829 if (!locked) 830 hw->phy.ops.release(hw); 831 832 return ret_val; 833 } 834 835 /** 836 * e1000_write_phy_reg_igp - Write igp PHY register 837 * @hw: pointer to the HW structure 838 * @offset: register offset to write to 839 * @data: data to write at register offset 840 * 841 * Acquires semaphore then writes the data to PHY register 842 * at the offset. Release any acquired semaphores before exiting. 843 **/ 844 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 845 { 846 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 847 } 848 849 /** 850 * e1000_write_phy_reg_igp_locked - Write igp PHY register 851 * @hw: pointer to the HW structure 852 * @offset: register offset to write to 853 * @data: data to write at register offset 854 * 855 * Writes the data to PHY register at the offset. 856 * Assumes semaphore already acquired. 857 **/ 858 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 859 { 860 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 861 } 862 863 /** 864 * __e1000_read_kmrn_reg - Read kumeran register 865 * @hw: pointer to the HW structure 866 * @offset: register offset to be read 867 * @data: pointer to the read data 868 * @locked: semaphore has already been acquired or not 869 * 870 * Acquires semaphore, if necessary. Then reads the PHY register at offset 871 * using the kumeran interface. The information retrieved is stored in data. 872 * Release any acquired semaphores before exiting. 873 **/ 874 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 875 bool locked) 876 { 877 u32 kmrnctrlsta; 878 879 DEBUGFUNC("__e1000_read_kmrn_reg"); 880 881 if (!locked) { 882 s32 ret_val = E1000_SUCCESS; 883 884 if (!hw->phy.ops.acquire) 885 return E1000_SUCCESS; 886 887 ret_val = hw->phy.ops.acquire(hw); 888 if (ret_val) 889 return ret_val; 890 } 891 892 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 893 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 894 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 895 E1000_WRITE_FLUSH(hw); 896 897 usec_delay(2); 898 899 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 900 *data = (u16)kmrnctrlsta; 901 902 if (!locked) 903 hw->phy.ops.release(hw); 904 905 return E1000_SUCCESS; 906 } 907 908 /** 909 * e1000_read_kmrn_reg_generic - Read kumeran register 910 * @hw: pointer to the HW structure 911 * @offset: register offset to be read 912 * @data: pointer to the read data 913 * 914 * Acquires semaphore then reads the PHY register at offset using the 915 * kumeran interface. The information retrieved is stored in data. 916 * Release the acquired semaphore before exiting. 917 **/ 918 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 919 { 920 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 921 } 922 923 /** 924 * e1000_read_kmrn_reg_locked - Read kumeran register 925 * @hw: pointer to the HW structure 926 * @offset: register offset to be read 927 * @data: pointer to the read data 928 * 929 * Reads the PHY register at offset using the kumeran interface. The 930 * information retrieved is stored in data. 931 * Assumes semaphore already acquired. 932 **/ 933 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 934 { 935 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 936 } 937 938 /** 939 * __e1000_write_kmrn_reg - Write kumeran register 940 * @hw: pointer to the HW structure 941 * @offset: register offset to write to 942 * @data: data to write at register offset 943 * @locked: semaphore has already been acquired or not 944 * 945 * Acquires semaphore, if necessary. Then write the data to PHY register 946 * at the offset using the kumeran interface. Release any acquired semaphores 947 * before exiting. 948 **/ 949 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 950 bool locked) 951 { 952 u32 kmrnctrlsta; 953 954 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 955 956 if (!locked) { 957 s32 ret_val = E1000_SUCCESS; 958 959 if (!hw->phy.ops.acquire) 960 return E1000_SUCCESS; 961 962 ret_val = hw->phy.ops.acquire(hw); 963 if (ret_val) 964 return ret_val; 965 } 966 967 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 968 E1000_KMRNCTRLSTA_OFFSET) | data; 969 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 970 E1000_WRITE_FLUSH(hw); 971 972 usec_delay(2); 973 974 if (!locked) 975 hw->phy.ops.release(hw); 976 977 return E1000_SUCCESS; 978 } 979 980 /** 981 * e1000_write_kmrn_reg_generic - Write kumeran register 982 * @hw: pointer to the HW structure 983 * @offset: register offset to write to 984 * @data: data to write at register offset 985 * 986 * Acquires semaphore then writes the data to the PHY register at the offset 987 * using the kumeran interface. Release the acquired semaphore before exiting. 988 **/ 989 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 990 { 991 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 992 } 993 994 /** 995 * e1000_write_kmrn_reg_locked - Write kumeran register 996 * @hw: pointer to the HW structure 997 * @offset: register offset to write to 998 * @data: data to write at register offset 999 * 1000 * Write the data to PHY register at the offset using the kumeran interface. 1001 * Assumes semaphore already acquired. 1002 **/ 1003 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 1004 { 1005 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 1006 } 1007 1008 /** 1009 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 1010 * @hw: pointer to the HW structure 1011 * 1012 * Sets up Master/slave mode 1013 **/ 1014 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 1015 { 1016 s32 ret_val; 1017 u16 phy_data; 1018 1019 /* Resolve Master/Slave mode */ 1020 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 1021 if (ret_val) 1022 return ret_val; 1023 1024 /* load defaults for future use */ 1025 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 1026 ((phy_data & CR_1000T_MS_VALUE) ? 1027 e1000_ms_force_master : 1028 e1000_ms_force_slave) : e1000_ms_auto; 1029 1030 switch (hw->phy.ms_type) { 1031 case e1000_ms_force_master: 1032 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1033 break; 1034 case e1000_ms_force_slave: 1035 phy_data |= CR_1000T_MS_ENABLE; 1036 phy_data &= ~(CR_1000T_MS_VALUE); 1037 break; 1038 case e1000_ms_auto: 1039 phy_data &= ~CR_1000T_MS_ENABLE; 1040 /* fall-through */ 1041 default: 1042 break; 1043 } 1044 1045 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 1046 } 1047 1048 /** 1049 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 1050 * @hw: pointer to the HW structure 1051 * 1052 * Sets up Carrier-sense on Transmit and downshift values. 1053 **/ 1054 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 1055 { 1056 s32 ret_val; 1057 u16 phy_data; 1058 1059 DEBUGFUNC("e1000_copper_link_setup_82577"); 1060 1061 if (hw->phy.type == e1000_phy_82580) { 1062 ret_val = hw->phy.ops.reset(hw); 1063 if (ret_val) { 1064 DEBUGOUT("Error resetting the PHY.\n"); 1065 return ret_val; 1066 } 1067 } 1068 1069 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1070 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 1071 if (ret_val) 1072 return ret_val; 1073 1074 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 1075 1076 /* Enable downshift */ 1077 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 1078 1079 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 1080 if (ret_val) 1081 return ret_val; 1082 1083 /* Set MDI/MDIX mode */ 1084 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 1085 if (ret_val) 1086 return ret_val; 1087 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 1088 /* Options: 1089 * 0 - Auto (default) 1090 * 1 - MDI mode 1091 * 2 - MDI-X mode 1092 */ 1093 switch (hw->phy.mdix) { 1094 case 1: 1095 break; 1096 case 2: 1097 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 1098 break; 1099 case 0: 1100 default: 1101 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 1102 break; 1103 } 1104 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 1105 if (ret_val) 1106 return ret_val; 1107 1108 return e1000_set_master_slave_mode(hw); 1109 } 1110 1111 /** 1112 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 1113 * @hw: pointer to the HW structure 1114 * 1115 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 1116 * and downshift values are set also. 1117 **/ 1118 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 1119 { 1120 struct e1000_phy_info *phy = &hw->phy; 1121 s32 ret_val; 1122 u16 phy_data; 1123 1124 DEBUGFUNC("e1000_copper_link_setup_m88"); 1125 1126 1127 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1128 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1129 if (ret_val) 1130 return ret_val; 1131 1132 /* For BM PHY this bit is downshift enable */ 1133 if (phy->type != e1000_phy_bm) 1134 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1135 1136 /* Options: 1137 * MDI/MDI-X = 0 (default) 1138 * 0 - Auto for all speeds 1139 * 1 - MDI mode 1140 * 2 - MDI-X mode 1141 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1142 */ 1143 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1144 1145 switch (phy->mdix) { 1146 case 1: 1147 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1148 break; 1149 case 2: 1150 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1151 break; 1152 case 3: 1153 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1154 break; 1155 case 0: 1156 default: 1157 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1158 break; 1159 } 1160 1161 /* Options: 1162 * disable_polarity_correction = 0 (default) 1163 * Automatic Correction for Reversed Cable Polarity 1164 * 0 - Disabled 1165 * 1 - Enabled 1166 */ 1167 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1168 if (phy->disable_polarity_correction) 1169 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1170 1171 /* Enable downshift on BM (disabled by default) */ 1172 if (phy->type == e1000_phy_bm) { 1173 /* For 82574/82583, first disable then enable downshift */ 1174 if (phy->id == BME1000_E_PHY_ID_R2) { 1175 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 1176 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1177 phy_data); 1178 if (ret_val) 1179 return ret_val; 1180 /* Commit the changes. */ 1181 ret_val = phy->ops.commit(hw); 1182 if (ret_val) { 1183 DEBUGOUT("Error committing the PHY changes\n"); 1184 return ret_val; 1185 } 1186 } 1187 1188 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 1189 } 1190 1191 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1192 if (ret_val) 1193 return ret_val; 1194 1195 if (phy->revision < E1000_REVISION_4 && 1196 (hw->mac.type >= e1000_82575 || 1197 (phy->type == e1000_phy_m88 && phy->id != BME1000_E_PHY_ID_R2))) { 1198 /* Force TX_CLK in the Extended PHY Specific Control Register 1199 * to 25MHz clock. 1200 */ 1201 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1202 &phy_data); 1203 if (ret_val) 1204 return ret_val; 1205 1206 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1207 1208 if ((phy->revision == E1000_REVISION_2) && 1209 (phy->id == M88E1111_I_PHY_ID)) { 1210 /* 82573L PHY - set the downshift counter to 5x. */ 1211 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 1212 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1213 } else { 1214 /* Configure Master and Slave downshift values */ 1215 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1216 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1217 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1218 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1219 } 1220 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1221 phy_data); 1222 if (ret_val) 1223 return ret_val; 1224 } 1225 1226 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 1227 /* Set PHY page 0, register 29 to 0x0003 */ 1228 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 1229 if (ret_val) 1230 return ret_val; 1231 1232 /* Set PHY page 0, register 30 to 0x0000 */ 1233 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 1234 if (ret_val) 1235 return ret_val; 1236 } 1237 1238 /* Commit the changes. */ 1239 ret_val = phy->ops.commit(hw); 1240 if (ret_val) { 1241 DEBUGOUT("Error committing the PHY changes\n"); 1242 return ret_val; 1243 } 1244 1245 if (phy->type == e1000_phy_82578) { 1246 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1247 &phy_data); 1248 if (ret_val) 1249 return ret_val; 1250 1251 /* 82578 PHY - set the downshift count to 1x. */ 1252 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 1253 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 1254 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1255 phy_data); 1256 if (ret_val) 1257 return ret_val; 1258 } 1259 1260 return E1000_SUCCESS; 1261 } 1262 1263 /** 1264 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 1265 * @hw: pointer to the HW structure 1266 * 1267 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1268 * Also enables and sets the downshift parameters. 1269 **/ 1270 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1271 { 1272 struct e1000_phy_info *phy = &hw->phy; 1273 s32 ret_val; 1274 u16 phy_data; 1275 1276 DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1277 1278 1279 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1280 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1281 if (ret_val) 1282 return ret_val; 1283 1284 /* Options: 1285 * MDI/MDI-X = 0 (default) 1286 * 0 - Auto for all speeds 1287 * 1 - MDI mode 1288 * 2 - MDI-X mode 1289 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1290 */ 1291 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1292 1293 switch (phy->mdix) { 1294 case 1: 1295 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1296 break; 1297 case 2: 1298 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1299 break; 1300 case 3: 1301 /* M88E1112 does not support this mode) */ 1302 if (phy->id != M88E1112_E_PHY_ID) { 1303 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1304 break; 1305 } 1306 case 0: 1307 default: 1308 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1309 break; 1310 } 1311 1312 /* Options: 1313 * disable_polarity_correction = 0 (default) 1314 * Automatic Correction for Reversed Cable Polarity 1315 * 0 - Disabled 1316 * 1 - Enabled 1317 */ 1318 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1319 if (phy->disable_polarity_correction) 1320 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1321 1322 /* Enable downshift and setting it to X6 */ 1323 if (phy->id == M88E1543_E_PHY_ID) { 1324 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE; 1325 ret_val = 1326 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1327 if (ret_val) 1328 return ret_val; 1329 1330 ret_val = phy->ops.commit(hw); 1331 if (ret_val) { 1332 DEBUGOUT("Error committing the PHY changes\n"); 1333 return ret_val; 1334 } 1335 } 1336 1337 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1338 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1339 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1340 1341 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1342 if (ret_val) 1343 return ret_val; 1344 1345 /* Commit the changes. */ 1346 ret_val = phy->ops.commit(hw); 1347 if (ret_val) { 1348 DEBUGOUT("Error committing the PHY changes\n"); 1349 return ret_val; 1350 } 1351 1352 ret_val = e1000_set_master_slave_mode(hw); 1353 if (ret_val) 1354 return ret_val; 1355 1356 return E1000_SUCCESS; 1357 } 1358 1359 /** 1360 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1361 * @hw: pointer to the HW structure 1362 * 1363 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1364 * igp PHY's. 1365 **/ 1366 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1367 { 1368 struct e1000_phy_info *phy = &hw->phy; 1369 s32 ret_val; 1370 u16 data; 1371 1372 DEBUGFUNC("e1000_copper_link_setup_igp"); 1373 1374 1375 ret_val = hw->phy.ops.reset(hw); 1376 if (ret_val) { 1377 DEBUGOUT("Error resetting the PHY.\n"); 1378 return ret_val; 1379 } 1380 1381 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1382 * timeout issues when LFS is enabled. 1383 */ 1384 msec_delay(100); 1385 1386 /* The NVM settings will configure LPLU in D3 for 1387 * non-IGP1 PHYs. 1388 */ 1389 if (phy->type == e1000_phy_igp) { 1390 /* disable lplu d3 during driver init */ 1391 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1392 if (ret_val) { 1393 DEBUGOUT("Error Disabling LPLU D3\n"); 1394 return ret_val; 1395 } 1396 } 1397 1398 /* disable lplu d0 during driver init */ 1399 if (hw->phy.ops.set_d0_lplu_state) { 1400 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1401 if (ret_val) { 1402 DEBUGOUT("Error Disabling LPLU D0\n"); 1403 return ret_val; 1404 } 1405 } 1406 /* Configure mdi-mdix settings */ 1407 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1408 if (ret_val) 1409 return ret_val; 1410 1411 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1412 1413 switch (phy->mdix) { 1414 case 1: 1415 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1416 break; 1417 case 2: 1418 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1419 break; 1420 case 0: 1421 default: 1422 data |= IGP01E1000_PSCR_AUTO_MDIX; 1423 break; 1424 } 1425 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1426 if (ret_val) 1427 return ret_val; 1428 1429 /* set auto-master slave resolution settings */ 1430 if (hw->mac.autoneg) { 1431 /* when autonegotiation advertisement is only 1000Mbps then we 1432 * should disable SmartSpeed and enable Auto MasterSlave 1433 * resolution as hardware default. 1434 */ 1435 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1436 /* Disable SmartSpeed */ 1437 ret_val = phy->ops.read_reg(hw, 1438 IGP01E1000_PHY_PORT_CONFIG, 1439 &data); 1440 if (ret_val) 1441 return ret_val; 1442 1443 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1444 ret_val = phy->ops.write_reg(hw, 1445 IGP01E1000_PHY_PORT_CONFIG, 1446 data); 1447 if (ret_val) 1448 return ret_val; 1449 1450 /* Set auto Master/Slave resolution process */ 1451 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1452 if (ret_val) 1453 return ret_val; 1454 1455 data &= ~CR_1000T_MS_ENABLE; 1456 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1457 if (ret_val) 1458 return ret_val; 1459 } 1460 1461 ret_val = e1000_set_master_slave_mode(hw); 1462 } 1463 1464 return ret_val; 1465 } 1466 1467 /** 1468 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1469 * @hw: pointer to the HW structure 1470 * 1471 * Reads the MII auto-neg advertisement register and/or the 1000T control 1472 * register and if the PHY is already setup for auto-negotiation, then 1473 * return successful. Otherwise, setup advertisement and flow control to 1474 * the appropriate values for the wanted auto-negotiation. 1475 **/ 1476 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1477 { 1478 struct e1000_phy_info *phy = &hw->phy; 1479 s32 ret_val; 1480 u16 mii_autoneg_adv_reg; 1481 u16 mii_1000t_ctrl_reg = 0; 1482 1483 DEBUGFUNC("e1000_phy_setup_autoneg"); 1484 1485 phy->autoneg_advertised &= phy->autoneg_mask; 1486 1487 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1488 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1489 if (ret_val) 1490 return ret_val; 1491 1492 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1493 /* Read the MII 1000Base-T Control Register (Address 9). */ 1494 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1495 &mii_1000t_ctrl_reg); 1496 if (ret_val) 1497 return ret_val; 1498 } 1499 1500 /* Need to parse both autoneg_advertised and fc and set up 1501 * the appropriate PHY registers. First we will parse for 1502 * autoneg_advertised software override. Since we can advertise 1503 * a plethora of combinations, we need to check each bit 1504 * individually. 1505 */ 1506 1507 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1508 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1509 * the 1000Base-T Control Register (Address 9). 1510 */ 1511 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1512 NWAY_AR_100TX_HD_CAPS | 1513 NWAY_AR_10T_FD_CAPS | 1514 NWAY_AR_10T_HD_CAPS); 1515 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1516 1517 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1518 1519 /* Do we want to advertise 10 Mb Half Duplex? */ 1520 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1521 DEBUGOUT("Advertise 10mb Half duplex\n"); 1522 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1523 } 1524 1525 /* Do we want to advertise 10 Mb Full Duplex? */ 1526 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1527 DEBUGOUT("Advertise 10mb Full duplex\n"); 1528 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1529 } 1530 1531 /* Do we want to advertise 100 Mb Half Duplex? */ 1532 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1533 DEBUGOUT("Advertise 100mb Half duplex\n"); 1534 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1535 } 1536 1537 /* Do we want to advertise 100 Mb Full Duplex? */ 1538 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1539 DEBUGOUT("Advertise 100mb Full duplex\n"); 1540 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1541 } 1542 1543 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1544 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1545 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1546 1547 /* Do we want to advertise 1000 Mb Full Duplex? */ 1548 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1549 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1550 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1551 } 1552 1553 /* Check for a software override of the flow control settings, and 1554 * setup the PHY advertisement registers accordingly. If 1555 * auto-negotiation is enabled, then software will have to set the 1556 * "PAUSE" bits to the correct value in the Auto-Negotiation 1557 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1558 * negotiation. 1559 * 1560 * The possible values of the "fc" parameter are: 1561 * 0: Flow control is completely disabled 1562 * 1: Rx flow control is enabled (we can receive pause frames 1563 * but not send pause frames). 1564 * 2: Tx flow control is enabled (we can send pause frames 1565 * but we do not support receiving pause frames). 1566 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1567 * other: No software override. The flow control configuration 1568 * in the EEPROM is used. 1569 */ 1570 switch (hw->fc.current_mode) { 1571 case e1000_fc_none: 1572 /* Flow control (Rx & Tx) is completely disabled by a 1573 * software over-ride. 1574 */ 1575 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1576 break; 1577 case e1000_fc_rx_pause: 1578 /* Rx Flow control is enabled, and Tx Flow control is 1579 * disabled, by a software over-ride. 1580 * 1581 * Since there really isn't a way to advertise that we are 1582 * capable of Rx Pause ONLY, we will advertise that we 1583 * support both symmetric and asymmetric Rx PAUSE. Later 1584 * (in e1000_config_fc_after_link_up) we will disable the 1585 * hw's ability to send PAUSE frames. 1586 */ 1587 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1588 break; 1589 case e1000_fc_tx_pause: 1590 /* Tx Flow control is enabled, and Rx Flow control is 1591 * disabled, by a software over-ride. 1592 */ 1593 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1594 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1595 break; 1596 case e1000_fc_full: 1597 /* Flow control (both Rx and Tx) is enabled by a software 1598 * over-ride. 1599 */ 1600 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1601 break; 1602 default: 1603 DEBUGOUT("Flow control param set incorrectly\n"); 1604 return -E1000_ERR_CONFIG; 1605 } 1606 1607 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1608 if (ret_val) 1609 return ret_val; 1610 1611 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1612 1613 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1614 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 1615 mii_1000t_ctrl_reg); 1616 1617 return ret_val; 1618 } 1619 1620 /** 1621 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1622 * @hw: pointer to the HW structure 1623 * 1624 * Performs initial bounds checking on autoneg advertisement parameter, then 1625 * configure to advertise the full capability. Setup the PHY to autoneg 1626 * and restart the negotiation process between the link partner. If 1627 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1628 **/ 1629 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1630 { 1631 struct e1000_phy_info *phy = &hw->phy; 1632 s32 ret_val; 1633 u16 phy_ctrl; 1634 1635 DEBUGFUNC("e1000_copper_link_autoneg"); 1636 1637 /* Perform some bounds checking on the autoneg advertisement 1638 * parameter. 1639 */ 1640 phy->autoneg_advertised &= phy->autoneg_mask; 1641 1642 /* If autoneg_advertised is zero, we assume it was not defaulted 1643 * by the calling code so we set to advertise full capability. 1644 */ 1645 if (!phy->autoneg_advertised) 1646 phy->autoneg_advertised = phy->autoneg_mask; 1647 1648 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1649 ret_val = e1000_phy_setup_autoneg(hw); 1650 if (ret_val) { 1651 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1652 return ret_val; 1653 } 1654 DEBUGOUT("Restarting Auto-Neg\n"); 1655 1656 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1657 * the Auto Neg Restart bit in the PHY control register. 1658 */ 1659 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1660 if (ret_val) 1661 return ret_val; 1662 1663 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1664 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1665 if (ret_val) 1666 return ret_val; 1667 1668 /* Does the user want to wait for Auto-Neg to complete here, or 1669 * check at a later time (for example, callback routine). 1670 */ 1671 if (phy->autoneg_wait_to_complete) { 1672 ret_val = e1000_wait_autoneg(hw); 1673 if (ret_val) { 1674 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1675 return ret_val; 1676 } 1677 } 1678 1679 hw->mac.get_link_status = TRUE; 1680 1681 return ret_val; 1682 } 1683 1684 /** 1685 * e1000_setup_copper_link_generic - Configure copper link settings 1686 * @hw: pointer to the HW structure 1687 * 1688 * Calls the appropriate function to configure the link for auto-neg or forced 1689 * speed and duplex. Then we check for link, once link is established calls 1690 * to configure collision distance and flow control are called. If link is 1691 * not established, we return -E1000_ERR_PHY (-2). 1692 **/ 1693 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1694 { 1695 s32 ret_val; 1696 bool link; 1697 1698 DEBUGFUNC("e1000_setup_copper_link_generic"); 1699 1700 if (hw->mac.autoneg) { 1701 /* Setup autoneg and flow control advertisement and perform 1702 * autonegotiation. 1703 */ 1704 ret_val = e1000_copper_link_autoneg(hw); 1705 if (ret_val) 1706 return ret_val; 1707 } else { 1708 /* PHY will be set to 10H, 10F, 100H or 100F 1709 * depending on user settings. 1710 */ 1711 DEBUGOUT("Forcing Speed and Duplex\n"); 1712 ret_val = hw->phy.ops.force_speed_duplex(hw); 1713 if (ret_val) { 1714 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1715 return ret_val; 1716 } 1717 } 1718 1719 /* Check link status. Wait up to 100 microseconds for link to become 1720 * valid. 1721 */ 1722 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1723 &link); 1724 if (ret_val) 1725 return ret_val; 1726 1727 if (link) { 1728 DEBUGOUT("Valid link established!!!\n"); 1729 hw->mac.ops.config_collision_dist(hw); 1730 ret_val = e1000_config_fc_after_link_up_generic(hw); 1731 } else { 1732 DEBUGOUT("Unable to establish link!!!\n"); 1733 } 1734 1735 return ret_val; 1736 } 1737 1738 /** 1739 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1740 * @hw: pointer to the HW structure 1741 * 1742 * Calls the PHY setup function to force speed and duplex. Clears the 1743 * auto-crossover to force MDI manually. Waits for link and returns 1744 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1745 **/ 1746 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1747 { 1748 struct e1000_phy_info *phy = &hw->phy; 1749 s32 ret_val; 1750 u16 phy_data; 1751 bool link; 1752 1753 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1754 1755 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1756 if (ret_val) 1757 return ret_val; 1758 1759 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1760 1761 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1762 if (ret_val) 1763 return ret_val; 1764 1765 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1766 * forced whenever speed and duplex are forced. 1767 */ 1768 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1769 if (ret_val) 1770 return ret_val; 1771 1772 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1773 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1774 1775 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1776 if (ret_val) 1777 return ret_val; 1778 1779 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1780 1781 usec_delay(1); 1782 1783 if (phy->autoneg_wait_to_complete) { 1784 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1785 1786 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1787 100000, &link); 1788 if (ret_val) 1789 return ret_val; 1790 1791 if (!link) 1792 DEBUGOUT("Link taking longer than expected.\n"); 1793 1794 /* Try once more */ 1795 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1796 100000, &link); 1797 } 1798 1799 return ret_val; 1800 } 1801 1802 /** 1803 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1804 * @hw: pointer to the HW structure 1805 * 1806 * Calls the PHY setup function to force speed and duplex. Clears the 1807 * auto-crossover to force MDI manually. Resets the PHY to commit the 1808 * changes. If time expires while waiting for link up, we reset the DSP. 1809 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1810 * successful completion, else return corresponding error code. 1811 **/ 1812 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1813 { 1814 struct e1000_phy_info *phy = &hw->phy; 1815 s32 ret_val; 1816 u16 phy_data; 1817 bool link; 1818 1819 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1820 1821 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1822 if (phy->type != e1000_phy_i210) { 1823 /* Clear Auto-Crossover to force MDI manually. M88E1000 1824 * requires MDI forced whenever speed and duplex are forced. 1825 */ 1826 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1827 &phy_data); 1828 if (ret_val) 1829 return ret_val; 1830 1831 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1832 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1833 phy_data); 1834 if (ret_val) 1835 return ret_val; 1836 1837 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1838 } 1839 1840 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1841 if (ret_val) 1842 return ret_val; 1843 1844 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1845 1846 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1847 if (ret_val) 1848 return ret_val; 1849 1850 /* Reset the phy to commit changes. */ 1851 ret_val = hw->phy.ops.commit(hw); 1852 if (ret_val) 1853 return ret_val; 1854 1855 if (phy->autoneg_wait_to_complete) { 1856 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1857 1858 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1859 100000, &link); 1860 if (ret_val) 1861 return ret_val; 1862 1863 if (!link) { 1864 bool reset_dsp = TRUE; 1865 1866 switch (hw->phy.id) { 1867 case I347AT4_E_PHY_ID: 1868 case M88E1340M_E_PHY_ID: 1869 case M88E1112_E_PHY_ID: 1870 case M88E1543_E_PHY_ID: 1871 case M88E1512_E_PHY_ID: 1872 case I210_I_PHY_ID: 1873 reset_dsp = FALSE; 1874 break; 1875 default: 1876 if (hw->phy.type != e1000_phy_m88) 1877 reset_dsp = FALSE; 1878 break; 1879 } 1880 1881 if (!reset_dsp) { 1882 DEBUGOUT("Link taking longer than expected.\n"); 1883 } else { 1884 /* We didn't get link. 1885 * Reset the DSP and cross our fingers. 1886 */ 1887 ret_val = phy->ops.write_reg(hw, 1888 M88E1000_PHY_PAGE_SELECT, 1889 0x001d); 1890 if (ret_val) 1891 return ret_val; 1892 ret_val = e1000_phy_reset_dsp_generic(hw); 1893 if (ret_val) 1894 return ret_val; 1895 } 1896 } 1897 1898 /* Try once more */ 1899 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1900 100000, &link); 1901 if (ret_val) 1902 return ret_val; 1903 } 1904 1905 if (hw->phy.type != e1000_phy_m88) 1906 return E1000_SUCCESS; 1907 1908 if (hw->phy.id == I347AT4_E_PHY_ID || 1909 hw->phy.id == M88E1340M_E_PHY_ID || 1910 hw->phy.id == M88E1112_E_PHY_ID) 1911 return E1000_SUCCESS; 1912 if (hw->phy.id == I210_I_PHY_ID) 1913 return E1000_SUCCESS; 1914 if ((hw->phy.id == M88E1543_E_PHY_ID) || 1915 (hw->phy.id == M88E1512_E_PHY_ID)) 1916 return E1000_SUCCESS; 1917 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1918 if (ret_val) 1919 return ret_val; 1920 1921 /* Resetting the phy means we need to re-force TX_CLK in the 1922 * Extended PHY Specific Control Register to 25MHz clock from 1923 * the reset value of 2.5MHz. 1924 */ 1925 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1926 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1927 if (ret_val) 1928 return ret_val; 1929 1930 /* In addition, we must re-enable CRS on Tx for both half and full 1931 * duplex. 1932 */ 1933 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1934 if (ret_val) 1935 return ret_val; 1936 1937 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1938 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1939 1940 return ret_val; 1941 } 1942 1943 /** 1944 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1945 * @hw: pointer to the HW structure 1946 * 1947 * Forces the speed and duplex settings of the PHY. 1948 * This is a function pointer entry point only called by 1949 * PHY setup routines. 1950 **/ 1951 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1952 { 1953 struct e1000_phy_info *phy = &hw->phy; 1954 s32 ret_val; 1955 u16 data; 1956 bool link; 1957 1958 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1959 1960 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1961 if (ret_val) 1962 return ret_val; 1963 1964 e1000_phy_force_speed_duplex_setup(hw, &data); 1965 1966 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1967 if (ret_val) 1968 return ret_val; 1969 1970 /* Disable MDI-X support for 10/100 */ 1971 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1972 if (ret_val) 1973 return ret_val; 1974 1975 data &= ~IFE_PMC_AUTO_MDIX; 1976 data &= ~IFE_PMC_FORCE_MDIX; 1977 1978 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1979 if (ret_val) 1980 return ret_val; 1981 1982 DEBUGOUT1("IFE PMC: %X\n", data); 1983 1984 usec_delay(1); 1985 1986 if (phy->autoneg_wait_to_complete) { 1987 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1988 1989 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1990 100000, &link); 1991 if (ret_val) 1992 return ret_val; 1993 1994 if (!link) 1995 DEBUGOUT("Link taking longer than expected.\n"); 1996 1997 /* Try once more */ 1998 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1999 100000, &link); 2000 if (ret_val) 2001 return ret_val; 2002 } 2003 2004 return E1000_SUCCESS; 2005 } 2006 2007 /** 2008 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 2009 * @hw: pointer to the HW structure 2010 * @phy_ctrl: pointer to current value of PHY_CONTROL 2011 * 2012 * Forces speed and duplex on the PHY by doing the following: disable flow 2013 * control, force speed/duplex on the MAC, disable auto speed detection, 2014 * disable auto-negotiation, configure duplex, configure speed, configure 2015 * the collision distance, write configuration to CTRL register. The 2016 * caller must write to the PHY_CONTROL register for these settings to 2017 * take affect. 2018 **/ 2019 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 2020 { 2021 struct e1000_mac_info *mac = &hw->mac; 2022 u32 ctrl; 2023 2024 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 2025 2026 /* Turn off flow control when forcing speed/duplex */ 2027 hw->fc.current_mode = e1000_fc_none; 2028 2029 /* Force speed/duplex on the mac */ 2030 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2031 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2032 ctrl &= ~E1000_CTRL_SPD_SEL; 2033 2034 /* Disable Auto Speed Detection */ 2035 ctrl &= ~E1000_CTRL_ASDE; 2036 2037 /* Disable autoneg on the phy */ 2038 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 2039 2040 /* Forcing Full or Half Duplex? */ 2041 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 2042 ctrl &= ~E1000_CTRL_FD; 2043 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 2044 DEBUGOUT("Half Duplex\n"); 2045 } else { 2046 ctrl |= E1000_CTRL_FD; 2047 *phy_ctrl |= MII_CR_FULL_DUPLEX; 2048 DEBUGOUT("Full Duplex\n"); 2049 } 2050 2051 /* Forcing 10mb or 100mb? */ 2052 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 2053 ctrl |= E1000_CTRL_SPD_100; 2054 *phy_ctrl |= MII_CR_SPEED_100; 2055 *phy_ctrl &= ~MII_CR_SPEED_1000; 2056 DEBUGOUT("Forcing 100mb\n"); 2057 } else { 2058 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2059 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2060 DEBUGOUT("Forcing 10mb\n"); 2061 } 2062 2063 hw->mac.ops.config_collision_dist(hw); 2064 2065 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2066 } 2067 2068 /** 2069 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 2070 * @hw: pointer to the HW structure 2071 * @active: boolean used to enable/disable lplu 2072 * 2073 * Success returns 0, Failure returns 1 2074 * 2075 * The low power link up (lplu) state is set to the power management level D3 2076 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 2077 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2078 * is used during Dx states where the power conservation is most important. 2079 * During driver activity, SmartSpeed should be enabled so performance is 2080 * maintained. 2081 **/ 2082 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 2083 { 2084 struct e1000_phy_info *phy = &hw->phy; 2085 s32 ret_val; 2086 u16 data; 2087 2088 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 2089 2090 if (!hw->phy.ops.read_reg) 2091 return E1000_SUCCESS; 2092 2093 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 2094 if (ret_val) 2095 return ret_val; 2096 2097 if (!active) { 2098 data &= ~IGP02E1000_PM_D3_LPLU; 2099 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2100 data); 2101 if (ret_val) 2102 return ret_val; 2103 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2104 * during Dx states where the power conservation is most 2105 * important. During driver activity we should enable 2106 * SmartSpeed, so performance is maintained. 2107 */ 2108 if (phy->smart_speed == e1000_smart_speed_on) { 2109 ret_val = phy->ops.read_reg(hw, 2110 IGP01E1000_PHY_PORT_CONFIG, 2111 &data); 2112 if (ret_val) 2113 return ret_val; 2114 2115 data |= IGP01E1000_PSCFR_SMART_SPEED; 2116 ret_val = phy->ops.write_reg(hw, 2117 IGP01E1000_PHY_PORT_CONFIG, 2118 data); 2119 if (ret_val) 2120 return ret_val; 2121 } else if (phy->smart_speed == e1000_smart_speed_off) { 2122 ret_val = phy->ops.read_reg(hw, 2123 IGP01E1000_PHY_PORT_CONFIG, 2124 &data); 2125 if (ret_val) 2126 return ret_val; 2127 2128 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2129 ret_val = phy->ops.write_reg(hw, 2130 IGP01E1000_PHY_PORT_CONFIG, 2131 data); 2132 if (ret_val) 2133 return ret_val; 2134 } 2135 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2136 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2137 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2138 data |= IGP02E1000_PM_D3_LPLU; 2139 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2140 data); 2141 if (ret_val) 2142 return ret_val; 2143 2144 /* When LPLU is enabled, we should disable SmartSpeed */ 2145 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2146 &data); 2147 if (ret_val) 2148 return ret_val; 2149 2150 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2151 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2152 data); 2153 } 2154 2155 return ret_val; 2156 } 2157 2158 /** 2159 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 2160 * @hw: pointer to the HW structure 2161 * 2162 * Success returns 0, Failure returns 1 2163 * 2164 * A downshift is detected by querying the PHY link health. 2165 **/ 2166 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 2167 { 2168 struct e1000_phy_info *phy = &hw->phy; 2169 s32 ret_val; 2170 u16 phy_data, offset, mask; 2171 2172 DEBUGFUNC("e1000_check_downshift_generic"); 2173 2174 switch (phy->type) { 2175 case e1000_phy_i210: 2176 case e1000_phy_m88: 2177 case e1000_phy_gg82563: 2178 case e1000_phy_bm: 2179 case e1000_phy_82578: 2180 offset = M88E1000_PHY_SPEC_STATUS; 2181 mask = M88E1000_PSSR_DOWNSHIFT; 2182 break; 2183 case e1000_phy_igp: 2184 case e1000_phy_igp_2: 2185 case e1000_phy_igp_3: 2186 offset = IGP01E1000_PHY_LINK_HEALTH; 2187 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 2188 break; 2189 default: 2190 /* speed downshift not supported */ 2191 phy->speed_downgraded = FALSE; 2192 return E1000_SUCCESS; 2193 } 2194 2195 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2196 2197 if (!ret_val) 2198 phy->speed_downgraded = !!(phy_data & mask); 2199 2200 return ret_val; 2201 } 2202 2203 /** 2204 * e1000_check_polarity_m88 - Checks the polarity. 2205 * @hw: pointer to the HW structure 2206 * 2207 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2208 * 2209 * Polarity is determined based on the PHY specific status register. 2210 **/ 2211 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 2212 { 2213 struct e1000_phy_info *phy = &hw->phy; 2214 s32 ret_val; 2215 u16 data; 2216 2217 DEBUGFUNC("e1000_check_polarity_m88"); 2218 2219 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 2220 2221 if (!ret_val) 2222 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) 2223 ? e1000_rev_polarity_reversed 2224 : e1000_rev_polarity_normal); 2225 2226 return ret_val; 2227 } 2228 2229 /** 2230 * e1000_check_polarity_igp - Checks the polarity. 2231 * @hw: pointer to the HW structure 2232 * 2233 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2234 * 2235 * Polarity is determined based on the PHY port status register, and the 2236 * current speed (since there is no polarity at 100Mbps). 2237 **/ 2238 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 2239 { 2240 struct e1000_phy_info *phy = &hw->phy; 2241 s32 ret_val; 2242 u16 data, offset, mask; 2243 2244 DEBUGFUNC("e1000_check_polarity_igp"); 2245 2246 /* Polarity is determined based on the speed of 2247 * our connection. 2248 */ 2249 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2250 if (ret_val) 2251 return ret_val; 2252 2253 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2254 IGP01E1000_PSSR_SPEED_1000MBPS) { 2255 offset = IGP01E1000_PHY_PCS_INIT_REG; 2256 mask = IGP01E1000_PHY_POLARITY_MASK; 2257 } else { 2258 /* This really only applies to 10Mbps since 2259 * there is no polarity for 100Mbps (always 0). 2260 */ 2261 offset = IGP01E1000_PHY_PORT_STATUS; 2262 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2263 } 2264 2265 ret_val = phy->ops.read_reg(hw, offset, &data); 2266 2267 if (!ret_val) 2268 phy->cable_polarity = ((data & mask) 2269 ? e1000_rev_polarity_reversed 2270 : e1000_rev_polarity_normal); 2271 2272 return ret_val; 2273 } 2274 2275 /** 2276 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2277 * @hw: pointer to the HW structure 2278 * 2279 * Polarity is determined on the polarity reversal feature being enabled. 2280 **/ 2281 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 2282 { 2283 struct e1000_phy_info *phy = &hw->phy; 2284 s32 ret_val; 2285 u16 phy_data, offset, mask; 2286 2287 DEBUGFUNC("e1000_check_polarity_ife"); 2288 2289 /* Polarity is determined based on the reversal feature being enabled. 2290 */ 2291 if (phy->polarity_correction) { 2292 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2293 mask = IFE_PESC_POLARITY_REVERSED; 2294 } else { 2295 offset = IFE_PHY_SPECIAL_CONTROL; 2296 mask = IFE_PSC_FORCE_POLARITY; 2297 } 2298 2299 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2300 2301 if (!ret_val) 2302 phy->cable_polarity = ((phy_data & mask) 2303 ? e1000_rev_polarity_reversed 2304 : e1000_rev_polarity_normal); 2305 2306 return ret_val; 2307 } 2308 2309 /** 2310 * e1000_wait_autoneg - Wait for auto-neg completion 2311 * @hw: pointer to the HW structure 2312 * 2313 * Waits for auto-negotiation to complete or for the auto-negotiation time 2314 * limit to expire, which ever happens first. 2315 **/ 2316 static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2317 { 2318 s32 ret_val = E1000_SUCCESS; 2319 u16 i, phy_status; 2320 2321 DEBUGFUNC("e1000_wait_autoneg"); 2322 2323 if (!hw->phy.ops.read_reg) 2324 return E1000_SUCCESS; 2325 2326 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2327 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2328 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2329 if (ret_val) 2330 break; 2331 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2332 if (ret_val) 2333 break; 2334 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2335 break; 2336 msec_delay(100); 2337 } 2338 2339 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2340 * has completed. 2341 */ 2342 return ret_val; 2343 } 2344 2345 /** 2346 * e1000_phy_has_link_generic - Polls PHY for link 2347 * @hw: pointer to the HW structure 2348 * @iterations: number of times to poll for link 2349 * @usec_interval: delay between polling attempts 2350 * @success: pointer to whether polling was successful or not 2351 * 2352 * Polls the PHY status register for link, 'iterations' number of times. 2353 **/ 2354 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2355 u32 usec_interval, bool *success) 2356 { 2357 s32 ret_val = E1000_SUCCESS; 2358 u16 i, phy_status; 2359 2360 DEBUGFUNC("e1000_phy_has_link_generic"); 2361 2362 if (!hw->phy.ops.read_reg) 2363 return E1000_SUCCESS; 2364 2365 for (i = 0; i < iterations; i++) { 2366 /* Some PHYs require the PHY_STATUS register to be read 2367 * twice due to the link bit being sticky. No harm doing 2368 * it across the board. 2369 */ 2370 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2371 if (ret_val) { 2372 /* If the first read fails, another entity may have 2373 * ownership of the resources, wait and try again to 2374 * see if they have relinquished the resources yet. 2375 */ 2376 if (usec_interval >= 1000) 2377 msec_delay(usec_interval/1000); 2378 else 2379 usec_delay(usec_interval); 2380 } 2381 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2382 if (ret_val) 2383 break; 2384 if (phy_status & MII_SR_LINK_STATUS) 2385 break; 2386 if (usec_interval >= 1000) 2387 msec_delay(usec_interval/1000); 2388 else 2389 usec_delay(usec_interval); 2390 } 2391 2392 *success = (i < iterations); 2393 2394 return ret_val; 2395 } 2396 2397 /** 2398 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2399 * @hw: pointer to the HW structure 2400 * 2401 * Reads the PHY specific status register to retrieve the cable length 2402 * information. The cable length is determined by averaging the minimum and 2403 * maximum values to get the "average" cable length. The m88 PHY has four 2404 * possible cable length values, which are: 2405 * Register Value Cable Length 2406 * 0 < 50 meters 2407 * 1 50 - 80 meters 2408 * 2 80 - 110 meters 2409 * 3 110 - 140 meters 2410 * 4 > 140 meters 2411 **/ 2412 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2413 { 2414 struct e1000_phy_info *phy = &hw->phy; 2415 s32 ret_val; 2416 u16 phy_data, index; 2417 2418 DEBUGFUNC("e1000_get_cable_length_m88"); 2419 2420 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2421 if (ret_val) 2422 return ret_val; 2423 2424 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2425 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 2426 2427 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2428 return -E1000_ERR_PHY; 2429 2430 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2431 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2432 2433 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2434 2435 return E1000_SUCCESS; 2436 } 2437 2438 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2439 { 2440 struct e1000_phy_info *phy = &hw->phy; 2441 s32 ret_val; 2442 u16 phy_data, phy_data2, is_cm; 2443 u16 index, default_page; 2444 2445 DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2446 2447 switch (hw->phy.id) { 2448 case I210_I_PHY_ID: 2449 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2450 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2451 (I347AT4_PCDL + phy->addr), 2452 &phy_data); 2453 if (ret_val) 2454 return ret_val; 2455 2456 /* Check if the unit of cable length is meters or cm */ 2457 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2458 I347AT4_PCDC, &phy_data2); 2459 if (ret_val) 2460 return ret_val; 2461 2462 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2463 2464 /* Populate the phy structure with cable length in meters */ 2465 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2466 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2467 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2468 break; 2469 case M88E1543_E_PHY_ID: 2470 case M88E1512_E_PHY_ID: 2471 case M88E1340M_E_PHY_ID: 2472 case I347AT4_E_PHY_ID: 2473 /* Remember the original page select and set it to 7 */ 2474 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2475 &default_page); 2476 if (ret_val) 2477 return ret_val; 2478 2479 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2480 if (ret_val) 2481 return ret_val; 2482 2483 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2484 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2485 &phy_data); 2486 if (ret_val) 2487 return ret_val; 2488 2489 /* Check if the unit of cable length is meters or cm */ 2490 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2491 if (ret_val) 2492 return ret_val; 2493 2494 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2495 2496 /* Populate the phy structure with cable length in meters */ 2497 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2498 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2499 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2500 2501 /* Reset the page select to its original value */ 2502 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2503 default_page); 2504 if (ret_val) 2505 return ret_val; 2506 break; 2507 2508 case M88E1112_E_PHY_ID: 2509 /* Remember the original page select and set it to 5 */ 2510 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2511 &default_page); 2512 if (ret_val) 2513 return ret_val; 2514 2515 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2516 if (ret_val) 2517 return ret_val; 2518 2519 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2520 &phy_data); 2521 if (ret_val) 2522 return ret_val; 2523 2524 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2525 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2526 2527 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2528 return -E1000_ERR_PHY; 2529 2530 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2531 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2532 2533 phy->cable_length = (phy->min_cable_length + 2534 phy->max_cable_length) / 2; 2535 2536 /* Reset the page select to its original value */ 2537 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2538 default_page); 2539 if (ret_val) 2540 return ret_val; 2541 2542 break; 2543 default: 2544 return -E1000_ERR_PHY; 2545 } 2546 2547 return ret_val; 2548 } 2549 2550 /** 2551 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2552 * @hw: pointer to the HW structure 2553 * 2554 * The automatic gain control (agc) normalizes the amplitude of the 2555 * received signal, adjusting for the attenuation produced by the 2556 * cable. By reading the AGC registers, which represent the 2557 * combination of coarse and fine gain value, the value can be put 2558 * into a lookup table to obtain the approximate cable length 2559 * for each channel. 2560 **/ 2561 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2562 { 2563 struct e1000_phy_info *phy = &hw->phy; 2564 s32 ret_val; 2565 u16 phy_data, i, agc_value = 0; 2566 u16 cur_agc_index, max_agc_index = 0; 2567 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2568 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2569 IGP02E1000_PHY_AGC_A, 2570 IGP02E1000_PHY_AGC_B, 2571 IGP02E1000_PHY_AGC_C, 2572 IGP02E1000_PHY_AGC_D 2573 }; 2574 2575 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2576 2577 /* Read the AGC registers for all channels */ 2578 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2579 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2580 if (ret_val) 2581 return ret_val; 2582 2583 /* Getting bits 15:9, which represent the combination of 2584 * coarse and fine gain values. The result is a number 2585 * that can be put into the lookup table to obtain the 2586 * approximate cable length. 2587 */ 2588 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2589 IGP02E1000_AGC_LENGTH_MASK); 2590 2591 /* Array index bound check. */ 2592 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2593 (cur_agc_index == 0)) 2594 return -E1000_ERR_PHY; 2595 2596 /* Remove min & max AGC values from calculation. */ 2597 if (e1000_igp_2_cable_length_table[min_agc_index] > 2598 e1000_igp_2_cable_length_table[cur_agc_index]) 2599 min_agc_index = cur_agc_index; 2600 if (e1000_igp_2_cable_length_table[max_agc_index] < 2601 e1000_igp_2_cable_length_table[cur_agc_index]) 2602 max_agc_index = cur_agc_index; 2603 2604 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2605 } 2606 2607 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2608 e1000_igp_2_cable_length_table[max_agc_index]); 2609 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2610 2611 /* Calculate cable length with the error range of +/- 10 meters. */ 2612 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2613 (agc_value - IGP02E1000_AGC_RANGE) : 0); 2614 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2615 2616 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2617 2618 return E1000_SUCCESS; 2619 } 2620 2621 /** 2622 * e1000_get_phy_info_m88 - Retrieve PHY information 2623 * @hw: pointer to the HW structure 2624 * 2625 * Valid for only copper links. Read the PHY status register (sticky read) 2626 * to verify that link is up. Read the PHY special control register to 2627 * determine the polarity and 10base-T extended distance. Read the PHY 2628 * special status register to determine MDI/MDIx and current speed. If 2629 * speed is 1000, then determine cable length, local and remote receiver. 2630 **/ 2631 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2632 { 2633 struct e1000_phy_info *phy = &hw->phy; 2634 s32 ret_val; 2635 u16 phy_data; 2636 bool link; 2637 2638 DEBUGFUNC("e1000_get_phy_info_m88"); 2639 2640 if (phy->media_type != e1000_media_type_copper) { 2641 DEBUGOUT("Phy info is only valid for copper media\n"); 2642 return -E1000_ERR_CONFIG; 2643 } 2644 2645 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2646 if (ret_val) 2647 return ret_val; 2648 2649 if (!link) { 2650 DEBUGOUT("Phy info is only valid if link is up\n"); 2651 return -E1000_ERR_CONFIG; 2652 } 2653 2654 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2655 if (ret_val) 2656 return ret_val; 2657 2658 phy->polarity_correction = !!(phy_data & 2659 M88E1000_PSCR_POLARITY_REVERSAL); 2660 2661 ret_val = e1000_check_polarity_m88(hw); 2662 if (ret_val) 2663 return ret_val; 2664 2665 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2666 if (ret_val) 2667 return ret_val; 2668 2669 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 2670 2671 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2672 ret_val = hw->phy.ops.get_cable_length(hw); 2673 if (ret_val) 2674 return ret_val; 2675 2676 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2677 if (ret_val) 2678 return ret_val; 2679 2680 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2681 ? e1000_1000t_rx_status_ok 2682 : e1000_1000t_rx_status_not_ok; 2683 2684 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2685 ? e1000_1000t_rx_status_ok 2686 : e1000_1000t_rx_status_not_ok; 2687 } else { 2688 /* Set values to "undefined" */ 2689 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2690 phy->local_rx = e1000_1000t_rx_status_undefined; 2691 phy->remote_rx = e1000_1000t_rx_status_undefined; 2692 } 2693 2694 return ret_val; 2695 } 2696 2697 /** 2698 * e1000_get_phy_info_igp - Retrieve igp PHY information 2699 * @hw: pointer to the HW structure 2700 * 2701 * Read PHY status to determine if link is up. If link is up, then 2702 * set/determine 10base-T extended distance and polarity correction. Read 2703 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2704 * determine on the cable length, local and remote receiver. 2705 **/ 2706 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2707 { 2708 struct e1000_phy_info *phy = &hw->phy; 2709 s32 ret_val; 2710 u16 data; 2711 bool link; 2712 2713 DEBUGFUNC("e1000_get_phy_info_igp"); 2714 2715 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2716 if (ret_val) 2717 return ret_val; 2718 2719 if (!link) { 2720 DEBUGOUT("Phy info is only valid if link is up\n"); 2721 return -E1000_ERR_CONFIG; 2722 } 2723 2724 phy->polarity_correction = TRUE; 2725 2726 ret_val = e1000_check_polarity_igp(hw); 2727 if (ret_val) 2728 return ret_val; 2729 2730 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2731 if (ret_val) 2732 return ret_val; 2733 2734 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 2735 2736 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2737 IGP01E1000_PSSR_SPEED_1000MBPS) { 2738 ret_val = phy->ops.get_cable_length(hw); 2739 if (ret_val) 2740 return ret_val; 2741 2742 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2743 if (ret_val) 2744 return ret_val; 2745 2746 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2747 ? e1000_1000t_rx_status_ok 2748 : e1000_1000t_rx_status_not_ok; 2749 2750 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2751 ? e1000_1000t_rx_status_ok 2752 : e1000_1000t_rx_status_not_ok; 2753 } else { 2754 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2755 phy->local_rx = e1000_1000t_rx_status_undefined; 2756 phy->remote_rx = e1000_1000t_rx_status_undefined; 2757 } 2758 2759 return ret_val; 2760 } 2761 2762 /** 2763 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2764 * @hw: pointer to the HW structure 2765 * 2766 * Populates "phy" structure with various feature states. 2767 **/ 2768 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2769 { 2770 struct e1000_phy_info *phy = &hw->phy; 2771 s32 ret_val; 2772 u16 data; 2773 bool link; 2774 2775 DEBUGFUNC("e1000_get_phy_info_ife"); 2776 2777 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2778 if (ret_val) 2779 return ret_val; 2780 2781 if (!link) { 2782 DEBUGOUT("Phy info is only valid if link is up\n"); 2783 return -E1000_ERR_CONFIG; 2784 } 2785 2786 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2787 if (ret_val) 2788 return ret_val; 2789 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2790 2791 if (phy->polarity_correction) { 2792 ret_val = e1000_check_polarity_ife(hw); 2793 if (ret_val) 2794 return ret_val; 2795 } else { 2796 /* Polarity is forced */ 2797 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) 2798 ? e1000_rev_polarity_reversed 2799 : e1000_rev_polarity_normal); 2800 } 2801 2802 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2803 if (ret_val) 2804 return ret_val; 2805 2806 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2807 2808 /* The following parameters are undefined for 10/100 operation. */ 2809 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2810 phy->local_rx = e1000_1000t_rx_status_undefined; 2811 phy->remote_rx = e1000_1000t_rx_status_undefined; 2812 2813 return E1000_SUCCESS; 2814 } 2815 2816 /** 2817 * e1000_phy_sw_reset_generic - PHY software reset 2818 * @hw: pointer to the HW structure 2819 * 2820 * Does a software reset of the PHY by reading the PHY control register and 2821 * setting/write the control register reset bit to the PHY. 2822 **/ 2823 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2824 { 2825 s32 ret_val; 2826 u16 phy_ctrl; 2827 2828 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2829 2830 if (!hw->phy.ops.read_reg) 2831 return E1000_SUCCESS; 2832 2833 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2834 if (ret_val) 2835 return ret_val; 2836 2837 phy_ctrl |= MII_CR_RESET; 2838 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2839 if (ret_val) 2840 return ret_val; 2841 2842 usec_delay(1); 2843 2844 return ret_val; 2845 } 2846 2847 /** 2848 * e1000_phy_hw_reset_generic - PHY hardware reset 2849 * @hw: pointer to the HW structure 2850 * 2851 * Verify the reset block is not blocking us from resetting. Acquire 2852 * semaphore (if necessary) and read/set/write the device control reset 2853 * bit in the PHY. Wait the appropriate delay time for the device to 2854 * reset and release the semaphore (if necessary). 2855 **/ 2856 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2857 { 2858 struct e1000_phy_info *phy = &hw->phy; 2859 s32 ret_val; 2860 u32 ctrl; 2861 2862 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2863 2864 if (phy->ops.check_reset_block) { 2865 ret_val = phy->ops.check_reset_block(hw); 2866 if (ret_val) 2867 return E1000_SUCCESS; 2868 } 2869 2870 ret_val = phy->ops.acquire(hw); 2871 if (ret_val) 2872 return ret_val; 2873 2874 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2875 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2876 E1000_WRITE_FLUSH(hw); 2877 2878 usec_delay(phy->reset_delay_us); 2879 2880 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2881 E1000_WRITE_FLUSH(hw); 2882 2883 usec_delay(150); 2884 2885 phy->ops.release(hw); 2886 2887 return phy->ops.get_cfg_done(hw); 2888 } 2889 2890 /** 2891 * e1000_get_cfg_done_generic - Generic configuration done 2892 * @hw: pointer to the HW structure 2893 * 2894 * Generic function to wait 10 milli-seconds for configuration to complete 2895 * and return success. 2896 **/ 2897 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2898 { 2899 DEBUGFUNC("e1000_get_cfg_done_generic"); 2900 2901 msec_delay_irq(10); 2902 2903 return E1000_SUCCESS; 2904 } 2905 2906 /** 2907 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2908 * @hw: pointer to the HW structure 2909 * 2910 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2911 **/ 2912 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2913 { 2914 DEBUGOUT("Running IGP 3 PHY init script\n"); 2915 2916 /* PHY init IGP 3 */ 2917 /* Enable rise/fall, 10-mode work in class-A */ 2918 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2919 /* Remove all caps from Replica path filter */ 2920 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2921 /* Bias trimming for ADC, AFE and Driver (Default) */ 2922 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2923 /* Increase Hybrid poly bias */ 2924 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2925 /* Add 4% to Tx amplitude in Gig mode */ 2926 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2927 /* Disable trimming (TTT) */ 2928 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2929 /* Poly DC correction to 94.6% + 2% for all channels */ 2930 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2931 /* ABS DC correction to 95.9% */ 2932 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2933 /* BG temp curve trim */ 2934 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2935 /* Increasing ADC OPAMP stage 1 currents to max */ 2936 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2937 /* Force 1000 ( required for enabling PHY regs configuration) */ 2938 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2939 /* Set upd_freq to 6 */ 2940 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2941 /* Disable NPDFE */ 2942 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2943 /* Disable adaptive fixed FFE (Default) */ 2944 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2945 /* Enable FFE hysteresis */ 2946 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2947 /* Fixed FFE for short cable lengths */ 2948 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2949 /* Fixed FFE for medium cable lengths */ 2950 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2951 /* Fixed FFE for long cable lengths */ 2952 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2953 /* Enable Adaptive Clip Threshold */ 2954 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2955 /* AHT reset limit to 1 */ 2956 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2957 /* Set AHT master delay to 127 msec */ 2958 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2959 /* Set scan bits for AHT */ 2960 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2961 /* Set AHT Preset bits */ 2962 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2963 /* Change integ_factor of channel A to 3 */ 2964 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2965 /* Change prop_factor of channels BCD to 8 */ 2966 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2967 /* Change cg_icount + enable integbp for channels BCD */ 2968 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2969 /* Change cg_icount + enable integbp + change prop_factor_master 2970 * to 8 for channel A 2971 */ 2972 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2973 /* Disable AHT in Slave mode on channel A */ 2974 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2975 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2976 * Enable SPD+B2B 2977 */ 2978 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2979 /* Enable restart AN on an1000_dis change */ 2980 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2981 /* Enable wh_fifo read clock in 10/100 modes */ 2982 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2983 /* Restart AN, Speed selection is 1000 */ 2984 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2985 2986 return E1000_SUCCESS; 2987 } 2988 2989 /** 2990 * e1000_get_phy_type_from_id - Get PHY type from id 2991 * @phy_id: phy_id read from the phy 2992 * 2993 * Returns the phy type from the id. 2994 **/ 2995 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2996 { 2997 enum e1000_phy_type phy_type = e1000_phy_unknown; 2998 2999 switch (phy_id) { 3000 case M88E1000_I_PHY_ID: 3001 case M88E1000_E_PHY_ID: 3002 case M88E1111_I_PHY_ID: 3003 case M88E1011_I_PHY_ID: 3004 case M88E1543_E_PHY_ID: 3005 case M88E1512_E_PHY_ID: 3006 case I347AT4_E_PHY_ID: 3007 case M88E1112_E_PHY_ID: 3008 case M88E1340M_E_PHY_ID: 3009 phy_type = e1000_phy_m88; 3010 break; 3011 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 3012 phy_type = e1000_phy_igp_2; 3013 break; 3014 case GG82563_E_PHY_ID: 3015 phy_type = e1000_phy_gg82563; 3016 break; 3017 case IGP03E1000_E_PHY_ID: 3018 phy_type = e1000_phy_igp_3; 3019 break; 3020 case IFE_E_PHY_ID: 3021 case IFE_PLUS_E_PHY_ID: 3022 case IFE_C_E_PHY_ID: 3023 phy_type = e1000_phy_ife; 3024 break; 3025 case BME1000_E_PHY_ID: 3026 case BME1000_E_PHY_ID_R2: 3027 phy_type = e1000_phy_bm; 3028 break; 3029 case I82578_E_PHY_ID: 3030 phy_type = e1000_phy_82578; 3031 break; 3032 case I82577_E_PHY_ID: 3033 phy_type = e1000_phy_82577; 3034 break; 3035 case I82579_E_PHY_ID: 3036 phy_type = e1000_phy_82579; 3037 break; 3038 case I82580_I_PHY_ID: 3039 phy_type = e1000_phy_82580; 3040 break; 3041 case I217_E_PHY_ID: 3042 phy_type = e1000_phy_i217; 3043 break; 3044 case I210_I_PHY_ID: 3045 phy_type = e1000_phy_i210; 3046 break; 3047 default: 3048 phy_type = e1000_phy_unknown; 3049 break; 3050 } 3051 return phy_type; 3052 } 3053 3054 /** 3055 * e1000_determine_phy_address - Determines PHY address. 3056 * @hw: pointer to the HW structure 3057 * 3058 * This uses a trial and error method to loop through possible PHY 3059 * addresses. It tests each by reading the PHY ID registers and 3060 * checking for a match. 3061 **/ 3062 s32 e1000_determine_phy_address(struct e1000_hw *hw) 3063 { 3064 u32 phy_addr = 0; 3065 u32 i; 3066 enum e1000_phy_type phy_type = e1000_phy_unknown; 3067 3068 hw->phy.id = phy_type; 3069 3070 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 3071 hw->phy.addr = phy_addr; 3072 i = 0; 3073 3074 do { 3075 e1000_get_phy_id(hw); 3076 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 3077 3078 /* If phy_type is valid, break - we found our 3079 * PHY address 3080 */ 3081 if (phy_type != e1000_phy_unknown) 3082 return E1000_SUCCESS; 3083 3084 msec_delay(1); 3085 i++; 3086 } while (i < 10); 3087 } 3088 3089 return -E1000_ERR_PHY_TYPE; 3090 } 3091 3092 /** 3093 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 3094 * @page: page to access 3095 * @reg: register to access 3096 * 3097 * Returns the phy address for the page requested. 3098 **/ 3099 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 3100 { 3101 u32 phy_addr = 2; 3102 3103 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 3104 phy_addr = 1; 3105 3106 return phy_addr; 3107 } 3108 3109 /** 3110 * e1000_write_phy_reg_bm - Write BM PHY register 3111 * @hw: pointer to the HW structure 3112 * @offset: register offset to write to 3113 * @data: data to write at register offset 3114 * 3115 * Acquires semaphore, if necessary, then writes the data to PHY register 3116 * at the offset. Release any acquired semaphores before exiting. 3117 **/ 3118 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 3119 { 3120 s32 ret_val; 3121 u32 page = offset >> IGP_PAGE_SHIFT; 3122 3123 DEBUGFUNC("e1000_write_phy_reg_bm"); 3124 3125 ret_val = hw->phy.ops.acquire(hw); 3126 if (ret_val) 3127 return ret_val; 3128 3129 /* Page 800 works differently than the rest so it has its own func */ 3130 if (page == BM_WUC_PAGE) { 3131 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3132 FALSE, false); 3133 goto release; 3134 } 3135 3136 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3137 3138 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3139 u32 page_shift, page_select; 3140 3141 /* Page select is register 31 for phy address 1 and 22 for 3142 * phy address 2 and 3. Page select is shifted only for 3143 * phy address 1. 3144 */ 3145 if (hw->phy.addr == 1) { 3146 page_shift = IGP_PAGE_SHIFT; 3147 page_select = IGP01E1000_PHY_PAGE_SELECT; 3148 } else { 3149 page_shift = 0; 3150 page_select = BM_PHY_PAGE_SELECT; 3151 } 3152 3153 /* Page is shifted left, PHY expects (page x 32) */ 3154 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3155 (page << page_shift)); 3156 if (ret_val) 3157 goto release; 3158 } 3159 3160 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3161 data); 3162 3163 release: 3164 hw->phy.ops.release(hw); 3165 return ret_val; 3166 } 3167 3168 /** 3169 * e1000_read_phy_reg_bm - Read BM PHY register 3170 * @hw: pointer to the HW structure 3171 * @offset: register offset to be read 3172 * @data: pointer to the read data 3173 * 3174 * Acquires semaphore, if necessary, then reads the PHY register at offset 3175 * and storing the retrieved information in data. Release any acquired 3176 * semaphores before exiting. 3177 **/ 3178 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 3179 { 3180 s32 ret_val; 3181 u32 page = offset >> IGP_PAGE_SHIFT; 3182 3183 DEBUGFUNC("e1000_read_phy_reg_bm"); 3184 3185 ret_val = hw->phy.ops.acquire(hw); 3186 if (ret_val) 3187 return ret_val; 3188 3189 /* Page 800 works differently than the rest so it has its own func */ 3190 if (page == BM_WUC_PAGE) { 3191 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3192 TRUE, FALSE); 3193 goto release; 3194 } 3195 3196 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3197 3198 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3199 u32 page_shift, page_select; 3200 3201 /* Page select is register 31 for phy address 1 and 22 for 3202 * phy address 2 and 3. Page select is shifted only for 3203 * phy address 1. 3204 */ 3205 if (hw->phy.addr == 1) { 3206 page_shift = IGP_PAGE_SHIFT; 3207 page_select = IGP01E1000_PHY_PAGE_SELECT; 3208 } else { 3209 page_shift = 0; 3210 page_select = BM_PHY_PAGE_SELECT; 3211 } 3212 3213 /* Page is shifted left, PHY expects (page x 32) */ 3214 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3215 (page << page_shift)); 3216 if (ret_val) 3217 goto release; 3218 } 3219 3220 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3221 data); 3222 release: 3223 hw->phy.ops.release(hw); 3224 return ret_val; 3225 } 3226 3227 /** 3228 * e1000_read_phy_reg_bm2 - Read BM PHY register 3229 * @hw: pointer to the HW structure 3230 * @offset: register offset to be read 3231 * @data: pointer to the read data 3232 * 3233 * Acquires semaphore, if necessary, then reads the PHY register at offset 3234 * and storing the retrieved information in data. Release any acquired 3235 * semaphores before exiting. 3236 **/ 3237 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3238 { 3239 s32 ret_val; 3240 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3241 3242 DEBUGFUNC("e1000_read_phy_reg_bm2"); 3243 3244 ret_val = hw->phy.ops.acquire(hw); 3245 if (ret_val) 3246 return ret_val; 3247 3248 /* Page 800 works differently than the rest so it has its own func */ 3249 if (page == BM_WUC_PAGE) { 3250 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3251 TRUE, FALSE); 3252 goto release; 3253 } 3254 3255 hw->phy.addr = 1; 3256 3257 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3258 /* Page is shifted left, PHY expects (page x 32) */ 3259 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3260 page); 3261 3262 if (ret_val) 3263 goto release; 3264 } 3265 3266 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3267 data); 3268 release: 3269 hw->phy.ops.release(hw); 3270 return ret_val; 3271 } 3272 3273 /** 3274 * e1000_write_phy_reg_bm2 - Write BM PHY register 3275 * @hw: pointer to the HW structure 3276 * @offset: register offset to write to 3277 * @data: data to write at register offset 3278 * 3279 * Acquires semaphore, if necessary, then writes the data to PHY register 3280 * at the offset. Release any acquired semaphores before exiting. 3281 **/ 3282 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3283 { 3284 s32 ret_val; 3285 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3286 3287 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3288 3289 ret_val = hw->phy.ops.acquire(hw); 3290 if (ret_val) 3291 return ret_val; 3292 3293 /* Page 800 works differently than the rest so it has its own func */ 3294 if (page == BM_WUC_PAGE) { 3295 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3296 FALSE, false); 3297 goto release; 3298 } 3299 3300 hw->phy.addr = 1; 3301 3302 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3303 /* Page is shifted left, PHY expects (page x 32) */ 3304 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3305 page); 3306 3307 if (ret_val) 3308 goto release; 3309 } 3310 3311 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3312 data); 3313 3314 release: 3315 hw->phy.ops.release(hw); 3316 return ret_val; 3317 } 3318 3319 /** 3320 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 3321 * @hw: pointer to the HW structure 3322 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 3323 * 3324 * Assumes semaphore already acquired and phy_reg points to a valid memory 3325 * address to store contents of the BM_WUC_ENABLE_REG register. 3326 **/ 3327 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3328 { 3329 s32 ret_val; 3330 u16 temp; 3331 3332 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm"); 3333 3334 if (!phy_reg) 3335 return -E1000_ERR_PARAM; 3336 3337 /* All page select, port ctrl and wakeup registers use phy address 1 */ 3338 hw->phy.addr = 1; 3339 3340 /* Select Port Control Registers page */ 3341 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3342 if (ret_val) { 3343 DEBUGOUT("Could not set Port Control page\n"); 3344 return ret_val; 3345 } 3346 3347 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3348 if (ret_val) { 3349 DEBUGOUT2("Could not read PHY register %d.%d\n", 3350 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3351 return ret_val; 3352 } 3353 3354 /* Enable both PHY wakeup mode and Wakeup register page writes. 3355 * Prevent a power state change by disabling ME and Host PHY wakeup. 3356 */ 3357 temp = *phy_reg; 3358 temp |= BM_WUC_ENABLE_BIT; 3359 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 3360 3361 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 3362 if (ret_val) { 3363 DEBUGOUT2("Could not write PHY register %d.%d\n", 3364 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3365 return ret_val; 3366 } 3367 3368 /* Select Host Wakeup Registers page - caller now able to write 3369 * registers on the Wakeup registers page 3370 */ 3371 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3372 } 3373 3374 /** 3375 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 3376 * @hw: pointer to the HW structure 3377 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 3378 * 3379 * Restore BM_WUC_ENABLE_REG to its original value. 3380 * 3381 * Assumes semaphore already acquired and *phy_reg is the contents of the 3382 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 3383 * caller. 3384 **/ 3385 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3386 { 3387 s32 ret_val; 3388 3389 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); 3390 3391 if (!phy_reg) 3392 return -E1000_ERR_PARAM; 3393 3394 /* Select Port Control Registers page */ 3395 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3396 if (ret_val) { 3397 DEBUGOUT("Could not set Port Control page\n"); 3398 return ret_val; 3399 } 3400 3401 /* Restore 769.17 to its original value */ 3402 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 3403 if (ret_val) 3404 DEBUGOUT2("Could not restore PHY register %d.%d\n", 3405 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3406 3407 return ret_val; 3408 } 3409 3410 /** 3411 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 3412 * @hw: pointer to the HW structure 3413 * @offset: register offset to be read or written 3414 * @data: pointer to the data to read or write 3415 * @read: determines if operation is read or write 3416 * @page_set: BM_WUC_PAGE already set and access enabled 3417 * 3418 * Read the PHY register at offset and store the retrieved information in 3419 * data, or write data to PHY register at offset. Note the procedure to 3420 * access the PHY wakeup registers is different than reading the other PHY 3421 * registers. It works as such: 3422 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 3423 * 2) Set page to 800 for host (801 if we were manageability) 3424 * 3) Write the address using the address opcode (0x11) 3425 * 4) Read or write the data using the data opcode (0x12) 3426 * 5) Restore 769.17.2 to its original value 3427 * 3428 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 3429 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 3430 * 3431 * Assumes semaphore is already acquired. When page_set==TRUE, assumes 3432 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 3433 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 3434 **/ 3435 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3436 u16 *data, bool read, bool page_set) 3437 { 3438 s32 ret_val; 3439 u16 reg = BM_PHY_REG_NUM(offset); 3440 u16 page = BM_PHY_REG_PAGE(offset); 3441 u16 phy_reg = 0; 3442 3443 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3444 3445 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 3446 if ((hw->mac.type == e1000_pchlan) && 3447 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3448 DEBUGOUT1("Attempting to access page %d while gig enabled.\n", 3449 page); 3450 3451 if (!page_set) { 3452 /* Enable access to PHY wakeup registers */ 3453 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3454 if (ret_val) { 3455 DEBUGOUT("Could not enable PHY wakeup reg access\n"); 3456 return ret_val; 3457 } 3458 } 3459 3460 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg); 3461 3462 /* Write the Wakeup register page offset value using opcode 0x11 */ 3463 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3464 if (ret_val) { 3465 DEBUGOUT1("Could not write address opcode to page %d\n", page); 3466 return ret_val; 3467 } 3468 3469 if (read) { 3470 /* Read the Wakeup register page value using opcode 0x12 */ 3471 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3472 data); 3473 } else { 3474 /* Write the Wakeup register page value using opcode 0x12 */ 3475 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3476 *data); 3477 } 3478 3479 if (ret_val) { 3480 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg); 3481 return ret_val; 3482 } 3483 3484 if (!page_set) 3485 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3486 3487 return ret_val; 3488 } 3489 3490 /** 3491 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3492 * @hw: pointer to the HW structure 3493 * 3494 * In the case of a PHY power down to save power, or to turn off link during a 3495 * driver unload, or wake on lan is not enabled, restore the link to previous 3496 * settings. 3497 **/ 3498 void e1000_power_up_phy_copper(struct e1000_hw *hw) 3499 { 3500 u16 mii_reg = 0; 3501 3502 /* The PHY will retain its settings across a power down/up cycle */ 3503 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3504 mii_reg &= ~MII_CR_POWER_DOWN; 3505 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3506 } 3507 3508 /** 3509 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3510 * @hw: pointer to the HW structure 3511 * 3512 * In the case of a PHY power down to save power, or to turn off link during a 3513 * driver unload, or wake on lan is not enabled, restore the link to previous 3514 * settings. 3515 **/ 3516 void e1000_power_down_phy_copper(struct e1000_hw *hw) 3517 { 3518 u16 mii_reg = 0; 3519 3520 /* The PHY will retain its settings across a power down/up cycle */ 3521 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3522 mii_reg |= MII_CR_POWER_DOWN; 3523 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3524 msec_delay(1); 3525 } 3526 3527 /** 3528 * __e1000_read_phy_reg_hv - Read HV PHY register 3529 * @hw: pointer to the HW structure 3530 * @offset: register offset to be read 3531 * @data: pointer to the read data 3532 * @locked: semaphore has already been acquired or not 3533 * @page_set: BM_WUC_PAGE already set and access enabled 3534 * 3535 * Acquires semaphore, if necessary, then reads the PHY register at offset 3536 * and stores the retrieved information in data. Release any acquired 3537 * semaphore before exiting. 3538 **/ 3539 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3540 bool locked, bool page_set) 3541 { 3542 s32 ret_val; 3543 u16 page = BM_PHY_REG_PAGE(offset); 3544 u16 reg = BM_PHY_REG_NUM(offset); 3545 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3546 3547 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3548 3549 if (!locked) { 3550 ret_val = hw->phy.ops.acquire(hw); 3551 if (ret_val) 3552 return ret_val; 3553 } 3554 /* Page 800 works differently than the rest so it has its own func */ 3555 if (page == BM_WUC_PAGE) { 3556 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3557 TRUE, page_set); 3558 goto out; 3559 } 3560 3561 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3562 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3563 data, TRUE); 3564 goto out; 3565 } 3566 3567 if (!page_set) { 3568 if (page == HV_INTC_FC_PAGE_START) 3569 page = 0; 3570 3571 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3572 /* Page is shifted left, PHY expects (page x 32) */ 3573 ret_val = e1000_set_page_igp(hw, 3574 (page << IGP_PAGE_SHIFT)); 3575 3576 hw->phy.addr = phy_addr; 3577 3578 if (ret_val) 3579 goto out; 3580 } 3581 } 3582 3583 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3584 page << IGP_PAGE_SHIFT, reg); 3585 3586 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3587 data); 3588 out: 3589 if (!locked) 3590 hw->phy.ops.release(hw); 3591 3592 return ret_val; 3593 } 3594 3595 /** 3596 * e1000_read_phy_reg_hv - Read HV PHY register 3597 * @hw: pointer to the HW structure 3598 * @offset: register offset to be read 3599 * @data: pointer to the read data 3600 * 3601 * Acquires semaphore then reads the PHY register at offset and stores 3602 * the retrieved information in data. Release the acquired semaphore 3603 * before exiting. 3604 **/ 3605 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3606 { 3607 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, false); 3608 } 3609 3610 /** 3611 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3612 * @hw: pointer to the HW structure 3613 * @offset: register offset to be read 3614 * @data: pointer to the read data 3615 * 3616 * Reads the PHY register at offset and stores the retrieved information 3617 * in data. Assumes semaphore already acquired. 3618 **/ 3619 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3620 { 3621 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3622 } 3623 3624 /** 3625 * e1000_read_phy_reg_page_hv - Read HV PHY register 3626 * @hw: pointer to the HW structure 3627 * @offset: register offset to write to 3628 * @data: data to write at register offset 3629 * 3630 * Reads the PHY register at offset and stores the retrieved information 3631 * in data. Assumes semaphore already acquired and page already set. 3632 **/ 3633 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3634 { 3635 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true); 3636 } 3637 3638 /** 3639 * __e1000_write_phy_reg_hv - Write HV PHY register 3640 * @hw: pointer to the HW structure 3641 * @offset: register offset to write to 3642 * @data: data to write at register offset 3643 * @locked: semaphore has already been acquired or not 3644 * @page_set: BM_WUC_PAGE already set and access enabled 3645 * 3646 * Acquires semaphore, if necessary, then writes the data to PHY register 3647 * at the offset. Release any acquired semaphores before exiting. 3648 **/ 3649 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3650 bool locked, bool page_set) 3651 { 3652 s32 ret_val; 3653 u16 page = BM_PHY_REG_PAGE(offset); 3654 u16 reg = BM_PHY_REG_NUM(offset); 3655 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3656 3657 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3658 3659 if (!locked) { 3660 ret_val = hw->phy.ops.acquire(hw); 3661 if (ret_val) 3662 return ret_val; 3663 } 3664 /* Page 800 works differently than the rest so it has its own func */ 3665 if (page == BM_WUC_PAGE) { 3666 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3667 FALSE, page_set); 3668 goto out; 3669 } 3670 3671 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3672 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3673 &data, FALSE); 3674 goto out; 3675 } 3676 3677 if (!page_set) { 3678 if (page == HV_INTC_FC_PAGE_START) 3679 page = 0; 3680 3681 /* Workaround MDIO accesses being disabled after entering IEEE 3682 * Power Down (when bit 11 of the PHY Control register is set) 3683 */ 3684 if ((hw->phy.type == e1000_phy_82578) && 3685 (hw->phy.revision >= 1) && 3686 (hw->phy.addr == 2) && 3687 !(MAX_PHY_REG_ADDRESS & reg) && 3688 (data & (1 << 11))) { 3689 u16 data2 = 0x7EFF; 3690 ret_val = e1000_access_phy_debug_regs_hv(hw, 3691 (1 << 6) | 0x3, 3692 &data2, FALSE); 3693 if (ret_val) 3694 goto out; 3695 } 3696 3697 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3698 /* Page is shifted left, PHY expects (page x 32) */ 3699 ret_val = e1000_set_page_igp(hw, 3700 (page << IGP_PAGE_SHIFT)); 3701 3702 hw->phy.addr = phy_addr; 3703 3704 if (ret_val) 3705 goto out; 3706 } 3707 } 3708 3709 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3710 page << IGP_PAGE_SHIFT, reg); 3711 3712 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3713 data); 3714 3715 out: 3716 if (!locked) 3717 hw->phy.ops.release(hw); 3718 3719 return ret_val; 3720 } 3721 3722 /** 3723 * e1000_write_phy_reg_hv - Write HV PHY register 3724 * @hw: pointer to the HW structure 3725 * @offset: register offset to write to 3726 * @data: data to write at register offset 3727 * 3728 * Acquires semaphore then writes the data to PHY register at the offset. 3729 * Release the acquired semaphores before exiting. 3730 **/ 3731 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3732 { 3733 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, false); 3734 } 3735 3736 /** 3737 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3738 * @hw: pointer to the HW structure 3739 * @offset: register offset to write to 3740 * @data: data to write at register offset 3741 * 3742 * Writes the data to PHY register at the offset. Assumes semaphore 3743 * already acquired. 3744 **/ 3745 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3746 { 3747 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3748 } 3749 3750 /** 3751 * e1000_write_phy_reg_page_hv - Write HV PHY register 3752 * @hw: pointer to the HW structure 3753 * @offset: register offset to write to 3754 * @data: data to write at register offset 3755 * 3756 * Writes the data to PHY register at the offset. Assumes semaphore 3757 * already acquired and page already set. 3758 **/ 3759 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3760 { 3761 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true); 3762 } 3763 3764 /** 3765 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3766 * @page: page to be accessed 3767 **/ 3768 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3769 { 3770 u32 phy_addr = 2; 3771 3772 if (page >= HV_INTC_FC_PAGE_START) 3773 phy_addr = 1; 3774 3775 return phy_addr; 3776 } 3777 3778 /** 3779 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3780 * @hw: pointer to the HW structure 3781 * @offset: register offset to be read or written 3782 * @data: pointer to the data to be read or written 3783 * @read: determines if operation is read or write 3784 * 3785 * Reads the PHY register at offset and stores the retreived information 3786 * in data. Assumes semaphore already acquired. Note that the procedure 3787 * to access these regs uses the address port and data port to read/write. 3788 * These accesses done with PHY address 2 and without using pages. 3789 **/ 3790 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3791 u16 *data, bool read) 3792 { 3793 s32 ret_val; 3794 u32 addr_reg; 3795 u32 data_reg; 3796 3797 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3798 3799 /* This takes care of the difference with desktop vs mobile phy */ 3800 addr_reg = ((hw->phy.type == e1000_phy_82578) ? 3801 I82578_ADDR_REG : I82577_ADDR_REG); 3802 data_reg = addr_reg + 1; 3803 3804 /* All operations in this function are phy address 2 */ 3805 hw->phy.addr = 2; 3806 3807 /* masking with 0x3F to remove the page from offset */ 3808 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3809 if (ret_val) { 3810 DEBUGOUT("Could not write the Address Offset port register\n"); 3811 return ret_val; 3812 } 3813 3814 /* Read or write the data value next */ 3815 if (read) 3816 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3817 else 3818 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3819 3820 if (ret_val) 3821 DEBUGOUT("Could not access the Data port register\n"); 3822 3823 return ret_val; 3824 } 3825 3826 /** 3827 * e1000_link_stall_workaround_hv - Si workaround 3828 * @hw: pointer to the HW structure 3829 * 3830 * This function works around a Si bug where the link partner can get 3831 * a link up indication before the PHY does. If small packets are sent 3832 * by the link partner they can be placed in the packet buffer without 3833 * being properly accounted for by the PHY and will stall preventing 3834 * further packets from being received. The workaround is to clear the 3835 * packet buffer after the PHY detects link up. 3836 **/ 3837 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3838 { 3839 s32 ret_val = E1000_SUCCESS; 3840 u16 data; 3841 3842 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3843 3844 if (hw->phy.type != e1000_phy_82578) 3845 return E1000_SUCCESS; 3846 3847 /* Do not apply workaround if in PHY loopback bit 14 set */ 3848 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3849 if (data & PHY_CONTROL_LB) 3850 return E1000_SUCCESS; 3851 3852 /* check if link is up and at 1Gbps */ 3853 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3854 if (ret_val) 3855 return ret_val; 3856 3857 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3858 BM_CS_STATUS_SPEED_MASK); 3859 3860 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3861 BM_CS_STATUS_SPEED_1000)) 3862 return E1000_SUCCESS; 3863 3864 msec_delay(200); 3865 3866 /* flush the packets in the fifo buffer */ 3867 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3868 (HV_MUX_DATA_CTRL_GEN_TO_MAC | 3869 HV_MUX_DATA_CTRL_FORCE_SPEED)); 3870 if (ret_val) 3871 return ret_val; 3872 3873 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3874 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3875 } 3876 3877 /** 3878 * e1000_check_polarity_82577 - Checks the polarity. 3879 * @hw: pointer to the HW structure 3880 * 3881 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3882 * 3883 * Polarity is determined based on the PHY specific status register. 3884 **/ 3885 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3886 { 3887 struct e1000_phy_info *phy = &hw->phy; 3888 s32 ret_val; 3889 u16 data; 3890 3891 DEBUGFUNC("e1000_check_polarity_82577"); 3892 3893 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3894 3895 if (!ret_val) 3896 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) 3897 ? e1000_rev_polarity_reversed 3898 : e1000_rev_polarity_normal); 3899 3900 return ret_val; 3901 } 3902 3903 /** 3904 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3905 * @hw: pointer to the HW structure 3906 * 3907 * Calls the PHY setup function to force speed and duplex. 3908 **/ 3909 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3910 { 3911 struct e1000_phy_info *phy = &hw->phy; 3912 s32 ret_val; 3913 u16 phy_data; 3914 bool link; 3915 3916 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3917 3918 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3919 if (ret_val) 3920 return ret_val; 3921 3922 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3923 3924 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3925 if (ret_val) 3926 return ret_val; 3927 3928 usec_delay(1); 3929 3930 if (phy->autoneg_wait_to_complete) { 3931 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3932 3933 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3934 100000, &link); 3935 if (ret_val) 3936 return ret_val; 3937 3938 if (!link) 3939 DEBUGOUT("Link taking longer than expected.\n"); 3940 3941 /* Try once more */ 3942 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3943 100000, &link); 3944 } 3945 3946 return ret_val; 3947 } 3948 3949 /** 3950 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3951 * @hw: pointer to the HW structure 3952 * 3953 * Read PHY status to determine if link is up. If link is up, then 3954 * set/determine 10base-T extended distance and polarity correction. Read 3955 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3956 * determine on the cable length, local and remote receiver. 3957 **/ 3958 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3959 { 3960 struct e1000_phy_info *phy = &hw->phy; 3961 s32 ret_val; 3962 u16 data; 3963 bool link; 3964 3965 DEBUGFUNC("e1000_get_phy_info_82577"); 3966 3967 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3968 if (ret_val) 3969 return ret_val; 3970 3971 if (!link) { 3972 DEBUGOUT("Phy info is only valid if link is up\n"); 3973 return -E1000_ERR_CONFIG; 3974 } 3975 3976 phy->polarity_correction = TRUE; 3977 3978 ret_val = e1000_check_polarity_82577(hw); 3979 if (ret_val) 3980 return ret_val; 3981 3982 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3983 if (ret_val) 3984 return ret_val; 3985 3986 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3987 3988 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3989 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3990 ret_val = hw->phy.ops.get_cable_length(hw); 3991 if (ret_val) 3992 return ret_val; 3993 3994 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3995 if (ret_val) 3996 return ret_val; 3997 3998 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3999 ? e1000_1000t_rx_status_ok 4000 : e1000_1000t_rx_status_not_ok; 4001 4002 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 4003 ? e1000_1000t_rx_status_ok 4004 : e1000_1000t_rx_status_not_ok; 4005 } else { 4006 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 4007 phy->local_rx = e1000_1000t_rx_status_undefined; 4008 phy->remote_rx = e1000_1000t_rx_status_undefined; 4009 } 4010 4011 return E1000_SUCCESS; 4012 } 4013 4014 /** 4015 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 4016 * @hw: pointer to the HW structure 4017 * 4018 * Reads the diagnostic status register and verifies result is valid before 4019 * placing it in the phy_cable_length field. 4020 **/ 4021 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 4022 { 4023 struct e1000_phy_info *phy = &hw->phy; 4024 s32 ret_val; 4025 u16 phy_data, length; 4026 4027 DEBUGFUNC("e1000_get_cable_length_82577"); 4028 4029 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 4030 if (ret_val) 4031 return ret_val; 4032 4033 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 4034 I82577_DSTATUS_CABLE_LENGTH_SHIFT); 4035 4036 if (length == E1000_CABLE_LENGTH_UNDEFINED) 4037 return -E1000_ERR_PHY; 4038 4039 phy->cable_length = length; 4040 4041 return E1000_SUCCESS; 4042 } 4043 4044 /** 4045 * e1000_write_phy_reg_gs40g - Write GS40G PHY register 4046 * @hw: pointer to the HW structure 4047 * @offset: register offset to write to 4048 * @data: data to write at register offset 4049 * 4050 * Acquires semaphore, if necessary, then writes the data to PHY register 4051 * at the offset. Release any acquired semaphores before exiting. 4052 **/ 4053 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 4054 { 4055 s32 ret_val; 4056 u16 page = offset >> GS40G_PAGE_SHIFT; 4057 4058 DEBUGFUNC("e1000_write_phy_reg_gs40g"); 4059 4060 offset = offset & GS40G_OFFSET_MASK; 4061 ret_val = hw->phy.ops.acquire(hw); 4062 if (ret_val) 4063 return ret_val; 4064 4065 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4066 if (ret_val) 4067 goto release; 4068 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 4069 4070 release: 4071 hw->phy.ops.release(hw); 4072 return ret_val; 4073 } 4074 4075 /** 4076 * e1000_read_phy_reg_gs40g - Read GS40G PHY register 4077 * @hw: pointer to the HW structure 4078 * @offset: lower half is register offset to read to 4079 * upper half is page to use. 4080 * @data: data to read at register offset 4081 * 4082 * Acquires semaphore, if necessary, then reads the data in the PHY register 4083 * at the offset. Release any acquired semaphores before exiting. 4084 **/ 4085 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 4086 { 4087 s32 ret_val; 4088 u16 page = offset >> GS40G_PAGE_SHIFT; 4089 4090 DEBUGFUNC("e1000_read_phy_reg_gs40g"); 4091 4092 offset = offset & GS40G_OFFSET_MASK; 4093 ret_val = hw->phy.ops.acquire(hw); 4094 if (ret_val) 4095 return ret_val; 4096 4097 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4098 if (ret_val) 4099 goto release; 4100 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 4101 4102 release: 4103 hw->phy.ops.release(hw); 4104 return ret_val; 4105 } 4106 4107 /** 4108 * e1000_read_phy_reg_mphy - Read mPHY control register 4109 * @hw: pointer to the HW structure 4110 * @address: address to be read 4111 * @data: pointer to the read data 4112 * 4113 * Reads the mPHY control register in the PHY at offset and stores the 4114 * information read to data. 4115 **/ 4116 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data) 4117 { 4118 u32 mphy_ctrl = 0; 4119 bool locked = FALSE; 4120 bool ready; 4121 4122 DEBUGFUNC("e1000_read_phy_reg_mphy"); 4123 4124 /* Check if mPHY is ready to read/write operations */ 4125 ready = e1000_is_mphy_ready(hw); 4126 if (!ready) 4127 return -E1000_ERR_PHY; 4128 4129 /* Check if mPHY access is disabled and enable it if so */ 4130 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4131 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4132 locked = TRUE; 4133 ready = e1000_is_mphy_ready(hw); 4134 if (!ready) 4135 return -E1000_ERR_PHY; 4136 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4137 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4138 } 4139 4140 /* Set the address that we want to read */ 4141 ready = e1000_is_mphy_ready(hw); 4142 if (!ready) 4143 return -E1000_ERR_PHY; 4144 4145 /* We mask address, because we want to use only current lane */ 4146 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK & 4147 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) | 4148 (address & E1000_MPHY_ADDRESS_MASK); 4149 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4150 4151 /* Read data from the address */ 4152 ready = e1000_is_mphy_ready(hw); 4153 if (!ready) 4154 return -E1000_ERR_PHY; 4155 *data = E1000_READ_REG(hw, E1000_MPHY_DATA); 4156 4157 /* Disable access to mPHY if it was originally disabled */ 4158 if (locked) 4159 ready = e1000_is_mphy_ready(hw); 4160 if (!ready) 4161 return -E1000_ERR_PHY; 4162 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4163 E1000_MPHY_DIS_ACCESS); 4164 4165 return E1000_SUCCESS; 4166 } 4167 4168 /** 4169 * e1000_write_phy_reg_mphy - Write mPHY control register 4170 * @hw: pointer to the HW structure 4171 * @address: address to write to 4172 * @data: data to write to register at offset 4173 * @line_override: used when we want to use different line than default one 4174 * 4175 * Writes data to mPHY control register. 4176 **/ 4177 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data, 4178 bool line_override) 4179 { 4180 u32 mphy_ctrl = 0; 4181 bool locked = FALSE; 4182 bool ready; 4183 4184 DEBUGFUNC("e1000_write_phy_reg_mphy"); 4185 4186 /* Check if mPHY is ready to read/write operations */ 4187 ready = e1000_is_mphy_ready(hw); 4188 if (!ready) 4189 return -E1000_ERR_PHY; 4190 4191 /* Check if mPHY access is disabled and enable it if so */ 4192 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4193 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4194 locked = TRUE; 4195 ready = e1000_is_mphy_ready(hw); 4196 if (!ready) 4197 return -E1000_ERR_PHY; 4198 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4199 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4200 } 4201 4202 /* Set the address that we want to read */ 4203 ready = e1000_is_mphy_ready(hw); 4204 if (!ready) 4205 return -E1000_ERR_PHY; 4206 4207 /* We mask address, because we want to use only current lane */ 4208 if (line_override) 4209 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE; 4210 else 4211 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE; 4212 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) | 4213 (address & E1000_MPHY_ADDRESS_MASK); 4214 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4215 4216 /* Read data from the address */ 4217 ready = e1000_is_mphy_ready(hw); 4218 if (!ready) 4219 return -E1000_ERR_PHY; 4220 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data); 4221 4222 /* Disable access to mPHY if it was originally disabled */ 4223 if (locked) 4224 ready = e1000_is_mphy_ready(hw); 4225 if (!ready) 4226 return -E1000_ERR_PHY; 4227 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4228 E1000_MPHY_DIS_ACCESS); 4229 4230 return E1000_SUCCESS; 4231 } 4232 4233 /** 4234 * e1000_is_mphy_ready - Check if mPHY control register is not busy 4235 * @hw: pointer to the HW structure 4236 * 4237 * Returns mPHY control register status. 4238 **/ 4239 bool e1000_is_mphy_ready(struct e1000_hw *hw) 4240 { 4241 u16 retry_count = 0; 4242 u32 mphy_ctrl = 0; 4243 bool ready = FALSE; 4244 4245 while (retry_count < 2) { 4246 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4247 if (mphy_ctrl & E1000_MPHY_BUSY) { 4248 usec_delay(20); 4249 retry_count++; 4250 continue; 4251 } 4252 ready = TRUE; 4253 break; 4254 } 4255 4256 if (!ready) 4257 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n"); 4258 4259 return ready; 4260 } 4261