1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "e1000_api.h" 36 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read, bool page_set); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51 static const u16 e1000_igp_2_cable_length_table[] = { 52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 59 124}; 60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64 /** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.set_page = e1000_null_set_page; 86 phy->ops.read_reg = e1000_null_read_reg; 87 phy->ops.read_reg_locked = e1000_null_read_reg; 88 phy->ops.read_reg_page = e1000_null_read_reg; 89 phy->ops.release = e1000_null_phy_generic; 90 phy->ops.reset = e1000_null_ops_generic; 91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 93 phy->ops.write_reg = e1000_null_write_reg; 94 phy->ops.write_reg_locked = e1000_null_write_reg; 95 phy->ops.write_reg_page = e1000_null_write_reg; 96 phy->ops.power_up = e1000_null_phy_generic; 97 phy->ops.power_down = e1000_null_phy_generic; 98 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 99 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null; 100 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null; 101 } 102 103 /** 104 * e1000_null_set_page - No-op function, return 0 105 * @hw: pointer to the HW structure 106 **/ 107 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data) 108 { 109 DEBUGFUNC("e1000_null_set_page"); 110 return E1000_SUCCESS; 111 } 112 113 /** 114 * e1000_null_read_reg - No-op function, return 0 115 * @hw: pointer to the HW structure 116 **/ 117 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 118 { 119 DEBUGFUNC("e1000_null_read_reg"); 120 return E1000_SUCCESS; 121 } 122 123 /** 124 * e1000_null_phy_generic - No-op function, return void 125 * @hw: pointer to the HW structure 126 **/ 127 void e1000_null_phy_generic(struct e1000_hw *hw) 128 { 129 DEBUGFUNC("e1000_null_phy_generic"); 130 return; 131 } 132 133 /** 134 * e1000_null_lplu_state - No-op function, return 0 135 * @hw: pointer to the HW structure 136 **/ 137 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 138 { 139 DEBUGFUNC("e1000_null_lplu_state"); 140 return E1000_SUCCESS; 141 } 142 143 /** 144 * e1000_null_write_reg - No-op function, return 0 145 * @hw: pointer to the HW structure 146 **/ 147 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 148 { 149 DEBUGFUNC("e1000_null_write_reg"); 150 return E1000_SUCCESS; 151 } 152 153 /** 154 * e1000_read_i2c_byte_null - No-op function, return 0 155 * @hw: pointer to hardware structure 156 * @byte_offset: byte offset to write 157 * @dev_addr: device address 158 * @data: data value read 159 * 160 **/ 161 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, 162 u8 dev_addr, u8 *data) 163 { 164 DEBUGFUNC("e1000_read_i2c_byte_null"); 165 return E1000_SUCCESS; 166 } 167 168 /** 169 * e1000_write_i2c_byte_null - No-op function, return 0 170 * @hw: pointer to hardware structure 171 * @byte_offset: byte offset to write 172 * @dev_addr: device address 173 * @data: data value to write 174 * 175 **/ 176 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, 177 u8 dev_addr, u8 data) 178 { 179 DEBUGFUNC("e1000_write_i2c_byte_null"); 180 return E1000_SUCCESS; 181 } 182 183 /** 184 * e1000_check_reset_block_generic - Check if PHY reset is blocked 185 * @hw: pointer to the HW structure 186 * 187 * Read the PHY management control register and check whether a PHY reset 188 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 189 * return E1000_BLK_PHY_RESET (12). 190 **/ 191 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 192 { 193 u32 manc; 194 195 DEBUGFUNC("e1000_check_reset_block"); 196 197 manc = E1000_READ_REG(hw, E1000_MANC); 198 199 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 200 E1000_BLK_PHY_RESET : E1000_SUCCESS; 201 } 202 203 /** 204 * e1000_get_phy_id - Retrieve the PHY ID and revision 205 * @hw: pointer to the HW structure 206 * 207 * Reads the PHY registers and stores the PHY ID and possibly the PHY 208 * revision in the hardware structure. 209 **/ 210 s32 e1000_get_phy_id(struct e1000_hw *hw) 211 { 212 struct e1000_phy_info *phy = &hw->phy; 213 s32 ret_val = E1000_SUCCESS; 214 u16 phy_id; 215 u16 retry_count = 0; 216 217 DEBUGFUNC("e1000_get_phy_id"); 218 219 if (!phy->ops.read_reg) 220 return E1000_SUCCESS; 221 222 while (retry_count < 2) { 223 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 224 if (ret_val) 225 return ret_val; 226 227 phy->id = (u32)(phy_id << 16); 228 usec_delay(20); 229 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 230 if (ret_val) 231 return ret_val; 232 233 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 234 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 235 236 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 237 return E1000_SUCCESS; 238 239 retry_count++; 240 } 241 242 return E1000_SUCCESS; 243 } 244 245 /** 246 * e1000_phy_reset_dsp_generic - Reset PHY DSP 247 * @hw: pointer to the HW structure 248 * 249 * Reset the digital signal processor. 250 **/ 251 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 252 { 253 s32 ret_val; 254 255 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 256 257 if (!hw->phy.ops.write_reg) 258 return E1000_SUCCESS; 259 260 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 261 if (ret_val) 262 return ret_val; 263 264 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 265 } 266 267 /** 268 * e1000_read_phy_reg_mdic - Read MDI control register 269 * @hw: pointer to the HW structure 270 * @offset: register offset to be read 271 * @data: pointer to the read data 272 * 273 * Reads the MDI control register in the PHY at offset and stores the 274 * information read to data. 275 **/ 276 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 277 { 278 struct e1000_phy_info *phy = &hw->phy; 279 u32 i, mdic = 0; 280 281 DEBUGFUNC("e1000_read_phy_reg_mdic"); 282 283 if (offset > MAX_PHY_REG_ADDRESS) { 284 DEBUGOUT1("PHY Address %d is out of range\n", offset); 285 return -E1000_ERR_PARAM; 286 } 287 288 /* 289 * Set up Op-code, Phy Address, and register offset in the MDI 290 * Control register. The MAC will take care of interfacing with the 291 * PHY to retrieve the desired data. 292 */ 293 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 294 (phy->addr << E1000_MDIC_PHY_SHIFT) | 295 (E1000_MDIC_OP_READ)); 296 297 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 298 299 /* 300 * Poll the ready bit to see if the MDI read completed 301 * Increasing the time out as testing showed failures with 302 * the lower time out 303 */ 304 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 305 usec_delay(50); 306 mdic = E1000_READ_REG(hw, E1000_MDIC); 307 if (mdic & E1000_MDIC_READY) 308 break; 309 } 310 if (!(mdic & E1000_MDIC_READY)) { 311 DEBUGOUT("MDI Read did not complete\n"); 312 return -E1000_ERR_PHY; 313 } 314 if (mdic & E1000_MDIC_ERROR) { 315 DEBUGOUT("MDI Error\n"); 316 return -E1000_ERR_PHY; 317 } 318 *data = (u16) mdic; 319 320 /* 321 * Allow some time after each MDIC transaction to avoid 322 * reading duplicate data in the next MDIC transaction. 323 */ 324 if (hw->mac.type == e1000_pch2lan) 325 usec_delay(100); 326 327 return E1000_SUCCESS; 328 } 329 330 /** 331 * e1000_write_phy_reg_mdic - Write MDI control register 332 * @hw: pointer to the HW structure 333 * @offset: register offset to write to 334 * @data: data to write to register at offset 335 * 336 * Writes data to MDI control register in the PHY at offset. 337 **/ 338 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 339 { 340 struct e1000_phy_info *phy = &hw->phy; 341 u32 i, mdic = 0; 342 343 DEBUGFUNC("e1000_write_phy_reg_mdic"); 344 345 if (offset > MAX_PHY_REG_ADDRESS) { 346 DEBUGOUT1("PHY Address %d is out of range\n", offset); 347 return -E1000_ERR_PARAM; 348 } 349 350 /* 351 * Set up Op-code, Phy Address, and register offset in the MDI 352 * Control register. The MAC will take care of interfacing with the 353 * PHY to retrieve the desired data. 354 */ 355 mdic = (((u32)data) | 356 (offset << E1000_MDIC_REG_SHIFT) | 357 (phy->addr << E1000_MDIC_PHY_SHIFT) | 358 (E1000_MDIC_OP_WRITE)); 359 360 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 361 362 /* 363 * Poll the ready bit to see if the MDI read completed 364 * Increasing the time out as testing showed failures with 365 * the lower time out 366 */ 367 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 368 usec_delay(50); 369 mdic = E1000_READ_REG(hw, E1000_MDIC); 370 if (mdic & E1000_MDIC_READY) 371 break; 372 } 373 if (!(mdic & E1000_MDIC_READY)) { 374 DEBUGOUT("MDI Write did not complete\n"); 375 return -E1000_ERR_PHY; 376 } 377 if (mdic & E1000_MDIC_ERROR) { 378 DEBUGOUT("MDI Error\n"); 379 return -E1000_ERR_PHY; 380 } 381 382 /* 383 * Allow some time after each MDIC transaction to avoid 384 * reading duplicate data in the next MDIC transaction. 385 */ 386 if (hw->mac.type == e1000_pch2lan) 387 usec_delay(100); 388 389 return E1000_SUCCESS; 390 } 391 392 /** 393 * e1000_read_phy_reg_i2c - Read PHY register using i2c 394 * @hw: pointer to the HW structure 395 * @offset: register offset to be read 396 * @data: pointer to the read data 397 * 398 * Reads the PHY register at offset using the i2c interface and stores the 399 * retrieved information in data. 400 **/ 401 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 402 { 403 struct e1000_phy_info *phy = &hw->phy; 404 u32 i, i2ccmd = 0; 405 406 DEBUGFUNC("e1000_read_phy_reg_i2c"); 407 408 /* 409 * Set up Op-code, Phy Address, and register address in the I2CCMD 410 * register. The MAC will take care of interfacing with the 411 * PHY to retrieve the desired data. 412 */ 413 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 414 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 415 (E1000_I2CCMD_OPCODE_READ)); 416 417 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 418 419 /* Poll the ready bit to see if the I2C read completed */ 420 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 421 usec_delay(50); 422 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 423 if (i2ccmd & E1000_I2CCMD_READY) 424 break; 425 } 426 if (!(i2ccmd & E1000_I2CCMD_READY)) { 427 DEBUGOUT("I2CCMD Read did not complete\n"); 428 return -E1000_ERR_PHY; 429 } 430 if (i2ccmd & E1000_I2CCMD_ERROR) { 431 DEBUGOUT("I2CCMD Error bit set\n"); 432 return -E1000_ERR_PHY; 433 } 434 435 /* Need to byte-swap the 16-bit value. */ 436 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 437 438 return E1000_SUCCESS; 439 } 440 441 /** 442 * e1000_write_phy_reg_i2c - Write PHY register using i2c 443 * @hw: pointer to the HW structure 444 * @offset: register offset to write to 445 * @data: data to write at register offset 446 * 447 * Writes the data to PHY register at the offset using the i2c interface. 448 **/ 449 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 450 { 451 struct e1000_phy_info *phy = &hw->phy; 452 u32 i, i2ccmd = 0; 453 u16 phy_data_swapped; 454 455 DEBUGFUNC("e1000_write_phy_reg_i2c"); 456 457 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 458 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 459 DEBUGOUT1("PHY I2C Address %d is out of range.\n", 460 hw->phy.addr); 461 return -E1000_ERR_CONFIG; 462 } 463 464 /* Swap the data bytes for the I2C interface */ 465 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 466 467 /* 468 * Set up Op-code, Phy Address, and register address in the I2CCMD 469 * register. The MAC will take care of interfacing with the 470 * PHY to retrieve the desired data. 471 */ 472 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 473 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 474 E1000_I2CCMD_OPCODE_WRITE | 475 phy_data_swapped); 476 477 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 478 479 /* Poll the ready bit to see if the I2C read completed */ 480 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 481 usec_delay(50); 482 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 483 if (i2ccmd & E1000_I2CCMD_READY) 484 break; 485 } 486 if (!(i2ccmd & E1000_I2CCMD_READY)) { 487 DEBUGOUT("I2CCMD Write did not complete\n"); 488 return -E1000_ERR_PHY; 489 } 490 if (i2ccmd & E1000_I2CCMD_ERROR) { 491 DEBUGOUT("I2CCMD Error bit set\n"); 492 return -E1000_ERR_PHY; 493 } 494 495 return E1000_SUCCESS; 496 } 497 498 /** 499 * e1000_read_sfp_data_byte - Reads SFP module data. 500 * @hw: pointer to the HW structure 501 * @offset: byte location offset to be read 502 * @data: read data buffer pointer 503 * 504 * Reads one byte from SFP module data stored 505 * in SFP resided EEPROM memory or SFP diagnostic area. 506 * Function should be called with 507 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 508 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 509 * access 510 **/ 511 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 512 { 513 u32 i = 0; 514 u32 i2ccmd = 0; 515 u32 data_local = 0; 516 517 DEBUGFUNC("e1000_read_sfp_data_byte"); 518 519 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 520 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 521 return -E1000_ERR_PHY; 522 } 523 524 /* 525 * Set up Op-code, EEPROM Address,in the I2CCMD 526 * register. The MAC will take care of interfacing with the 527 * EEPROM to retrieve the desired data. 528 */ 529 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 530 E1000_I2CCMD_OPCODE_READ); 531 532 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 533 534 /* Poll the ready bit to see if the I2C read completed */ 535 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 536 usec_delay(50); 537 data_local = E1000_READ_REG(hw, E1000_I2CCMD); 538 if (data_local & E1000_I2CCMD_READY) 539 break; 540 } 541 if (!(data_local & E1000_I2CCMD_READY)) { 542 DEBUGOUT("I2CCMD Read did not complete\n"); 543 return -E1000_ERR_PHY; 544 } 545 if (data_local & E1000_I2CCMD_ERROR) { 546 DEBUGOUT("I2CCMD Error bit set\n"); 547 return -E1000_ERR_PHY; 548 } 549 *data = (u8) data_local & 0xFF; 550 551 return E1000_SUCCESS; 552 } 553 554 /** 555 * e1000_write_sfp_data_byte - Writes SFP module data. 556 * @hw: pointer to the HW structure 557 * @offset: byte location offset to write to 558 * @data: data to write 559 * 560 * Writes one byte to SFP module data stored 561 * in SFP resided EEPROM memory or SFP diagnostic area. 562 * Function should be called with 563 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 564 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 565 * access 566 **/ 567 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 568 { 569 u32 i = 0; 570 u32 i2ccmd = 0; 571 u32 data_local = 0; 572 573 DEBUGFUNC("e1000_write_sfp_data_byte"); 574 575 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 576 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 577 return -E1000_ERR_PHY; 578 } 579 /* 580 * The programming interface is 16 bits wide 581 * so we need to read the whole word first 582 * then update appropriate byte lane and write 583 * the updated word back. 584 */ 585 /* 586 * Set up Op-code, EEPROM Address,in the I2CCMD 587 * register. The MAC will take care of interfacing 588 * with an EEPROM to write the data given. 589 */ 590 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 591 E1000_I2CCMD_OPCODE_READ); 592 /* Set a command to read single word */ 593 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 594 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 595 usec_delay(50); 596 /* 597 * Poll the ready bit to see if lastly 598 * launched I2C operation completed 599 */ 600 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 601 if (i2ccmd & E1000_I2CCMD_READY) { 602 /* Check if this is READ or WRITE phase */ 603 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 604 E1000_I2CCMD_OPCODE_READ) { 605 /* 606 * Write the selected byte 607 * lane and update whole word 608 */ 609 data_local = i2ccmd & 0xFF00; 610 data_local |= data; 611 i2ccmd = ((offset << 612 E1000_I2CCMD_REG_ADDR_SHIFT) | 613 E1000_I2CCMD_OPCODE_WRITE | data_local); 614 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 615 } else { 616 break; 617 } 618 } 619 } 620 if (!(i2ccmd & E1000_I2CCMD_READY)) { 621 DEBUGOUT("I2CCMD Write did not complete\n"); 622 return -E1000_ERR_PHY; 623 } 624 if (i2ccmd & E1000_I2CCMD_ERROR) { 625 DEBUGOUT("I2CCMD Error bit set\n"); 626 return -E1000_ERR_PHY; 627 } 628 return E1000_SUCCESS; 629 } 630 631 /** 632 * e1000_read_phy_reg_m88 - Read m88 PHY register 633 * @hw: pointer to the HW structure 634 * @offset: register offset to be read 635 * @data: pointer to the read data 636 * 637 * Acquires semaphore, if necessary, then reads the PHY register at offset 638 * and storing the retrieved information in data. Release any acquired 639 * semaphores before exiting. 640 **/ 641 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 642 { 643 s32 ret_val; 644 645 DEBUGFUNC("e1000_read_phy_reg_m88"); 646 647 if (!hw->phy.ops.acquire) 648 return E1000_SUCCESS; 649 650 ret_val = hw->phy.ops.acquire(hw); 651 if (ret_val) 652 return ret_val; 653 654 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 655 data); 656 657 hw->phy.ops.release(hw); 658 659 return ret_val; 660 } 661 662 /** 663 * e1000_write_phy_reg_m88 - Write m88 PHY register 664 * @hw: pointer to the HW structure 665 * @offset: register offset to write to 666 * @data: data to write at register offset 667 * 668 * Acquires semaphore, if necessary, then writes the data to PHY register 669 * at the offset. Release any acquired semaphores before exiting. 670 **/ 671 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 672 { 673 s32 ret_val; 674 675 DEBUGFUNC("e1000_write_phy_reg_m88"); 676 677 if (!hw->phy.ops.acquire) 678 return E1000_SUCCESS; 679 680 ret_val = hw->phy.ops.acquire(hw); 681 if (ret_val) 682 return ret_val; 683 684 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 685 data); 686 687 hw->phy.ops.release(hw); 688 689 return ret_val; 690 } 691 692 /** 693 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 694 * @hw: pointer to the HW structure 695 * @page: page to set (shifted left when necessary) 696 * 697 * Sets PHY page required for PHY register access. Assumes semaphore is 698 * already acquired. Note, this function sets phy.addr to 1 so the caller 699 * must set it appropriately (if necessary) after this function returns. 700 **/ 701 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 702 { 703 DEBUGFUNC("e1000_set_page_igp"); 704 705 DEBUGOUT1("Setting page 0x%x\n", page); 706 707 hw->phy.addr = 1; 708 709 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 710 } 711 712 /** 713 * __e1000_read_phy_reg_igp - Read igp PHY register 714 * @hw: pointer to the HW structure 715 * @offset: register offset to be read 716 * @data: pointer to the read data 717 * @locked: semaphore has already been acquired or not 718 * 719 * Acquires semaphore, if necessary, then reads the PHY register at offset 720 * and stores the retrieved information in data. Release any acquired 721 * semaphores before exiting. 722 **/ 723 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 724 bool locked) 725 { 726 s32 ret_val = E1000_SUCCESS; 727 728 DEBUGFUNC("__e1000_read_phy_reg_igp"); 729 730 if (!locked) { 731 if (!hw->phy.ops.acquire) 732 return E1000_SUCCESS; 733 734 ret_val = hw->phy.ops.acquire(hw); 735 if (ret_val) 736 return ret_val; 737 } 738 739 if (offset > MAX_PHY_MULTI_PAGE_REG) 740 ret_val = e1000_write_phy_reg_mdic(hw, 741 IGP01E1000_PHY_PAGE_SELECT, 742 (u16)offset); 743 if (!ret_val) 744 ret_val = e1000_read_phy_reg_mdic(hw, 745 MAX_PHY_REG_ADDRESS & offset, 746 data); 747 if (!locked) 748 hw->phy.ops.release(hw); 749 750 return ret_val; 751 } 752 753 /** 754 * e1000_read_phy_reg_igp - Read igp PHY register 755 * @hw: pointer to the HW structure 756 * @offset: register offset to be read 757 * @data: pointer to the read data 758 * 759 * Acquires semaphore then reads the PHY register at offset and stores the 760 * retrieved information in data. 761 * Release the acquired semaphore before exiting. 762 **/ 763 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 764 { 765 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 766 } 767 768 /** 769 * e1000_read_phy_reg_igp_locked - Read igp PHY register 770 * @hw: pointer to the HW structure 771 * @offset: register offset to be read 772 * @data: pointer to the read data 773 * 774 * Reads the PHY register at offset and stores the retrieved information 775 * in data. Assumes semaphore already acquired. 776 **/ 777 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 778 { 779 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 780 } 781 782 /** 783 * e1000_write_phy_reg_igp - Write igp PHY register 784 * @hw: pointer to the HW structure 785 * @offset: register offset to write to 786 * @data: data to write at register offset 787 * @locked: semaphore has already been acquired or not 788 * 789 * Acquires semaphore, if necessary, then writes the data to PHY register 790 * at the offset. Release any acquired semaphores before exiting. 791 **/ 792 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 793 bool locked) 794 { 795 s32 ret_val = E1000_SUCCESS; 796 797 DEBUGFUNC("e1000_write_phy_reg_igp"); 798 799 if (!locked) { 800 if (!hw->phy.ops.acquire) 801 return E1000_SUCCESS; 802 803 ret_val = hw->phy.ops.acquire(hw); 804 if (ret_val) 805 return ret_val; 806 } 807 808 if (offset > MAX_PHY_MULTI_PAGE_REG) 809 ret_val = e1000_write_phy_reg_mdic(hw, 810 IGP01E1000_PHY_PAGE_SELECT, 811 (u16)offset); 812 if (!ret_val) 813 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 814 offset, 815 data); 816 if (!locked) 817 hw->phy.ops.release(hw); 818 819 return ret_val; 820 } 821 822 /** 823 * e1000_write_phy_reg_igp - Write igp PHY register 824 * @hw: pointer to the HW structure 825 * @offset: register offset to write to 826 * @data: data to write at register offset 827 * 828 * Acquires semaphore then writes the data to PHY register 829 * at the offset. Release any acquired semaphores before exiting. 830 **/ 831 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 832 { 833 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 834 } 835 836 /** 837 * e1000_write_phy_reg_igp_locked - Write igp PHY register 838 * @hw: pointer to the HW structure 839 * @offset: register offset to write to 840 * @data: data to write at register offset 841 * 842 * Writes the data to PHY register at the offset. 843 * Assumes semaphore already acquired. 844 **/ 845 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 846 { 847 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 848 } 849 850 /** 851 * __e1000_read_kmrn_reg - Read kumeran register 852 * @hw: pointer to the HW structure 853 * @offset: register offset to be read 854 * @data: pointer to the read data 855 * @locked: semaphore has already been acquired or not 856 * 857 * Acquires semaphore, if necessary. Then reads the PHY register at offset 858 * using the kumeran interface. The information retrieved is stored in data. 859 * Release any acquired semaphores before exiting. 860 **/ 861 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 862 bool locked) 863 { 864 u32 kmrnctrlsta; 865 866 DEBUGFUNC("__e1000_read_kmrn_reg"); 867 868 if (!locked) { 869 s32 ret_val = E1000_SUCCESS; 870 871 if (!hw->phy.ops.acquire) 872 return E1000_SUCCESS; 873 874 ret_val = hw->phy.ops.acquire(hw); 875 if (ret_val) 876 return ret_val; 877 } 878 879 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 880 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 881 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 882 E1000_WRITE_FLUSH(hw); 883 884 usec_delay(2); 885 886 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 887 *data = (u16)kmrnctrlsta; 888 889 if (!locked) 890 hw->phy.ops.release(hw); 891 892 return E1000_SUCCESS; 893 } 894 895 /** 896 * e1000_read_kmrn_reg_generic - Read kumeran register 897 * @hw: pointer to the HW structure 898 * @offset: register offset to be read 899 * @data: pointer to the read data 900 * 901 * Acquires semaphore then reads the PHY register at offset using the 902 * kumeran interface. The information retrieved is stored in data. 903 * Release the acquired semaphore before exiting. 904 **/ 905 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 906 { 907 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 908 } 909 910 /** 911 * e1000_read_kmrn_reg_locked - Read kumeran register 912 * @hw: pointer to the HW structure 913 * @offset: register offset to be read 914 * @data: pointer to the read data 915 * 916 * Reads the PHY register at offset using the kumeran interface. The 917 * information retrieved is stored in data. 918 * Assumes semaphore already acquired. 919 **/ 920 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 921 { 922 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 923 } 924 925 /** 926 * __e1000_write_kmrn_reg - Write kumeran register 927 * @hw: pointer to the HW structure 928 * @offset: register offset to write to 929 * @data: data to write at register offset 930 * @locked: semaphore has already been acquired or not 931 * 932 * Acquires semaphore, if necessary. Then write the data to PHY register 933 * at the offset using the kumeran interface. Release any acquired semaphores 934 * before exiting. 935 **/ 936 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 937 bool locked) 938 { 939 u32 kmrnctrlsta; 940 941 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 942 943 if (!locked) { 944 s32 ret_val = E1000_SUCCESS; 945 946 if (!hw->phy.ops.acquire) 947 return E1000_SUCCESS; 948 949 ret_val = hw->phy.ops.acquire(hw); 950 if (ret_val) 951 return ret_val; 952 } 953 954 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 955 E1000_KMRNCTRLSTA_OFFSET) | data; 956 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 957 E1000_WRITE_FLUSH(hw); 958 959 usec_delay(2); 960 961 if (!locked) 962 hw->phy.ops.release(hw); 963 964 return E1000_SUCCESS; 965 } 966 967 /** 968 * e1000_write_kmrn_reg_generic - Write kumeran register 969 * @hw: pointer to the HW structure 970 * @offset: register offset to write to 971 * @data: data to write at register offset 972 * 973 * Acquires semaphore then writes the data to the PHY register at the offset 974 * using the kumeran interface. Release the acquired semaphore before exiting. 975 **/ 976 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 977 { 978 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 979 } 980 981 /** 982 * e1000_write_kmrn_reg_locked - Write kumeran register 983 * @hw: pointer to the HW structure 984 * @offset: register offset to write to 985 * @data: data to write at register offset 986 * 987 * Write the data to PHY register at the offset using the kumeran interface. 988 * Assumes semaphore already acquired. 989 **/ 990 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 991 { 992 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 993 } 994 995 /** 996 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 997 * @hw: pointer to the HW structure 998 * 999 * Sets up Master/slave mode 1000 **/ 1001 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 1002 { 1003 s32 ret_val; 1004 u16 phy_data; 1005 1006 /* Resolve Master/Slave mode */ 1007 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 1008 if (ret_val) 1009 return ret_val; 1010 1011 /* load defaults for future use */ 1012 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 1013 ((phy_data & CR_1000T_MS_VALUE) ? 1014 e1000_ms_force_master : 1015 e1000_ms_force_slave) : e1000_ms_auto; 1016 1017 switch (hw->phy.ms_type) { 1018 case e1000_ms_force_master: 1019 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1020 break; 1021 case e1000_ms_force_slave: 1022 phy_data |= CR_1000T_MS_ENABLE; 1023 phy_data &= ~(CR_1000T_MS_VALUE); 1024 break; 1025 case e1000_ms_auto: 1026 phy_data &= ~CR_1000T_MS_ENABLE; 1027 /* fall-through */ 1028 default: 1029 break; 1030 } 1031 1032 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 1033 } 1034 1035 /** 1036 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 1037 * @hw: pointer to the HW structure 1038 * 1039 * Sets up Carrier-sense on Transmit and downshift values. 1040 **/ 1041 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 1042 { 1043 s32 ret_val; 1044 u16 phy_data; 1045 1046 DEBUGFUNC("e1000_copper_link_setup_82577"); 1047 1048 if (hw->phy.type == e1000_phy_82580) { 1049 ret_val = hw->phy.ops.reset(hw); 1050 if (ret_val) { 1051 DEBUGOUT("Error resetting the PHY.\n"); 1052 return ret_val; 1053 } 1054 } 1055 1056 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1057 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 1058 if (ret_val) 1059 return ret_val; 1060 1061 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 1062 1063 /* Enable downshift */ 1064 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 1065 1066 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 1067 if (ret_val) 1068 return ret_val; 1069 1070 /* Set MDI/MDIX mode */ 1071 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 1072 if (ret_val) 1073 return ret_val; 1074 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 1075 /* 1076 * Options: 1077 * 0 - Auto (default) 1078 * 1 - MDI mode 1079 * 2 - MDI-X mode 1080 */ 1081 switch (hw->phy.mdix) { 1082 case 1: 1083 break; 1084 case 2: 1085 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 1086 break; 1087 case 0: 1088 default: 1089 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 1090 break; 1091 } 1092 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 1093 if (ret_val) 1094 return ret_val; 1095 1096 return e1000_set_master_slave_mode(hw); 1097 } 1098 1099 /** 1100 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 1101 * @hw: pointer to the HW structure 1102 * 1103 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 1104 * and downshift values are set also. 1105 **/ 1106 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 1107 { 1108 struct e1000_phy_info *phy = &hw->phy; 1109 s32 ret_val; 1110 u16 phy_data; 1111 1112 DEBUGFUNC("e1000_copper_link_setup_m88"); 1113 1114 1115 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1116 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1117 if (ret_val) 1118 return ret_val; 1119 1120 /* For BM PHY this bit is downshift enable */ 1121 if (phy->type != e1000_phy_bm) 1122 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1123 1124 /* 1125 * Options: 1126 * MDI/MDI-X = 0 (default) 1127 * 0 - Auto for all speeds 1128 * 1 - MDI mode 1129 * 2 - MDI-X mode 1130 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1131 */ 1132 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1133 1134 switch (phy->mdix) { 1135 case 1: 1136 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1137 break; 1138 case 2: 1139 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1140 break; 1141 case 3: 1142 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1143 break; 1144 case 0: 1145 default: 1146 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1147 break; 1148 } 1149 1150 /* 1151 * Options: 1152 * disable_polarity_correction = 0 (default) 1153 * Automatic Correction for Reversed Cable Polarity 1154 * 0 - Disabled 1155 * 1 - Enabled 1156 */ 1157 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1158 if (phy->disable_polarity_correction) 1159 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1160 1161 /* Enable downshift on BM (disabled by default) */ 1162 if (phy->type == e1000_phy_bm) { 1163 /* For 82574/82583, first disable then enable downshift */ 1164 if (phy->id == BME1000_E_PHY_ID_R2) { 1165 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 1166 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1167 phy_data); 1168 if (ret_val) 1169 return ret_val; 1170 /* Commit the changes. */ 1171 ret_val = phy->ops.commit(hw); 1172 if (ret_val) { 1173 DEBUGOUT("Error committing the PHY changes\n"); 1174 return ret_val; 1175 } 1176 } 1177 1178 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 1179 } 1180 1181 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1182 if (ret_val) 1183 return ret_val; 1184 1185 if ((phy->type == e1000_phy_m88) && 1186 (phy->revision < E1000_REVISION_4) && 1187 (phy->id != BME1000_E_PHY_ID_R2)) { 1188 /* 1189 * Force TX_CLK in the Extended PHY Specific Control Register 1190 * to 25MHz clock. 1191 */ 1192 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1193 &phy_data); 1194 if (ret_val) 1195 return ret_val; 1196 1197 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1198 1199 if ((phy->revision == E1000_REVISION_2) && 1200 (phy->id == M88E1111_I_PHY_ID)) { 1201 /* 82573L PHY - set the downshift counter to 5x. */ 1202 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 1203 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1204 } else { 1205 /* Configure Master and Slave downshift values */ 1206 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1207 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1208 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1209 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1210 } 1211 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1212 phy_data); 1213 if (ret_val) 1214 return ret_val; 1215 } 1216 1217 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 1218 /* Set PHY page 0, register 29 to 0x0003 */ 1219 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 1220 if (ret_val) 1221 return ret_val; 1222 1223 /* Set PHY page 0, register 30 to 0x0000 */ 1224 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 1225 if (ret_val) 1226 return ret_val; 1227 } 1228 1229 /* Commit the changes. */ 1230 ret_val = phy->ops.commit(hw); 1231 if (ret_val) { 1232 DEBUGOUT("Error committing the PHY changes\n"); 1233 return ret_val; 1234 } 1235 1236 if (phy->type == e1000_phy_82578) { 1237 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1238 &phy_data); 1239 if (ret_val) 1240 return ret_val; 1241 1242 /* 82578 PHY - set the downshift count to 1x. */ 1243 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 1244 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 1245 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1246 phy_data); 1247 if (ret_val) 1248 return ret_val; 1249 } 1250 1251 if (phy->type == e1000_phy_i210) { 1252 ret_val = e1000_set_master_slave_mode(hw); 1253 if (ret_val) 1254 return ret_val; 1255 } 1256 1257 return E1000_SUCCESS; 1258 } 1259 1260 /** 1261 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 1262 * @hw: pointer to the HW structure 1263 * 1264 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1265 * Also enables and sets the downshift parameters. 1266 **/ 1267 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1268 { 1269 struct e1000_phy_info *phy = &hw->phy; 1270 s32 ret_val; 1271 u16 phy_data; 1272 1273 DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1274 1275 1276 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1277 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1278 if (ret_val) 1279 return ret_val; 1280 1281 /* 1282 * Options: 1283 * MDI/MDI-X = 0 (default) 1284 * 0 - Auto for all speeds 1285 * 1 - MDI mode 1286 * 2 - MDI-X mode 1287 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1288 */ 1289 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1290 1291 switch (phy->mdix) { 1292 case 1: 1293 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1294 break; 1295 case 2: 1296 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1297 break; 1298 case 3: 1299 /* M88E1112 does not support this mode) */ 1300 if (phy->id != M88E1112_E_PHY_ID) { 1301 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1302 break; 1303 } 1304 case 0: 1305 default: 1306 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1307 break; 1308 } 1309 1310 /* 1311 * Options: 1312 * disable_polarity_correction = 0 (default) 1313 * Automatic Correction for Reversed Cable Polarity 1314 * 0 - Disabled 1315 * 1 - Enabled 1316 */ 1317 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1318 if (phy->disable_polarity_correction) 1319 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1320 1321 /* Enable downshift and setting it to X6 */ 1322 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1323 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1324 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1325 1326 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1327 if (ret_val) 1328 return ret_val; 1329 1330 /* Commit the changes. */ 1331 ret_val = phy->ops.commit(hw); 1332 if (ret_val) { 1333 DEBUGOUT("Error committing the PHY changes\n"); 1334 return ret_val; 1335 } 1336 1337 return E1000_SUCCESS; 1338 } 1339 1340 /** 1341 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1342 * @hw: pointer to the HW structure 1343 * 1344 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1345 * igp PHY's. 1346 **/ 1347 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1348 { 1349 struct e1000_phy_info *phy = &hw->phy; 1350 s32 ret_val; 1351 u16 data; 1352 1353 DEBUGFUNC("e1000_copper_link_setup_igp"); 1354 1355 1356 ret_val = hw->phy.ops.reset(hw); 1357 if (ret_val) { 1358 DEBUGOUT("Error resetting the PHY.\n"); 1359 return ret_val; 1360 } 1361 1362 /* 1363 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1364 * timeout issues when LFS is enabled. 1365 */ 1366 msec_delay(100); 1367 1368 /* 1369 * The NVM settings will configure LPLU in D3 for 1370 * non-IGP1 PHYs. 1371 */ 1372 if (phy->type == e1000_phy_igp) { 1373 /* disable lplu d3 during driver init */ 1374 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1375 if (ret_val) { 1376 DEBUGOUT("Error Disabling LPLU D3\n"); 1377 return ret_val; 1378 } 1379 } 1380 1381 /* disable lplu d0 during driver init */ 1382 if (hw->phy.ops.set_d0_lplu_state) { 1383 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1384 if (ret_val) { 1385 DEBUGOUT("Error Disabling LPLU D0\n"); 1386 return ret_val; 1387 } 1388 } 1389 /* Configure mdi-mdix settings */ 1390 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1391 if (ret_val) 1392 return ret_val; 1393 1394 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1395 1396 switch (phy->mdix) { 1397 case 1: 1398 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1399 break; 1400 case 2: 1401 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1402 break; 1403 case 0: 1404 default: 1405 data |= IGP01E1000_PSCR_AUTO_MDIX; 1406 break; 1407 } 1408 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1409 if (ret_val) 1410 return ret_val; 1411 1412 /* set auto-master slave resolution settings */ 1413 if (hw->mac.autoneg) { 1414 /* 1415 * when autonegotiation advertisement is only 1000Mbps then we 1416 * should disable SmartSpeed and enable Auto MasterSlave 1417 * resolution as hardware default. 1418 */ 1419 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1420 /* Disable SmartSpeed */ 1421 ret_val = phy->ops.read_reg(hw, 1422 IGP01E1000_PHY_PORT_CONFIG, 1423 &data); 1424 if (ret_val) 1425 return ret_val; 1426 1427 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1428 ret_val = phy->ops.write_reg(hw, 1429 IGP01E1000_PHY_PORT_CONFIG, 1430 data); 1431 if (ret_val) 1432 return ret_val; 1433 1434 /* Set auto Master/Slave resolution process */ 1435 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1436 if (ret_val) 1437 return ret_val; 1438 1439 data &= ~CR_1000T_MS_ENABLE; 1440 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1441 if (ret_val) 1442 return ret_val; 1443 } 1444 1445 ret_val = e1000_set_master_slave_mode(hw); 1446 } 1447 1448 return ret_val; 1449 } 1450 1451 /** 1452 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1453 * @hw: pointer to the HW structure 1454 * 1455 * Reads the MII auto-neg advertisement register and/or the 1000T control 1456 * register and if the PHY is already setup for auto-negotiation, then 1457 * return successful. Otherwise, setup advertisement and flow control to 1458 * the appropriate values for the wanted auto-negotiation. 1459 **/ 1460 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1461 { 1462 struct e1000_phy_info *phy = &hw->phy; 1463 s32 ret_val; 1464 u16 mii_autoneg_adv_reg; 1465 u16 mii_1000t_ctrl_reg = 0; 1466 1467 DEBUGFUNC("e1000_phy_setup_autoneg"); 1468 1469 phy->autoneg_advertised &= phy->autoneg_mask; 1470 1471 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1472 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1473 if (ret_val) 1474 return ret_val; 1475 1476 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1477 /* Read the MII 1000Base-T Control Register (Address 9). */ 1478 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1479 &mii_1000t_ctrl_reg); 1480 if (ret_val) 1481 return ret_val; 1482 } 1483 1484 /* 1485 * Need to parse both autoneg_advertised and fc and set up 1486 * the appropriate PHY registers. First we will parse for 1487 * autoneg_advertised software override. Since we can advertise 1488 * a plethora of combinations, we need to check each bit 1489 * individually. 1490 */ 1491 1492 /* 1493 * First we clear all the 10/100 mb speed bits in the Auto-Neg 1494 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1495 * the 1000Base-T Control Register (Address 9). 1496 */ 1497 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1498 NWAY_AR_100TX_HD_CAPS | 1499 NWAY_AR_10T_FD_CAPS | 1500 NWAY_AR_10T_HD_CAPS); 1501 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1502 1503 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1504 1505 /* Do we want to advertise 10 Mb Half Duplex? */ 1506 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1507 DEBUGOUT("Advertise 10mb Half duplex\n"); 1508 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1509 } 1510 1511 /* Do we want to advertise 10 Mb Full Duplex? */ 1512 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1513 DEBUGOUT("Advertise 10mb Full duplex\n"); 1514 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1515 } 1516 1517 /* Do we want to advertise 100 Mb Half Duplex? */ 1518 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1519 DEBUGOUT("Advertise 100mb Half duplex\n"); 1520 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1521 } 1522 1523 /* Do we want to advertise 100 Mb Full Duplex? */ 1524 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1525 DEBUGOUT("Advertise 100mb Full duplex\n"); 1526 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1527 } 1528 1529 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1530 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1531 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1532 1533 /* Do we want to advertise 1000 Mb Full Duplex? */ 1534 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1535 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1536 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1537 } 1538 1539 /* 1540 * Check for a software override of the flow control settings, and 1541 * setup the PHY advertisement registers accordingly. If 1542 * auto-negotiation is enabled, then software will have to set the 1543 * "PAUSE" bits to the correct value in the Auto-Negotiation 1544 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1545 * negotiation. 1546 * 1547 * The possible values of the "fc" parameter are: 1548 * 0: Flow control is completely disabled 1549 * 1: Rx flow control is enabled (we can receive pause frames 1550 * but not send pause frames). 1551 * 2: Tx flow control is enabled (we can send pause frames 1552 * but we do not support receiving pause frames). 1553 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1554 * other: No software override. The flow control configuration 1555 * in the EEPROM is used. 1556 */ 1557 switch (hw->fc.current_mode) { 1558 case e1000_fc_none: 1559 /* 1560 * Flow control (Rx & Tx) is completely disabled by a 1561 * software over-ride. 1562 */ 1563 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1564 break; 1565 case e1000_fc_rx_pause: 1566 /* 1567 * Rx Flow control is enabled, and Tx Flow control is 1568 * disabled, by a software over-ride. 1569 * 1570 * Since there really isn't a way to advertise that we are 1571 * capable of Rx Pause ONLY, we will advertise that we 1572 * support both symmetric and asymmetric Rx PAUSE. Later 1573 * (in e1000_config_fc_after_link_up) we will disable the 1574 * hw's ability to send PAUSE frames. 1575 */ 1576 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1577 break; 1578 case e1000_fc_tx_pause: 1579 /* 1580 * Tx Flow control is enabled, and Rx Flow control is 1581 * disabled, by a software over-ride. 1582 */ 1583 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1584 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1585 break; 1586 case e1000_fc_full: 1587 /* 1588 * Flow control (both Rx and Tx) is enabled by a software 1589 * over-ride. 1590 */ 1591 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1592 break; 1593 default: 1594 DEBUGOUT("Flow control param set incorrectly\n"); 1595 return -E1000_ERR_CONFIG; 1596 } 1597 1598 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1599 if (ret_val) 1600 return ret_val; 1601 1602 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1603 1604 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1605 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 1606 mii_1000t_ctrl_reg); 1607 1608 return ret_val; 1609 } 1610 1611 /** 1612 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1613 * @hw: pointer to the HW structure 1614 * 1615 * Performs initial bounds checking on autoneg advertisement parameter, then 1616 * configure to advertise the full capability. Setup the PHY to autoneg 1617 * and restart the negotiation process between the link partner. If 1618 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1619 **/ 1620 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1621 { 1622 struct e1000_phy_info *phy = &hw->phy; 1623 s32 ret_val; 1624 u16 phy_ctrl; 1625 1626 DEBUGFUNC("e1000_copper_link_autoneg"); 1627 1628 /* 1629 * Perform some bounds checking on the autoneg advertisement 1630 * parameter. 1631 */ 1632 phy->autoneg_advertised &= phy->autoneg_mask; 1633 1634 /* 1635 * If autoneg_advertised is zero, we assume it was not defaulted 1636 * by the calling code so we set to advertise full capability. 1637 */ 1638 if (!phy->autoneg_advertised) 1639 phy->autoneg_advertised = phy->autoneg_mask; 1640 1641 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1642 ret_val = e1000_phy_setup_autoneg(hw); 1643 if (ret_val) { 1644 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1645 return ret_val; 1646 } 1647 DEBUGOUT("Restarting Auto-Neg\n"); 1648 1649 /* 1650 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1651 * the Auto Neg Restart bit in the PHY control register. 1652 */ 1653 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1654 if (ret_val) 1655 return ret_val; 1656 1657 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1658 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1659 if (ret_val) 1660 return ret_val; 1661 1662 /* 1663 * Does the user want to wait for Auto-Neg to complete here, or 1664 * check at a later time (for example, callback routine). 1665 */ 1666 if (phy->autoneg_wait_to_complete) { 1667 ret_val = hw->mac.ops.wait_autoneg(hw); 1668 if (ret_val) { 1669 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1670 return ret_val; 1671 } 1672 } 1673 1674 hw->mac.get_link_status = TRUE; 1675 1676 return ret_val; 1677 } 1678 1679 /** 1680 * e1000_setup_copper_link_generic - Configure copper link settings 1681 * @hw: pointer to the HW structure 1682 * 1683 * Calls the appropriate function to configure the link for auto-neg or forced 1684 * speed and duplex. Then we check for link, once link is established calls 1685 * to configure collision distance and flow control are called. If link is 1686 * not established, we return -E1000_ERR_PHY (-2). 1687 **/ 1688 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1689 { 1690 s32 ret_val; 1691 bool link; 1692 1693 DEBUGFUNC("e1000_setup_copper_link_generic"); 1694 1695 if (hw->mac.autoneg) { 1696 /* 1697 * Setup autoneg and flow control advertisement and perform 1698 * autonegotiation. 1699 */ 1700 ret_val = e1000_copper_link_autoneg(hw); 1701 if (ret_val) 1702 return ret_val; 1703 } else { 1704 /* 1705 * PHY will be set to 10H, 10F, 100H or 100F 1706 * depending on user settings. 1707 */ 1708 DEBUGOUT("Forcing Speed and Duplex\n"); 1709 ret_val = hw->phy.ops.force_speed_duplex(hw); 1710 if (ret_val) { 1711 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1712 return ret_val; 1713 } 1714 } 1715 1716 /* 1717 * Check link status. Wait up to 100 microseconds for link to become 1718 * valid. 1719 */ 1720 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1721 &link); 1722 if (ret_val) 1723 return ret_val; 1724 1725 if (link) { 1726 DEBUGOUT("Valid link established!!!\n"); 1727 hw->mac.ops.config_collision_dist(hw); 1728 ret_val = e1000_config_fc_after_link_up_generic(hw); 1729 } else { 1730 DEBUGOUT("Unable to establish link!!!\n"); 1731 } 1732 1733 return ret_val; 1734 } 1735 1736 /** 1737 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1738 * @hw: pointer to the HW structure 1739 * 1740 * Calls the PHY setup function to force speed and duplex. Clears the 1741 * auto-crossover to force MDI manually. Waits for link and returns 1742 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1743 **/ 1744 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1745 { 1746 struct e1000_phy_info *phy = &hw->phy; 1747 s32 ret_val; 1748 u16 phy_data; 1749 bool link; 1750 1751 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1752 1753 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1754 if (ret_val) 1755 return ret_val; 1756 1757 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1758 1759 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1760 if (ret_val) 1761 return ret_val; 1762 1763 /* 1764 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1765 * forced whenever speed and duplex are forced. 1766 */ 1767 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1768 if (ret_val) 1769 return ret_val; 1770 1771 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1772 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1773 1774 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1775 if (ret_val) 1776 return ret_val; 1777 1778 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1779 1780 usec_delay(1); 1781 1782 if (phy->autoneg_wait_to_complete) { 1783 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1784 1785 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1786 100000, &link); 1787 if (ret_val) 1788 return ret_val; 1789 1790 if (!link) 1791 DEBUGOUT("Link taking longer than expected.\n"); 1792 1793 /* Try once more */ 1794 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1795 100000, &link); 1796 } 1797 1798 return ret_val; 1799 } 1800 1801 /** 1802 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1803 * @hw: pointer to the HW structure 1804 * 1805 * Calls the PHY setup function to force speed and duplex. Clears the 1806 * auto-crossover to force MDI manually. Resets the PHY to commit the 1807 * changes. If time expires while waiting for link up, we reset the DSP. 1808 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1809 * successful completion, else return corresponding error code. 1810 **/ 1811 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1812 { 1813 struct e1000_phy_info *phy = &hw->phy; 1814 s32 ret_val; 1815 u16 phy_data; 1816 bool link; 1817 1818 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1819 1820 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1821 if (phy->type != e1000_phy_i210) { 1822 /* 1823 * Clear Auto-Crossover to force MDI manually. M88E1000 1824 * requires MDI forced whenever speed and duplex are forced. 1825 */ 1826 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1827 &phy_data); 1828 if (ret_val) 1829 return ret_val; 1830 1831 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1832 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1833 phy_data); 1834 if (ret_val) 1835 return ret_val; 1836 } 1837 1838 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1839 1840 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1841 if (ret_val) 1842 return ret_val; 1843 1844 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1845 1846 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1847 if (ret_val) 1848 return ret_val; 1849 1850 /* Reset the phy to commit changes. */ 1851 ret_val = hw->phy.ops.commit(hw); 1852 if (ret_val) 1853 return ret_val; 1854 1855 if (phy->autoneg_wait_to_complete) { 1856 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1857 1858 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1859 100000, &link); 1860 if (ret_val) 1861 return ret_val; 1862 1863 if (!link) { 1864 #if !defined(NO_DH89XXCC_SUPPORT) || defined(SPRINGVILLE_HW) 1865 bool reset_dsp = TRUE; 1866 1867 switch (hw->phy.id) { 1868 case I347AT4_E_PHY_ID: 1869 case M88E1340M_E_PHY_ID: 1870 case M88E1112_E_PHY_ID: 1871 case I210_I_PHY_ID: 1872 reset_dsp = FALSE; 1873 break; 1874 default: 1875 if (hw->phy.type != e1000_phy_m88) 1876 reset_dsp = FALSE; 1877 break; 1878 } 1879 1880 if (!reset_dsp) { 1881 #else /* !defined(NO_DH89XXCC_SUPPORT) || defined(SPRINGVILLE_HW) */ 1882 if (hw->phy.type != e1000_phy_m88) { 1883 #endif /* !defined(NO_DH89XXCC_SUPPORT) || defined(SPRINGVILLE_HW) */ 1884 DEBUGOUT("Link taking longer than expected.\n"); 1885 } else { 1886 /* 1887 * We didn't get link. 1888 * Reset the DSP and cross our fingers. 1889 */ 1890 ret_val = phy->ops.write_reg(hw, 1891 M88E1000_PHY_PAGE_SELECT, 1892 0x001d); 1893 if (ret_val) 1894 return ret_val; 1895 ret_val = e1000_phy_reset_dsp_generic(hw); 1896 if (ret_val) 1897 return ret_val; 1898 } 1899 } 1900 1901 /* Try once more */ 1902 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1903 100000, &link); 1904 if (ret_val) 1905 return ret_val; 1906 } 1907 1908 if (hw->phy.type != e1000_phy_m88) 1909 return E1000_SUCCESS; 1910 1911 if (hw->phy.id == I347AT4_E_PHY_ID || 1912 hw->phy.id == M88E1340M_E_PHY_ID || 1913 hw->phy.id == M88E1112_E_PHY_ID) 1914 return E1000_SUCCESS; 1915 if (hw->phy.id == I210_I_PHY_ID) 1916 return E1000_SUCCESS; 1917 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1918 if (ret_val) 1919 return ret_val; 1920 1921 /* 1922 * Resetting the phy means we need to re-force TX_CLK in the 1923 * Extended PHY Specific Control Register to 25MHz clock from 1924 * the reset value of 2.5MHz. 1925 */ 1926 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1927 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1928 if (ret_val) 1929 return ret_val; 1930 1931 /* 1932 * In addition, we must re-enable CRS on Tx for both half and full 1933 * duplex. 1934 */ 1935 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1936 if (ret_val) 1937 return ret_val; 1938 1939 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1940 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1941 1942 return ret_val; 1943 } 1944 1945 /** 1946 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1947 * @hw: pointer to the HW structure 1948 * 1949 * Forces the speed and duplex settings of the PHY. 1950 * This is a function pointer entry point only called by 1951 * PHY setup routines. 1952 **/ 1953 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1954 { 1955 struct e1000_phy_info *phy = &hw->phy; 1956 s32 ret_val; 1957 u16 data; 1958 bool link; 1959 1960 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1961 1962 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1963 if (ret_val) 1964 return ret_val; 1965 1966 e1000_phy_force_speed_duplex_setup(hw, &data); 1967 1968 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1969 if (ret_val) 1970 return ret_val; 1971 1972 /* Disable MDI-X support for 10/100 */ 1973 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1974 if (ret_val) 1975 return ret_val; 1976 1977 data &= ~IFE_PMC_AUTO_MDIX; 1978 data &= ~IFE_PMC_FORCE_MDIX; 1979 1980 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1981 if (ret_val) 1982 return ret_val; 1983 1984 DEBUGOUT1("IFE PMC: %X\n", data); 1985 1986 usec_delay(1); 1987 1988 if (phy->autoneg_wait_to_complete) { 1989 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1990 1991 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1992 100000, &link); 1993 if (ret_val) 1994 return ret_val; 1995 1996 if (!link) 1997 DEBUGOUT("Link taking longer than expected.\n"); 1998 1999 /* Try once more */ 2000 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 2001 100000, &link); 2002 if (ret_val) 2003 return ret_val; 2004 } 2005 2006 return E1000_SUCCESS; 2007 } 2008 2009 /** 2010 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 2011 * @hw: pointer to the HW structure 2012 * @phy_ctrl: pointer to current value of PHY_CONTROL 2013 * 2014 * Forces speed and duplex on the PHY by doing the following: disable flow 2015 * control, force speed/duplex on the MAC, disable auto speed detection, 2016 * disable auto-negotiation, configure duplex, configure speed, configure 2017 * the collision distance, write configuration to CTRL register. The 2018 * caller must write to the PHY_CONTROL register for these settings to 2019 * take affect. 2020 **/ 2021 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 2022 { 2023 struct e1000_mac_info *mac = &hw->mac; 2024 u32 ctrl; 2025 2026 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 2027 2028 /* Turn off flow control when forcing speed/duplex */ 2029 hw->fc.current_mode = e1000_fc_none; 2030 2031 /* Force speed/duplex on the mac */ 2032 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2033 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2034 ctrl &= ~E1000_CTRL_SPD_SEL; 2035 2036 /* Disable Auto Speed Detection */ 2037 ctrl &= ~E1000_CTRL_ASDE; 2038 2039 /* Disable autoneg on the phy */ 2040 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 2041 2042 /* Forcing Full or Half Duplex? */ 2043 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 2044 ctrl &= ~E1000_CTRL_FD; 2045 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 2046 DEBUGOUT("Half Duplex\n"); 2047 } else { 2048 ctrl |= E1000_CTRL_FD; 2049 *phy_ctrl |= MII_CR_FULL_DUPLEX; 2050 DEBUGOUT("Full Duplex\n"); 2051 } 2052 2053 /* Forcing 10mb or 100mb? */ 2054 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 2055 ctrl |= E1000_CTRL_SPD_100; 2056 *phy_ctrl |= MII_CR_SPEED_100; 2057 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 2058 DEBUGOUT("Forcing 100mb\n"); 2059 } else { 2060 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2061 *phy_ctrl |= MII_CR_SPEED_10; 2062 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2063 DEBUGOUT("Forcing 10mb\n"); 2064 } 2065 2066 hw->mac.ops.config_collision_dist(hw); 2067 2068 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2069 } 2070 2071 /** 2072 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 2073 * @hw: pointer to the HW structure 2074 * @active: boolean used to enable/disable lplu 2075 * 2076 * Success returns 0, Failure returns 1 2077 * 2078 * The low power link up (lplu) state is set to the power management level D3 2079 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 2080 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2081 * is used during Dx states where the power conservation is most important. 2082 * During driver activity, SmartSpeed should be enabled so performance is 2083 * maintained. 2084 **/ 2085 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 2086 { 2087 struct e1000_phy_info *phy = &hw->phy; 2088 s32 ret_val; 2089 u16 data; 2090 2091 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 2092 2093 if (!hw->phy.ops.read_reg) 2094 return E1000_SUCCESS; 2095 2096 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 2097 if (ret_val) 2098 return ret_val; 2099 2100 if (!active) { 2101 data &= ~IGP02E1000_PM_D3_LPLU; 2102 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2103 data); 2104 if (ret_val) 2105 return ret_val; 2106 /* 2107 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 2108 * during Dx states where the power conservation is most 2109 * important. During driver activity we should enable 2110 * SmartSpeed, so performance is maintained. 2111 */ 2112 if (phy->smart_speed == e1000_smart_speed_on) { 2113 ret_val = phy->ops.read_reg(hw, 2114 IGP01E1000_PHY_PORT_CONFIG, 2115 &data); 2116 if (ret_val) 2117 return ret_val; 2118 2119 data |= IGP01E1000_PSCFR_SMART_SPEED; 2120 ret_val = phy->ops.write_reg(hw, 2121 IGP01E1000_PHY_PORT_CONFIG, 2122 data); 2123 if (ret_val) 2124 return ret_val; 2125 } else if (phy->smart_speed == e1000_smart_speed_off) { 2126 ret_val = phy->ops.read_reg(hw, 2127 IGP01E1000_PHY_PORT_CONFIG, 2128 &data); 2129 if (ret_val) 2130 return ret_val; 2131 2132 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2133 ret_val = phy->ops.write_reg(hw, 2134 IGP01E1000_PHY_PORT_CONFIG, 2135 data); 2136 if (ret_val) 2137 return ret_val; 2138 } 2139 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2140 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2141 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2142 data |= IGP02E1000_PM_D3_LPLU; 2143 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2144 data); 2145 if (ret_val) 2146 return ret_val; 2147 2148 /* When LPLU is enabled, we should disable SmartSpeed */ 2149 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2150 &data); 2151 if (ret_val) 2152 return ret_val; 2153 2154 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2155 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2156 data); 2157 } 2158 2159 return ret_val; 2160 } 2161 2162 /** 2163 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 2164 * @hw: pointer to the HW structure 2165 * 2166 * Success returns 0, Failure returns 1 2167 * 2168 * A downshift is detected by querying the PHY link health. 2169 **/ 2170 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 2171 { 2172 struct e1000_phy_info *phy = &hw->phy; 2173 s32 ret_val; 2174 u16 phy_data, offset, mask; 2175 2176 DEBUGFUNC("e1000_check_downshift_generic"); 2177 2178 switch (phy->type) { 2179 case e1000_phy_i210: 2180 case e1000_phy_m88: 2181 case e1000_phy_gg82563: 2182 case e1000_phy_bm: 2183 case e1000_phy_82578: 2184 offset = M88E1000_PHY_SPEC_STATUS; 2185 mask = M88E1000_PSSR_DOWNSHIFT; 2186 break; 2187 case e1000_phy_igp: 2188 case e1000_phy_igp_2: 2189 case e1000_phy_igp_3: 2190 offset = IGP01E1000_PHY_LINK_HEALTH; 2191 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 2192 break; 2193 default: 2194 /* speed downshift not supported */ 2195 phy->speed_downgraded = FALSE; 2196 return E1000_SUCCESS; 2197 } 2198 2199 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2200 2201 if (!ret_val) 2202 phy->speed_downgraded = !!(phy_data & mask); 2203 2204 return ret_val; 2205 } 2206 2207 /** 2208 * e1000_check_polarity_m88 - Checks the polarity. 2209 * @hw: pointer to the HW structure 2210 * 2211 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2212 * 2213 * Polarity is determined based on the PHY specific status register. 2214 **/ 2215 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 2216 { 2217 struct e1000_phy_info *phy = &hw->phy; 2218 s32 ret_val; 2219 u16 data; 2220 2221 DEBUGFUNC("e1000_check_polarity_m88"); 2222 2223 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 2224 2225 if (!ret_val) 2226 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 2227 ? e1000_rev_polarity_reversed 2228 : e1000_rev_polarity_normal; 2229 2230 return ret_val; 2231 } 2232 2233 /** 2234 * e1000_check_polarity_igp - Checks the polarity. 2235 * @hw: pointer to the HW structure 2236 * 2237 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2238 * 2239 * Polarity is determined based on the PHY port status register, and the 2240 * current speed (since there is no polarity at 100Mbps). 2241 **/ 2242 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 2243 { 2244 struct e1000_phy_info *phy = &hw->phy; 2245 s32 ret_val; 2246 u16 data, offset, mask; 2247 2248 DEBUGFUNC("e1000_check_polarity_igp"); 2249 2250 /* 2251 * Polarity is determined based on the speed of 2252 * our connection. 2253 */ 2254 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2255 if (ret_val) 2256 return ret_val; 2257 2258 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2259 IGP01E1000_PSSR_SPEED_1000MBPS) { 2260 offset = IGP01E1000_PHY_PCS_INIT_REG; 2261 mask = IGP01E1000_PHY_POLARITY_MASK; 2262 } else { 2263 /* 2264 * This really only applies to 10Mbps since 2265 * there is no polarity for 100Mbps (always 0). 2266 */ 2267 offset = IGP01E1000_PHY_PORT_STATUS; 2268 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2269 } 2270 2271 ret_val = phy->ops.read_reg(hw, offset, &data); 2272 2273 if (!ret_val) 2274 phy->cable_polarity = (data & mask) 2275 ? e1000_rev_polarity_reversed 2276 : e1000_rev_polarity_normal; 2277 2278 return ret_val; 2279 } 2280 2281 /** 2282 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2283 * @hw: pointer to the HW structure 2284 * 2285 * Polarity is determined on the polarity reversal feature being enabled. 2286 **/ 2287 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 2288 { 2289 struct e1000_phy_info *phy = &hw->phy; 2290 s32 ret_val; 2291 u16 phy_data, offset, mask; 2292 2293 DEBUGFUNC("e1000_check_polarity_ife"); 2294 2295 /* 2296 * Polarity is determined based on the reversal feature being enabled. 2297 */ 2298 if (phy->polarity_correction) { 2299 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2300 mask = IFE_PESC_POLARITY_REVERSED; 2301 } else { 2302 offset = IFE_PHY_SPECIAL_CONTROL; 2303 mask = IFE_PSC_FORCE_POLARITY; 2304 } 2305 2306 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2307 2308 if (!ret_val) 2309 phy->cable_polarity = (phy_data & mask) 2310 ? e1000_rev_polarity_reversed 2311 : e1000_rev_polarity_normal; 2312 2313 return ret_val; 2314 } 2315 2316 /** 2317 * e1000_wait_autoneg_generic - Wait for auto-neg completion 2318 * @hw: pointer to the HW structure 2319 * 2320 * Waits for auto-negotiation to complete or for the auto-negotiation time 2321 * limit to expire, which ever happens first. 2322 **/ 2323 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) 2324 { 2325 s32 ret_val = E1000_SUCCESS; 2326 u16 i, phy_status; 2327 2328 DEBUGFUNC("e1000_wait_autoneg_generic"); 2329 2330 if (!hw->phy.ops.read_reg) 2331 return E1000_SUCCESS; 2332 2333 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2334 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2335 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2336 if (ret_val) 2337 break; 2338 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2339 if (ret_val) 2340 break; 2341 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2342 break; 2343 msec_delay(100); 2344 } 2345 2346 /* 2347 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2348 * has completed. 2349 */ 2350 return ret_val; 2351 } 2352 2353 /** 2354 * e1000_phy_has_link_generic - Polls PHY for link 2355 * @hw: pointer to the HW structure 2356 * @iterations: number of times to poll for link 2357 * @usec_interval: delay between polling attempts 2358 * @success: pointer to whether polling was successful or not 2359 * 2360 * Polls the PHY status register for link, 'iterations' number of times. 2361 **/ 2362 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2363 u32 usec_interval, bool *success) 2364 { 2365 s32 ret_val = E1000_SUCCESS; 2366 u16 i, phy_status; 2367 2368 DEBUGFUNC("e1000_phy_has_link_generic"); 2369 2370 if (!hw->phy.ops.read_reg) 2371 return E1000_SUCCESS; 2372 2373 for (i = 0; i < iterations; i++) { 2374 /* 2375 * Some PHYs require the PHY_STATUS register to be read 2376 * twice due to the link bit being sticky. No harm doing 2377 * it across the board. 2378 */ 2379 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2380 if (ret_val) 2381 /* 2382 * If the first read fails, another entity may have 2383 * ownership of the resources, wait and try again to 2384 * see if they have relinquished the resources yet. 2385 */ 2386 usec_delay(usec_interval); 2387 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2388 if (ret_val) 2389 break; 2390 if (phy_status & MII_SR_LINK_STATUS) 2391 break; 2392 if (usec_interval >= 1000) 2393 msec_delay_irq(usec_interval/1000); 2394 else 2395 usec_delay(usec_interval); 2396 } 2397 2398 *success = (i < iterations); 2399 2400 return ret_val; 2401 } 2402 2403 /** 2404 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2405 * @hw: pointer to the HW structure 2406 * 2407 * Reads the PHY specific status register to retrieve the cable length 2408 * information. The cable length is determined by averaging the minimum and 2409 * maximum values to get the "average" cable length. The m88 PHY has four 2410 * possible cable length values, which are: 2411 * Register Value Cable Length 2412 * 0 < 50 meters 2413 * 1 50 - 80 meters 2414 * 2 80 - 110 meters 2415 * 3 110 - 140 meters 2416 * 4 > 140 meters 2417 **/ 2418 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2419 { 2420 struct e1000_phy_info *phy = &hw->phy; 2421 s32 ret_val; 2422 u16 phy_data, index; 2423 2424 DEBUGFUNC("e1000_get_cable_length_m88"); 2425 2426 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2427 if (ret_val) 2428 return ret_val; 2429 2430 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2431 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2432 2433 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2434 return -E1000_ERR_PHY; 2435 2436 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2437 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2438 2439 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2440 2441 return E1000_SUCCESS; 2442 } 2443 2444 #if !defined(NO_DH89XXCC_SUPPORT) || defined(SPRINGVILLE_HW) 2445 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2446 { 2447 struct e1000_phy_info *phy = &hw->phy; 2448 s32 ret_val; 2449 u16 phy_data, phy_data2, index, default_page, is_cm; 2450 2451 DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2452 2453 switch (hw->phy.id) { 2454 case I210_I_PHY_ID: 2455 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2456 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2457 (I347AT4_PCDL + phy->addr), 2458 &phy_data); 2459 if (ret_val) 2460 return ret_val; 2461 2462 /* Check if the unit of cable length is meters or cm */ 2463 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2464 I347AT4_PCDC, &phy_data2); 2465 if (ret_val) 2466 return ret_val; 2467 2468 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2469 2470 /* Populate the phy structure with cable length in meters */ 2471 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2472 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2473 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2474 break; 2475 case M88E1340M_E_PHY_ID: 2476 case I347AT4_E_PHY_ID: 2477 /* Remember the original page select and set it to 7 */ 2478 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2479 &default_page); 2480 if (ret_val) 2481 return ret_val; 2482 2483 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2484 if (ret_val) 2485 return ret_val; 2486 2487 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2488 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2489 &phy_data); 2490 if (ret_val) 2491 return ret_val; 2492 2493 /* Check if the unit of cable length is meters or cm */ 2494 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2495 if (ret_val) 2496 return ret_val; 2497 2498 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2499 2500 /* Populate the phy structure with cable length in meters */ 2501 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2502 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2503 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2504 2505 /* Reset the page select to its original value */ 2506 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2507 default_page); 2508 if (ret_val) 2509 return ret_val; 2510 break; 2511 2512 case M88E1112_E_PHY_ID: 2513 /* Remember the original page select and set it to 5 */ 2514 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2515 &default_page); 2516 if (ret_val) 2517 return ret_val; 2518 2519 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2520 if (ret_val) 2521 return ret_val; 2522 2523 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2524 &phy_data); 2525 if (ret_val) 2526 return ret_val; 2527 2528 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2529 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2530 2531 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2532 return -E1000_ERR_PHY; 2533 2534 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2535 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2536 2537 phy->cable_length = (phy->min_cable_length + 2538 phy->max_cable_length) / 2; 2539 2540 /* Reset the page select to its original value */ 2541 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2542 default_page); 2543 if (ret_val) 2544 return ret_val; 2545 2546 break; 2547 default: 2548 return -E1000_ERR_PHY; 2549 } 2550 2551 return ret_val; 2552 } 2553 2554 #endif /* !defined(NO_DH89XXCC_SUPPORT) || defined(SPRINGVILLE_HW) */ 2555 /** 2556 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2557 * @hw: pointer to the HW structure 2558 * 2559 * The automatic gain control (agc) normalizes the amplitude of the 2560 * received signal, adjusting for the attenuation produced by the 2561 * cable. By reading the AGC registers, which represent the 2562 * combination of coarse and fine gain value, the value can be put 2563 * into a lookup table to obtain the approximate cable length 2564 * for each channel. 2565 **/ 2566 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2567 { 2568 struct e1000_phy_info *phy = &hw->phy; 2569 s32 ret_val; 2570 u16 phy_data, i, agc_value = 0; 2571 u16 cur_agc_index, max_agc_index = 0; 2572 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2573 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2574 IGP02E1000_PHY_AGC_A, 2575 IGP02E1000_PHY_AGC_B, 2576 IGP02E1000_PHY_AGC_C, 2577 IGP02E1000_PHY_AGC_D 2578 }; 2579 2580 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2581 2582 /* Read the AGC registers for all channels */ 2583 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2584 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2585 if (ret_val) 2586 return ret_val; 2587 2588 /* 2589 * Getting bits 15:9, which represent the combination of 2590 * coarse and fine gain values. The result is a number 2591 * that can be put into the lookup table to obtain the 2592 * approximate cable length. 2593 */ 2594 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2595 IGP02E1000_AGC_LENGTH_MASK; 2596 2597 /* Array index bound check. */ 2598 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2599 (cur_agc_index == 0)) 2600 return -E1000_ERR_PHY; 2601 2602 /* Remove min & max AGC values from calculation. */ 2603 if (e1000_igp_2_cable_length_table[min_agc_index] > 2604 e1000_igp_2_cable_length_table[cur_agc_index]) 2605 min_agc_index = cur_agc_index; 2606 if (e1000_igp_2_cable_length_table[max_agc_index] < 2607 e1000_igp_2_cable_length_table[cur_agc_index]) 2608 max_agc_index = cur_agc_index; 2609 2610 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2611 } 2612 2613 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2614 e1000_igp_2_cable_length_table[max_agc_index]); 2615 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2616 2617 /* Calculate cable length with the error range of +/- 10 meters. */ 2618 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2619 (agc_value - IGP02E1000_AGC_RANGE) : 0; 2620 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2621 2622 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2623 2624 return E1000_SUCCESS; 2625 } 2626 2627 /** 2628 * e1000_get_phy_info_m88 - Retrieve PHY information 2629 * @hw: pointer to the HW structure 2630 * 2631 * Valid for only copper links. Read the PHY status register (sticky read) 2632 * to verify that link is up. Read the PHY special control register to 2633 * determine the polarity and 10base-T extended distance. Read the PHY 2634 * special status register to determine MDI/MDIx and current speed. If 2635 * speed is 1000, then determine cable length, local and remote receiver. 2636 **/ 2637 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2638 { 2639 struct e1000_phy_info *phy = &hw->phy; 2640 s32 ret_val; 2641 u16 phy_data; 2642 bool link; 2643 2644 DEBUGFUNC("e1000_get_phy_info_m88"); 2645 2646 if (phy->media_type != e1000_media_type_copper) { 2647 DEBUGOUT("Phy info is only valid for copper media\n"); 2648 return -E1000_ERR_CONFIG; 2649 } 2650 2651 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2652 if (ret_val) 2653 return ret_val; 2654 2655 if (!link) { 2656 DEBUGOUT("Phy info is only valid if link is up\n"); 2657 return -E1000_ERR_CONFIG; 2658 } 2659 2660 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2661 if (ret_val) 2662 return ret_val; 2663 2664 phy->polarity_correction = !!(phy_data & 2665 M88E1000_PSCR_POLARITY_REVERSAL); 2666 2667 ret_val = e1000_check_polarity_m88(hw); 2668 if (ret_val) 2669 return ret_val; 2670 2671 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2672 if (ret_val) 2673 return ret_val; 2674 2675 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 2676 2677 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2678 ret_val = hw->phy.ops.get_cable_length(hw); 2679 if (ret_val) 2680 return ret_val; 2681 2682 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2683 if (ret_val) 2684 return ret_val; 2685 2686 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2687 ? e1000_1000t_rx_status_ok 2688 : e1000_1000t_rx_status_not_ok; 2689 2690 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2691 ? e1000_1000t_rx_status_ok 2692 : e1000_1000t_rx_status_not_ok; 2693 } else { 2694 /* Set values to "undefined" */ 2695 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2696 phy->local_rx = e1000_1000t_rx_status_undefined; 2697 phy->remote_rx = e1000_1000t_rx_status_undefined; 2698 } 2699 2700 return ret_val; 2701 } 2702 2703 /** 2704 * e1000_get_phy_info_igp - Retrieve igp PHY information 2705 * @hw: pointer to the HW structure 2706 * 2707 * Read PHY status to determine if link is up. If link is up, then 2708 * set/determine 10base-T extended distance and polarity correction. Read 2709 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2710 * determine on the cable length, local and remote receiver. 2711 **/ 2712 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2713 { 2714 struct e1000_phy_info *phy = &hw->phy; 2715 s32 ret_val; 2716 u16 data; 2717 bool link; 2718 2719 DEBUGFUNC("e1000_get_phy_info_igp"); 2720 2721 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2722 if (ret_val) 2723 return ret_val; 2724 2725 if (!link) { 2726 DEBUGOUT("Phy info is only valid if link is up\n"); 2727 return -E1000_ERR_CONFIG; 2728 } 2729 2730 phy->polarity_correction = TRUE; 2731 2732 ret_val = e1000_check_polarity_igp(hw); 2733 if (ret_val) 2734 return ret_val; 2735 2736 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2737 if (ret_val) 2738 return ret_val; 2739 2740 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 2741 2742 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2743 IGP01E1000_PSSR_SPEED_1000MBPS) { 2744 ret_val = phy->ops.get_cable_length(hw); 2745 if (ret_val) 2746 return ret_val; 2747 2748 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2749 if (ret_val) 2750 return ret_val; 2751 2752 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2753 ? e1000_1000t_rx_status_ok 2754 : e1000_1000t_rx_status_not_ok; 2755 2756 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2757 ? e1000_1000t_rx_status_ok 2758 : e1000_1000t_rx_status_not_ok; 2759 } else { 2760 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2761 phy->local_rx = e1000_1000t_rx_status_undefined; 2762 phy->remote_rx = e1000_1000t_rx_status_undefined; 2763 } 2764 2765 return ret_val; 2766 } 2767 2768 /** 2769 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2770 * @hw: pointer to the HW structure 2771 * 2772 * Populates "phy" structure with various feature states. 2773 **/ 2774 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2775 { 2776 struct e1000_phy_info *phy = &hw->phy; 2777 s32 ret_val; 2778 u16 data; 2779 bool link; 2780 2781 DEBUGFUNC("e1000_get_phy_info_ife"); 2782 2783 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2784 if (ret_val) 2785 return ret_val; 2786 2787 if (!link) { 2788 DEBUGOUT("Phy info is only valid if link is up\n"); 2789 return -E1000_ERR_CONFIG; 2790 } 2791 2792 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2793 if (ret_val) 2794 return ret_val; 2795 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2796 2797 if (phy->polarity_correction) { 2798 ret_val = e1000_check_polarity_ife(hw); 2799 if (ret_val) 2800 return ret_val; 2801 } else { 2802 /* Polarity is forced */ 2803 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2804 ? e1000_rev_polarity_reversed 2805 : e1000_rev_polarity_normal; 2806 } 2807 2808 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2809 if (ret_val) 2810 return ret_val; 2811 2812 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2813 2814 /* The following parameters are undefined for 10/100 operation. */ 2815 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2816 phy->local_rx = e1000_1000t_rx_status_undefined; 2817 phy->remote_rx = e1000_1000t_rx_status_undefined; 2818 2819 return E1000_SUCCESS; 2820 } 2821 2822 /** 2823 * e1000_phy_sw_reset_generic - PHY software reset 2824 * @hw: pointer to the HW structure 2825 * 2826 * Does a software reset of the PHY by reading the PHY control register and 2827 * setting/write the control register reset bit to the PHY. 2828 **/ 2829 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2830 { 2831 s32 ret_val; 2832 u16 phy_ctrl; 2833 2834 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2835 2836 if (!hw->phy.ops.read_reg) 2837 return E1000_SUCCESS; 2838 2839 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2840 if (ret_val) 2841 return ret_val; 2842 2843 phy_ctrl |= MII_CR_RESET; 2844 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2845 if (ret_val) 2846 return ret_val; 2847 2848 usec_delay(1); 2849 2850 return ret_val; 2851 } 2852 2853 /** 2854 * e1000_phy_hw_reset_generic - PHY hardware reset 2855 * @hw: pointer to the HW structure 2856 * 2857 * Verify the reset block is not blocking us from resetting. Acquire 2858 * semaphore (if necessary) and read/set/write the device control reset 2859 * bit in the PHY. Wait the appropriate delay time for the device to 2860 * reset and release the semaphore (if necessary). 2861 **/ 2862 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2863 { 2864 struct e1000_phy_info *phy = &hw->phy; 2865 s32 ret_val; 2866 u32 ctrl; 2867 2868 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2869 2870 if (phy->ops.check_reset_block) { 2871 ret_val = phy->ops.check_reset_block(hw); 2872 if (ret_val) 2873 return E1000_SUCCESS; 2874 } 2875 2876 ret_val = phy->ops.acquire(hw); 2877 if (ret_val) 2878 return ret_val; 2879 2880 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2881 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2882 E1000_WRITE_FLUSH(hw); 2883 2884 usec_delay(phy->reset_delay_us); 2885 2886 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2887 E1000_WRITE_FLUSH(hw); 2888 2889 usec_delay(150); 2890 2891 phy->ops.release(hw); 2892 2893 return phy->ops.get_cfg_done(hw); 2894 } 2895 2896 /** 2897 * e1000_get_cfg_done_generic - Generic configuration done 2898 * @hw: pointer to the HW structure 2899 * 2900 * Generic function to wait 10 milli-seconds for configuration to complete 2901 * and return success. 2902 **/ 2903 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2904 { 2905 DEBUGFUNC("e1000_get_cfg_done_generic"); 2906 2907 msec_delay_irq(10); 2908 2909 return E1000_SUCCESS; 2910 } 2911 2912 /** 2913 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2914 * @hw: pointer to the HW structure 2915 * 2916 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2917 **/ 2918 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2919 { 2920 DEBUGOUT("Running IGP 3 PHY init script\n"); 2921 2922 /* PHY init IGP 3 */ 2923 /* Enable rise/fall, 10-mode work in class-A */ 2924 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2925 /* Remove all caps from Replica path filter */ 2926 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2927 /* Bias trimming for ADC, AFE and Driver (Default) */ 2928 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2929 /* Increase Hybrid poly bias */ 2930 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2931 /* Add 4% to Tx amplitude in Gig mode */ 2932 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2933 /* Disable trimming (TTT) */ 2934 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2935 /* Poly DC correction to 94.6% + 2% for all channels */ 2936 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2937 /* ABS DC correction to 95.9% */ 2938 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2939 /* BG temp curve trim */ 2940 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2941 /* Increasing ADC OPAMP stage 1 currents to max */ 2942 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2943 /* Force 1000 ( required for enabling PHY regs configuration) */ 2944 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2945 /* Set upd_freq to 6 */ 2946 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2947 /* Disable NPDFE */ 2948 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2949 /* Disable adaptive fixed FFE (Default) */ 2950 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2951 /* Enable FFE hysteresis */ 2952 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2953 /* Fixed FFE for short cable lengths */ 2954 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2955 /* Fixed FFE for medium cable lengths */ 2956 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2957 /* Fixed FFE for long cable lengths */ 2958 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2959 /* Enable Adaptive Clip Threshold */ 2960 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2961 /* AHT reset limit to 1 */ 2962 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2963 /* Set AHT master delay to 127 msec */ 2964 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2965 /* Set scan bits for AHT */ 2966 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2967 /* Set AHT Preset bits */ 2968 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2969 /* Change integ_factor of channel A to 3 */ 2970 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2971 /* Change prop_factor of channels BCD to 8 */ 2972 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2973 /* Change cg_icount + enable integbp for channels BCD */ 2974 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2975 /* 2976 * Change cg_icount + enable integbp + change prop_factor_master 2977 * to 8 for channel A 2978 */ 2979 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2980 /* Disable AHT in Slave mode on channel A */ 2981 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2982 /* 2983 * Enable LPLU and disable AN to 1000 in non-D0a states, 2984 * Enable SPD+B2B 2985 */ 2986 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2987 /* Enable restart AN on an1000_dis change */ 2988 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2989 /* Enable wh_fifo read clock in 10/100 modes */ 2990 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2991 /* Restart AN, Speed selection is 1000 */ 2992 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2993 2994 return E1000_SUCCESS; 2995 } 2996 2997 /** 2998 * e1000_get_phy_type_from_id - Get PHY type from id 2999 * @phy_id: phy_id read from the phy 3000 * 3001 * Returns the phy type from the id. 3002 **/ 3003 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 3004 { 3005 enum e1000_phy_type phy_type = e1000_phy_unknown; 3006 3007 switch (phy_id) { 3008 case M88E1000_I_PHY_ID: 3009 case M88E1000_E_PHY_ID: 3010 case M88E1111_I_PHY_ID: 3011 case M88E1011_I_PHY_ID: 3012 case I347AT4_E_PHY_ID: 3013 case M88E1112_E_PHY_ID: 3014 case M88E1340M_E_PHY_ID: 3015 phy_type = e1000_phy_m88; 3016 break; 3017 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 3018 phy_type = e1000_phy_igp_2; 3019 break; 3020 case GG82563_E_PHY_ID: 3021 phy_type = e1000_phy_gg82563; 3022 break; 3023 case IGP03E1000_E_PHY_ID: 3024 phy_type = e1000_phy_igp_3; 3025 break; 3026 case IFE_E_PHY_ID: 3027 case IFE_PLUS_E_PHY_ID: 3028 case IFE_C_E_PHY_ID: 3029 phy_type = e1000_phy_ife; 3030 break; 3031 case BME1000_E_PHY_ID: 3032 case BME1000_E_PHY_ID_R2: 3033 phy_type = e1000_phy_bm; 3034 break; 3035 case I82578_E_PHY_ID: 3036 phy_type = e1000_phy_82578; 3037 break; 3038 case I82577_E_PHY_ID: 3039 phy_type = e1000_phy_82577; 3040 break; 3041 case I82579_E_PHY_ID: 3042 phy_type = e1000_phy_82579; 3043 break; 3044 case I82580_I_PHY_ID: 3045 phy_type = e1000_phy_82580; 3046 break; 3047 case I210_I_PHY_ID: 3048 phy_type = e1000_phy_i210; 3049 break; 3050 default: 3051 phy_type = e1000_phy_unknown; 3052 break; 3053 } 3054 return phy_type; 3055 } 3056 3057 /** 3058 * e1000_determine_phy_address - Determines PHY address. 3059 * @hw: pointer to the HW structure 3060 * 3061 * This uses a trial and error method to loop through possible PHY 3062 * addresses. It tests each by reading the PHY ID registers and 3063 * checking for a match. 3064 **/ 3065 s32 e1000_determine_phy_address(struct e1000_hw *hw) 3066 { 3067 u32 phy_addr = 0; 3068 u32 i; 3069 enum e1000_phy_type phy_type = e1000_phy_unknown; 3070 3071 hw->phy.id = phy_type; 3072 3073 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 3074 hw->phy.addr = phy_addr; 3075 i = 0; 3076 3077 do { 3078 e1000_get_phy_id(hw); 3079 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 3080 3081 /* 3082 * If phy_type is valid, break - we found our 3083 * PHY address 3084 */ 3085 if (phy_type != e1000_phy_unknown) 3086 return E1000_SUCCESS; 3087 3088 msec_delay(1); 3089 i++; 3090 } while (i < 10); 3091 } 3092 3093 return -E1000_ERR_PHY_TYPE; 3094 } 3095 3096 /** 3097 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 3098 * @page: page to access 3099 * 3100 * Returns the phy address for the page requested. 3101 **/ 3102 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 3103 { 3104 u32 phy_addr = 2; 3105 3106 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 3107 phy_addr = 1; 3108 3109 return phy_addr; 3110 } 3111 3112 /** 3113 * e1000_write_phy_reg_bm - Write BM PHY register 3114 * @hw: pointer to the HW structure 3115 * @offset: register offset to write to 3116 * @data: data to write at register offset 3117 * 3118 * Acquires semaphore, if necessary, then writes the data to PHY register 3119 * at the offset. Release any acquired semaphores before exiting. 3120 **/ 3121 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 3122 { 3123 s32 ret_val; 3124 u32 page = offset >> IGP_PAGE_SHIFT; 3125 3126 DEBUGFUNC("e1000_write_phy_reg_bm"); 3127 3128 ret_val = hw->phy.ops.acquire(hw); 3129 if (ret_val) 3130 return ret_val; 3131 3132 /* Page 800 works differently than the rest so it has its own func */ 3133 if (page == BM_WUC_PAGE) { 3134 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3135 FALSE, FALSE); 3136 goto release; 3137 } 3138 3139 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3140 3141 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3142 u32 page_shift, page_select; 3143 3144 /* 3145 * Page select is register 31 for phy address 1 and 22 for 3146 * phy address 2 and 3. Page select is shifted only for 3147 * phy address 1. 3148 */ 3149 if (hw->phy.addr == 1) { 3150 page_shift = IGP_PAGE_SHIFT; 3151 page_select = IGP01E1000_PHY_PAGE_SELECT; 3152 } else { 3153 page_shift = 0; 3154 page_select = BM_PHY_PAGE_SELECT; 3155 } 3156 3157 /* Page is shifted left, PHY expects (page x 32) */ 3158 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3159 (page << page_shift)); 3160 if (ret_val) 3161 goto release; 3162 } 3163 3164 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3165 data); 3166 3167 release: 3168 hw->phy.ops.release(hw); 3169 return ret_val; 3170 } 3171 3172 /** 3173 * e1000_read_phy_reg_bm - Read BM PHY register 3174 * @hw: pointer to the HW structure 3175 * @offset: register offset to be read 3176 * @data: pointer to the read data 3177 * 3178 * Acquires semaphore, if necessary, then reads the PHY register at offset 3179 * and storing the retrieved information in data. Release any acquired 3180 * semaphores before exiting. 3181 **/ 3182 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 3183 { 3184 s32 ret_val; 3185 u32 page = offset >> IGP_PAGE_SHIFT; 3186 3187 DEBUGFUNC("e1000_read_phy_reg_bm"); 3188 3189 ret_val = hw->phy.ops.acquire(hw); 3190 if (ret_val) 3191 return ret_val; 3192 3193 /* Page 800 works differently than the rest so it has its own func */ 3194 if (page == BM_WUC_PAGE) { 3195 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3196 TRUE, FALSE); 3197 goto release; 3198 } 3199 3200 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3201 3202 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3203 u32 page_shift, page_select; 3204 3205 /* 3206 * Page select is register 31 for phy address 1 and 22 for 3207 * phy address 2 and 3. Page select is shifted only for 3208 * phy address 1. 3209 */ 3210 if (hw->phy.addr == 1) { 3211 page_shift = IGP_PAGE_SHIFT; 3212 page_select = IGP01E1000_PHY_PAGE_SELECT; 3213 } else { 3214 page_shift = 0; 3215 page_select = BM_PHY_PAGE_SELECT; 3216 } 3217 3218 /* Page is shifted left, PHY expects (page x 32) */ 3219 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3220 (page << page_shift)); 3221 if (ret_val) 3222 goto release; 3223 } 3224 3225 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3226 data); 3227 release: 3228 hw->phy.ops.release(hw); 3229 return ret_val; 3230 } 3231 3232 /** 3233 * e1000_read_phy_reg_bm2 - Read BM PHY register 3234 * @hw: pointer to the HW structure 3235 * @offset: register offset to be read 3236 * @data: pointer to the read data 3237 * 3238 * Acquires semaphore, if necessary, then reads the PHY register at offset 3239 * and storing the retrieved information in data. Release any acquired 3240 * semaphores before exiting. 3241 **/ 3242 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3243 { 3244 s32 ret_val; 3245 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3246 3247 DEBUGFUNC("e1000_read_phy_reg_bm2"); 3248 3249 ret_val = hw->phy.ops.acquire(hw); 3250 if (ret_val) 3251 return ret_val; 3252 3253 /* Page 800 works differently than the rest so it has its own func */ 3254 if (page == BM_WUC_PAGE) { 3255 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3256 TRUE, FALSE); 3257 goto release; 3258 } 3259 3260 hw->phy.addr = 1; 3261 3262 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3263 3264 /* Page is shifted left, PHY expects (page x 32) */ 3265 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3266 page); 3267 3268 if (ret_val) 3269 goto release; 3270 } 3271 3272 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3273 data); 3274 release: 3275 hw->phy.ops.release(hw); 3276 return ret_val; 3277 } 3278 3279 /** 3280 * e1000_write_phy_reg_bm2 - Write BM PHY register 3281 * @hw: pointer to the HW structure 3282 * @offset: register offset to write to 3283 * @data: data to write at register offset 3284 * 3285 * Acquires semaphore, if necessary, then writes the data to PHY register 3286 * at the offset. Release any acquired semaphores before exiting. 3287 **/ 3288 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3289 { 3290 s32 ret_val; 3291 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3292 3293 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3294 3295 ret_val = hw->phy.ops.acquire(hw); 3296 if (ret_val) 3297 return ret_val; 3298 3299 /* Page 800 works differently than the rest so it has its own func */ 3300 if (page == BM_WUC_PAGE) { 3301 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3302 FALSE, FALSE); 3303 goto release; 3304 } 3305 3306 hw->phy.addr = 1; 3307 3308 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3309 /* Page is shifted left, PHY expects (page x 32) */ 3310 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3311 page); 3312 3313 if (ret_val) 3314 goto release; 3315 } 3316 3317 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3318 data); 3319 3320 release: 3321 hw->phy.ops.release(hw); 3322 return ret_val; 3323 } 3324 3325 /** 3326 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 3327 * @hw: pointer to the HW structure 3328 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 3329 * 3330 * Assumes semaphore already acquired and phy_reg points to a valid memory 3331 * address to store contents of the BM_WUC_ENABLE_REG register. 3332 **/ 3333 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3334 { 3335 s32 ret_val; 3336 u16 temp; 3337 3338 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm"); 3339 3340 if (!phy_reg) 3341 return -E1000_ERR_PARAM; 3342 3343 /* All page select, port ctrl and wakeup registers use phy address 1 */ 3344 hw->phy.addr = 1; 3345 3346 /* Select Port Control Registers page */ 3347 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3348 if (ret_val) { 3349 DEBUGOUT("Could not set Port Control page\n"); 3350 return ret_val; 3351 } 3352 3353 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3354 if (ret_val) { 3355 DEBUGOUT2("Could not read PHY register %d.%d\n", 3356 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3357 return ret_val; 3358 } 3359 3360 /* 3361 * Enable both PHY wakeup mode and Wakeup register page writes. 3362 * Prevent a power state change by disabling ME and Host PHY wakeup. 3363 */ 3364 temp = *phy_reg; 3365 temp |= BM_WUC_ENABLE_BIT; 3366 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 3367 3368 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 3369 if (ret_val) { 3370 DEBUGOUT2("Could not write PHY register %d.%d\n", 3371 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3372 return ret_val; 3373 } 3374 3375 /* 3376 * Select Host Wakeup Registers page - caller now able to write 3377 * registers on the Wakeup registers page 3378 */ 3379 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3380 } 3381 3382 /** 3383 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 3384 * @hw: pointer to the HW structure 3385 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 3386 * 3387 * Restore BM_WUC_ENABLE_REG to its original value. 3388 * 3389 * Assumes semaphore already acquired and *phy_reg is the contents of the 3390 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 3391 * caller. 3392 **/ 3393 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3394 { 3395 s32 ret_val = E1000_SUCCESS; 3396 3397 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); 3398 3399 if (!phy_reg) 3400 return -E1000_ERR_PARAM; 3401 3402 /* Select Port Control Registers page */ 3403 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3404 if (ret_val) { 3405 DEBUGOUT("Could not set Port Control page\n"); 3406 return ret_val; 3407 } 3408 3409 /* Restore 769.17 to its original value */ 3410 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 3411 if (ret_val) 3412 DEBUGOUT2("Could not restore PHY register %d.%d\n", 3413 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3414 3415 return ret_val; 3416 } 3417 3418 /** 3419 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 3420 * @hw: pointer to the HW structure 3421 * @offset: register offset to be read or written 3422 * @data: pointer to the data to read or write 3423 * @read: determines if operation is read or write 3424 * @page_set: BM_WUC_PAGE already set and access enabled 3425 * 3426 * Read the PHY register at offset and store the retrieved information in 3427 * data, or write data to PHY register at offset. Note the procedure to 3428 * access the PHY wakeup registers is different than reading the other PHY 3429 * registers. It works as such: 3430 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 3431 * 2) Set page to 800 for host (801 if we were manageability) 3432 * 3) Write the address using the address opcode (0x11) 3433 * 4) Read or write the data using the data opcode (0x12) 3434 * 5) Restore 769.17.2 to its original value 3435 * 3436 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 3437 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 3438 * 3439 * Assumes semaphore is already acquired. When page_set==TRUE, assumes 3440 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 3441 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 3442 **/ 3443 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3444 u16 *data, bool read, bool page_set) 3445 { 3446 s32 ret_val; 3447 u16 reg = BM_PHY_REG_NUM(offset); 3448 u16 phy_reg = 0; 3449 3450 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3451 3452 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 3453 if ((hw->mac.type == e1000_pchlan) && 3454 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3455 DEBUGOUT1("Attempting to access page %d while gig enabled.\n", 3456 page); 3457 3458 if (!page_set) { 3459 /* Enable access to PHY wakeup registers */ 3460 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3461 if (ret_val) { 3462 DEBUGOUT("Could not enable PHY wakeup reg access\n"); 3463 return ret_val; 3464 } 3465 } 3466 3467 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg); 3468 3469 /* Write the Wakeup register page offset value using opcode 0x11 */ 3470 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3471 if (ret_val) { 3472 DEBUGOUT1("Could not write address opcode to page %d\n", page); 3473 return ret_val; 3474 } 3475 3476 if (read) { 3477 /* Read the Wakeup register page value using opcode 0x12 */ 3478 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3479 data); 3480 } else { 3481 /* Write the Wakeup register page value using opcode 0x12 */ 3482 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3483 *data); 3484 } 3485 3486 if (ret_val) { 3487 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg); 3488 return ret_val; 3489 } 3490 3491 if (!page_set) 3492 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3493 3494 return ret_val; 3495 } 3496 3497 /** 3498 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3499 * @hw: pointer to the HW structure 3500 * 3501 * In the case of a PHY power down to save power, or to turn off link during a 3502 * driver unload, or wake on lan is not enabled, restore the link to previous 3503 * settings. 3504 **/ 3505 void e1000_power_up_phy_copper(struct e1000_hw *hw) 3506 { 3507 u16 mii_reg = 0; 3508 u16 power_reg = 0; 3509 3510 /* The PHY will retain its settings across a power down/up cycle */ 3511 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3512 mii_reg &= ~MII_CR_POWER_DOWN; 3513 if (hw->phy.type == e1000_phy_i210) { 3514 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3515 power_reg &= ~GS40G_CS_POWER_DOWN; 3516 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3517 } 3518 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3519 } 3520 3521 /** 3522 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3523 * @hw: pointer to the HW structure 3524 * 3525 * In the case of a PHY power down to save power, or to turn off link during a 3526 * driver unload, or wake on lan is not enabled, restore the link to previous 3527 * settings. 3528 **/ 3529 void e1000_power_down_phy_copper(struct e1000_hw *hw) 3530 { 3531 u16 mii_reg = 0; 3532 u16 power_reg = 0; 3533 3534 /* The PHY will retain its settings across a power down/up cycle */ 3535 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3536 mii_reg |= MII_CR_POWER_DOWN; 3537 /* i210 Phy requires an additional bit for power up/down */ 3538 if (hw->phy.type == e1000_phy_i210) { 3539 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3540 power_reg |= GS40G_CS_POWER_DOWN; 3541 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3542 } 3543 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3544 msec_delay(1); 3545 } 3546 3547 /** 3548 * __e1000_read_phy_reg_hv - Read HV PHY register 3549 * @hw: pointer to the HW structure 3550 * @offset: register offset to be read 3551 * @data: pointer to the read data 3552 * @locked: semaphore has already been acquired or not 3553 * 3554 * Acquires semaphore, if necessary, then reads the PHY register at offset 3555 * and stores the retrieved information in data. Release any acquired 3556 * semaphore before exiting. 3557 **/ 3558 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3559 bool locked, bool page_set) 3560 { 3561 s32 ret_val; 3562 u16 page = BM_PHY_REG_PAGE(offset); 3563 u16 reg = BM_PHY_REG_NUM(offset); 3564 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3565 3566 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3567 3568 if (!locked) { 3569 ret_val = hw->phy.ops.acquire(hw); 3570 if (ret_val) 3571 return ret_val; 3572 } 3573 3574 /* Page 800 works differently than the rest so it has its own func */ 3575 if (page == BM_WUC_PAGE) { 3576 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3577 TRUE, page_set); 3578 goto out; 3579 } 3580 3581 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3582 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3583 data, TRUE); 3584 goto out; 3585 } 3586 3587 if (!page_set) { 3588 if (page == HV_INTC_FC_PAGE_START) 3589 page = 0; 3590 3591 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3592 /* Page is shifted left, PHY expects (page x 32) */ 3593 ret_val = e1000_set_page_igp(hw, 3594 (page << IGP_PAGE_SHIFT)); 3595 3596 hw->phy.addr = phy_addr; 3597 3598 if (ret_val) 3599 goto out; 3600 } 3601 } 3602 3603 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3604 page << IGP_PAGE_SHIFT, reg); 3605 3606 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3607 data); 3608 out: 3609 if (!locked) 3610 hw->phy.ops.release(hw); 3611 3612 return ret_val; 3613 } 3614 3615 /** 3616 * e1000_read_phy_reg_hv - Read HV PHY register 3617 * @hw: pointer to the HW structure 3618 * @offset: register offset to be read 3619 * @data: pointer to the read data 3620 * 3621 * Acquires semaphore then reads the PHY register at offset and stores 3622 * the retrieved information in data. Release the acquired semaphore 3623 * before exiting. 3624 **/ 3625 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3626 { 3627 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3628 } 3629 3630 /** 3631 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3632 * @hw: pointer to the HW structure 3633 * @offset: register offset to be read 3634 * @data: pointer to the read data 3635 * 3636 * Reads the PHY register at offset and stores the retrieved information 3637 * in data. Assumes semaphore already acquired. 3638 **/ 3639 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3640 { 3641 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3642 } 3643 3644 /** 3645 * e1000_read_phy_reg_page_hv - Read HV PHY register 3646 * @hw: pointer to the HW structure 3647 * @offset: register offset to write to 3648 * @data: data to write at register offset 3649 * 3650 * Reads the PHY register at offset and stores the retrieved information 3651 * in data. Assumes semaphore already acquired and page already set. 3652 **/ 3653 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3654 { 3655 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, TRUE); 3656 } 3657 3658 /** 3659 * __e1000_write_phy_reg_hv - Write HV PHY register 3660 * @hw: pointer to the HW structure 3661 * @offset: register offset to write to 3662 * @data: data to write at register offset 3663 * @locked: semaphore has already been acquired or not 3664 * 3665 * Acquires semaphore, if necessary, then writes the data to PHY register 3666 * at the offset. Release any acquired semaphores before exiting. 3667 **/ 3668 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3669 bool locked, bool page_set) 3670 { 3671 s32 ret_val; 3672 u16 page = BM_PHY_REG_PAGE(offset); 3673 u16 reg = BM_PHY_REG_NUM(offset); 3674 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3675 3676 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3677 3678 if (!locked) { 3679 ret_val = hw->phy.ops.acquire(hw); 3680 if (ret_val) 3681 return ret_val; 3682 } 3683 3684 /* Page 800 works differently than the rest so it has its own func */ 3685 if (page == BM_WUC_PAGE) { 3686 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3687 FALSE, page_set); 3688 goto out; 3689 } 3690 3691 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3692 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3693 &data, FALSE); 3694 goto out; 3695 } 3696 3697 if (!page_set) { 3698 if (page == HV_INTC_FC_PAGE_START) 3699 page = 0; 3700 3701 /* 3702 * Workaround MDIO accesses being disabled after entering IEEE 3703 * Power Down (when bit 11 of the PHY Control register is set) 3704 */ 3705 if ((hw->phy.type == e1000_phy_82578) && 3706 (hw->phy.revision >= 1) && 3707 (hw->phy.addr == 2) && 3708 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 3709 (data & (1 << 11))) { 3710 u16 data2 = 0x7EFF; 3711 ret_val = e1000_access_phy_debug_regs_hv(hw, 3712 (1 << 6) | 0x3, 3713 &data2, FALSE); 3714 if (ret_val) 3715 goto out; 3716 } 3717 3718 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3719 /* Page is shifted left, PHY expects (page x 32) */ 3720 ret_val = e1000_set_page_igp(hw, 3721 (page << IGP_PAGE_SHIFT)); 3722 3723 hw->phy.addr = phy_addr; 3724 3725 if (ret_val) 3726 goto out; 3727 } 3728 } 3729 3730 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3731 page << IGP_PAGE_SHIFT, reg); 3732 3733 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3734 data); 3735 3736 out: 3737 if (!locked) 3738 hw->phy.ops.release(hw); 3739 3740 return ret_val; 3741 } 3742 3743 /** 3744 * e1000_write_phy_reg_hv - Write HV PHY register 3745 * @hw: pointer to the HW structure 3746 * @offset: register offset to write to 3747 * @data: data to write at register offset 3748 * 3749 * Acquires semaphore then writes the data to PHY register at the offset. 3750 * Release the acquired semaphores before exiting. 3751 **/ 3752 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3753 { 3754 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3755 } 3756 3757 /** 3758 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3759 * @hw: pointer to the HW structure 3760 * @offset: register offset to write to 3761 * @data: data to write at register offset 3762 * 3763 * Writes the data to PHY register at the offset. Assumes semaphore 3764 * already acquired. 3765 **/ 3766 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3767 { 3768 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3769 } 3770 3771 /** 3772 * e1000_write_phy_reg_page_hv - Write HV PHY register 3773 * @hw: pointer to the HW structure 3774 * @offset: register offset to write to 3775 * @data: data to write at register offset 3776 * 3777 * Writes the data to PHY register at the offset. Assumes semaphore 3778 * already acquired and page already set. 3779 **/ 3780 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3781 { 3782 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, TRUE); 3783 } 3784 3785 /** 3786 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3787 * @page: page to be accessed 3788 **/ 3789 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3790 { 3791 u32 phy_addr = 2; 3792 3793 if (page >= HV_INTC_FC_PAGE_START) 3794 phy_addr = 1; 3795 3796 return phy_addr; 3797 } 3798 3799 /** 3800 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3801 * @hw: pointer to the HW structure 3802 * @offset: register offset to be read or written 3803 * @data: pointer to the data to be read or written 3804 * @read: determines if operation is read or write 3805 * 3806 * Reads the PHY register at offset and stores the retreived information 3807 * in data. Assumes semaphore already acquired. Note that the procedure 3808 * to access these regs uses the address port and data port to read/write. 3809 * These accesses done with PHY address 2 and without using pages. 3810 **/ 3811 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3812 u16 *data, bool read) 3813 { 3814 s32 ret_val; 3815 u32 addr_reg = 0; 3816 u32 data_reg = 0; 3817 3818 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3819 3820 /* This takes care of the difference with desktop vs mobile phy */ 3821 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3822 I82578_ADDR_REG : I82577_ADDR_REG; 3823 data_reg = addr_reg + 1; 3824 3825 /* All operations in this function are phy address 2 */ 3826 hw->phy.addr = 2; 3827 3828 /* masking with 0x3F to remove the page from offset */ 3829 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3830 if (ret_val) { 3831 DEBUGOUT("Could not write the Address Offset port register\n"); 3832 return ret_val; 3833 } 3834 3835 /* Read or write the data value next */ 3836 if (read) 3837 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3838 else 3839 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3840 3841 if (ret_val) 3842 DEBUGOUT("Could not access the Data port register\n"); 3843 3844 return ret_val; 3845 } 3846 3847 /** 3848 * e1000_link_stall_workaround_hv - Si workaround 3849 * @hw: pointer to the HW structure 3850 * 3851 * This function works around a Si bug where the link partner can get 3852 * a link up indication before the PHY does. If small packets are sent 3853 * by the link partner they can be placed in the packet buffer without 3854 * being properly accounted for by the PHY and will stall preventing 3855 * further packets from being received. The workaround is to clear the 3856 * packet buffer after the PHY detects link up. 3857 **/ 3858 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3859 { 3860 s32 ret_val = E1000_SUCCESS; 3861 u16 data; 3862 3863 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3864 3865 if (hw->phy.type != e1000_phy_82578) 3866 return E1000_SUCCESS; 3867 3868 /* Do not apply workaround if in PHY loopback bit 14 set */ 3869 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3870 if (data & PHY_CONTROL_LB) 3871 return E1000_SUCCESS; 3872 3873 /* check if link is up and at 1Gbps */ 3874 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3875 if (ret_val) 3876 return ret_val; 3877 3878 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3879 BM_CS_STATUS_SPEED_MASK; 3880 3881 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3882 BM_CS_STATUS_SPEED_1000)) 3883 return E1000_SUCCESS; 3884 3885 msec_delay(200); 3886 3887 /* flush the packets in the fifo buffer */ 3888 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3889 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3890 HV_MUX_DATA_CTRL_FORCE_SPEED); 3891 if (ret_val) 3892 return ret_val; 3893 3894 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3895 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3896 } 3897 3898 /** 3899 * e1000_check_polarity_82577 - Checks the polarity. 3900 * @hw: pointer to the HW structure 3901 * 3902 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3903 * 3904 * Polarity is determined based on the PHY specific status register. 3905 **/ 3906 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3907 { 3908 struct e1000_phy_info *phy = &hw->phy; 3909 s32 ret_val; 3910 u16 data; 3911 3912 DEBUGFUNC("e1000_check_polarity_82577"); 3913 3914 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3915 3916 if (!ret_val) 3917 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3918 ? e1000_rev_polarity_reversed 3919 : e1000_rev_polarity_normal; 3920 3921 return ret_val; 3922 } 3923 3924 /** 3925 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3926 * @hw: pointer to the HW structure 3927 * 3928 * Calls the PHY setup function to force speed and duplex. 3929 **/ 3930 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3931 { 3932 struct e1000_phy_info *phy = &hw->phy; 3933 s32 ret_val; 3934 u16 phy_data; 3935 bool link; 3936 3937 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3938 3939 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3940 if (ret_val) 3941 return ret_val; 3942 3943 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3944 3945 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3946 if (ret_val) 3947 return ret_val; 3948 3949 usec_delay(1); 3950 3951 if (phy->autoneg_wait_to_complete) { 3952 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3953 3954 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3955 100000, &link); 3956 if (ret_val) 3957 return ret_val; 3958 3959 if (!link) 3960 DEBUGOUT("Link taking longer than expected.\n"); 3961 3962 /* Try once more */ 3963 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3964 100000, &link); 3965 } 3966 3967 return ret_val; 3968 } 3969 3970 /** 3971 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3972 * @hw: pointer to the HW structure 3973 * 3974 * Read PHY status to determine if link is up. If link is up, then 3975 * set/determine 10base-T extended distance and polarity correction. Read 3976 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3977 * determine on the cable length, local and remote receiver. 3978 **/ 3979 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3980 { 3981 struct e1000_phy_info *phy = &hw->phy; 3982 s32 ret_val; 3983 u16 data; 3984 bool link; 3985 3986 DEBUGFUNC("e1000_get_phy_info_82577"); 3987 3988 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3989 if (ret_val) 3990 return ret_val; 3991 3992 if (!link) { 3993 DEBUGOUT("Phy info is only valid if link is up\n"); 3994 return -E1000_ERR_CONFIG; 3995 } 3996 3997 phy->polarity_correction = TRUE; 3998 3999 ret_val = e1000_check_polarity_82577(hw); 4000 if (ret_val) 4001 return ret_val; 4002 4003 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 4004 if (ret_val) 4005 return ret_val; 4006 4007 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 4008 4009 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 4010 I82577_PHY_STATUS2_SPEED_1000MBPS) { 4011 ret_val = hw->phy.ops.get_cable_length(hw); 4012 if (ret_val) 4013 return ret_val; 4014 4015 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 4016 if (ret_val) 4017 return ret_val; 4018 4019 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 4020 ? e1000_1000t_rx_status_ok 4021 : e1000_1000t_rx_status_not_ok; 4022 4023 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 4024 ? e1000_1000t_rx_status_ok 4025 : e1000_1000t_rx_status_not_ok; 4026 } else { 4027 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 4028 phy->local_rx = e1000_1000t_rx_status_undefined; 4029 phy->remote_rx = e1000_1000t_rx_status_undefined; 4030 } 4031 4032 return E1000_SUCCESS; 4033 } 4034 4035 /** 4036 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 4037 * @hw: pointer to the HW structure 4038 * 4039 * Reads the diagnostic status register and verifies result is valid before 4040 * placing it in the phy_cable_length field. 4041 **/ 4042 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 4043 { 4044 struct e1000_phy_info *phy = &hw->phy; 4045 s32 ret_val; 4046 u16 phy_data, length; 4047 4048 DEBUGFUNC("e1000_get_cable_length_82577"); 4049 4050 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 4051 if (ret_val) 4052 return ret_val; 4053 4054 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 4055 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 4056 4057 if (length == E1000_CABLE_LENGTH_UNDEFINED) 4058 ret_val = -E1000_ERR_PHY; 4059 4060 phy->cable_length = length; 4061 4062 return E1000_SUCCESS; 4063 } 4064 4065 /** 4066 * e1000_write_phy_reg_gs40g - Write GS40G PHY register 4067 * @hw: pointer to the HW structure 4068 * @offset: register offset to write to 4069 * @data: data to write at register offset 4070 * 4071 * Acquires semaphore, if necessary, then writes the data to PHY register 4072 * at the offset. Release any acquired semaphores before exiting. 4073 **/ 4074 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 4075 { 4076 s32 ret_val; 4077 u16 page = offset >> GS40G_PAGE_SHIFT; 4078 4079 DEBUGFUNC("e1000_write_phy_reg_gs40g"); 4080 4081 offset = offset & GS40G_OFFSET_MASK; 4082 ret_val = hw->phy.ops.acquire(hw); 4083 if (ret_val) 4084 return ret_val; 4085 4086 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4087 if (ret_val) 4088 goto release; 4089 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 4090 4091 release: 4092 hw->phy.ops.release(hw); 4093 return ret_val; 4094 } 4095 4096 /** 4097 * e1000_read_phy_reg_gs40g - Read GS40G PHY register 4098 * @hw: pointer to the HW structure 4099 * @offset: lower half is register offset to read to 4100 * upper half is page to use. 4101 * @data: data to read at register offset 4102 * 4103 * Acquires semaphore, if necessary, then reads the data in the PHY register 4104 * at the offset. Release any acquired semaphores before exiting. 4105 **/ 4106 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 4107 { 4108 s32 ret_val; 4109 u16 page = offset >> GS40G_PAGE_SHIFT; 4110 4111 DEBUGFUNC("e1000_read_phy_reg_gs40g"); 4112 4113 offset = offset & GS40G_OFFSET_MASK; 4114 ret_val = hw->phy.ops.acquire(hw); 4115 if (ret_val) 4116 return ret_val; 4117 4118 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4119 if (ret_val) 4120 goto release; 4121 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 4122 4123 release: 4124 hw->phy.ops.release(hw); 4125 return ret_val; 4126 } 4127