1 /****************************************************************************** 2 3 Copyright (c) 2001-2009, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: $*/ 34 35 #include "e1000_api.h" 36 37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read); 40 static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44 /* Cable length tables */ 45 static const u16 e1000_m88_cable_length_table[] = 46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51 static const u16 e1000_igp_2_cable_length_table[] = 52 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 53 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 54 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 55 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 56 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 57 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 58 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 59 104, 109, 114, 118, 121, 124}; 60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64 /** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70 void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71 { 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.read_reg = e1000_null_read_reg; 86 phy->ops.read_reg_locked = e1000_null_read_reg; 87 phy->ops.release = e1000_null_phy_generic; 88 phy->ops.reset = e1000_null_ops_generic; 89 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 90 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 91 phy->ops.write_reg = e1000_null_write_reg; 92 phy->ops.write_reg_locked = e1000_null_write_reg; 93 phy->ops.power_up = e1000_null_phy_generic; 94 phy->ops.power_down = e1000_null_phy_generic; 95 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 96 } 97 98 /** 99 * e1000_null_read_reg - No-op function, return 0 100 * @hw: pointer to the HW structure 101 **/ 102 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 103 { 104 DEBUGFUNC("e1000_null_read_reg"); 105 return E1000_SUCCESS; 106 } 107 108 /** 109 * e1000_null_phy_generic - No-op function, return void 110 * @hw: pointer to the HW structure 111 **/ 112 void e1000_null_phy_generic(struct e1000_hw *hw) 113 { 114 DEBUGFUNC("e1000_null_phy_generic"); 115 return; 116 } 117 118 /** 119 * e1000_null_lplu_state - No-op function, return 0 120 * @hw: pointer to the HW structure 121 **/ 122 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 123 { 124 DEBUGFUNC("e1000_null_lplu_state"); 125 return E1000_SUCCESS; 126 } 127 128 /** 129 * e1000_null_write_reg - No-op function, return 0 130 * @hw: pointer to the HW structure 131 **/ 132 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 133 { 134 DEBUGFUNC("e1000_null_write_reg"); 135 return E1000_SUCCESS; 136 } 137 138 /** 139 * e1000_check_reset_block_generic - Check if PHY reset is blocked 140 * @hw: pointer to the HW structure 141 * 142 * Read the PHY management control register and check whether a PHY reset 143 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 144 * return E1000_BLK_PHY_RESET (12). 145 **/ 146 s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 147 { 148 u32 manc; 149 150 DEBUGFUNC("e1000_check_reset_block"); 151 152 manc = E1000_READ_REG(hw, E1000_MANC); 153 154 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 155 E1000_BLK_PHY_RESET : E1000_SUCCESS; 156 } 157 158 /** 159 * e1000_get_phy_id - Retrieve the PHY ID and revision 160 * @hw: pointer to the HW structure 161 * 162 * Reads the PHY registers and stores the PHY ID and possibly the PHY 163 * revision in the hardware structure. 164 **/ 165 s32 e1000_get_phy_id(struct e1000_hw *hw) 166 { 167 struct e1000_phy_info *phy = &hw->phy; 168 s32 ret_val = E1000_SUCCESS; 169 u16 phy_id; 170 u16 retry_count = 0; 171 172 DEBUGFUNC("e1000_get_phy_id"); 173 174 if (!(phy->ops.read_reg)) 175 goto out; 176 177 while (retry_count < 2) { 178 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 179 if (ret_val) 180 goto out; 181 182 phy->id = (u32)(phy_id << 16); 183 usec_delay(20); 184 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 185 if (ret_val) 186 goto out; 187 188 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 189 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 190 191 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 192 goto out; 193 194 retry_count++; 195 } 196 out: 197 return ret_val; 198 } 199 200 /** 201 * e1000_phy_reset_dsp_generic - Reset PHY DSP 202 * @hw: pointer to the HW structure 203 * 204 * Reset the digital signal processor. 205 **/ 206 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 207 { 208 s32 ret_val = E1000_SUCCESS; 209 210 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 211 212 if (!(hw->phy.ops.write_reg)) 213 goto out; 214 215 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 216 if (ret_val) 217 goto out; 218 219 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 220 221 out: 222 return ret_val; 223 } 224 225 /** 226 * e1000_read_phy_reg_mdic - Read MDI control register 227 * @hw: pointer to the HW structure 228 * @offset: register offset to be read 229 * @data: pointer to the read data 230 * 231 * Reads the MDI control register in the PHY at offset and stores the 232 * information read to data. 233 **/ 234 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 235 { 236 struct e1000_phy_info *phy = &hw->phy; 237 u32 i, mdic = 0; 238 s32 ret_val = E1000_SUCCESS; 239 240 DEBUGFUNC("e1000_read_phy_reg_mdic"); 241 242 if (offset > MAX_PHY_REG_ADDRESS) { 243 DEBUGOUT1("PHY Address %d is out of range\n", offset); 244 return -E1000_ERR_PARAM; 245 } 246 247 /* 248 * Set up Op-code, Phy Address, and register offset in the MDI 249 * Control register. The MAC will take care of interfacing with the 250 * PHY to retrieve the desired data. 251 */ 252 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 253 (phy->addr << E1000_MDIC_PHY_SHIFT) | 254 (E1000_MDIC_OP_READ)); 255 256 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 257 258 /* Workaround for Si errata */ 259 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2)) 260 msec_delay(10); 261 262 /* 263 * Poll the ready bit to see if the MDI read completed 264 * Increasing the time out as testing showed failures with 265 * the lower time out 266 */ 267 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 268 usec_delay(50); 269 mdic = E1000_READ_REG(hw, E1000_MDIC); 270 if (mdic & E1000_MDIC_READY) 271 break; 272 } 273 if (!(mdic & E1000_MDIC_READY)) { 274 DEBUGOUT("MDI Read did not complete\n"); 275 ret_val = -E1000_ERR_PHY; 276 goto out; 277 } 278 if (mdic & E1000_MDIC_ERROR) { 279 DEBUGOUT("MDI Error\n"); 280 ret_val = -E1000_ERR_PHY; 281 goto out; 282 } 283 *data = (u16) mdic; 284 285 /* 286 * Allow some time after each MDIC transaction to avoid 287 * reading duplicate data in the next MDIC transaction. 288 */ 289 if (hw->mac.type == e1000_pch2lan) 290 usec_delay(100); 291 292 out: 293 return ret_val; 294 } 295 296 /** 297 * e1000_write_phy_reg_mdic - Write MDI control register 298 * @hw: pointer to the HW structure 299 * @offset: register offset to write to 300 * @data: data to write to register at offset 301 * 302 * Writes data to MDI control register in the PHY at offset. 303 **/ 304 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 305 { 306 struct e1000_phy_info *phy = &hw->phy; 307 u32 i, mdic = 0; 308 s32 ret_val = E1000_SUCCESS; 309 310 DEBUGFUNC("e1000_write_phy_reg_mdic"); 311 312 if (offset > MAX_PHY_REG_ADDRESS) { 313 DEBUGOUT1("PHY Address %d is out of range\n", offset); 314 return -E1000_ERR_PARAM; 315 } 316 317 /* 318 * Set up Op-code, Phy Address, and register offset in the MDI 319 * Control register. The MAC will take care of interfacing with the 320 * PHY to retrieve the desired data. 321 */ 322 mdic = (((u32)data) | 323 (offset << E1000_MDIC_REG_SHIFT) | 324 (phy->addr << E1000_MDIC_PHY_SHIFT) | 325 (E1000_MDIC_OP_WRITE)); 326 327 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 328 329 /* Workaround for Si errata */ 330 if ((hw->phy.type == e1000_phy_82577) && (hw->revision_id <= 2)) 331 msec_delay(10); 332 333 /* 334 * Poll the ready bit to see if the MDI read completed 335 * Increasing the time out as testing showed failures with 336 * the lower time out 337 */ 338 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 339 usec_delay(50); 340 mdic = E1000_READ_REG(hw, E1000_MDIC); 341 if (mdic & E1000_MDIC_READY) 342 break; 343 } 344 if (!(mdic & E1000_MDIC_READY)) { 345 DEBUGOUT("MDI Write did not complete\n"); 346 ret_val = -E1000_ERR_PHY; 347 goto out; 348 } 349 if (mdic & E1000_MDIC_ERROR) { 350 DEBUGOUT("MDI Error\n"); 351 ret_val = -E1000_ERR_PHY; 352 goto out; 353 } 354 355 /* 356 * Allow some time after each MDIC transaction to avoid 357 * reading duplicate data in the next MDIC transaction. 358 */ 359 if (hw->mac.type == e1000_pch2lan) 360 usec_delay(100); 361 362 out: 363 return ret_val; 364 } 365 366 /** 367 * e1000_read_phy_reg_m88 - Read m88 PHY register 368 * @hw: pointer to the HW structure 369 * @offset: register offset to be read 370 * @data: pointer to the read data 371 * 372 * Acquires semaphore, if necessary, then reads the PHY register at offset 373 * and storing the retrieved information in data. Release any acquired 374 * semaphores before exiting. 375 **/ 376 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 377 { 378 s32 ret_val = E1000_SUCCESS; 379 380 DEBUGFUNC("e1000_read_phy_reg_m88"); 381 382 if (!(hw->phy.ops.acquire)) 383 goto out; 384 385 ret_val = hw->phy.ops.acquire(hw); 386 if (ret_val) 387 goto out; 388 389 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 390 data); 391 392 hw->phy.ops.release(hw); 393 394 out: 395 return ret_val; 396 } 397 398 /** 399 * e1000_write_phy_reg_m88 - Write m88 PHY register 400 * @hw: pointer to the HW structure 401 * @offset: register offset to write to 402 * @data: data to write at register offset 403 * 404 * Acquires semaphore, if necessary, then writes the data to PHY register 405 * at the offset. Release any acquired semaphores before exiting. 406 **/ 407 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 408 { 409 s32 ret_val = E1000_SUCCESS; 410 411 DEBUGFUNC("e1000_write_phy_reg_m88"); 412 413 if (!(hw->phy.ops.acquire)) 414 goto out; 415 416 ret_val = hw->phy.ops.acquire(hw); 417 if (ret_val) 418 goto out; 419 420 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 421 data); 422 423 hw->phy.ops.release(hw); 424 425 out: 426 return ret_val; 427 } 428 429 /** 430 * __e1000_read_phy_reg_igp - Read igp PHY register 431 * @hw: pointer to the HW structure 432 * @offset: register offset to be read 433 * @data: pointer to the read data 434 * @locked: semaphore has already been acquired or not 435 * 436 * Acquires semaphore, if necessary, then reads the PHY register at offset 437 * and stores the retrieved information in data. Release any acquired 438 * semaphores before exiting. 439 **/ 440 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 441 bool locked) 442 { 443 s32 ret_val = E1000_SUCCESS; 444 445 DEBUGFUNC("__e1000_read_phy_reg_igp"); 446 447 if (!locked) { 448 if (!(hw->phy.ops.acquire)) 449 goto out; 450 451 ret_val = hw->phy.ops.acquire(hw); 452 if (ret_val) 453 goto out; 454 } 455 456 if (offset > MAX_PHY_MULTI_PAGE_REG) { 457 ret_val = e1000_write_phy_reg_mdic(hw, 458 IGP01E1000_PHY_PAGE_SELECT, 459 (u16)offset); 460 if (ret_val) 461 goto release; 462 } 463 464 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 465 data); 466 467 release: 468 if (!locked) 469 hw->phy.ops.release(hw); 470 out: 471 return ret_val; 472 } 473 474 /** 475 * e1000_read_phy_reg_igp - Read igp PHY register 476 * @hw: pointer to the HW structure 477 * @offset: register offset to be read 478 * @data: pointer to the read data 479 * 480 * Acquires semaphore then reads the PHY register at offset and stores the 481 * retrieved information in data. 482 * Release the acquired semaphore before exiting. 483 **/ 484 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 485 { 486 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 487 } 488 489 /** 490 * e1000_read_phy_reg_igp_locked - Read igp PHY register 491 * @hw: pointer to the HW structure 492 * @offset: register offset to be read 493 * @data: pointer to the read data 494 * 495 * Reads the PHY register at offset and stores the retrieved information 496 * in data. Assumes semaphore already acquired. 497 **/ 498 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 499 { 500 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 501 } 502 503 /** 504 * e1000_write_phy_reg_igp - Write igp PHY register 505 * @hw: pointer to the HW structure 506 * @offset: register offset to write to 507 * @data: data to write at register offset 508 * @locked: semaphore has already been acquired or not 509 * 510 * Acquires semaphore, if necessary, then writes the data to PHY register 511 * at the offset. Release any acquired semaphores before exiting. 512 **/ 513 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 514 bool locked) 515 { 516 s32 ret_val = E1000_SUCCESS; 517 518 DEBUGFUNC("e1000_write_phy_reg_igp"); 519 520 if (!locked) { 521 if (!(hw->phy.ops.acquire)) 522 goto out; 523 524 ret_val = hw->phy.ops.acquire(hw); 525 if (ret_val) 526 goto out; 527 } 528 529 if (offset > MAX_PHY_MULTI_PAGE_REG) { 530 ret_val = e1000_write_phy_reg_mdic(hw, 531 IGP01E1000_PHY_PAGE_SELECT, 532 (u16)offset); 533 if (ret_val) 534 goto release; 535 } 536 537 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 538 data); 539 540 release: 541 if (!locked) 542 hw->phy.ops.release(hw); 543 544 out: 545 return ret_val; 546 } 547 548 /** 549 * e1000_write_phy_reg_igp - Write igp PHY register 550 * @hw: pointer to the HW structure 551 * @offset: register offset to write to 552 * @data: data to write at register offset 553 * 554 * Acquires semaphore then writes the data to PHY register 555 * at the offset. Release any acquired semaphores before exiting. 556 **/ 557 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 558 { 559 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 560 } 561 562 /** 563 * e1000_write_phy_reg_igp_locked - Write igp PHY register 564 * @hw: pointer to the HW structure 565 * @offset: register offset to write to 566 * @data: data to write at register offset 567 * 568 * Writes the data to PHY register at the offset. 569 * Assumes semaphore already acquired. 570 **/ 571 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 572 { 573 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 574 } 575 576 /** 577 * __e1000_read_kmrn_reg - Read kumeran register 578 * @hw: pointer to the HW structure 579 * @offset: register offset to be read 580 * @data: pointer to the read data 581 * @locked: semaphore has already been acquired or not 582 * 583 * Acquires semaphore, if necessary. Then reads the PHY register at offset 584 * using the kumeran interface. The information retrieved is stored in data. 585 * Release any acquired semaphores before exiting. 586 **/ 587 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 588 bool locked) 589 { 590 u32 kmrnctrlsta; 591 s32 ret_val = E1000_SUCCESS; 592 593 DEBUGFUNC("__e1000_read_kmrn_reg"); 594 595 if (!locked) { 596 if (!(hw->phy.ops.acquire)) 597 goto out; 598 599 ret_val = hw->phy.ops.acquire(hw); 600 if (ret_val) 601 goto out; 602 } 603 604 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 605 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 606 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 607 608 usec_delay(2); 609 610 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 611 *data = (u16)kmrnctrlsta; 612 613 if (!locked) 614 hw->phy.ops.release(hw); 615 616 out: 617 return ret_val; 618 } 619 620 /** 621 * e1000_read_kmrn_reg_generic - Read kumeran register 622 * @hw: pointer to the HW structure 623 * @offset: register offset to be read 624 * @data: pointer to the read data 625 * 626 * Acquires semaphore then reads the PHY register at offset using the 627 * kumeran interface. The information retrieved is stored in data. 628 * Release the acquired semaphore before exiting. 629 **/ 630 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 631 { 632 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 633 } 634 635 /** 636 * e1000_read_kmrn_reg_locked - Read kumeran register 637 * @hw: pointer to the HW structure 638 * @offset: register offset to be read 639 * @data: pointer to the read data 640 * 641 * Reads the PHY register at offset using the kumeran interface. The 642 * information retrieved is stored in data. 643 * Assumes semaphore already acquired. 644 **/ 645 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 646 { 647 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 648 } 649 650 /** 651 * __e1000_write_kmrn_reg - Write kumeran register 652 * @hw: pointer to the HW structure 653 * @offset: register offset to write to 654 * @data: data to write at register offset 655 * @locked: semaphore has already been acquired or not 656 * 657 * Acquires semaphore, if necessary. Then write the data to PHY register 658 * at the offset using the kumeran interface. Release any acquired semaphores 659 * before exiting. 660 **/ 661 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 662 bool locked) 663 { 664 u32 kmrnctrlsta; 665 s32 ret_val = E1000_SUCCESS; 666 667 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 668 669 if (!locked) { 670 if (!(hw->phy.ops.acquire)) 671 goto out; 672 673 ret_val = hw->phy.ops.acquire(hw); 674 if (ret_val) 675 goto out; 676 } 677 678 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 679 E1000_KMRNCTRLSTA_OFFSET) | data; 680 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 681 682 usec_delay(2); 683 684 if (!locked) 685 hw->phy.ops.release(hw); 686 687 out: 688 return ret_val; 689 } 690 691 /** 692 * e1000_write_kmrn_reg_generic - Write kumeran register 693 * @hw: pointer to the HW structure 694 * @offset: register offset to write to 695 * @data: data to write at register offset 696 * 697 * Acquires semaphore then writes the data to the PHY register at the offset 698 * using the kumeran interface. Release the acquired semaphore before exiting. 699 **/ 700 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 701 { 702 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 703 } 704 705 /** 706 * e1000_write_kmrn_reg_locked - Write kumeran register 707 * @hw: pointer to the HW structure 708 * @offset: register offset to write to 709 * @data: data to write at register offset 710 * 711 * Write the data to PHY register at the offset using the kumeran interface. 712 * Assumes semaphore already acquired. 713 **/ 714 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 715 { 716 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 717 } 718 719 /** 720 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 721 * @hw: pointer to the HW structure 722 * 723 * Sets up Carrier-sense on Transmit and downshift values. 724 **/ 725 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 726 { 727 s32 ret_val; 728 u16 phy_data; 729 730 DEBUGFUNC("e1000_copper_link_setup_82577"); 731 732 if (hw->phy.reset_disable) { 733 ret_val = E1000_SUCCESS; 734 goto out; 735 } 736 737 if (hw->phy.type == e1000_phy_82580) { 738 ret_val = hw->phy.ops.reset(hw); 739 if (ret_val) { 740 DEBUGOUT("Error resetting the PHY.\n"); 741 goto out; 742 } 743 } 744 745 /* Enable CRS on TX. This must be set for half-duplex operation. */ 746 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 747 if (ret_val) 748 goto out; 749 750 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 751 752 /* Enable downshift */ 753 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 754 755 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 756 757 out: 758 return ret_val; 759 } 760 761 /** 762 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 763 * @hw: pointer to the HW structure 764 * 765 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 766 * and downshift values are set also. 767 **/ 768 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 769 { 770 struct e1000_phy_info *phy = &hw->phy; 771 s32 ret_val; 772 u16 phy_data; 773 774 DEBUGFUNC("e1000_copper_link_setup_m88"); 775 776 if (phy->reset_disable) { 777 ret_val = E1000_SUCCESS; 778 goto out; 779 } 780 781 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 782 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 783 if (ret_val) 784 goto out; 785 786 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 787 /* For BM PHY this bit is downshift enable */ 788 if (phy->type == e1000_phy_bm) 789 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 790 791 /* 792 * Options: 793 * MDI/MDI-X = 0 (default) 794 * 0 - Auto for all speeds 795 * 1 - MDI mode 796 * 2 - MDI-X mode 797 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 798 */ 799 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 800 801 switch (phy->mdix) { 802 case 1: 803 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 804 break; 805 case 2: 806 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 807 break; 808 case 3: 809 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 810 break; 811 case 0: 812 default: 813 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 814 break; 815 } 816 817 /* 818 * Options: 819 * disable_polarity_correction = 0 (default) 820 * Automatic Correction for Reversed Cable Polarity 821 * 0 - Disabled 822 * 1 - Enabled 823 */ 824 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 825 if (phy->disable_polarity_correction == 1) 826 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 827 828 /* Enable downshift on BM (disabled by default) */ 829 if (phy->type == e1000_phy_bm) 830 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 831 832 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 833 if (ret_val) 834 goto out; 835 836 if ((phy->type == e1000_phy_m88) && 837 (phy->revision < E1000_REVISION_4) && 838 (phy->id != BME1000_E_PHY_ID_R2)) { 839 /* 840 * Force TX_CLK in the Extended PHY Specific Control Register 841 * to 25MHz clock. 842 */ 843 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 844 &phy_data); 845 if (ret_val) 846 goto out; 847 848 phy_data |= M88E1000_EPSCR_TX_CLK_25; 849 850 if ((phy->revision == E1000_REVISION_2) && 851 (phy->id == M88E1111_I_PHY_ID)) { 852 /* 82573L PHY - set the downshift counter to 5x. */ 853 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 854 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 855 } else { 856 /* Configure Master and Slave downshift values */ 857 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 858 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 859 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 860 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 861 } 862 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 863 phy_data); 864 if (ret_val) 865 goto out; 866 } 867 868 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 869 /* Set PHY page 0, register 29 to 0x0003 */ 870 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 871 if (ret_val) 872 goto out; 873 874 /* Set PHY page 0, register 30 to 0x0000 */ 875 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 876 if (ret_val) 877 goto out; 878 } 879 880 /* Commit the changes. */ 881 ret_val = phy->ops.commit(hw); 882 if (ret_val) { 883 DEBUGOUT("Error committing the PHY changes\n"); 884 goto out; 885 } 886 887 if (phy->type == e1000_phy_82578) { 888 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 889 &phy_data); 890 if (ret_val) 891 goto out; 892 893 /* 82578 PHY - set the downshift count to 1x. */ 894 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 895 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 896 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 897 phy_data); 898 if (ret_val) 899 goto out; 900 } 901 902 out: 903 return ret_val; 904 } 905 906 /** 907 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 908 * @hw: pointer to the HW structure 909 * 910 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 911 * igp PHY's. 912 **/ 913 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 914 { 915 struct e1000_phy_info *phy = &hw->phy; 916 s32 ret_val; 917 u16 data; 918 919 DEBUGFUNC("e1000_copper_link_setup_igp"); 920 921 if (phy->reset_disable) { 922 ret_val = E1000_SUCCESS; 923 goto out; 924 } 925 926 ret_val = hw->phy.ops.reset(hw); 927 if (ret_val) { 928 DEBUGOUT("Error resetting the PHY.\n"); 929 goto out; 930 } 931 932 /* 933 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 934 * timeout issues when LFS is enabled. 935 */ 936 msec_delay(100); 937 938 /* 939 * The NVM settings will configure LPLU in D3 for 940 * non-IGP1 PHYs. 941 */ 942 if (phy->type == e1000_phy_igp) { 943 /* disable lplu d3 during driver init */ 944 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 945 if (ret_val) { 946 DEBUGOUT("Error Disabling LPLU D3\n"); 947 goto out; 948 } 949 } 950 951 /* disable lplu d0 during driver init */ 952 if (hw->phy.ops.set_d0_lplu_state) { 953 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 954 if (ret_val) { 955 DEBUGOUT("Error Disabling LPLU D0\n"); 956 goto out; 957 } 958 } 959 /* Configure mdi-mdix settings */ 960 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 961 if (ret_val) 962 goto out; 963 964 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 965 966 switch (phy->mdix) { 967 case 1: 968 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 969 break; 970 case 2: 971 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 972 break; 973 case 0: 974 default: 975 data |= IGP01E1000_PSCR_AUTO_MDIX; 976 break; 977 } 978 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 979 if (ret_val) 980 goto out; 981 982 /* set auto-master slave resolution settings */ 983 if (hw->mac.autoneg) { 984 /* 985 * when autonegotiation advertisement is only 1000Mbps then we 986 * should disable SmartSpeed and enable Auto MasterSlave 987 * resolution as hardware default. 988 */ 989 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 990 /* Disable SmartSpeed */ 991 ret_val = phy->ops.read_reg(hw, 992 IGP01E1000_PHY_PORT_CONFIG, 993 &data); 994 if (ret_val) 995 goto out; 996 997 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 998 ret_val = phy->ops.write_reg(hw, 999 IGP01E1000_PHY_PORT_CONFIG, 1000 data); 1001 if (ret_val) 1002 goto out; 1003 1004 /* Set auto Master/Slave resolution process */ 1005 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1006 if (ret_val) 1007 goto out; 1008 1009 data &= ~CR_1000T_MS_ENABLE; 1010 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1011 if (ret_val) 1012 goto out; 1013 } 1014 1015 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1016 if (ret_val) 1017 goto out; 1018 1019 /* load defaults for future use */ 1020 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 1021 ((data & CR_1000T_MS_VALUE) ? 1022 e1000_ms_force_master : 1023 e1000_ms_force_slave) : 1024 e1000_ms_auto; 1025 1026 switch (phy->ms_type) { 1027 case e1000_ms_force_master: 1028 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1029 break; 1030 case e1000_ms_force_slave: 1031 data |= CR_1000T_MS_ENABLE; 1032 data &= ~(CR_1000T_MS_VALUE); 1033 break; 1034 case e1000_ms_auto: 1035 data &= ~CR_1000T_MS_ENABLE; 1036 default: 1037 break; 1038 } 1039 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1040 if (ret_val) 1041 goto out; 1042 } 1043 1044 out: 1045 return ret_val; 1046 } 1047 1048 /** 1049 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1050 * @hw: pointer to the HW structure 1051 * 1052 * Performs initial bounds checking on autoneg advertisement parameter, then 1053 * configure to advertise the full capability. Setup the PHY to autoneg 1054 * and restart the negotiation process between the link partner. If 1055 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1056 **/ 1057 s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1058 { 1059 struct e1000_phy_info *phy = &hw->phy; 1060 s32 ret_val; 1061 u16 phy_ctrl; 1062 1063 DEBUGFUNC("e1000_copper_link_autoneg"); 1064 1065 /* 1066 * Perform some bounds checking on the autoneg advertisement 1067 * parameter. 1068 */ 1069 phy->autoneg_advertised &= phy->autoneg_mask; 1070 1071 /* 1072 * If autoneg_advertised is zero, we assume it was not defaulted 1073 * by the calling code so we set to advertise full capability. 1074 */ 1075 if (phy->autoneg_advertised == 0) 1076 phy->autoneg_advertised = phy->autoneg_mask; 1077 1078 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1079 ret_val = e1000_phy_setup_autoneg(hw); 1080 if (ret_val) { 1081 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1082 goto out; 1083 } 1084 DEBUGOUT("Restarting Auto-Neg\n"); 1085 1086 /* 1087 * Restart auto-negotiation by setting the Auto Neg Enable bit and 1088 * the Auto Neg Restart bit in the PHY control register. 1089 */ 1090 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1091 if (ret_val) 1092 goto out; 1093 1094 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1095 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1096 if (ret_val) 1097 goto out; 1098 1099 /* 1100 * Does the user want to wait for Auto-Neg to complete here, or 1101 * check at a later time (for example, callback routine). 1102 */ 1103 if (phy->autoneg_wait_to_complete) { 1104 ret_val = hw->mac.ops.wait_autoneg(hw); 1105 if (ret_val) { 1106 DEBUGOUT("Error while waiting for " 1107 "autoneg to complete\n"); 1108 goto out; 1109 } 1110 } 1111 1112 hw->mac.get_link_status = TRUE; 1113 1114 out: 1115 return ret_val; 1116 } 1117 1118 /** 1119 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1120 * @hw: pointer to the HW structure 1121 * 1122 * Reads the MII auto-neg advertisement register and/or the 1000T control 1123 * register and if the PHY is already setup for auto-negotiation, then 1124 * return successful. Otherwise, setup advertisement and flow control to 1125 * the appropriate values for the wanted auto-negotiation. 1126 **/ 1127 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1128 { 1129 struct e1000_phy_info *phy = &hw->phy; 1130 s32 ret_val; 1131 u16 mii_autoneg_adv_reg; 1132 u16 mii_1000t_ctrl_reg = 0; 1133 1134 DEBUGFUNC("e1000_phy_setup_autoneg"); 1135 1136 phy->autoneg_advertised &= phy->autoneg_mask; 1137 1138 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1139 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1140 if (ret_val) 1141 goto out; 1142 1143 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1144 /* Read the MII 1000Base-T Control Register (Address 9). */ 1145 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1146 &mii_1000t_ctrl_reg); 1147 if (ret_val) 1148 goto out; 1149 } 1150 1151 /* 1152 * Need to parse both autoneg_advertised and fc and set up 1153 * the appropriate PHY registers. First we will parse for 1154 * autoneg_advertised software override. Since we can advertise 1155 * a plethora of combinations, we need to check each bit 1156 * individually. 1157 */ 1158 1159 /* 1160 * First we clear all the 10/100 mb speed bits in the Auto-Neg 1161 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1162 * the 1000Base-T Control Register (Address 9). 1163 */ 1164 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1165 NWAY_AR_100TX_HD_CAPS | 1166 NWAY_AR_10T_FD_CAPS | 1167 NWAY_AR_10T_HD_CAPS); 1168 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1169 1170 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1171 1172 /* Do we want to advertise 10 Mb Half Duplex? */ 1173 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1174 DEBUGOUT("Advertise 10mb Half duplex\n"); 1175 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1176 } 1177 1178 /* Do we want to advertise 10 Mb Full Duplex? */ 1179 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1180 DEBUGOUT("Advertise 10mb Full duplex\n"); 1181 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1182 } 1183 1184 /* Do we want to advertise 100 Mb Half Duplex? */ 1185 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1186 DEBUGOUT("Advertise 100mb Half duplex\n"); 1187 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1188 } 1189 1190 /* Do we want to advertise 100 Mb Full Duplex? */ 1191 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1192 DEBUGOUT("Advertise 100mb Full duplex\n"); 1193 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1194 } 1195 1196 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1197 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1198 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1199 1200 /* Do we want to advertise 1000 Mb Full Duplex? */ 1201 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1202 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1203 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1204 } 1205 1206 /* 1207 * Check for a software override of the flow control settings, and 1208 * setup the PHY advertisement registers accordingly. If 1209 * auto-negotiation is enabled, then software will have to set the 1210 * "PAUSE" bits to the correct value in the Auto-Negotiation 1211 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1212 * negotiation. 1213 * 1214 * The possible values of the "fc" parameter are: 1215 * 0: Flow control is completely disabled 1216 * 1: Rx flow control is enabled (we can receive pause frames 1217 * but not send pause frames). 1218 * 2: Tx flow control is enabled (we can send pause frames 1219 * but we do not support receiving pause frames). 1220 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1221 * other: No software override. The flow control configuration 1222 * in the EEPROM is used. 1223 */ 1224 switch (hw->fc.current_mode) { 1225 case e1000_fc_none: 1226 /* 1227 * Flow control (Rx & Tx) is completely disabled by a 1228 * software over-ride. 1229 */ 1230 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1231 break; 1232 case e1000_fc_rx_pause: 1233 /* 1234 * Rx Flow control is enabled, and Tx Flow control is 1235 * disabled, by a software over-ride. 1236 * 1237 * Since there really isn't a way to advertise that we are 1238 * capable of Rx Pause ONLY, we will advertise that we 1239 * support both symmetric and asymmetric Rx PAUSE. Later 1240 * (in e1000_config_fc_after_link_up) we will disable the 1241 * hw's ability to send PAUSE frames. 1242 */ 1243 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1244 break; 1245 case e1000_fc_tx_pause: 1246 /* 1247 * Tx Flow control is enabled, and Rx Flow control is 1248 * disabled, by a software over-ride. 1249 */ 1250 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1251 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1252 break; 1253 case e1000_fc_full: 1254 /* 1255 * Flow control (both Rx and Tx) is enabled by a software 1256 * over-ride. 1257 */ 1258 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1259 break; 1260 default: 1261 DEBUGOUT("Flow control param set incorrectly\n"); 1262 ret_val = -E1000_ERR_CONFIG; 1263 goto out; 1264 } 1265 1266 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1267 if (ret_val) 1268 goto out; 1269 1270 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1271 1272 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1273 ret_val = phy->ops.write_reg(hw, 1274 PHY_1000T_CTRL, 1275 mii_1000t_ctrl_reg); 1276 if (ret_val) 1277 goto out; 1278 } 1279 1280 out: 1281 return ret_val; 1282 } 1283 1284 /** 1285 * e1000_setup_copper_link_generic - Configure copper link settings 1286 * @hw: pointer to the HW structure 1287 * 1288 * Calls the appropriate function to configure the link for auto-neg or forced 1289 * speed and duplex. Then we check for link, once link is established calls 1290 * to configure collision distance and flow control are called. If link is 1291 * not established, we return -E1000_ERR_PHY (-2). 1292 **/ 1293 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1294 { 1295 s32 ret_val; 1296 bool link; 1297 1298 DEBUGFUNC("e1000_setup_copper_link_generic"); 1299 1300 if (hw->mac.autoneg) { 1301 /* 1302 * Setup autoneg and flow control advertisement and perform 1303 * autonegotiation. 1304 */ 1305 ret_val = e1000_copper_link_autoneg(hw); 1306 if (ret_val) 1307 goto out; 1308 } else { 1309 /* 1310 * PHY will be set to 10H, 10F, 100H or 100F 1311 * depending on user settings. 1312 */ 1313 DEBUGOUT("Forcing Speed and Duplex\n"); 1314 ret_val = hw->phy.ops.force_speed_duplex(hw); 1315 if (ret_val) { 1316 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1317 goto out; 1318 } 1319 } 1320 1321 /* 1322 * Check link status. Wait up to 100 microseconds for link to become 1323 * valid. 1324 */ 1325 ret_val = e1000_phy_has_link_generic(hw, 1326 COPPER_LINK_UP_LIMIT, 1327 10, 1328 &link); 1329 if (ret_val) 1330 goto out; 1331 1332 if (link) { 1333 DEBUGOUT("Valid link established!!!\n"); 1334 e1000_config_collision_dist_generic(hw); 1335 ret_val = e1000_config_fc_after_link_up_generic(hw); 1336 } else { 1337 DEBUGOUT("Unable to establish link!!!\n"); 1338 } 1339 1340 out: 1341 return ret_val; 1342 } 1343 1344 /** 1345 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1346 * @hw: pointer to the HW structure 1347 * 1348 * Calls the PHY setup function to force speed and duplex. Clears the 1349 * auto-crossover to force MDI manually. Waits for link and returns 1350 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1351 **/ 1352 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1353 { 1354 struct e1000_phy_info *phy = &hw->phy; 1355 s32 ret_val; 1356 u16 phy_data; 1357 bool link; 1358 1359 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1360 1361 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1362 if (ret_val) 1363 goto out; 1364 1365 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1366 1367 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1368 if (ret_val) 1369 goto out; 1370 1371 /* 1372 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1373 * forced whenever speed and duplex are forced. 1374 */ 1375 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1376 if (ret_val) 1377 goto out; 1378 1379 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1380 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1381 1382 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1383 if (ret_val) 1384 goto out; 1385 1386 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1387 1388 usec_delay(1); 1389 1390 if (phy->autoneg_wait_to_complete) { 1391 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1392 1393 ret_val = e1000_phy_has_link_generic(hw, 1394 PHY_FORCE_LIMIT, 1395 100000, 1396 &link); 1397 if (ret_val) 1398 goto out; 1399 1400 if (!link) 1401 DEBUGOUT("Link taking longer than expected.\n"); 1402 1403 /* Try once more */ 1404 ret_val = e1000_phy_has_link_generic(hw, 1405 PHY_FORCE_LIMIT, 1406 100000, 1407 &link); 1408 if (ret_val) 1409 goto out; 1410 } 1411 1412 out: 1413 return ret_val; 1414 } 1415 1416 /** 1417 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1418 * @hw: pointer to the HW structure 1419 * 1420 * Calls the PHY setup function to force speed and duplex. Clears the 1421 * auto-crossover to force MDI manually. Resets the PHY to commit the 1422 * changes. If time expires while waiting for link up, we reset the DSP. 1423 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1424 * successful completion, else return corresponding error code. 1425 **/ 1426 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1427 { 1428 struct e1000_phy_info *phy = &hw->phy; 1429 s32 ret_val; 1430 u16 phy_data; 1431 bool link; 1432 1433 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1434 1435 /* 1436 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1437 * forced whenever speed and duplex are forced. 1438 */ 1439 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1440 if (ret_val) 1441 goto out; 1442 1443 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1444 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1445 if (ret_val) 1446 goto out; 1447 1448 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1449 1450 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1451 if (ret_val) 1452 goto out; 1453 1454 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1455 1456 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1457 if (ret_val) 1458 goto out; 1459 1460 /* Reset the phy to commit changes. */ 1461 ret_val = hw->phy.ops.commit(hw); 1462 if (ret_val) 1463 goto out; 1464 1465 if (phy->autoneg_wait_to_complete) { 1466 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1467 1468 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1469 100000, &link); 1470 if (ret_val) 1471 goto out; 1472 1473 if (!link) { 1474 if (hw->phy.type != e1000_phy_m88) { 1475 DEBUGOUT("Link taking longer than expected.\n"); 1476 } else { 1477 /* 1478 * We didn't get link. 1479 * Reset the DSP and cross our fingers. 1480 */ 1481 ret_val = phy->ops.write_reg(hw, 1482 M88E1000_PHY_PAGE_SELECT, 1483 0x001d); 1484 if (ret_val) 1485 goto out; 1486 ret_val = e1000_phy_reset_dsp_generic(hw); 1487 if (ret_val) 1488 goto out; 1489 } 1490 } 1491 1492 /* Try once more */ 1493 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1494 100000, &link); 1495 if (ret_val) 1496 goto out; 1497 } 1498 1499 if (hw->phy.type != e1000_phy_m88) 1500 goto out; 1501 1502 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1503 if (ret_val) 1504 goto out; 1505 1506 /* 1507 * Resetting the phy means we need to re-force TX_CLK in the 1508 * Extended PHY Specific Control Register to 25MHz clock from 1509 * the reset value of 2.5MHz. 1510 */ 1511 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1512 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1513 if (ret_val) 1514 goto out; 1515 1516 /* 1517 * In addition, we must re-enable CRS on Tx for both half and full 1518 * duplex. 1519 */ 1520 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1521 if (ret_val) 1522 goto out; 1523 1524 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1525 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1526 1527 out: 1528 return ret_val; 1529 } 1530 1531 /** 1532 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1533 * @hw: pointer to the HW structure 1534 * 1535 * Forces the speed and duplex settings of the PHY. 1536 * This is a function pointer entry point only called by 1537 * PHY setup routines. 1538 **/ 1539 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1540 { 1541 struct e1000_phy_info *phy = &hw->phy; 1542 s32 ret_val; 1543 u16 data; 1544 bool link; 1545 1546 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1547 1548 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1549 if (ret_val) 1550 goto out; 1551 1552 e1000_phy_force_speed_duplex_setup(hw, &data); 1553 1554 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1555 if (ret_val) 1556 goto out; 1557 1558 /* Disable MDI-X support for 10/100 */ 1559 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1560 if (ret_val) 1561 goto out; 1562 1563 data &= ~IFE_PMC_AUTO_MDIX; 1564 data &= ~IFE_PMC_FORCE_MDIX; 1565 1566 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1567 if (ret_val) 1568 goto out; 1569 1570 DEBUGOUT1("IFE PMC: %X\n", data); 1571 1572 usec_delay(1); 1573 1574 if (phy->autoneg_wait_to_complete) { 1575 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1576 1577 ret_val = e1000_phy_has_link_generic(hw, 1578 PHY_FORCE_LIMIT, 1579 100000, 1580 &link); 1581 if (ret_val) 1582 goto out; 1583 1584 if (!link) 1585 DEBUGOUT("Link taking longer than expected.\n"); 1586 1587 /* Try once more */ 1588 ret_val = e1000_phy_has_link_generic(hw, 1589 PHY_FORCE_LIMIT, 1590 100000, 1591 &link); 1592 if (ret_val) 1593 goto out; 1594 } 1595 1596 out: 1597 return ret_val; 1598 } 1599 1600 /** 1601 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1602 * @hw: pointer to the HW structure 1603 * @phy_ctrl: pointer to current value of PHY_CONTROL 1604 * 1605 * Forces speed and duplex on the PHY by doing the following: disable flow 1606 * control, force speed/duplex on the MAC, disable auto speed detection, 1607 * disable auto-negotiation, configure duplex, configure speed, configure 1608 * the collision distance, write configuration to CTRL register. The 1609 * caller must write to the PHY_CONTROL register for these settings to 1610 * take affect. 1611 **/ 1612 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1613 { 1614 struct e1000_mac_info *mac = &hw->mac; 1615 u32 ctrl; 1616 1617 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1618 1619 /* Turn off flow control when forcing speed/duplex */ 1620 hw->fc.current_mode = e1000_fc_none; 1621 1622 /* Force speed/duplex on the mac */ 1623 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1624 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1625 ctrl &= ~E1000_CTRL_SPD_SEL; 1626 1627 /* Disable Auto Speed Detection */ 1628 ctrl &= ~E1000_CTRL_ASDE; 1629 1630 /* Disable autoneg on the phy */ 1631 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1632 1633 /* Forcing Full or Half Duplex? */ 1634 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1635 ctrl &= ~E1000_CTRL_FD; 1636 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1637 DEBUGOUT("Half Duplex\n"); 1638 } else { 1639 ctrl |= E1000_CTRL_FD; 1640 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1641 DEBUGOUT("Full Duplex\n"); 1642 } 1643 1644 /* Forcing 10mb or 100mb? */ 1645 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1646 ctrl |= E1000_CTRL_SPD_100; 1647 *phy_ctrl |= MII_CR_SPEED_100; 1648 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1649 DEBUGOUT("Forcing 100mb\n"); 1650 } else { 1651 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1652 *phy_ctrl |= MII_CR_SPEED_10; 1653 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1654 DEBUGOUT("Forcing 10mb\n"); 1655 } 1656 1657 e1000_config_collision_dist_generic(hw); 1658 1659 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1660 } 1661 1662 /** 1663 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1664 * @hw: pointer to the HW structure 1665 * @active: boolean used to enable/disable lplu 1666 * 1667 * Success returns 0, Failure returns 1 1668 * 1669 * The low power link up (lplu) state is set to the power management level D3 1670 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 1671 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1672 * is used during Dx states where the power conservation is most important. 1673 * During driver activity, SmartSpeed should be enabled so performance is 1674 * maintained. 1675 **/ 1676 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1677 { 1678 struct e1000_phy_info *phy = &hw->phy; 1679 s32 ret_val = E1000_SUCCESS; 1680 u16 data; 1681 1682 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1683 1684 if (!(hw->phy.ops.read_reg)) 1685 goto out; 1686 1687 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1688 if (ret_val) 1689 goto out; 1690 1691 if (!active) { 1692 data &= ~IGP02E1000_PM_D3_LPLU; 1693 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1694 data); 1695 if (ret_val) 1696 goto out; 1697 /* 1698 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1699 * during Dx states where the power conservation is most 1700 * important. During driver activity we should enable 1701 * SmartSpeed, so performance is maintained. 1702 */ 1703 if (phy->smart_speed == e1000_smart_speed_on) { 1704 ret_val = phy->ops.read_reg(hw, 1705 IGP01E1000_PHY_PORT_CONFIG, 1706 &data); 1707 if (ret_val) 1708 goto out; 1709 1710 data |= IGP01E1000_PSCFR_SMART_SPEED; 1711 ret_val = phy->ops.write_reg(hw, 1712 IGP01E1000_PHY_PORT_CONFIG, 1713 data); 1714 if (ret_val) 1715 goto out; 1716 } else if (phy->smart_speed == e1000_smart_speed_off) { 1717 ret_val = phy->ops.read_reg(hw, 1718 IGP01E1000_PHY_PORT_CONFIG, 1719 &data); 1720 if (ret_val) 1721 goto out; 1722 1723 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1724 ret_val = phy->ops.write_reg(hw, 1725 IGP01E1000_PHY_PORT_CONFIG, 1726 data); 1727 if (ret_val) 1728 goto out; 1729 } 1730 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1731 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1732 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1733 data |= IGP02E1000_PM_D3_LPLU; 1734 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1735 data); 1736 if (ret_val) 1737 goto out; 1738 1739 /* When LPLU is enabled, we should disable SmartSpeed */ 1740 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1741 &data); 1742 if (ret_val) 1743 goto out; 1744 1745 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1746 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1747 data); 1748 } 1749 1750 out: 1751 return ret_val; 1752 } 1753 1754 /** 1755 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1756 * @hw: pointer to the HW structure 1757 * 1758 * Success returns 0, Failure returns 1 1759 * 1760 * A downshift is detected by querying the PHY link health. 1761 **/ 1762 s32 e1000_check_downshift_generic(struct e1000_hw *hw) 1763 { 1764 struct e1000_phy_info *phy = &hw->phy; 1765 s32 ret_val; 1766 u16 phy_data, offset, mask; 1767 1768 DEBUGFUNC("e1000_check_downshift_generic"); 1769 1770 switch (phy->type) { 1771 case e1000_phy_m88: 1772 case e1000_phy_gg82563: 1773 case e1000_phy_bm: 1774 case e1000_phy_82578: 1775 offset = M88E1000_PHY_SPEC_STATUS; 1776 mask = M88E1000_PSSR_DOWNSHIFT; 1777 break; 1778 case e1000_phy_igp: 1779 case e1000_phy_igp_2: 1780 case e1000_phy_igp_3: 1781 offset = IGP01E1000_PHY_LINK_HEALTH; 1782 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1783 break; 1784 default: 1785 /* speed downshift not supported */ 1786 phy->speed_downgraded = FALSE; 1787 ret_val = E1000_SUCCESS; 1788 goto out; 1789 } 1790 1791 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1792 1793 if (!ret_val) 1794 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1795 1796 out: 1797 return ret_val; 1798 } 1799 1800 /** 1801 * e1000_check_polarity_m88 - Checks the polarity. 1802 * @hw: pointer to the HW structure 1803 * 1804 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1805 * 1806 * Polarity is determined based on the PHY specific status register. 1807 **/ 1808 s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1809 { 1810 struct e1000_phy_info *phy = &hw->phy; 1811 s32 ret_val; 1812 u16 data; 1813 1814 DEBUGFUNC("e1000_check_polarity_m88"); 1815 1816 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1817 1818 if (!ret_val) 1819 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1820 ? e1000_rev_polarity_reversed 1821 : e1000_rev_polarity_normal; 1822 1823 return ret_val; 1824 } 1825 1826 /** 1827 * e1000_check_polarity_igp - Checks the polarity. 1828 * @hw: pointer to the HW structure 1829 * 1830 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1831 * 1832 * Polarity is determined based on the PHY port status register, and the 1833 * current speed (since there is no polarity at 100Mbps). 1834 **/ 1835 s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1836 { 1837 struct e1000_phy_info *phy = &hw->phy; 1838 s32 ret_val; 1839 u16 data, offset, mask; 1840 1841 DEBUGFUNC("e1000_check_polarity_igp"); 1842 1843 /* 1844 * Polarity is determined based on the speed of 1845 * our connection. 1846 */ 1847 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1848 if (ret_val) 1849 goto out; 1850 1851 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1852 IGP01E1000_PSSR_SPEED_1000MBPS) { 1853 offset = IGP01E1000_PHY_PCS_INIT_REG; 1854 mask = IGP01E1000_PHY_POLARITY_MASK; 1855 } else { 1856 /* 1857 * This really only applies to 10Mbps since 1858 * there is no polarity for 100Mbps (always 0). 1859 */ 1860 offset = IGP01E1000_PHY_PORT_STATUS; 1861 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1862 } 1863 1864 ret_val = phy->ops.read_reg(hw, offset, &data); 1865 1866 if (!ret_val) 1867 phy->cable_polarity = (data & mask) 1868 ? e1000_rev_polarity_reversed 1869 : e1000_rev_polarity_normal; 1870 1871 out: 1872 return ret_val; 1873 } 1874 1875 /** 1876 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 1877 * @hw: pointer to the HW structure 1878 * 1879 * Polarity is determined on the polarity reversal feature being enabled. 1880 **/ 1881 s32 e1000_check_polarity_ife(struct e1000_hw *hw) 1882 { 1883 struct e1000_phy_info *phy = &hw->phy; 1884 s32 ret_val; 1885 u16 phy_data, offset, mask; 1886 1887 DEBUGFUNC("e1000_check_polarity_ife"); 1888 1889 /* 1890 * Polarity is determined based on the reversal feature being enabled. 1891 */ 1892 if (phy->polarity_correction) { 1893 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1894 mask = IFE_PESC_POLARITY_REVERSED; 1895 } else { 1896 offset = IFE_PHY_SPECIAL_CONTROL; 1897 mask = IFE_PSC_FORCE_POLARITY; 1898 } 1899 1900 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1901 1902 if (!ret_val) 1903 phy->cable_polarity = (phy_data & mask) 1904 ? e1000_rev_polarity_reversed 1905 : e1000_rev_polarity_normal; 1906 1907 return ret_val; 1908 } 1909 1910 /** 1911 * e1000_wait_autoneg_generic - Wait for auto-neg completion 1912 * @hw: pointer to the HW structure 1913 * 1914 * Waits for auto-negotiation to complete or for the auto-negotiation time 1915 * limit to expire, which ever happens first. 1916 **/ 1917 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) 1918 { 1919 s32 ret_val = E1000_SUCCESS; 1920 u16 i, phy_status; 1921 1922 DEBUGFUNC("e1000_wait_autoneg_generic"); 1923 1924 if (!(hw->phy.ops.read_reg)) 1925 return E1000_SUCCESS; 1926 1927 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1928 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1929 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1930 if (ret_val) 1931 break; 1932 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1933 if (ret_val) 1934 break; 1935 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1936 break; 1937 msec_delay(100); 1938 } 1939 1940 /* 1941 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1942 * has completed. 1943 */ 1944 return ret_val; 1945 } 1946 1947 /** 1948 * e1000_phy_has_link_generic - Polls PHY for link 1949 * @hw: pointer to the HW structure 1950 * @iterations: number of times to poll for link 1951 * @usec_interval: delay between polling attempts 1952 * @success: pointer to whether polling was successful or not 1953 * 1954 * Polls the PHY status register for link, 'iterations' number of times. 1955 **/ 1956 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1957 u32 usec_interval, bool *success) 1958 { 1959 s32 ret_val = E1000_SUCCESS; 1960 u16 i, phy_status; 1961 1962 DEBUGFUNC("e1000_phy_has_link_generic"); 1963 1964 if (!(hw->phy.ops.read_reg)) 1965 return E1000_SUCCESS; 1966 1967 for (i = 0; i < iterations; i++) { 1968 /* 1969 * Some PHYs require the PHY_STATUS register to be read 1970 * twice due to the link bit being sticky. No harm doing 1971 * it across the board. 1972 */ 1973 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1974 if (ret_val) 1975 /* 1976 * If the first read fails, another entity may have 1977 * ownership of the resources, wait and try again to 1978 * see if they have relinquished the resources yet. 1979 */ 1980 usec_delay(usec_interval); 1981 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1982 if (ret_val) 1983 break; 1984 if (phy_status & MII_SR_LINK_STATUS) 1985 break; 1986 if (usec_interval >= 1000) 1987 msec_delay_irq(usec_interval/1000); 1988 else 1989 usec_delay(usec_interval); 1990 } 1991 1992 *success = (i < iterations) ? TRUE : FALSE; 1993 1994 return ret_val; 1995 } 1996 1997 /** 1998 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1999 * @hw: pointer to the HW structure 2000 * 2001 * Reads the PHY specific status register to retrieve the cable length 2002 * information. The cable length is determined by averaging the minimum and 2003 * maximum values to get the "average" cable length. The m88 PHY has four 2004 * possible cable length values, which are: 2005 * Register Value Cable Length 2006 * 0 < 50 meters 2007 * 1 50 - 80 meters 2008 * 2 80 - 110 meters 2009 * 3 110 - 140 meters 2010 * 4 > 140 meters 2011 **/ 2012 s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2013 { 2014 struct e1000_phy_info *phy = &hw->phy; 2015 s32 ret_val; 2016 u16 phy_data, index; 2017 2018 DEBUGFUNC("e1000_get_cable_length_m88"); 2019 2020 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2021 if (ret_val) 2022 goto out; 2023 2024 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2025 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2026 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 2027 ret_val = -E1000_ERR_PHY; 2028 goto out; 2029 } 2030 2031 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2032 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2033 2034 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2035 2036 out: 2037 return ret_val; 2038 } 2039 2040 /** 2041 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2042 * @hw: pointer to the HW structure 2043 * 2044 * The automatic gain control (agc) normalizes the amplitude of the 2045 * received signal, adjusting for the attenuation produced by the 2046 * cable. By reading the AGC registers, which represent the 2047 * combination of coarse and fine gain value, the value can be put 2048 * into a lookup table to obtain the approximate cable length 2049 * for each channel. 2050 **/ 2051 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2052 { 2053 struct e1000_phy_info *phy = &hw->phy; 2054 s32 ret_val = E1000_SUCCESS; 2055 u16 phy_data, i, agc_value = 0; 2056 u16 cur_agc_index, max_agc_index = 0; 2057 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2058 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 2059 {IGP02E1000_PHY_AGC_A, 2060 IGP02E1000_PHY_AGC_B, 2061 IGP02E1000_PHY_AGC_C, 2062 IGP02E1000_PHY_AGC_D}; 2063 2064 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2065 2066 /* Read the AGC registers for all channels */ 2067 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2068 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2069 if (ret_val) 2070 goto out; 2071 2072 /* 2073 * Getting bits 15:9, which represent the combination of 2074 * coarse and fine gain values. The result is a number 2075 * that can be put into the lookup table to obtain the 2076 * approximate cable length. 2077 */ 2078 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2079 IGP02E1000_AGC_LENGTH_MASK; 2080 2081 /* Array index bound check. */ 2082 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2083 (cur_agc_index == 0)) { 2084 ret_val = -E1000_ERR_PHY; 2085 goto out; 2086 } 2087 2088 /* Remove min & max AGC values from calculation. */ 2089 if (e1000_igp_2_cable_length_table[min_agc_index] > 2090 e1000_igp_2_cable_length_table[cur_agc_index]) 2091 min_agc_index = cur_agc_index; 2092 if (e1000_igp_2_cable_length_table[max_agc_index] < 2093 e1000_igp_2_cable_length_table[cur_agc_index]) 2094 max_agc_index = cur_agc_index; 2095 2096 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2097 } 2098 2099 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2100 e1000_igp_2_cable_length_table[max_agc_index]); 2101 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2102 2103 /* Calculate cable length with the error range of +/- 10 meters. */ 2104 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2105 (agc_value - IGP02E1000_AGC_RANGE) : 0; 2106 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2107 2108 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2109 2110 out: 2111 return ret_val; 2112 } 2113 2114 /** 2115 * e1000_get_phy_info_m88 - Retrieve PHY information 2116 * @hw: pointer to the HW structure 2117 * 2118 * Valid for only copper links. Read the PHY status register (sticky read) 2119 * to verify that link is up. Read the PHY special control register to 2120 * determine the polarity and 10base-T extended distance. Read the PHY 2121 * special status register to determine MDI/MDIx and current speed. If 2122 * speed is 1000, then determine cable length, local and remote receiver. 2123 **/ 2124 s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2125 { 2126 struct e1000_phy_info *phy = &hw->phy; 2127 s32 ret_val; 2128 u16 phy_data; 2129 bool link; 2130 2131 DEBUGFUNC("e1000_get_phy_info_m88"); 2132 2133 if (phy->media_type != e1000_media_type_copper) { 2134 DEBUGOUT("Phy info is only valid for copper media\n"); 2135 ret_val = -E1000_ERR_CONFIG; 2136 goto out; 2137 } 2138 2139 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2140 if (ret_val) 2141 goto out; 2142 2143 if (!link) { 2144 DEBUGOUT("Phy info is only valid if link is up\n"); 2145 ret_val = -E1000_ERR_CONFIG; 2146 goto out; 2147 } 2148 2149 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2150 if (ret_val) 2151 goto out; 2152 2153 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 2154 ? TRUE : FALSE; 2155 2156 ret_val = e1000_check_polarity_m88(hw); 2157 if (ret_val) 2158 goto out; 2159 2160 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2161 if (ret_val) 2162 goto out; 2163 2164 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 2165 2166 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2167 ret_val = hw->phy.ops.get_cable_length(hw); 2168 if (ret_val) 2169 goto out; 2170 2171 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2172 if (ret_val) 2173 goto out; 2174 2175 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2176 ? e1000_1000t_rx_status_ok 2177 : e1000_1000t_rx_status_not_ok; 2178 2179 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2180 ? e1000_1000t_rx_status_ok 2181 : e1000_1000t_rx_status_not_ok; 2182 } else { 2183 /* Set values to "undefined" */ 2184 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2185 phy->local_rx = e1000_1000t_rx_status_undefined; 2186 phy->remote_rx = e1000_1000t_rx_status_undefined; 2187 } 2188 2189 out: 2190 return ret_val; 2191 } 2192 2193 /** 2194 * e1000_get_phy_info_igp - Retrieve igp PHY information 2195 * @hw: pointer to the HW structure 2196 * 2197 * Read PHY status to determine if link is up. If link is up, then 2198 * set/determine 10base-T extended distance and polarity correction. Read 2199 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2200 * determine on the cable length, local and remote receiver. 2201 **/ 2202 s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2203 { 2204 struct e1000_phy_info *phy = &hw->phy; 2205 s32 ret_val; 2206 u16 data; 2207 bool link; 2208 2209 DEBUGFUNC("e1000_get_phy_info_igp"); 2210 2211 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2212 if (ret_val) 2213 goto out; 2214 2215 if (!link) { 2216 DEBUGOUT("Phy info is only valid if link is up\n"); 2217 ret_val = -E1000_ERR_CONFIG; 2218 goto out; 2219 } 2220 2221 phy->polarity_correction = TRUE; 2222 2223 ret_val = e1000_check_polarity_igp(hw); 2224 if (ret_val) 2225 goto out; 2226 2227 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2228 if (ret_val) 2229 goto out; 2230 2231 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 2232 2233 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2234 IGP01E1000_PSSR_SPEED_1000MBPS) { 2235 ret_val = phy->ops.get_cable_length(hw); 2236 if (ret_val) 2237 goto out; 2238 2239 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2240 if (ret_val) 2241 goto out; 2242 2243 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2244 ? e1000_1000t_rx_status_ok 2245 : e1000_1000t_rx_status_not_ok; 2246 2247 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2248 ? e1000_1000t_rx_status_ok 2249 : e1000_1000t_rx_status_not_ok; 2250 } else { 2251 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2252 phy->local_rx = e1000_1000t_rx_status_undefined; 2253 phy->remote_rx = e1000_1000t_rx_status_undefined; 2254 } 2255 2256 out: 2257 return ret_val; 2258 } 2259 2260 /** 2261 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2262 * @hw: pointer to the HW structure 2263 * 2264 * Populates "phy" structure with various feature states. 2265 **/ 2266 s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2267 { 2268 struct e1000_phy_info *phy = &hw->phy; 2269 s32 ret_val; 2270 u16 data; 2271 bool link; 2272 2273 DEBUGFUNC("e1000_get_phy_info_ife"); 2274 2275 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2276 if (ret_val) 2277 goto out; 2278 2279 if (!link) { 2280 DEBUGOUT("Phy info is only valid if link is up\n"); 2281 ret_val = -E1000_ERR_CONFIG; 2282 goto out; 2283 } 2284 2285 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2286 if (ret_val) 2287 goto out; 2288 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 2289 ? FALSE : TRUE; 2290 2291 if (phy->polarity_correction) { 2292 ret_val = e1000_check_polarity_ife(hw); 2293 if (ret_val) 2294 goto out; 2295 } else { 2296 /* Polarity is forced */ 2297 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 2298 ? e1000_rev_polarity_reversed 2299 : e1000_rev_polarity_normal; 2300 } 2301 2302 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2303 if (ret_val) 2304 goto out; 2305 2306 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE; 2307 2308 /* The following parameters are undefined for 10/100 operation. */ 2309 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2310 phy->local_rx = e1000_1000t_rx_status_undefined; 2311 phy->remote_rx = e1000_1000t_rx_status_undefined; 2312 2313 out: 2314 return ret_val; 2315 } 2316 2317 /** 2318 * e1000_phy_sw_reset_generic - PHY software reset 2319 * @hw: pointer to the HW structure 2320 * 2321 * Does a software reset of the PHY by reading the PHY control register and 2322 * setting/write the control register reset bit to the PHY. 2323 **/ 2324 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2325 { 2326 s32 ret_val = E1000_SUCCESS; 2327 u16 phy_ctrl; 2328 2329 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2330 2331 if (!(hw->phy.ops.read_reg)) 2332 goto out; 2333 2334 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2335 if (ret_val) 2336 goto out; 2337 2338 phy_ctrl |= MII_CR_RESET; 2339 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2340 if (ret_val) 2341 goto out; 2342 2343 usec_delay(1); 2344 2345 out: 2346 return ret_val; 2347 } 2348 2349 /** 2350 * e1000_phy_hw_reset_generic - PHY hardware reset 2351 * @hw: pointer to the HW structure 2352 * 2353 * Verify the reset block is not blocking us from resetting. Acquire 2354 * semaphore (if necessary) and read/set/write the device control reset 2355 * bit in the PHY. Wait the appropriate delay time for the device to 2356 * reset and release the semaphore (if necessary). 2357 **/ 2358 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2359 { 2360 struct e1000_phy_info *phy = &hw->phy; 2361 s32 ret_val = E1000_SUCCESS; 2362 u32 ctrl; 2363 2364 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2365 2366 ret_val = phy->ops.check_reset_block(hw); 2367 if (ret_val) { 2368 ret_val = E1000_SUCCESS; 2369 goto out; 2370 } 2371 2372 ret_val = phy->ops.acquire(hw); 2373 if (ret_val) 2374 goto out; 2375 2376 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2377 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2378 E1000_WRITE_FLUSH(hw); 2379 2380 usec_delay(phy->reset_delay_us); 2381 2382 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2383 E1000_WRITE_FLUSH(hw); 2384 2385 usec_delay(150); 2386 2387 phy->ops.release(hw); 2388 2389 ret_val = phy->ops.get_cfg_done(hw); 2390 2391 out: 2392 return ret_val; 2393 } 2394 2395 /** 2396 * e1000_get_cfg_done_generic - Generic configuration done 2397 * @hw: pointer to the HW structure 2398 * 2399 * Generic function to wait 10 milli-seconds for configuration to complete 2400 * and return success. 2401 **/ 2402 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 2403 { 2404 DEBUGFUNC("e1000_get_cfg_done_generic"); 2405 2406 msec_delay_irq(10); 2407 2408 return E1000_SUCCESS; 2409 } 2410 2411 /** 2412 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2413 * @hw: pointer to the HW structure 2414 * 2415 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2416 **/ 2417 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2418 { 2419 DEBUGOUT("Running IGP 3 PHY init script\n"); 2420 2421 /* PHY init IGP 3 */ 2422 /* Enable rise/fall, 10-mode work in class-A */ 2423 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2424 /* Remove all caps from Replica path filter */ 2425 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2426 /* Bias trimming for ADC, AFE and Driver (Default) */ 2427 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2428 /* Increase Hybrid poly bias */ 2429 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2430 /* Add 4% to Tx amplitude in Gig mode */ 2431 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2432 /* Disable trimming (TTT) */ 2433 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2434 /* Poly DC correction to 94.6% + 2% for all channels */ 2435 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2436 /* ABS DC correction to 95.9% */ 2437 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2438 /* BG temp curve trim */ 2439 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2440 /* Increasing ADC OPAMP stage 1 currents to max */ 2441 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2442 /* Force 1000 ( required for enabling PHY regs configuration) */ 2443 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2444 /* Set upd_freq to 6 */ 2445 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2446 /* Disable NPDFE */ 2447 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2448 /* Disable adaptive fixed FFE (Default) */ 2449 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2450 /* Enable FFE hysteresis */ 2451 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2452 /* Fixed FFE for short cable lengths */ 2453 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2454 /* Fixed FFE for medium cable lengths */ 2455 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2456 /* Fixed FFE for long cable lengths */ 2457 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2458 /* Enable Adaptive Clip Threshold */ 2459 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2460 /* AHT reset limit to 1 */ 2461 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2462 /* Set AHT master delay to 127 msec */ 2463 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2464 /* Set scan bits for AHT */ 2465 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2466 /* Set AHT Preset bits */ 2467 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2468 /* Change integ_factor of channel A to 3 */ 2469 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2470 /* Change prop_factor of channels BCD to 8 */ 2471 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2472 /* Change cg_icount + enable integbp for channels BCD */ 2473 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2474 /* 2475 * Change cg_icount + enable integbp + change prop_factor_master 2476 * to 8 for channel A 2477 */ 2478 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2479 /* Disable AHT in Slave mode on channel A */ 2480 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2481 /* 2482 * Enable LPLU and disable AN to 1000 in non-D0a states, 2483 * Enable SPD+B2B 2484 */ 2485 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2486 /* Enable restart AN on an1000_dis change */ 2487 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2488 /* Enable wh_fifo read clock in 10/100 modes */ 2489 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2490 /* Restart AN, Speed selection is 1000 */ 2491 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2492 2493 return E1000_SUCCESS; 2494 } 2495 2496 /** 2497 * e1000_get_phy_type_from_id - Get PHY type from id 2498 * @phy_id: phy_id read from the phy 2499 * 2500 * Returns the phy type from the id. 2501 **/ 2502 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2503 { 2504 enum e1000_phy_type phy_type = e1000_phy_unknown; 2505 2506 switch (phy_id) { 2507 case M88E1000_I_PHY_ID: 2508 case M88E1000_E_PHY_ID: 2509 case M88E1111_I_PHY_ID: 2510 case M88E1011_I_PHY_ID: 2511 phy_type = e1000_phy_m88; 2512 break; 2513 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2514 phy_type = e1000_phy_igp_2; 2515 break; 2516 case GG82563_E_PHY_ID: 2517 phy_type = e1000_phy_gg82563; 2518 break; 2519 case IGP03E1000_E_PHY_ID: 2520 phy_type = e1000_phy_igp_3; 2521 break; 2522 case IFE_E_PHY_ID: 2523 case IFE_PLUS_E_PHY_ID: 2524 case IFE_C_E_PHY_ID: 2525 phy_type = e1000_phy_ife; 2526 break; 2527 case BME1000_E_PHY_ID: 2528 case BME1000_E_PHY_ID_R2: 2529 phy_type = e1000_phy_bm; 2530 break; 2531 case I82578_E_PHY_ID: 2532 phy_type = e1000_phy_82578; 2533 break; 2534 case I82577_E_PHY_ID: 2535 phy_type = e1000_phy_82577; 2536 break; 2537 case I82579_E_PHY_ID: 2538 phy_type = e1000_phy_82579; 2539 break; 2540 case I82580_I_PHY_ID: 2541 phy_type = e1000_phy_82580; 2542 break; 2543 default: 2544 phy_type = e1000_phy_unknown; 2545 break; 2546 } 2547 return phy_type; 2548 } 2549 2550 /** 2551 * e1000_determine_phy_address - Determines PHY address. 2552 * @hw: pointer to the HW structure 2553 * 2554 * This uses a trial and error method to loop through possible PHY 2555 * addresses. It tests each by reading the PHY ID registers and 2556 * checking for a match. 2557 **/ 2558 s32 e1000_determine_phy_address(struct e1000_hw *hw) 2559 { 2560 s32 ret_val = -E1000_ERR_PHY_TYPE; 2561 u32 phy_addr = 0; 2562 u32 i; 2563 enum e1000_phy_type phy_type = e1000_phy_unknown; 2564 2565 hw->phy.id = phy_type; 2566 2567 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2568 hw->phy.addr = phy_addr; 2569 i = 0; 2570 2571 do { 2572 e1000_get_phy_id(hw); 2573 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2574 2575 /* 2576 * If phy_type is valid, break - we found our 2577 * PHY address 2578 */ 2579 if (phy_type != e1000_phy_unknown) { 2580 ret_val = E1000_SUCCESS; 2581 goto out; 2582 } 2583 msec_delay(1); 2584 i++; 2585 } while (i < 10); 2586 } 2587 2588 out: 2589 return ret_val; 2590 } 2591 2592 /** 2593 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2594 * @page: page to access 2595 * 2596 * Returns the phy address for the page requested. 2597 **/ 2598 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2599 { 2600 u32 phy_addr = 2; 2601 2602 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2603 phy_addr = 1; 2604 2605 return phy_addr; 2606 } 2607 2608 /** 2609 * e1000_write_phy_reg_bm - Write BM PHY register 2610 * @hw: pointer to the HW structure 2611 * @offset: register offset to write to 2612 * @data: data to write at register offset 2613 * 2614 * Acquires semaphore, if necessary, then writes the data to PHY register 2615 * at the offset. Release any acquired semaphores before exiting. 2616 **/ 2617 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2618 { 2619 s32 ret_val; 2620 u32 page_select = 0; 2621 u32 page = offset >> IGP_PAGE_SHIFT; 2622 u32 page_shift = 0; 2623 2624 DEBUGFUNC("e1000_write_phy_reg_bm"); 2625 2626 ret_val = hw->phy.ops.acquire(hw); 2627 if (ret_val) 2628 return ret_val; 2629 2630 /* Page 800 works differently than the rest so it has its own func */ 2631 if (page == BM_WUC_PAGE) { 2632 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2633 FALSE); 2634 goto out; 2635 } 2636 2637 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2638 2639 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2640 /* 2641 * Page select is register 31 for phy address 1 and 22 for 2642 * phy address 2 and 3. Page select is shifted only for 2643 * phy address 1. 2644 */ 2645 if (hw->phy.addr == 1) { 2646 page_shift = IGP_PAGE_SHIFT; 2647 page_select = IGP01E1000_PHY_PAGE_SELECT; 2648 } else { 2649 page_shift = 0; 2650 page_select = BM_PHY_PAGE_SELECT; 2651 } 2652 2653 /* Page is shifted left, PHY expects (page x 32) */ 2654 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2655 (page << page_shift)); 2656 if (ret_val) 2657 goto out; 2658 } 2659 2660 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2661 data); 2662 2663 out: 2664 hw->phy.ops.release(hw); 2665 return ret_val; 2666 } 2667 2668 /** 2669 * e1000_read_phy_reg_bm - Read BM PHY register 2670 * @hw: pointer to the HW structure 2671 * @offset: register offset to be read 2672 * @data: pointer to the read data 2673 * 2674 * Acquires semaphore, if necessary, then reads the PHY register at offset 2675 * and storing the retrieved information in data. Release any acquired 2676 * semaphores before exiting. 2677 **/ 2678 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2679 { 2680 s32 ret_val; 2681 u32 page_select = 0; 2682 u32 page = offset >> IGP_PAGE_SHIFT; 2683 u32 page_shift = 0; 2684 2685 DEBUGFUNC("e1000_read_phy_reg_bm"); 2686 2687 ret_val = hw->phy.ops.acquire(hw); 2688 if (ret_val) 2689 return ret_val; 2690 2691 /* Page 800 works differently than the rest so it has its own func */ 2692 if (page == BM_WUC_PAGE) { 2693 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2694 TRUE); 2695 goto out; 2696 } 2697 2698 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2699 2700 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2701 /* 2702 * Page select is register 31 for phy address 1 and 22 for 2703 * phy address 2 and 3. Page select is shifted only for 2704 * phy address 1. 2705 */ 2706 if (hw->phy.addr == 1) { 2707 page_shift = IGP_PAGE_SHIFT; 2708 page_select = IGP01E1000_PHY_PAGE_SELECT; 2709 } else { 2710 page_shift = 0; 2711 page_select = BM_PHY_PAGE_SELECT; 2712 } 2713 2714 /* Page is shifted left, PHY expects (page x 32) */ 2715 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2716 (page << page_shift)); 2717 if (ret_val) 2718 goto out; 2719 } 2720 2721 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2722 data); 2723 out: 2724 hw->phy.ops.release(hw); 2725 return ret_val; 2726 } 2727 2728 /** 2729 * e1000_read_phy_reg_bm2 - Read BM PHY register 2730 * @hw: pointer to the HW structure 2731 * @offset: register offset to be read 2732 * @data: pointer to the read data 2733 * 2734 * Acquires semaphore, if necessary, then reads the PHY register at offset 2735 * and storing the retrieved information in data. Release any acquired 2736 * semaphores before exiting. 2737 **/ 2738 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2739 { 2740 s32 ret_val; 2741 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2742 2743 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2744 2745 ret_val = hw->phy.ops.acquire(hw); 2746 if (ret_val) 2747 return ret_val; 2748 2749 /* Page 800 works differently than the rest so it has its own func */ 2750 if (page == BM_WUC_PAGE) { 2751 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2752 TRUE); 2753 goto out; 2754 } 2755 2756 hw->phy.addr = 1; 2757 2758 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2759 2760 /* Page is shifted left, PHY expects (page x 32) */ 2761 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2762 page); 2763 2764 if (ret_val) 2765 goto out; 2766 } 2767 2768 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2769 data); 2770 out: 2771 hw->phy.ops.release(hw); 2772 return ret_val; 2773 } 2774 2775 /** 2776 * e1000_write_phy_reg_bm2 - Write BM PHY register 2777 * @hw: pointer to the HW structure 2778 * @offset: register offset to write to 2779 * @data: data to write at register offset 2780 * 2781 * Acquires semaphore, if necessary, then writes the data to PHY register 2782 * at the offset. Release any acquired semaphores before exiting. 2783 **/ 2784 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2785 { 2786 s32 ret_val; 2787 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2788 2789 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2790 2791 ret_val = hw->phy.ops.acquire(hw); 2792 if (ret_val) 2793 return ret_val; 2794 2795 /* Page 800 works differently than the rest so it has its own func */ 2796 if (page == BM_WUC_PAGE) { 2797 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2798 FALSE); 2799 goto out; 2800 } 2801 2802 hw->phy.addr = 1; 2803 2804 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2805 /* Page is shifted left, PHY expects (page x 32) */ 2806 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2807 page); 2808 2809 if (ret_val) 2810 goto out; 2811 } 2812 2813 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2814 data); 2815 2816 out: 2817 hw->phy.ops.release(hw); 2818 return ret_val; 2819 } 2820 2821 /** 2822 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register 2823 * @hw: pointer to the HW structure 2824 * @offset: register offset to be read or written 2825 * @data: pointer to the data to read or write 2826 * @read: determines if operation is read or write 2827 * 2828 * Acquires semaphore, if necessary, then reads the PHY register at offset 2829 * and storing the retrieved information in data. Release any acquired 2830 * semaphores before exiting. Note that procedure to read the wakeup 2831 * registers are different. It works as such: 2832 * 1) Set page 769, register 17, bit 2 = 1 2833 * 2) Set page to 800 for host (801 if we were manageability) 2834 * 3) Write the address using the address opcode (0x11) 2835 * 4) Read or write the data using the data opcode (0x12) 2836 * 5) Restore 769_17.2 to its original value 2837 * 2838 * Assumes semaphore already acquired. 2839 **/ 2840 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2841 u16 *data, bool read) 2842 { 2843 s32 ret_val; 2844 u16 reg = BM_PHY_REG_NUM(offset); 2845 u16 phy_reg = 0; 2846 2847 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 2848 2849 /* Gig must be disabled for MDIO accesses to page 800 */ 2850 if ((hw->mac.type == e1000_pchlan) && 2851 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 2852 DEBUGOUT("Attempting to access page 800 while gig enabled.\n"); 2853 2854 /* All operations in this function are phy address 1 */ 2855 hw->phy.addr = 1; 2856 2857 /* Set page 769 */ 2858 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2859 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2860 2861 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2862 if (ret_val) { 2863 DEBUGOUT("Could not read PHY page 769\n"); 2864 goto out; 2865 } 2866 2867 /* First clear bit 4 to avoid a power state change */ 2868 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2869 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2870 if (ret_val) { 2871 DEBUGOUT("Could not clear PHY page 769 bit 4\n"); 2872 goto out; 2873 } 2874 2875 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2876 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2877 phy_reg | BM_WUC_ENABLE_BIT); 2878 if (ret_val) { 2879 DEBUGOUT("Could not write PHY page 769 bit 2\n"); 2880 goto out; 2881 } 2882 2883 /* Select page 800 */ 2884 ret_val = e1000_write_phy_reg_mdic(hw, 2885 IGP01E1000_PHY_PAGE_SELECT, 2886 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2887 2888 /* Write the page 800 offset value using opcode 0x11 */ 2889 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2890 if (ret_val) { 2891 DEBUGOUT("Could not write address opcode to page 800\n"); 2892 goto out; 2893 } 2894 2895 if (read) { 2896 /* Read the page 800 value using opcode 0x12 */ 2897 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2898 data); 2899 } else { 2900 /* Write the page 800 value using opcode 0x12 */ 2901 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2902 *data); 2903 } 2904 2905 if (ret_val) { 2906 DEBUGOUT("Could not access data value from page 800\n"); 2907 goto out; 2908 } 2909 2910 /* 2911 * Restore 769_17.2 to its original value 2912 * Set page 769 2913 */ 2914 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2915 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2916 2917 /* Clear 769_17.2 */ 2918 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2919 if (ret_val) { 2920 DEBUGOUT("Could not clear PHY page 769 bit 2\n"); 2921 goto out; 2922 } 2923 2924 out: 2925 return ret_val; 2926 } 2927 2928 /** 2929 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2930 * @hw: pointer to the HW structure 2931 * 2932 * In the case of a PHY power down to save power, or to turn off link during a 2933 * driver unload, or wake on lan is not enabled, restore the link to previous 2934 * settings. 2935 **/ 2936 void e1000_power_up_phy_copper(struct e1000_hw *hw) 2937 { 2938 u16 mii_reg = 0; 2939 2940 /* The PHY will retain its settings across a power down/up cycle */ 2941 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2942 mii_reg &= ~MII_CR_POWER_DOWN; 2943 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2944 } 2945 2946 /** 2947 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2948 * @hw: pointer to the HW structure 2949 * 2950 * In the case of a PHY power down to save power, or to turn off link during a 2951 * driver unload, or wake on lan is not enabled, restore the link to previous 2952 * settings. 2953 **/ 2954 void e1000_power_down_phy_copper(struct e1000_hw *hw) 2955 { 2956 u16 mii_reg = 0; 2957 2958 /* The PHY will retain its settings across a power down/up cycle */ 2959 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2960 mii_reg |= MII_CR_POWER_DOWN; 2961 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2962 msec_delay(1); 2963 } 2964 2965 /** 2966 * __e1000_read_phy_reg_hv - Read HV PHY register 2967 * @hw: pointer to the HW structure 2968 * @offset: register offset to be read 2969 * @data: pointer to the read data 2970 * @locked: semaphore has already been acquired or not 2971 * 2972 * Acquires semaphore, if necessary, then reads the PHY register at offset 2973 * and stores the retrieved information in data. Release any acquired 2974 * semaphore before exiting. 2975 **/ 2976 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 2977 bool locked) 2978 { 2979 s32 ret_val; 2980 u16 page = BM_PHY_REG_PAGE(offset); 2981 u16 reg = BM_PHY_REG_NUM(offset); 2982 2983 DEBUGFUNC("__e1000_read_phy_reg_hv"); 2984 2985 if (!locked) { 2986 ret_val = hw->phy.ops.acquire(hw); 2987 if (ret_val) 2988 return ret_val; 2989 } 2990 2991 /* Page 800 works differently than the rest so it has its own func */ 2992 if (page == BM_WUC_PAGE) { 2993 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 2994 data, TRUE); 2995 goto out; 2996 } 2997 2998 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 2999 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3000 data, TRUE); 3001 goto out; 3002 } 3003 3004 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3005 3006 if (page == HV_INTC_FC_PAGE_START) 3007 page = 0; 3008 3009 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3010 u32 phy_addr = hw->phy.addr; 3011 3012 hw->phy.addr = 1; 3013 3014 /* Page is shifted left, PHY expects (page x 32) */ 3015 ret_val = e1000_write_phy_reg_mdic(hw, 3016 IGP01E1000_PHY_PAGE_SELECT, 3017 (page << IGP_PAGE_SHIFT)); 3018 hw->phy.addr = phy_addr; 3019 3020 if (ret_val) 3021 goto out; 3022 } 3023 3024 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3025 data); 3026 out: 3027 if (!locked) 3028 hw->phy.ops.release(hw); 3029 3030 return ret_val; 3031 } 3032 3033 /** 3034 * e1000_read_phy_reg_hv - Read HV PHY register 3035 * @hw: pointer to the HW structure 3036 * @offset: register offset to be read 3037 * @data: pointer to the read data 3038 * 3039 * Acquires semaphore then reads the PHY register at offset and stores 3040 * the retrieved information in data. Release the acquired semaphore 3041 * before exiting. 3042 **/ 3043 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3044 { 3045 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE); 3046 } 3047 3048 /** 3049 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3050 * @hw: pointer to the HW structure 3051 * @offset: register offset to be read 3052 * @data: pointer to the read data 3053 * 3054 * Reads the PHY register at offset and stores the retrieved information 3055 * in data. Assumes semaphore already acquired. 3056 **/ 3057 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3058 { 3059 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE); 3060 } 3061 3062 /** 3063 * __e1000_write_phy_reg_hv - Write HV PHY register 3064 * @hw: pointer to the HW structure 3065 * @offset: register offset to write to 3066 * @data: data to write at register offset 3067 * @locked: semaphore has already been acquired or not 3068 * 3069 * Acquires semaphore, if necessary, then writes the data to PHY register 3070 * at the offset. Release any acquired semaphores before exiting. 3071 **/ 3072 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3073 bool locked) 3074 { 3075 s32 ret_val; 3076 u16 page = BM_PHY_REG_PAGE(offset); 3077 u16 reg = BM_PHY_REG_NUM(offset); 3078 3079 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3080 3081 if (!locked) { 3082 ret_val = hw->phy.ops.acquire(hw); 3083 if (ret_val) 3084 return ret_val; 3085 } 3086 3087 /* Page 800 works differently than the rest so it has its own func */ 3088 if (page == BM_WUC_PAGE) { 3089 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, 3090 &data, FALSE); 3091 goto out; 3092 } 3093 3094 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3095 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3096 &data, FALSE); 3097 goto out; 3098 } 3099 3100 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3101 3102 if (page == HV_INTC_FC_PAGE_START) 3103 page = 0; 3104 3105 /* 3106 * Workaround MDIO accesses being disabled after entering IEEE Power 3107 * Down (whenever bit 11 of the PHY Control register is set) 3108 */ 3109 if ((hw->phy.type == e1000_phy_82578) && 3110 (hw->phy.revision >= 1) && 3111 (hw->phy.addr == 2) && 3112 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 3113 (data & (1 << 11))) { 3114 u16 data2 = 0x7EFF; 3115 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 3116 &data2, FALSE); 3117 if (ret_val) 3118 goto out; 3119 } 3120 3121 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3122 u32 phy_addr = hw->phy.addr; 3123 3124 hw->phy.addr = 1; 3125 3126 /* Page is shifted left, PHY expects (page x 32) */ 3127 ret_val = e1000_write_phy_reg_mdic(hw, 3128 IGP01E1000_PHY_PAGE_SELECT, 3129 (page << IGP_PAGE_SHIFT)); 3130 hw->phy.addr = phy_addr; 3131 3132 if (ret_val) 3133 goto out; 3134 } 3135 3136 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3137 data); 3138 3139 out: 3140 if (!locked) 3141 hw->phy.ops.release(hw); 3142 3143 return ret_val; 3144 } 3145 3146 /** 3147 * e1000_write_phy_reg_hv - Write HV PHY register 3148 * @hw: pointer to the HW structure 3149 * @offset: register offset to write to 3150 * @data: data to write at register offset 3151 * 3152 * Acquires semaphore then writes the data to PHY register at the offset. 3153 * Release the acquired semaphores before exiting. 3154 **/ 3155 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3156 { 3157 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE); 3158 } 3159 3160 /** 3161 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3162 * @hw: pointer to the HW structure 3163 * @offset: register offset to write to 3164 * @data: data to write at register offset 3165 * 3166 * Writes the data to PHY register at the offset. Assumes semaphore 3167 * already acquired. 3168 **/ 3169 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3170 { 3171 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE); 3172 } 3173 3174 /** 3175 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3176 * @page: page to be accessed 3177 **/ 3178 static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3179 { 3180 u32 phy_addr = 2; 3181 3182 if (page >= HV_INTC_FC_PAGE_START) 3183 phy_addr = 1; 3184 3185 return phy_addr; 3186 } 3187 3188 /** 3189 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3190 * @hw: pointer to the HW structure 3191 * @offset: register offset to be read or written 3192 * @data: pointer to the data to be read or written 3193 * @read: determines if operation is read or written 3194 * 3195 * Reads the PHY register at offset and stores the retreived information 3196 * in data. Assumes semaphore already acquired. Note that the procedure 3197 * to read these regs uses the address port and data port to read/write. 3198 **/ 3199 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3200 u16 *data, bool read) 3201 { 3202 s32 ret_val; 3203 u32 addr_reg = 0; 3204 u32 data_reg = 0; 3205 3206 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3207 3208 /* This takes care of the difference with desktop vs mobile phy */ 3209 addr_reg = (hw->phy.type == e1000_phy_82578) ? 3210 I82578_ADDR_REG : I82577_ADDR_REG; 3211 data_reg = addr_reg + 1; 3212 3213 /* All operations in this function are phy address 2 */ 3214 hw->phy.addr = 2; 3215 3216 /* masking with 0x3F to remove the page from offset */ 3217 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3218 if (ret_val) { 3219 DEBUGOUT("Could not write PHY the HV address register\n"); 3220 goto out; 3221 } 3222 3223 /* Read or write the data value next */ 3224 if (read) 3225 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3226 else 3227 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3228 3229 if (ret_val) { 3230 DEBUGOUT("Could not read data value from HV data register\n"); 3231 goto out; 3232 } 3233 3234 out: 3235 return ret_val; 3236 } 3237 3238 /** 3239 * e1000_link_stall_workaround_hv - Si workaround 3240 * @hw: pointer to the HW structure 3241 * 3242 * This function works around a Si bug where the link partner can get 3243 * a link up indication before the PHY does. If small packets are sent 3244 * by the link partner they can be placed in the packet buffer without 3245 * being properly accounted for by the PHY and will stall preventing 3246 * further packets from being received. The workaround is to clear the 3247 * packet buffer after the PHY detects link up. 3248 **/ 3249 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3250 { 3251 s32 ret_val = E1000_SUCCESS; 3252 u16 data; 3253 3254 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3255 3256 if (hw->phy.type != e1000_phy_82578) 3257 goto out; 3258 3259 /* Do not apply workaround if in PHY loopback bit 14 set */ 3260 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3261 if (data & PHY_CONTROL_LB) 3262 goto out; 3263 3264 /* check if link is up and at 1Gbps */ 3265 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3266 if (ret_val) 3267 goto out; 3268 3269 data &= BM_CS_STATUS_LINK_UP | 3270 BM_CS_STATUS_RESOLVED | 3271 BM_CS_STATUS_SPEED_MASK; 3272 3273 if (data != (BM_CS_STATUS_LINK_UP | 3274 BM_CS_STATUS_RESOLVED | 3275 BM_CS_STATUS_SPEED_1000)) 3276 goto out; 3277 3278 msec_delay(200); 3279 3280 /* flush the packets in the fifo buffer */ 3281 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3282 HV_MUX_DATA_CTRL_GEN_TO_MAC | 3283 HV_MUX_DATA_CTRL_FORCE_SPEED); 3284 if (ret_val) 3285 goto out; 3286 3287 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3288 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3289 3290 out: 3291 return ret_val; 3292 } 3293 3294 /** 3295 * e1000_check_polarity_82577 - Checks the polarity. 3296 * @hw: pointer to the HW structure 3297 * 3298 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3299 * 3300 * Polarity is determined based on the PHY specific status register. 3301 **/ 3302 s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3303 { 3304 struct e1000_phy_info *phy = &hw->phy; 3305 s32 ret_val; 3306 u16 data; 3307 3308 DEBUGFUNC("e1000_check_polarity_82577"); 3309 3310 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3311 3312 if (!ret_val) 3313 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 3314 ? e1000_rev_polarity_reversed 3315 : e1000_rev_polarity_normal; 3316 3317 return ret_val; 3318 } 3319 3320 /** 3321 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3322 * @hw: pointer to the HW structure 3323 * 3324 * Calls the PHY setup function to force speed and duplex. 3325 **/ 3326 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3327 { 3328 struct e1000_phy_info *phy = &hw->phy; 3329 s32 ret_val; 3330 u16 phy_data; 3331 bool link; 3332 3333 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3334 3335 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3336 if (ret_val) 3337 goto out; 3338 3339 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3340 3341 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3342 if (ret_val) 3343 goto out; 3344 3345 usec_delay(1); 3346 3347 if (phy->autoneg_wait_to_complete) { 3348 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3349 3350 ret_val = e1000_phy_has_link_generic(hw, 3351 PHY_FORCE_LIMIT, 3352 100000, 3353 &link); 3354 if (ret_val) 3355 goto out; 3356 3357 if (!link) 3358 DEBUGOUT("Link taking longer than expected.\n"); 3359 3360 /* Try once more */ 3361 ret_val = e1000_phy_has_link_generic(hw, 3362 PHY_FORCE_LIMIT, 3363 100000, 3364 &link); 3365 if (ret_val) 3366 goto out; 3367 } 3368 3369 out: 3370 return ret_val; 3371 } 3372 3373 /** 3374 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3375 * @hw: pointer to the HW structure 3376 * 3377 * Read PHY status to determine if link is up. If link is up, then 3378 * set/determine 10base-T extended distance and polarity correction. Read 3379 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3380 * determine on the cable length, local and remote receiver. 3381 **/ 3382 s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3383 { 3384 struct e1000_phy_info *phy = &hw->phy; 3385 s32 ret_val; 3386 u16 data; 3387 bool link; 3388 3389 DEBUGFUNC("e1000_get_phy_info_82577"); 3390 3391 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3392 if (ret_val) 3393 goto out; 3394 3395 if (!link) { 3396 DEBUGOUT("Phy info is only valid if link is up\n"); 3397 ret_val = -E1000_ERR_CONFIG; 3398 goto out; 3399 } 3400 3401 phy->polarity_correction = TRUE; 3402 3403 ret_val = e1000_check_polarity_82577(hw); 3404 if (ret_val) 3405 goto out; 3406 3407 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3408 if (ret_val) 3409 goto out; 3410 3411 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE; 3412 3413 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3414 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3415 ret_val = hw->phy.ops.get_cable_length(hw); 3416 if (ret_val) 3417 goto out; 3418 3419 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3420 if (ret_val) 3421 goto out; 3422 3423 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 3424 ? e1000_1000t_rx_status_ok 3425 : e1000_1000t_rx_status_not_ok; 3426 3427 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 3428 ? e1000_1000t_rx_status_ok 3429 : e1000_1000t_rx_status_not_ok; 3430 } else { 3431 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 3432 phy->local_rx = e1000_1000t_rx_status_undefined; 3433 phy->remote_rx = e1000_1000t_rx_status_undefined; 3434 } 3435 3436 out: 3437 return ret_val; 3438 } 3439 3440 /** 3441 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 3442 * @hw: pointer to the HW structure 3443 * 3444 * Reads the diagnostic status register and verifies result is valid before 3445 * placing it in the phy_cable_length field. 3446 **/ 3447 s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 3448 { 3449 struct e1000_phy_info *phy = &hw->phy; 3450 s32 ret_val; 3451 u16 phy_data, length; 3452 3453 DEBUGFUNC("e1000_get_cable_length_82577"); 3454 3455 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 3456 if (ret_val) 3457 goto out; 3458 3459 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 3460 I82577_DSTATUS_CABLE_LENGTH_SHIFT; 3461 3462 if (length == E1000_CABLE_LENGTH_UNDEFINED) 3463 ret_val = -E1000_ERR_PHY; 3464 3465 phy->cable_length = length; 3466 3467 out: 3468 return ret_val; 3469 } 3470