1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 #ifndef _E1000_PHY_H_ 36 #define _E1000_PHY_H_ 37 38 void e1000_init_phy_ops_generic(struct e1000_hw *hw); 39 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data); 40 void e1000_null_phy_generic(struct e1000_hw *hw); 41 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active); 42 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data); 43 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data); 44 s32 e1000_check_downshift_generic(struct e1000_hw *hw); 45 s32 e1000_check_polarity_m88(struct e1000_hw *hw); 46 s32 e1000_check_polarity_igp(struct e1000_hw *hw); 47 s32 e1000_check_polarity_ife(struct e1000_hw *hw); 48 s32 e1000_check_reset_block_generic(struct e1000_hw *hw); 49 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 50 s32 e1000_copper_link_autoneg(struct e1000_hw *hw); 51 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); 52 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); 53 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw); 54 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); 55 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); 56 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 57 s32 e1000_get_cable_length_m88(struct e1000_hw *hw); 58 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw); 59 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); 60 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw); 61 s32 e1000_get_phy_id(struct e1000_hw *hw); 62 s32 e1000_get_phy_info_igp(struct e1000_hw *hw); 63 s32 e1000_get_phy_info_m88(struct e1000_hw *hw); 64 s32 e1000_get_phy_info_ife(struct e1000_hw *hw); 65 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); 66 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 67 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); 68 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); 69 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); 70 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); 71 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 72 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 73 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); 74 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 75 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); 76 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); 77 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); 78 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); 79 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); 80 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 81 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); 82 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 83 s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 84 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 85 u32 usec_interval, bool *success); 86 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); 87 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); 88 s32 e1000_determine_phy_address(struct e1000_hw *hw); 89 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 90 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 91 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 92 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 93 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 94 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 95 void e1000_power_up_phy_copper(struct e1000_hw *hw); 96 void e1000_power_down_phy_copper(struct e1000_hw *hw); 97 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 98 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 99 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 100 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); 101 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); 102 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 103 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); 104 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); 105 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 106 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); 107 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); 108 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 109 s32 e1000_check_polarity_82577(struct e1000_hw *hw); 110 s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 111 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 112 s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 113 114 #define E1000_MAX_PHY_ADDR 4 115 116 /* IGP01E1000 Specific Registers */ 117 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 118 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 119 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 120 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 121 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 122 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ 123 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 124 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 125 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 126 #define IGP_PAGE_SHIFT 5 127 #define PHY_REG_MASK 0x1F 128 129 /* BM/HV Specific Registers */ 130 #define BM_PORT_CTRL_PAGE 769 131 #define BM_PORT_GEN_CFG_REG PHY_REG(BM_PORT_CTRL_PAGE, 17) 132 #define BM_PCIE_PAGE 770 133 #define BM_WUC_PAGE 800 134 #define BM_WUC_ADDRESS_OPCODE 0x11 135 #define BM_WUC_DATA_OPCODE 0x12 136 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 137 #define BM_WUC_ENABLE_REG 17 138 #define BM_WUC_ENABLE_BIT (1 << 2) 139 #define BM_WUC_HOST_WU_BIT (1 << 4) 140 #define BM_WUC_ME_WU_BIT (1 << 5) 141 142 #define PHY_UPPER_SHIFT 21 143 #define BM_PHY_REG(page, reg) \ 144 (((reg) & MAX_PHY_REG_ADDRESS) |\ 145 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 146 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 147 #define BM_PHY_REG_PAGE(offset) \ 148 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 149 #define BM_PHY_REG_NUM(offset) \ 150 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 151 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 152 ~MAX_PHY_REG_ADDRESS))) 153 154 #define HV_INTC_FC_PAGE_START 768 155 #define I82578_ADDR_REG 29 156 #define I82577_ADDR_REG 16 157 #define I82577_CFG_REG 22 158 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 159 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 160 #define I82577_CTRL_REG 23 161 162 /* 82577 specific PHY registers */ 163 #define I82577_PHY_CTRL_2 18 164 #define I82577_PHY_LBK_CTRL 19 165 #define I82577_PHY_STATUS_2 26 166 #define I82577_PHY_DIAG_STATUS 31 167 168 /* I82577 PHY Status 2 */ 169 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 170 #define I82577_PHY_STATUS2_MDIX 0x0800 171 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 172 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 173 #define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100 174 175 /* I82577 PHY Control 2 */ 176 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 177 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 178 179 /* I82577 PHY Diagnostics Status */ 180 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 181 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 182 183 /* 82580 PHY Power Management */ 184 #define E1000_82580_PHY_POWER_MGMT 0xE14 185 #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */ 186 #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */ 187 #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */ 188 189 /* BM PHY Copper Specific Control 1 */ 190 #define BM_CS_CTRL1 16 191 #define BM_CS_CTRL1_ENERGY_DETECT 0x0300 /* Enable Energy Detect */ 192 193 /* BM PHY Copper Specific Status */ 194 #define BM_CS_STATUS 17 195 #define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */ 196 #define BM_CS_STATUS_LINK_UP 0x0400 197 #define BM_CS_STATUS_RESOLVED 0x0800 198 #define BM_CS_STATUS_SPEED_MASK 0xC000 199 #define BM_CS_STATUS_SPEED_1000 0x8000 200 201 /* 82577 Mobile Phy Status Register */ 202 #define HV_M_STATUS 26 203 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 204 #define HV_M_STATUS_SPEED_MASK 0x0300 205 #define HV_M_STATUS_SPEED_1000 0x0200 206 #define HV_M_STATUS_LINK_UP 0x0040 207 208 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 209 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 210 211 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 212 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 213 214 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 215 216 /* Enable flexible speed on link-up */ 217 #define IGP01E1000_GMII_FLEX_SPD 0x0010 218 #define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ 219 220 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 221 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 222 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 223 224 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 225 226 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 227 #define IGP01E1000_PSSR_MDIX 0x0800 228 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 229 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 230 231 #define IGP02E1000_PHY_CHANNEL_NUM 4 232 #define IGP02E1000_PHY_AGC_A 0x11B1 233 #define IGP02E1000_PHY_AGC_B 0x12B1 234 #define IGP02E1000_PHY_AGC_C 0x14B1 235 #define IGP02E1000_PHY_AGC_D 0x18B1 236 237 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ 238 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 239 #define IGP02E1000_AGC_RANGE 15 240 241 #define IGP03E1000_PHY_MISC_CTRL 0x1B 242 #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ 243 244 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 245 246 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 247 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 248 #define E1000_KMRNCTRLSTA_REN 0x00200000 249 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ 250 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 251 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 252 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 253 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 254 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 255 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 256 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 257 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ 258 259 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 260 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ 261 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ 262 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 263 264 /* IFE PHY Extended Status Control */ 265 #define IFE_PESC_POLARITY_REVERSED 0x0100 266 267 /* IFE PHY Special Control */ 268 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 269 #define IFE_PSC_FORCE_POLARITY 0x0020 270 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 271 272 /* IFE PHY Special Control and LED Control */ 273 #define IFE_PSCL_PROBE_MODE 0x0020 274 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 275 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 276 277 /* IFE PHY MDIX Control */ 278 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 279 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 280 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ 281 282 /* SFP modules ID memory locations */ 283 #define E1000_SFF_IDENTIFIER_OFFSET 0x00 284 #define E1000_SFF_IDENTIFIER_SFF 0x02 285 #define E1000_SFF_IDENTIFIER_SFP 0x03 286 287 #define E1000_SFF_ETH_FLAGS_OFFSET 0x06 288 /* Flags for SFP modules compatible with ETH up to 1Gb */ 289 struct sfp_e1000_flags { 290 u8 e1000_base_sx:1; 291 u8 e1000_base_lx:1; 292 u8 e1000_base_cx:1; 293 u8 e1000_base_t:1; 294 u8 e100_base_lx:1; 295 u8 e100_base_fx:1; 296 u8 e10_base_bx10:1; 297 u8 e10_base_px:1; 298 }; 299 300 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 301 #define E1000_SFF_VENDOR_OUI_TYCO 0x00407600 302 #define E1000_SFF_VENDOR_OUI_FTL 0x00906500 303 #define E1000_SFF_VENDOR_OUI_AVAGO 0x00176A00 304 #define E1000_SFF_VENDOR_OUI_INTEL 0x001B2100 305 306 #endif 307