1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_VF_H_ 36 #define _E1000_VF_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82576_VF 0x10CA 45 #define E1000_DEV_ID_I350_VF 0x1520 46 47 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 48 49 /* Additional Descriptor Control definitions */ 50 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 51 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ 52 53 /* SRRCTL bit definitions */ 54 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 55 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 56 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 57 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 58 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 59 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 60 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 61 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 62 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 63 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 64 #define E1000_SRRCTL_DROP_EN 0x80000000 65 66 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 67 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 68 69 /* Interrupt Defines */ 70 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 71 #define E1000_EITR(_n) (0x01680 + ((_n) << 2)) 72 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 73 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 74 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 75 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 76 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 77 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 78 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 79 #define E1000_IVAR_VALID 0x80 80 81 /* Receive Descriptor - Advanced */ 82 union e1000_adv_rx_desc { 83 struct { 84 u64 pkt_addr; /* Packet buffer address */ 85 u64 hdr_addr; /* Header buffer address */ 86 } read; 87 struct { 88 struct { 89 union { 90 u32 data; 91 struct { 92 /* RSS type, Packet type */ 93 u16 pkt_info; 94 /* Split Header, header buffer len */ 95 u16 hdr_info; 96 } hs_rss; 97 } lo_dword; 98 union { 99 u32 rss; /* RSS Hash */ 100 struct { 101 u16 ip_id; /* IP id */ 102 u16 csum; /* Packet Checksum */ 103 } csum_ip; 104 } hi_dword; 105 } lower; 106 struct { 107 u32 status_error; /* ext status/error */ 108 u16 length; /* Packet length */ 109 u16 vlan; /* VLAN tag */ 110 } upper; 111 } wb; /* writeback */ 112 }; 113 114 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 115 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 116 117 /* Transmit Descriptor - Advanced */ 118 union e1000_adv_tx_desc { 119 struct { 120 u64 buffer_addr; /* Address of descriptor's data buf */ 121 u32 cmd_type_len; 122 u32 olinfo_status; 123 } read; 124 struct { 125 u64 rsvd; /* Reserved */ 126 u32 nxtseq_seed; 127 u32 status; 128 } wb; 129 }; 130 131 /* Adv Transmit Descriptor Config Masks */ 132 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 133 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 134 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 135 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 136 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 137 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 138 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 139 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 140 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 141 142 /* Context descriptors */ 143 struct e1000_adv_tx_context_desc { 144 u32 vlan_macip_lens; 145 u32 seqnum_seed; 146 u32 type_tucmd_mlhl; 147 u32 mss_l4len_idx; 148 }; 149 150 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 151 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 152 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 153 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 154 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 155 156 enum e1000_mac_type { 157 e1000_undefined = 0, 158 e1000_vfadapt, 159 e1000_vfadapt_i350, 160 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 161 }; 162 163 struct e1000_vf_stats { 164 u64 base_gprc; 165 u64 base_gptc; 166 u64 base_gorc; 167 u64 base_gotc; 168 u64 base_mprc; 169 u64 base_gotlbc; 170 u64 base_gptlbc; 171 u64 base_gorlbc; 172 u64 base_gprlbc; 173 174 u32 last_gprc; 175 u32 last_gptc; 176 u32 last_gorc; 177 u32 last_gotc; 178 u32 last_mprc; 179 u32 last_gotlbc; 180 u32 last_gptlbc; 181 u32 last_gorlbc; 182 u32 last_gprlbc; 183 184 u64 gprc; 185 u64 gptc; 186 u64 gorc; 187 u64 gotc; 188 u64 mprc; 189 u64 gotlbc; 190 u64 gptlbc; 191 u64 gorlbc; 192 u64 gprlbc; 193 }; 194 195 #include "e1000_mbx.h" 196 197 struct e1000_mac_operations { 198 /* Function pointers for the MAC. */ 199 s32 (*init_params)(struct e1000_hw *); 200 s32 (*check_for_link)(struct e1000_hw *); 201 void (*clear_vfta)(struct e1000_hw *); 202 s32 (*get_bus_info)(struct e1000_hw *); 203 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 204 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 205 s32 (*reset_hw)(struct e1000_hw *); 206 s32 (*init_hw)(struct e1000_hw *); 207 s32 (*setup_link)(struct e1000_hw *); 208 void (*write_vfta)(struct e1000_hw *, u32, u32); 209 void (*rar_set)(struct e1000_hw *, u8*, u32); 210 s32 (*read_mac_addr)(struct e1000_hw *); 211 }; 212 213 struct e1000_mac_info { 214 struct e1000_mac_operations ops; 215 u8 addr[6]; 216 u8 perm_addr[6]; 217 218 enum e1000_mac_type type; 219 220 u16 mta_reg_count; 221 u16 rar_entry_count; 222 223 bool get_link_status; 224 }; 225 226 struct e1000_mbx_operations { 227 s32 (*init_params)(struct e1000_hw *hw); 228 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 229 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 230 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 231 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 232 s32 (*check_for_msg)(struct e1000_hw *, u16); 233 s32 (*check_for_ack)(struct e1000_hw *, u16); 234 s32 (*check_for_rst)(struct e1000_hw *, u16); 235 }; 236 237 struct e1000_mbx_stats { 238 u32 msgs_tx; 239 u32 msgs_rx; 240 241 u32 acks; 242 u32 reqs; 243 u32 rsts; 244 }; 245 246 struct e1000_mbx_info { 247 struct e1000_mbx_operations ops; 248 struct e1000_mbx_stats stats; 249 u32 timeout; 250 u32 usec_delay; 251 u16 size; 252 }; 253 254 struct e1000_dev_spec_vf { 255 u32 vf_number; 256 u32 v2p_mailbox; 257 }; 258 259 struct e1000_hw { 260 void *back; 261 262 u8 *hw_addr; 263 u8 *flash_address; 264 unsigned long io_base; 265 266 struct e1000_mac_info mac; 267 struct e1000_mbx_info mbx; 268 269 union { 270 struct e1000_dev_spec_vf vf; 271 } dev_spec; 272 273 u16 device_id; 274 u16 subsystem_vendor_id; 275 u16 subsystem_device_id; 276 u16 vendor_id; 277 278 u8 revision_id; 279 }; 280 281 enum e1000_promisc_type { 282 e1000_promisc_disabled = 0, /* all promisc modes disabled */ 283 e1000_promisc_unicast = 1, /* unicast promiscuous enabled */ 284 e1000_promisc_multicast = 2, /* multicast promiscuous enabled */ 285 e1000_promisc_enabled = 3, /* both uni and multicast promisc */ 286 e1000_num_promisc_types 287 }; 288 289 /* These functions must be implemented by drivers */ 290 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 291 void e1000_vfta_set_vf(struct e1000_hw *, u16, bool); 292 void e1000_rlpml_set_vf(struct e1000_hw *, u16); 293 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type); 294 #endif /* _E1000_VF_H_ */ 295