1 /* 2 * Copyright (c) 2001-2011, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_IGB_H_ 33 #define _IF_IGB_H_ 34 35 /* Tunables */ 36 37 /* 38 * Max ring count 39 */ 40 #define IGB_MAX_RING_I210 4 41 #define IGB_MAX_RING_I211 2 42 #define IGB_MAX_RING_I350 8 43 #define IGB_MAX_RING_I354 8 44 #define IGB_MAX_RING_82580 8 45 #define IGB_MAX_RING_82576 16 46 #define IGB_MAX_RING_82575 4 47 #define IGB_MIN_RING 1 48 #define IGB_MIN_RING_RSS 2 49 50 /* 51 * Max TX/RX interrupt bits 52 */ 53 #define IGB_MAX_TXRXINT_I210 4 54 #define IGB_MAX_TXRXINT_I211 4 55 #define IGB_MAX_TXRXINT_I350 8 56 #define IGB_MAX_TXRXINT_I354 8 57 #define IGB_MAX_TXRXINT_82580 8 58 #define IGB_MAX_TXRXINT_82576 16 59 #define IGB_MAX_TXRXINT_82575 4 /* XXX not used */ 60 #define IGB_MIN_TXRXINT 2 /* XXX VF? */ 61 62 /* 63 * Max IVAR count 64 */ 65 #define IGB_MAX_IVAR_I210 4 66 #define IGB_MAX_IVAR_I211 4 67 #define IGB_MAX_IVAR_I350 4 68 #define IGB_MAX_IVAR_I354 4 69 #define IGB_MAX_IVAR_82580 4 70 #define IGB_MAX_IVAR_82576 8 71 #define IGB_MAX_IVAR_VF 1 72 73 /* 74 * Default number of segments received before writing to RX related registers 75 */ 76 #define IGB_DEF_RXWREG_NSEGS 32 77 78 /* 79 * Default number of segments sent before writing to TX related registers 80 */ 81 #define IGB_DEF_TXWREG_NSEGS 8 82 83 /* 84 * IGB_TXD: Maximum number of Transmit Descriptors 85 * 86 * This value is the number of transmit descriptors allocated by the driver. 87 * Increasing this value allows the driver to queue more transmits. Each 88 * descriptor is 16 bytes. 89 * Since TDLEN should be multiple of 128bytes, the number of transmit 90 * desscriptors should meet the following condition. 91 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 92 */ 93 #define IGB_MIN_TXD 256 94 #define IGB_DEFAULT_TXD 1024 95 #define IGB_MAX_TXD 4096 96 97 /* 98 * IGB_RXD: Maximum number of Transmit Descriptors 99 * 100 * This value is the number of receive descriptors allocated by the driver. 101 * Increasing this value allows the driver to buffer more incoming packets. 102 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 103 * descriptor. The maximum MTU size is 16110. 104 * Since TDLEN should be multiple of 128bytes, the number of transmit 105 * desscriptors should meet the following condition. 106 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 107 */ 108 #define IGB_MIN_RXD 256 109 #define IGB_DEFAULT_RXD 512 110 #define IGB_MAX_RXD 4096 111 112 /* 113 * This parameter controls when the driver calls the routine to reclaim 114 * transmit descriptors. Cleaning earlier seems a win. 115 */ 116 #define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2) 117 118 /* 119 * This parameter controls whether or not autonegotation is enabled. 120 * 0 - Disable autonegotiation 121 * 1 - Enable autonegotiation 122 */ 123 #define DO_AUTO_NEG 1 124 125 /* 126 * This parameter control whether or not the driver will wait for 127 * autonegotiation to complete. 128 * 1 - Wait for autonegotiation to complete 129 * 0 - Don't wait for autonegotiation to complete 130 */ 131 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 132 133 /* Tunables -- End */ 134 135 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 136 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 137 ADVERTISE_1000_FULL) 138 139 #define AUTO_ALL_MODES 0 140 141 /* PHY master/slave setting */ 142 #define IGB_MASTER_SLAVE e1000_ms_hw_default 143 144 /* 145 * Micellaneous constants 146 */ 147 #define IGB_VENDOR_ID 0x8086 148 149 #define IGB_JUMBO_PBA 0x00000028 150 #define IGB_DEFAULT_PBA 0x00000030 151 #define IGB_SMARTSPEED_DOWNSHIFT 3 152 #define IGB_SMARTSPEED_MAX 15 153 #define IGB_MAX_LOOP 10 154 155 #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) 156 #define IGB_RX_HTHRESH 8 157 #define IGB_RX_WTHRESH 1 158 159 #define IGB_TX_PTHRESH 8 160 #define IGB_TX_HTHRESH 1 161 #define IGB_TX_WTHRESH 16 162 163 #define MAX_NUM_MULTICAST_ADDRESSES 128 164 #define IGB_FC_PAUSE_TIME 0x0680 165 166 #define IGB_INTR_RATE 6000 167 #define IGB_MSIX_RX_RATE 6000 168 #define IGB_MSIX_TX_RATE 4000 169 170 /* 171 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 172 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 173 * also optimize cache line size effect. H/W supports up to cache line size 128. 174 */ 175 #define IGB_DBA_ALIGN 128 176 177 /* PCI Config defines */ 178 #define IGB_MSIX_BAR 3 179 #define IGB_MSIX_BAR_ALT 4 180 181 #define IGB_MAX_SCATTER 64 182 #define IGB_VFTA_SIZE 128 183 #define IGB_TSO_SIZE (IP_MAXPACKET + \ 184 sizeof(struct ether_vlan_header)) 185 #define IGB_HDR_BUF 128 186 #define IGB_PKTTYPE_MASK 0x0000FFF0 187 188 #define IGB_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 189 190 /* One for TX csum offloading desc, the other 2 are reserved */ 191 #define IGB_TX_RESERVED 3 192 193 /* Large enough for 64K TSO */ 194 #define IGB_TX_SPARE 33 195 196 #define IGB_TX_OACTIVE_MAX 64 197 198 #define IGB_NRSSRK 10 199 #define IGB_RSSRK_SIZE 4 200 #define IGB_RSSRK_VAL(key, i) (key[(i) * IGB_RSSRK_SIZE] | \ 201 key[(i) * IGB_RSSRK_SIZE + 1] << 8 | \ 202 key[(i) * IGB_RSSRK_SIZE + 2] << 16 | \ 203 key[(i) * IGB_RSSRK_SIZE + 3] << 24) 204 205 #define IGB_NRETA 32 206 #define IGB_RETA_SIZE 4 207 #define IGB_RETA_SHIFT 0 208 #define IGB_RETA_SHIFT_82575 6 209 210 #define IGB_EITR_INTVL_MASK 0x7ffc 211 #define IGB_EITR_INTVL_SHIFT 2 212 213 struct igb_softc; 214 215 /* 216 * Bus dma information structure 217 */ 218 struct igb_dma { 219 bus_addr_t dma_paddr; 220 void *dma_vaddr; 221 bus_dma_tag_t dma_tag; 222 bus_dmamap_t dma_map; 223 }; 224 225 /* 226 * Transmit ring: one per queue 227 */ 228 struct igb_tx_ring { 229 struct lwkt_serialize tx_serialize; 230 struct igb_softc *sc; 231 struct ifaltq_subque *ifsq; 232 uint32_t me; 233 uint32_t tx_flags; 234 #define IGB_TXFLAG_TSO_IPLEN0 0x1 235 #define IGB_TXFLAG_ENABLED 0x2 236 struct e1000_tx_desc *tx_base; 237 int num_tx_desc; 238 uint32_t next_avail_desc; 239 uint32_t next_to_clean; 240 uint32_t *tx_hdr; 241 int tx_avail; 242 struct igb_tx_buf *tx_buf; 243 bus_dma_tag_t tx_tag; 244 int tx_nsegs; 245 int spare_desc; 246 int oact_lo_desc; 247 int oact_hi_desc; 248 int intr_nsegs; 249 int wreg_nsegs; 250 int tx_intr_bit; 251 uint32_t tx_intr_mask; 252 struct ifsubq_watchdog tx_watchdog; 253 254 /* Soft stats */ 255 u_long tx_packets; 256 257 struct igb_dma txdma; 258 bus_dma_tag_t tx_hdr_dtag; 259 bus_dmamap_t tx_hdr_dmap; 260 bus_addr_t tx_hdr_paddr; 261 int tx_intr_cpuid; 262 } __cachealign; 263 264 /* 265 * Receive ring: one per queue 266 */ 267 struct igb_rx_ring { 268 struct lwkt_serialize rx_serialize; 269 struct igb_softc *sc; 270 uint32_t me; 271 union e1000_adv_rx_desc *rx_base; 272 boolean_t discard; 273 int num_rx_desc; 274 uint32_t next_to_check; 275 struct igb_rx_buf *rx_buf; 276 bus_dma_tag_t rx_tag; 277 bus_dmamap_t rx_sparemap; 278 int rx_intr_bit; 279 uint32_t rx_intr_mask; 280 281 /* 282 * First/last mbuf pointers, for 283 * collecting multisegment RX packets. 284 */ 285 struct mbuf *fmp; 286 struct mbuf *lmp; 287 int wreg_nsegs; 288 289 /* Soft stats */ 290 u_long rx_packets; 291 292 struct igb_dma rxdma; 293 } __cachealign; 294 295 struct igb_msix_data { 296 struct lwkt_serialize *msix_serialize; 297 struct lwkt_serialize msix_serialize0; 298 struct igb_softc *msix_sc; 299 uint32_t msix_mask; 300 struct igb_rx_ring *msix_rx; 301 struct igb_tx_ring *msix_tx; 302 303 driver_intr_t *msix_func; 304 void *msix_arg; 305 306 int msix_cpuid; 307 char msix_desc[32]; 308 int msix_rid; 309 struct resource *msix_res; 310 void *msix_handle; 311 u_int msix_vector; 312 int msix_rate; 313 char msix_rate_desc[32]; 314 } __cachealign; 315 316 struct igb_softc { 317 struct arpcom arpcom; 318 struct e1000_hw hw; 319 320 struct e1000_osdep osdep; 321 device_t dev; 322 uint32_t flags; 323 #define IGB_FLAG_SHARED_INTR 0x1 324 #define IGB_FLAG_HAS_MGMT 0x2 325 326 bus_dma_tag_t parent_tag; 327 328 int mem_rid; 329 struct resource *mem_res; 330 331 struct ifmedia media; 332 struct callout timer; 333 int timer_cpuid; 334 335 int intr_type; 336 int intr_rid; 337 struct resource *intr_res; 338 void *intr_tag; 339 340 int if_flags; 341 int max_frame_size; 342 int pause_frames; 343 uint16_t vf_ifp; /* a VF interface */ 344 345 /* Management and WOL features */ 346 int wol; 347 348 /* Info about the interface */ 349 uint8_t link_active; 350 uint16_t link_speed; 351 uint16_t link_duplex; 352 uint32_t smartspeed; 353 uint32_t dma_coalesce; 354 355 /* Multicast array pointer */ 356 uint8_t *mta; 357 358 int rx_npoll_off; 359 int tx_npoll_off; 360 int serialize_cnt; 361 struct lwkt_serialize **serializes; 362 struct lwkt_serialize main_serialize; 363 364 int intr_rate; 365 uint32_t intr_mask; 366 int sts_intr_bit; 367 uint32_t sts_intr_mask; 368 369 /* 370 * Transmit rings 371 */ 372 int tx_ring_cnt; 373 int tx_ring_msix; 374 int tx_ring_inuse; 375 struct igb_tx_ring *tx_rings; 376 377 /* 378 * Receive rings 379 */ 380 int rss_debug; 381 int rx_ring_cnt; 382 int rx_ring_msix; 383 int rx_ring_inuse; 384 struct igb_rx_ring *rx_rings; 385 386 /* Misc stats maintained by the driver */ 387 u_long dropped_pkts; 388 u_long mbuf_defrag_failed; 389 u_long no_tx_dma_setup; 390 u_long watchdog_events; 391 u_long rx_overruns; 392 u_long device_control; 393 u_long rx_control; 394 u_long int_mask; 395 u_long eint_mask; 396 u_long packet_buf_alloc_rx; 397 u_long packet_buf_alloc_tx; 398 399 void *stats; 400 401 int msix_mem_rid; 402 struct resource *msix_mem_res; 403 int msix_cnt; 404 struct igb_msix_data *msix_data; 405 }; 406 407 #define IGB_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1) 408 #define IGB_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1) 409 410 struct igb_tx_buf { 411 struct mbuf *m_head; 412 bus_dmamap_t map; /* bus_dma map for packet */ 413 }; 414 415 struct igb_rx_buf { 416 struct mbuf *m_head; 417 bus_dmamap_t map; /* bus_dma map for packet */ 418 bus_addr_t paddr; 419 }; 420 421 #define UPDATE_VF_REG(reg, last, cur) \ 422 { \ 423 uint32_t new = E1000_READ_REG(hw, reg); \ 424 if (new < last) \ 425 cur += 0x100000000LL; \ 426 last = new; \ 427 cur &= 0xFFFFFFFF00000000LL; \ 428 cur |= new; \ 429 } 430 431 #define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc) 432 #define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc) 433 434 #define IGB_I210_LINK_DELAY 1000 /* unit: ms */ 435 436 #endif /* _IF_IGB_H_ */ 437