1 /* 2 * Copyright (c) 2001-2011, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_IGB_H_ 33 #define _IF_IGB_H_ 34 35 /* Tunables */ 36 37 /* 38 * Max ring count 39 */ 40 #define IGB_MAX_RING_82575 4 41 #define IGB_MAX_RING_I350 8 42 #define IGB_MAX_RING_82580 8 43 #define IGB_MAX_RING_82576 16 44 #define IGB_MIN_RING 1 45 #define IGB_MIN_RING_RSS 2 46 47 /* 48 * Max TX/RX interrupt bits 49 */ 50 #define IGB_MAX_TXRXINT_82575 4 /* XXX not used */ 51 #define IGB_MAX_TXRXINT_I350 8 52 #define IGB_MAX_TXRXINT_82580 8 53 #define IGB_MAX_TXRXINT_82576 16 54 #define IGB_MIN_TXRXINT 2 /* XXX VF? */ 55 56 /* 57 * Max IVAR count 58 */ 59 #define IGB_MAX_IVAR_I350 4 60 #define IGB_MAX_IVAR_82580 4 61 #define IGB_MAX_IVAR_82576 8 62 #define IGB_MAX_IVAR_VF 1 63 64 /* 65 * IGB_TXD: Maximum number of Transmit Descriptors 66 * 67 * This value is the number of transmit descriptors allocated by the driver. 68 * Increasing this value allows the driver to queue more transmits. Each 69 * descriptor is 16 bytes. 70 * Since TDLEN should be multiple of 128bytes, the number of transmit 71 * desscriptors should meet the following condition. 72 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 73 */ 74 #define IGB_MIN_TXD 256 75 #define IGB_DEFAULT_TXD 1024 76 #define IGB_MAX_TXD 4096 77 78 /* 79 * IGB_RXD: Maximum number of Transmit Descriptors 80 * 81 * This value is the number of receive descriptors allocated by the driver. 82 * Increasing this value allows the driver to buffer more incoming packets. 83 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 84 * descriptor. The maximum MTU size is 16110. 85 * Since TDLEN should be multiple of 128bytes, the number of transmit 86 * desscriptors should meet the following condition. 87 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 88 */ 89 #define IGB_MIN_RXD 256 90 #define IGB_DEFAULT_RXD 1024 91 #define IGB_MAX_RXD 4096 92 93 /* 94 * This parameter controls when the driver calls the routine to reclaim 95 * transmit descriptors. Cleaning earlier seems a win. 96 */ 97 #define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2) 98 99 /* 100 * This parameter controls whether or not autonegotation is enabled. 101 * 0 - Disable autonegotiation 102 * 1 - Enable autonegotiation 103 */ 104 #define DO_AUTO_NEG 1 105 106 /* 107 * This parameter control whether or not the driver will wait for 108 * autonegotiation to complete. 109 * 1 - Wait for autonegotiation to complete 110 * 0 - Don't wait for autonegotiation to complete 111 */ 112 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 113 114 /* Tunables -- End */ 115 116 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 117 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 118 ADVERTISE_1000_FULL) 119 120 #define AUTO_ALL_MODES 0 121 122 /* PHY master/slave setting */ 123 #define IGB_MASTER_SLAVE e1000_ms_hw_default 124 125 /* 126 * Micellaneous constants 127 */ 128 #define IGB_VENDOR_ID 0x8086 129 130 #define IGB_JUMBO_PBA 0x00000028 131 #define IGB_DEFAULT_PBA 0x00000030 132 #define IGB_SMARTSPEED_DOWNSHIFT 3 133 #define IGB_SMARTSPEED_MAX 15 134 #define IGB_MAX_LOOP 10 135 136 #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) 137 #define IGB_RX_HTHRESH 8 138 #define IGB_RX_WTHRESH 1 139 140 #define IGB_TX_PTHRESH 8 141 #define IGB_TX_HTHRESH 1 142 #define IGB_TX_WTHRESH 16 143 144 #define MAX_NUM_MULTICAST_ADDRESSES 128 145 #define IGB_FC_PAUSE_TIME 0x0680 146 147 #define IGB_INTR_RATE 6000 148 #define IGB_MSIX_RX_RATE 6000 149 #define IGB_MSIX_TX_RATE 4000 150 151 /* 152 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 153 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 154 * also optimize cache line size effect. H/W supports up to cache line size 128. 155 */ 156 #define IGB_DBA_ALIGN 128 157 158 /* PCI Config defines */ 159 #define IGB_MSIX_BAR 3 160 161 #define IGB_MAX_SCATTER 64 162 #define IGB_VFTA_SIZE 128 163 #define IGB_TSO_SIZE (65535 + \ 164 sizeof(struct ether_vlan_header)) 165 #define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 166 #define IGB_HDR_BUF 128 167 #define IGB_PKTTYPE_MASK 0x0000FFF0 168 169 #define IGB_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 #define IGB_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */ 171 #define IGB_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \ 172 IGB_IPVHL_SIZE) 173 174 /* One for TX csum offloading desc, the other 2 are reserved */ 175 #define IGB_TX_RESERVED 3 176 177 /* Large enough for 64K TSO */ 178 #define IGB_TX_SPARE 32 179 180 #define IGB_TX_OACTIVE_MAX 64 181 182 /* main + 16x RX + 16x TX */ 183 #define IGB_NSERIALIZE 33 184 185 #define IGB_NRSSRK 10 186 #define IGB_RSSRK_SIZE 4 187 #define IGB_RSSRK_VAL(key, i) (key[(i) * IGB_RSSRK_SIZE] | \ 188 key[(i) * IGB_RSSRK_SIZE + 1] << 8 | \ 189 key[(i) * IGB_RSSRK_SIZE + 2] << 16 | \ 190 key[(i) * IGB_RSSRK_SIZE + 3] << 24) 191 192 #define IGB_NRETA 32 193 #define IGB_RETA_SIZE 4 194 #define IGB_RETA_SHIFT 0 195 #define IGB_RETA_SHIFT_82575 6 196 197 #define IGB_EITR_INTVL_MASK 0x7ffc 198 #define IGB_EITR_INTVL_SHIFT 2 199 200 struct igb_softc; 201 202 /* 203 * Bus dma information structure 204 */ 205 struct igb_dma { 206 bus_addr_t dma_paddr; 207 void *dma_vaddr; 208 bus_dma_tag_t dma_tag; 209 bus_dmamap_t dma_map; 210 }; 211 212 /* 213 * Transmit ring: one per queue 214 */ 215 struct igb_tx_ring { 216 struct lwkt_serialize tx_serialize; 217 struct igb_softc *sc; 218 uint32_t me; 219 struct igb_dma txdma; 220 bus_dma_tag_t tx_hdr_dtag; 221 bus_dmamap_t tx_hdr_dmap; 222 bus_addr_t tx_hdr_paddr; 223 struct e1000_tx_desc *tx_base; 224 int num_tx_desc; 225 uint32_t next_avail_desc; 226 uint32_t next_to_clean; 227 uint32_t *tx_hdr; 228 int tx_avail; 229 struct igb_tx_buf *tx_buf; 230 bus_dma_tag_t tx_tag; 231 int tx_nsegs; 232 int spare_desc; 233 int oact_lo_desc; 234 int oact_hi_desc; 235 int intr_nsegs; 236 int tx_intr_bit; 237 uint32_t tx_intr_mask; 238 239 u_long no_desc_avail; 240 u_long tx_packets; 241 242 u_long ctx_try_pullup; 243 u_long ctx_drop1; 244 u_long ctx_drop2; 245 u_long ctx_pullup1; 246 u_long ctx_pullup1_failed; 247 u_long ctx_pullup2; 248 u_long ctx_pullup2_failed; 249 }; 250 251 /* 252 * Receive ring: one per queue 253 */ 254 struct igb_rx_ring { 255 struct lwkt_serialize rx_serialize; 256 struct igb_softc *sc; 257 uint32_t me; 258 struct igb_dma rxdma; 259 union e1000_adv_rx_desc *rx_base; 260 boolean_t discard; 261 int num_rx_desc; 262 uint32_t next_to_check; 263 struct igb_rx_buf *rx_buf; 264 bus_dma_tag_t rx_tag; 265 bus_dmamap_t rx_sparemap; 266 int rx_intr_bit; 267 uint32_t rx_intr_mask; 268 269 /* 270 * First/last mbuf pointers, for 271 * collecting multisegment RX packets. 272 */ 273 struct mbuf *fmp; 274 struct mbuf *lmp; 275 276 /* Soft stats */ 277 u_long rx_packets; 278 }; 279 280 struct igb_msix_data { 281 struct lwkt_serialize *msix_serialize; 282 struct lwkt_serialize msix_serialize0; 283 struct igb_softc *msix_sc; 284 uint32_t msix_mask; 285 struct igb_rx_ring *msix_rx; 286 struct igb_tx_ring *msix_tx; 287 288 driver_intr_t *msix_func; 289 void *msix_arg; 290 291 int msix_cpuid; 292 char msix_desc[32]; 293 int msix_rid; 294 struct resource *msix_res; 295 void *msix_handle; 296 u_int msix_vector; 297 int msix_rate; 298 char msix_rate_desc[32]; 299 }; 300 301 struct igb_softc { 302 struct arpcom arpcom; 303 struct e1000_hw hw; 304 305 struct e1000_osdep osdep; 306 device_t dev; 307 uint32_t flags; 308 #define IGB_FLAG_SHARED_INTR 0x1 309 #define IGB_FLAG_HAS_MGMT 0x2 310 311 bus_dma_tag_t parent_tag; 312 313 int mem_rid; 314 struct resource *mem_res; 315 316 struct ifmedia media; 317 struct callout timer; 318 319 int intr_type; 320 int intr_rid; 321 struct resource *intr_res; 322 void *intr_tag; 323 324 int if_flags; 325 int max_frame_size; 326 int pause_frames; 327 uint16_t vf_ifp; /* a VF interface */ 328 329 /* Management and WOL features */ 330 int wol; 331 332 /* Info about the interface */ 333 uint8_t link_active; 334 uint16_t link_speed; 335 uint16_t link_duplex; 336 uint32_t smartspeed; 337 uint32_t dma_coalesce; 338 339 /* Multicast array pointer */ 340 uint8_t *mta; 341 342 int serialize_cnt; 343 int tx_serialize; 344 int rx_serialize; 345 struct lwkt_serialize *serializes[IGB_NSERIALIZE]; 346 struct lwkt_serialize main_serialize; 347 348 int intr_rate; 349 uint32_t intr_mask; 350 int sts_intr_bit; 351 uint32_t sts_intr_mask; 352 353 /* 354 * Transmit rings 355 */ 356 int tx_ring_cnt; 357 struct igb_tx_ring *tx_rings; 358 359 /* 360 * Receive rings 361 */ 362 int rss_debug; 363 int rx_ring_cnt; 364 int rx_ring_msix; 365 int rx_ring_inuse; 366 struct igb_rx_ring *rx_rings; 367 368 /* Misc stats maintained by the driver */ 369 u_long dropped_pkts; 370 u_long mbuf_defrag_failed; 371 u_long no_tx_dma_setup; 372 u_long watchdog_events; 373 u_long rx_overruns; 374 u_long device_control; 375 u_long rx_control; 376 u_long int_mask; 377 u_long eint_mask; 378 u_long packet_buf_alloc_rx; 379 u_long packet_buf_alloc_tx; 380 381 /* sysctl tree glue */ 382 struct sysctl_ctx_list sysctl_ctx; 383 struct sysctl_oid *sysctl_tree; 384 385 void *stats; 386 387 int msix_tx_cpuid; 388 int msix_mem_rid; 389 struct resource *msix_mem_res; 390 int msix_cnt; 391 struct igb_msix_data *msix_data; 392 }; 393 394 #define IGB_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1) 395 396 struct igb_tx_buf { 397 struct mbuf *m_head; 398 bus_dmamap_t map; /* bus_dma map for packet */ 399 }; 400 401 struct igb_rx_buf { 402 struct mbuf *m_head; 403 bus_dmamap_t map; /* bus_dma map for packet */ 404 bus_addr_t paddr; 405 }; 406 407 #define UPDATE_VF_REG(reg, last, cur) \ 408 { \ 409 uint32_t new = E1000_READ_REG(hw, reg); \ 410 if (new < last) \ 411 cur += 0x100000000LL; \ 412 last = new; \ 413 cur &= 0xFFFFFFFF00000000LL; \ 414 cur |= new; \ 415 } 416 417 #define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc) 418 #define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc) 419 420 #endif /* _IF_IGB_H_ */ 421