1 /* 2 * Copyright (c) 2001-2011, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_IGB_H_ 33 #define _IF_IGB_H_ 34 35 /* Tunables */ 36 37 /* 38 * Max ring count 39 */ 40 #define IGB_MAX_RING_I210 4 41 #define IGB_MAX_RING_I211 2 42 #define IGB_MAX_RING_I350 8 43 #define IGB_MAX_RING_82580 8 44 #define IGB_MAX_RING_82576 16 45 #define IGB_MAX_RING_82575 4 46 #define IGB_MIN_RING 1 47 #define IGB_MIN_RING_RSS 2 48 49 /* 50 * Max TX/RX interrupt bits 51 */ 52 #define IGB_MAX_TXRXINT_I210 4 53 #define IGB_MAX_TXRXINT_I211 4 54 #define IGB_MAX_TXRXINT_I350 8 55 #define IGB_MAX_TXRXINT_82580 8 56 #define IGB_MAX_TXRXINT_82576 16 57 #define IGB_MAX_TXRXINT_82575 4 /* XXX not used */ 58 #define IGB_MIN_TXRXINT 2 /* XXX VF? */ 59 60 /* 61 * Max IVAR count 62 */ 63 #define IGB_MAX_IVAR_I210 4 64 #define IGB_MAX_IVAR_I211 4 65 #define IGB_MAX_IVAR_I350 4 66 #define IGB_MAX_IVAR_82580 4 67 #define IGB_MAX_IVAR_82576 8 68 #define IGB_MAX_IVAR_VF 1 69 70 /* 71 * Default number of segments received before writing to RX related registers 72 */ 73 #define IGB_DEF_RXWREG_NSEGS 32 74 75 /* 76 * Default number of segments sent before writing to TX related registers 77 */ 78 #define IGB_DEF_TXWREG_NSEGS 8 79 80 /* 81 * IGB_TXD: Maximum number of Transmit Descriptors 82 * 83 * This value is the number of transmit descriptors allocated by the driver. 84 * Increasing this value allows the driver to queue more transmits. Each 85 * descriptor is 16 bytes. 86 * Since TDLEN should be multiple of 128bytes, the number of transmit 87 * desscriptors should meet the following condition. 88 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 89 */ 90 #define IGB_MIN_TXD 256 91 #define IGB_DEFAULT_TXD 1024 92 #define IGB_MAX_TXD 4096 93 94 /* 95 * IGB_RXD: Maximum number of Transmit Descriptors 96 * 97 * This value is the number of receive descriptors allocated by the driver. 98 * Increasing this value allows the driver to buffer more incoming packets. 99 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 100 * descriptor. The maximum MTU size is 16110. 101 * Since TDLEN should be multiple of 128bytes, the number of transmit 102 * desscriptors should meet the following condition. 103 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 104 */ 105 #define IGB_MIN_RXD 256 106 #define IGB_DEFAULT_RXD 512 107 #define IGB_MAX_RXD 4096 108 109 /* 110 * This parameter controls when the driver calls the routine to reclaim 111 * transmit descriptors. Cleaning earlier seems a win. 112 */ 113 #define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2) 114 115 /* 116 * This parameter controls whether or not autonegotation is enabled. 117 * 0 - Disable autonegotiation 118 * 1 - Enable autonegotiation 119 */ 120 #define DO_AUTO_NEG 1 121 122 /* 123 * This parameter control whether or not the driver will wait for 124 * autonegotiation to complete. 125 * 1 - Wait for autonegotiation to complete 126 * 0 - Don't wait for autonegotiation to complete 127 */ 128 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 129 130 /* Tunables -- End */ 131 132 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 133 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 134 ADVERTISE_1000_FULL) 135 136 #define AUTO_ALL_MODES 0 137 138 /* PHY master/slave setting */ 139 #define IGB_MASTER_SLAVE e1000_ms_hw_default 140 141 /* 142 * Micellaneous constants 143 */ 144 #define IGB_VENDOR_ID 0x8086 145 146 #define IGB_JUMBO_PBA 0x00000028 147 #define IGB_DEFAULT_PBA 0x00000030 148 #define IGB_SMARTSPEED_DOWNSHIFT 3 149 #define IGB_SMARTSPEED_MAX 15 150 #define IGB_MAX_LOOP 10 151 152 #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) 153 #define IGB_RX_HTHRESH 8 154 #define IGB_RX_WTHRESH 1 155 156 #define IGB_TX_PTHRESH 8 157 #define IGB_TX_HTHRESH 1 158 #define IGB_TX_WTHRESH 16 159 160 #define MAX_NUM_MULTICAST_ADDRESSES 128 161 #define IGB_FC_PAUSE_TIME 0x0680 162 163 #define IGB_INTR_RATE 6000 164 #define IGB_MSIX_RX_RATE 6000 165 #define IGB_MSIX_TX_RATE 4000 166 167 /* 168 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 169 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 170 * also optimize cache line size effect. H/W supports up to cache line size 128. 171 */ 172 #define IGB_DBA_ALIGN 128 173 174 /* PCI Config defines */ 175 #define IGB_MSIX_BAR 3 176 177 #define IGB_MAX_SCATTER 64 178 #define IGB_VFTA_SIZE 128 179 #define IGB_TSO_SIZE (IP_MAXPACKET + \ 180 sizeof(struct ether_vlan_header)) 181 #define IGB_HDR_BUF 128 182 #define IGB_PKTTYPE_MASK 0x0000FFF0 183 184 #define IGB_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 185 186 /* One for TX csum offloading desc, the other 2 are reserved */ 187 #define IGB_TX_RESERVED 3 188 189 /* Large enough for 64K TSO */ 190 #define IGB_TX_SPARE 33 191 192 #define IGB_TX_OACTIVE_MAX 64 193 194 #define IGB_NRSSRK 10 195 #define IGB_RSSRK_SIZE 4 196 #define IGB_RSSRK_VAL(key, i) (key[(i) * IGB_RSSRK_SIZE] | \ 197 key[(i) * IGB_RSSRK_SIZE + 1] << 8 | \ 198 key[(i) * IGB_RSSRK_SIZE + 2] << 16 | \ 199 key[(i) * IGB_RSSRK_SIZE + 3] << 24) 200 201 #define IGB_NRETA 32 202 #define IGB_RETA_SIZE 4 203 #define IGB_RETA_SHIFT 0 204 #define IGB_RETA_SHIFT_82575 6 205 206 #define IGB_EITR_INTVL_MASK 0x7ffc 207 #define IGB_EITR_INTVL_SHIFT 2 208 209 struct igb_softc; 210 211 /* 212 * Bus dma information structure 213 */ 214 struct igb_dma { 215 bus_addr_t dma_paddr; 216 void *dma_vaddr; 217 bus_dma_tag_t dma_tag; 218 bus_dmamap_t dma_map; 219 }; 220 221 /* 222 * Transmit ring: one per queue 223 */ 224 struct igb_tx_ring { 225 struct lwkt_serialize tx_serialize; 226 struct igb_softc *sc; 227 struct ifaltq_subque *ifsq; 228 uint32_t me; 229 uint32_t tx_flags; 230 #define IGB_TXFLAG_TSO_IPLEN0 0x1 231 #define IGB_TXFLAG_ENABLED 0x2 232 struct e1000_tx_desc *tx_base; 233 int num_tx_desc; 234 uint32_t next_avail_desc; 235 uint32_t next_to_clean; 236 uint32_t *tx_hdr; 237 int tx_avail; 238 struct igb_tx_buf *tx_buf; 239 bus_dma_tag_t tx_tag; 240 int tx_nsegs; 241 int spare_desc; 242 int oact_lo_desc; 243 int oact_hi_desc; 244 int intr_nsegs; 245 int wreg_nsegs; 246 int tx_intr_bit; 247 uint32_t tx_intr_mask; 248 struct ifsubq_watchdog tx_watchdog; 249 250 /* Soft stats */ 251 u_long tx_packets; 252 253 struct igb_dma txdma; 254 bus_dma_tag_t tx_hdr_dtag; 255 bus_dmamap_t tx_hdr_dmap; 256 bus_addr_t tx_hdr_paddr; 257 int tx_intr_cpuid; 258 } __cachealign; 259 260 /* 261 * Receive ring: one per queue 262 */ 263 struct igb_rx_ring { 264 struct lwkt_serialize rx_serialize; 265 struct igb_softc *sc; 266 uint32_t me; 267 union e1000_adv_rx_desc *rx_base; 268 boolean_t discard; 269 int num_rx_desc; 270 uint32_t next_to_check; 271 struct igb_rx_buf *rx_buf; 272 bus_dma_tag_t rx_tag; 273 bus_dmamap_t rx_sparemap; 274 int rx_intr_bit; 275 uint32_t rx_intr_mask; 276 277 /* 278 * First/last mbuf pointers, for 279 * collecting multisegment RX packets. 280 */ 281 struct mbuf *fmp; 282 struct mbuf *lmp; 283 int wreg_nsegs; 284 285 /* Soft stats */ 286 u_long rx_packets; 287 288 struct igb_dma rxdma; 289 } __cachealign; 290 291 struct igb_msix_data { 292 struct lwkt_serialize *msix_serialize; 293 struct lwkt_serialize msix_serialize0; 294 struct igb_softc *msix_sc; 295 uint32_t msix_mask; 296 struct igb_rx_ring *msix_rx; 297 struct igb_tx_ring *msix_tx; 298 299 driver_intr_t *msix_func; 300 void *msix_arg; 301 302 int msix_cpuid; 303 char msix_desc[32]; 304 int msix_rid; 305 struct resource *msix_res; 306 void *msix_handle; 307 u_int msix_vector; 308 int msix_rate; 309 char msix_rate_desc[32]; 310 } __cachealign; 311 312 struct igb_softc { 313 struct arpcom arpcom; 314 struct e1000_hw hw; 315 316 struct e1000_osdep osdep; 317 device_t dev; 318 uint32_t flags; 319 #define IGB_FLAG_SHARED_INTR 0x1 320 #define IGB_FLAG_HAS_MGMT 0x2 321 322 bus_dma_tag_t parent_tag; 323 324 int mem_rid; 325 struct resource *mem_res; 326 327 struct ifmedia media; 328 struct callout timer; 329 int timer_cpuid; 330 331 int intr_type; 332 int intr_rid; 333 struct resource *intr_res; 334 void *intr_tag; 335 336 int if_flags; 337 int max_frame_size; 338 int pause_frames; 339 uint16_t vf_ifp; /* a VF interface */ 340 341 /* Management and WOL features */ 342 int wol; 343 344 /* Info about the interface */ 345 uint8_t link_active; 346 uint16_t link_speed; 347 uint16_t link_duplex; 348 uint32_t smartspeed; 349 uint32_t dma_coalesce; 350 351 /* Multicast array pointer */ 352 uint8_t *mta; 353 354 int rx_npoll_off; 355 int tx_npoll_off; 356 int serialize_cnt; 357 struct lwkt_serialize **serializes; 358 struct lwkt_serialize main_serialize; 359 360 int intr_rate; 361 uint32_t intr_mask; 362 int sts_intr_bit; 363 uint32_t sts_intr_mask; 364 365 /* 366 * Transmit rings 367 */ 368 int tx_ring_cnt; 369 int tx_ring_msix; 370 int tx_ring_inuse; 371 struct igb_tx_ring *tx_rings; 372 373 /* 374 * Receive rings 375 */ 376 int rss_debug; 377 int rx_ring_cnt; 378 int rx_ring_msix; 379 int rx_ring_inuse; 380 struct igb_rx_ring *rx_rings; 381 382 /* Misc stats maintained by the driver */ 383 u_long dropped_pkts; 384 u_long mbuf_defrag_failed; 385 u_long no_tx_dma_setup; 386 u_long watchdog_events; 387 u_long rx_overruns; 388 u_long device_control; 389 u_long rx_control; 390 u_long int_mask; 391 u_long eint_mask; 392 u_long packet_buf_alloc_rx; 393 u_long packet_buf_alloc_tx; 394 395 /* sysctl tree glue */ 396 struct sysctl_ctx_list sysctl_ctx; 397 struct sysctl_oid *sysctl_tree; 398 399 void *stats; 400 401 int msix_mem_rid; 402 struct resource *msix_mem_res; 403 int msix_cnt; 404 struct igb_msix_data *msix_data; 405 }; 406 407 #define IGB_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1) 408 #define IGB_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1) 409 410 struct igb_tx_buf { 411 struct mbuf *m_head; 412 bus_dmamap_t map; /* bus_dma map for packet */ 413 }; 414 415 struct igb_rx_buf { 416 struct mbuf *m_head; 417 bus_dmamap_t map; /* bus_dma map for packet */ 418 bus_addr_t paddr; 419 }; 420 421 #define UPDATE_VF_REG(reg, last, cur) \ 422 { \ 423 uint32_t new = E1000_READ_REG(hw, reg); \ 424 if (new < last) \ 425 cur += 0x100000000LL; \ 426 last = new; \ 427 cur &= 0xFFFFFFFF00000000LL; \ 428 cur |= new; \ 429 } 430 431 #define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc) 432 #define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc) 433 434 #endif /* _IF_IGB_H_ */ 435