1 /* 2 * Copyright (c) 2004, 2005 3 * Damien Bergamini <damien.bergamini@free.fr>. 4 * Copyright (c) 2004, 2005 5 * Andrew Atrens <atrens@nortelnetworks.com>. 6 * 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $DragonFly: src/sys/dev/netif/iwi/if_iwireg.h,v 1.1 2005/03/06 05:02:02 dillon Exp $ 32 */ 33 34 #define IWI_TX_RING_SIZE 64 35 #define IWI_CMD_RING_SIZE 16 36 #define IWI_RX_RING_SIZE 32 37 38 #define IWI_CSR_INTR 0x0008 39 #define IWI_CSR_INTR_MASK 0x000c 40 #define IWI_CSR_INDIRECT_ADDR 0x0010 41 #define IWI_CSR_INDIRECT_DATA 0x0014 42 #define IWI_CSR_AUTOINC_ADDR 0x0018 43 #define IWI_CSR_AUTOINC_DATA 0x001c 44 #define IWI_CSR_RST 0x0020 45 #define IWI_CSR_CTL 0x0024 46 #define IWI_CSR_IO 0x0030 47 #define IWI_CSR_CMD_BASE 0x0200 48 #define IWI_CSR_CMD_SIZE 0x0204 49 #define IWI_CSR_TX1_BASE 0x0208 50 #define IWI_CSR_TX1_SIZE 0x020c 51 #define IWI_CSR_TX2_BASE 0x0210 52 #define IWI_CSR_TX2_SIZE 0x0214 53 #define IWI_CSR_TX3_BASE 0x0218 54 #define IWI_CSR_TX3_SIZE 0x021c 55 #define IWI_CSR_TX4_BASE 0x0220 56 #define IWI_CSR_TX4_SIZE 0x0224 57 #define IWI_CSR_CMD_READ_INDEX 0x0280 58 #define IWI_CSR_TX1_READ_INDEX 0x0284 59 #define IWI_CSR_TX2_READ_INDEX 0x0288 60 #define IWI_CSR_TX3_READ_INDEX 0x028c 61 #define IWI_CSR_TX4_READ_INDEX 0x0290 62 #define IWI_CSR_RX_READ_INDEX 0x02a0 63 #define IWI_CSR_RX_BASE 0x0500 64 #define IWI_CSR_TABLE0_SIZE 0x0700 65 #define IWI_CSR_TABLE0_BASE 0x0704 66 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE 67 68 #define IWI_CSR_GET_TABLE0_BASE 0x0380 69 #define IWI_CSR_GET_TABLE1_BASE 0x0384 70 #define IWI_CSR_GET_TABLE2_BASE 0x0388 71 #define IWI_CSR_GET_TABLE3_BASE 0x038C 72 73 #define IWI_CSR_CMD_WRITE_INDEX 0x0f80 74 #define IWI_CSR_TX1_WRITE_INDEX 0x0f84 75 #define IWI_CSR_TX2_WRITE_INDEX 0x0f88 76 #define IWI_CSR_TX3_WRITE_INDEX 0x0f8c 77 #define IWI_CSR_TX4_WRITE_INDEX 0x0f90 78 #define IWI_CSR_RX_WRITE_INDEX 0x0fa0 79 #define IWI_CSR_READ_INT 0x0ff4 80 81 #define IWI_STATION_TABLE 0x0c0c 82 83 #define IWI_FW_ERROR_LOG 0x0610 84 #define IWI_FW_EVENT_LOG 0x0614 85 86 87 /* possible flags for IWI_CSR_INTR */ 88 #define IWI_INTR_RX_TRANSFER 0x00000002 89 #define IWI_INTR_STATUS_CHG 0x00000010 90 #define IWI_INTR_BEACON_EXP 0x00000020 91 #define IWI_INTR_CMD_TRANSFER 0x00000800 92 #define IWI_INTR_TX1_TRANSFER 0x00001000 93 #define IWI_INTR_TX2_TRANSFER 0x00002000 94 #define IWI_INTR_TX3_TRANSFER 0x00004000 95 #define IWI_INTR_TX4_TRANSFER 0x00008000 96 #define IWI_INTR_SLMODE_CDONE 0x00010000 97 #define IWI_INTR_PREP_PWDOWN 0x00100000 98 #define IWI_INTR_PWDOWN 0x00200000 99 #define IWI_INTR_FW_INITED 0x01000000 100 #define IWI_INTR_DIS_PHY_DONE 0x02000000 101 #define IWI_INTR_RADIO_OFF 0x04000000 102 #define IWI_INTR_FATAL_ERROR 0x40000000 103 #define IWI_INTR_PARITY_ERROR 0x80000000 104 105 #define IWI_HANDLED_INTR_MASK \ 106 (IWI_INTR_RX_TRANSFER | IWI_INTR_CMD_TRANSFER | \ 107 IWI_INTR_TX1_TRANSFER | IWI_INTR_TX2_TRANSFER | \ 108 IWI_INTR_TX3_TRANSFER | IWI_INTR_TX4_TRANSFER | \ 109 IWI_INTR_FW_INITED | IWI_INTR_FATAL_ERROR | \ 110 IWI_INTR_RADIO_OFF | IWI_INTR_PARITY_ERROR) 111 112 #define IWI_INTR_MASK \ 113 (IWI_INTR_RX_TRANSFER | IWI_INTR_CMD_TRANSFER | \ 114 IWI_INTR_TX1_TRANSFER | IWI_INTR_TX2_TRANSFER | \ 115 IWI_INTR_TX3_TRANSFER | IWI_INTR_TX4_TRANSFER | \ 116 IWI_INTR_FW_INITED | IWI_INTR_FATAL_ERROR | \ 117 IWI_INTR_PARITY_ERROR | IWI_INTR_STATUS_CHG | \ 118 IWI_INTR_BEACON_EXP | IWI_INTR_SLMODE_CDONE | \ 119 IWI_INTR_PREP_PWDOWN | IWI_INTR_PWDOWN | \ 120 IWI_INTR_DIS_PHY_DONE | IWI_INTR_RADIO_OFF) 121 122 /* possible flags for register IWI_CSR_RST */ 123 #define IWI_RST_PRINCETON_RESET 0x00000001 124 #define IWI_RST_SW_RESET 0x00000080 125 #define IWI_RST_MASTER_DISABLED 0x00000100 126 #define IWI_RST_STOP_MASTER 0x00000200 127 128 /* possible flags for register IWI_CSR_CTL */ 129 #define IWI_CTL_CLOCK_READY 0x00000001 130 #define IWI_CTL_ALLOW_STANDBY 0x00000002 131 #define IWI_CTL_INIT 0x00000004 132 133 /* possible flags for register IWI_CSR_IO */ 134 #define IWI_IO_RADIO_ENABLED 0x00010000 135 136 /* possible flags for IWI_CSR_READ_INT */ 137 #define IWI_READ_INT_INIT_HOST 0x20000000 138 139 /* table2 offsets */ 140 #define IWI_INFO_ADAPTER_MAC 40 141 142 /* constants for command blocks */ 143 #define IWI_CB_DEFAULT_CTL 0x8cea0000 144 #define IWI_CB_MAXDATALEN 8191 145 146 /* supported rates */ 147 #define IWI_RATE_DS1 10 148 #define IWI_RATE_DS2 20 149 #define IWI_RATE_DS5 55 150 #define IWI_RATE_DS11 110 151 #define IWI_RATE_OFDM6 13 152 #define IWI_RATE_OFDM9 15 153 #define IWI_RATE_OFDM12 5 154 #define IWI_RATE_OFDM18 7 155 #define IWI_RATE_OFDM24 9 156 #define IWI_RATE_OFDM36 11 157 #define IWI_RATE_OFDM48 1 158 #define IWI_RATE_OFDM54 3 159 160 struct iwi_hdr { 161 u_int8_t type; 162 #define IWI_HDR_TYPE_DATA 0 163 #define IWI_HDR_TYPE_COMMAND 1 164 #define IWI_HDR_TYPE_NOTIF 3 165 #define IWI_HDR_TYPE_FRAME 9 166 u_int8_t seq; 167 u_int8_t flags; 168 #define IWI_HDR_FLAG_IRQ 0x04 169 u_int8_t reserved; 170 } __packed; 171 172 struct iwi_notif { 173 u_int32_t reserved[2]; 174 u_int8_t type; 175 #define IWI_NOTIF_TYPE_ASSOCIATION 10 176 #define IWI_NOTIF_TYPE_AUTHENTICATION 11 177 #define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 178 #define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 179 #define IWI_NOTIF_TYPE_BEACON 17 180 #define IWI_NOTIF_TYPE_CALIBRATION 20 181 #define IWI_NOTIF_TYPE_NOISE 25 182 u_int8_t flags; 183 u_int16_t len; 184 } __packed; 185 186 /* structure for notification IWI_NOTIF_TYPE_NOISE */ 187 struct iwi_notif_noise { 188 u_int32_t value; 189 } __packed; 190 191 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ 192 struct iwi_notif_authentication { 193 u_int8_t state; 194 #define IWI_DEAUTHENTICATED 0 195 #define IWI_AUTHENTICATED 9 196 } __packed; 197 198 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ 199 struct iwi_notif_association { 200 u_int8_t state; 201 #define IWI_DEASSOCIATED 0 202 #define IWI_ASSOCIATED 12 203 struct ieee80211_frame frame; 204 u_int16_t capinfo; 205 u_int16_t status; 206 u_int16_t associd; 207 } __packed; 208 209 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ 210 struct iwi_notif_scan_channel { 211 u_int8_t nchan; 212 u_int8_t reserved[47]; 213 } __packed; 214 215 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ 216 struct iwi_notif_scan_complete { 217 u_int8_t type; 218 u_int8_t nchan; 219 u_int8_t status; 220 u_int8_t reserved; 221 } __packed; 222 223 /* received frame header */ 224 struct iwi_frame { 225 u_int32_t reserved1; 226 u_int8_t parent_tsf[4]; 227 u_int8_t chan; 228 u_int8_t status; 229 u_int8_t rate; 230 u_int8_t rssi; /* receiver signal strength indicator */ 231 u_int8_t agc; /* automatic gain control */ 232 u_int8_t rssi_dbm; 233 u_int16_t signal; 234 u_int16_t noise; 235 u_int8_t antenna; 236 u_int8_t control; 237 u_int8_t rtscts_rate; 238 u_int8_t rtscts_seen; 239 u_int16_t len; 240 } __packed; 241 242 /* header for transmission */ 243 struct iwi_tx_desc { 244 struct iwi_hdr hdr; 245 u_int32_t work_area_ptr; 246 u_int8_t station_number; /* 0 for BSS */ 247 u_int8_t reserved1[3]; 248 u_int8_t cmd; 249 #define IWI_DATA_CMD_TX 0x0b 250 u_int8_t seq; 251 u_int16_t len; 252 u_int8_t priority; 253 u_int8_t flags; 254 #define IWI_DATA_FLAG_SHPREAMBLE 0x04 255 #define IWI_DATA_FLAG_NO_WEP 0x20 256 #define IWI_DATA_FLAG_NEED_ACK 0x80 257 u_int8_t xflags; 258 u_int8_t wep_txkey; 259 u_int8_t wepkey[IEEE80211_KEYBUF_SIZE]; 260 u_int8_t rate; 261 u_int8_t antenna; 262 u_int8_t reserved2[10]; 263 264 struct ieee80211_qosframe_addr4 wh; 265 u_int32_t iv[2]; 266 267 u_int32_t nseg; 268 #define IWI_MAX_NSEG 6 269 u_int32_t seg_addr[IWI_MAX_NSEG]; 270 u_int16_t seg_len[IWI_MAX_NSEG]; 271 } __packed; 272 273 /* command */ 274 struct iwi_cmd_desc { 275 struct iwi_hdr hdr; 276 u_int8_t type; 277 #define IWI_CMD_ENABLE 2 278 #define IWI_CMD_SET_CONFIGURATION 6 279 #define IWI_CMD_SET_ESSID 8 280 #define IWI_CMD_SET_MAC_ADDRESS 11 281 #define IWI_CMD_SET_RTS_THRESHOLD 15 282 #define IWI_CMD_SET_POWER_MODE 17 283 #define IWI_CMD_SET_WEP_KEY 18 284 #define IWI_CMD_SCAN 20 285 #define IWI_CMD_ASSOCIATE 21 286 #define IWI_CMD_SET_RATES 22 287 #define IWI_CMD_SCAN_ABORT 23 288 #define IWI_CMD_DISABLE 33 289 #define IWI_CMD_SET_IV 34 290 #define IWI_CMD_SET_TX_POWER 35 291 #define IWI_CMD_SET_SENSITIVITY 42 292 u_int8_t len; 293 u_int16_t reserved; 294 u_int8_t data[120]; 295 } __packed; 296 297 /* constants for 'mode' fields */ 298 #define IWI_MODE_11A 0 299 #define IWI_MODE_11B 1 300 #define IWI_MODE_11G 2 301 302 /* macro for command IWI_CMD_SET_SENSITIVITY */ 303 #define IWI_RSSIDBM2RAW(rssi) ((rssi) - 112) 304 305 /* possible values for command IWI_CMD_SET_POWER_MODE */ 306 #define IWI_POWER_MODE_CAM 0 307 308 /* structure for command IWI_CMD_SET_RATES */ 309 struct iwi_rateset { 310 u_int8_t mode; 311 u_int8_t nrates; 312 u_int8_t type; 313 #define IWI_RATESET_TYPE_NEGOTIATED 0 314 #define IWI_RATESET_TYPE_SUPPORTED 1 315 u_int8_t reserved; 316 u_int8_t rates[12]; 317 } __packed; 318 319 /* structure for command IWI_CMD_SET_TX_POWER */ 320 struct iwi_txpower { 321 u_int8_t nchan; 322 u_int8_t mode; 323 struct { 324 u_int8_t chan; 325 u_int8_t power; 326 #define IWI_TXPOWER_MAX 20 327 #define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) 328 } __packed chan[37]; 329 } __packed; 330 331 /* structure for command IWI_CMD_ASSOCIATE */ 332 struct iwi_associate { 333 u_int8_t chan; 334 u_int8_t auth; 335 #define IWI_AUTH_OPEN 0 336 #define IWI_AUTH_SHARED 1 337 #define IWI_AUTH_NONE 3 338 u_int8_t type; 339 u_int8_t reserved; 340 u_int16_t policy_support; 341 u_int8_t plen; 342 u_int8_t mode; 343 u_int8_t bssid[IEEE80211_ADDR_LEN]; 344 u_int8_t tstamp[8]; 345 u_int16_t capinfo; 346 u_int16_t lintval; 347 u_int16_t intval; 348 u_int8_t dst[IEEE80211_ADDR_LEN]; 349 u_int16_t atim_window; 350 u_int8_t smr; 351 u_int8_t reserved1; 352 u_int16_t reserved2; 353 } __packed; 354 355 /* structure for command IWI_CMD_SCAN */ 356 struct iwi_scan { 357 u_int8_t type; 358 #define IWI_SCAN_PASSIVE_TILL_FIRST_BEACON 0 359 #define IWI_SCAN_PASSIVE_FULL_DWELL 1 360 #define IWI_SCAN_TYPE_DIRECT 2 361 #define IWI_SCAN_TYPE_BROADCAST 3 362 #define IWI_SCAN_TYPE_BROADCAST_AND_DIRECT 4 363 u_int16_t intval; 364 u_int8_t channels[54]; 365 #define IWI_CHAN_5GHZ (0 << 6) 366 #define IWI_CHAN_2GHZ (1 << 6) 367 u_int8_t reserved[3]; 368 } __packed; 369 370 /* structure for command IWI_CMD_SET_CONFIGURATION */ 371 struct iwi_configuration { 372 u_int8_t bluetooth_coexistence; 373 u_int8_t reserved1; 374 u_int8_t answer_broadcast_probe_req; 375 u_int8_t allow_invalid_frames; 376 u_int8_t enable_multicast; 377 u_int8_t exclude_unicast_unencrypted; 378 u_int8_t disable_unicast_decryption; 379 u_int8_t exclude_multicast_unencrypted; 380 u_int8_t disable_multicast_decryption; 381 u_int8_t antenna_diversity; 382 u_int8_t pass_crc_to_host; 383 u_int8_t bg_autodetect; 384 u_int8_t enable_cts_to_self; 385 u_int8_t enable_multicast_filtering; 386 u_int8_t bluetooth_threshold; 387 u_int8_t reserved2; 388 u_int8_t allow_beacon_and_probe_resp; 389 u_int8_t allow_mgt; 390 u_int8_t noise_reported; 391 u_int8_t reserved3; 392 } __packed; 393 394 /* structure for command IWI_CMD_SET_WEP_KEY */ 395 struct iwi_wep_key { 396 u_int8_t cmd; 397 #define IWI_WEP_KEY_CMD_SETKEY 0x08 398 u_int8_t seq; 399 u_int8_t idx; 400 u_int8_t len; 401 u_int8_t key[IEEE80211_KEYBUF_SIZE]; 402 } __packed; 403 404 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */ 405 406 #define IWI_MEM_EEPROM_CTL 0x00300040 407 408 #define IWI_EEPROM_MAC 0x21 409 410 #define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 411 412 #define IWI_EEPROM_C (1 << 0) /* Serial Clock */ 413 #define IWI_EEPROM_S (1 << 1) /* Chip Select */ 414 #define IWI_EEPROM_D (1 << 2) /* Serial data input */ 415 #define IWI_EEPROM_Q (1 << 4) /* Serial data output */ 416 417 #define IWI_EEPROM_SHIFT_D 2 418 #define IWI_EEPROM_SHIFT_Q 4 419 420 /* 421 * control and status registers access macros 422 */ 423 #define CSR_READ_1(sc, reg) \ 424 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 425 426 #define CSR_READ_2(sc, reg) \ 427 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 428 429 #define CSR_READ_4(sc, reg) \ 430 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 431 432 #define CSR_READ_REGION_4(sc, offset, datap, count) \ 433 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 434 (datap), (count)) 435 436 #define CSR_WRITE_1(sc, reg, val) \ 437 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 438 439 #define CSR_WRITE_2(sc, reg, val) \ 440 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 441 442 #define CSR_WRITE_4(sc, reg, val) \ 443 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 444 445 /* 446 * indirect memory space access macros 447 */ 448 #define MEM_WRITE_1(sc, addr, val) do { \ 449 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 450 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 451 } while (/* CONSTCOND */0) 452 453 #define MEM_WRITE_2(sc, addr, val) do { \ 454 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 455 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 456 } while (/* CONSTCOND */0) 457 458 #define MEM_WRITE_4(sc, addr, val) do { \ 459 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 460 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 461 } while (/* CONSTCOND */0) 462 463 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 464 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 465 CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ 466 } while (/* CONSTCOND */0) 467 468 469 #define IWI_FW_ERROR_OK 0 470 #define IWI_FW_ERROR_FAIL 1 471 #define IWI_FW_ERROR_MEMORY_UNDERFLOW 2 472 #define IWI_FW_ERROR_MEMORY_OVERFLOW 3 473 #define IWI_FW_ERROR_BAD_PARAM 4 474 #define IWI_FW_ERROR_BAD_CHECKSUM 5 475 #define IWI_FW_ERROR_NMI_INTERRUPT 6 476 #define IWI_FW_ERROR_BAD_DATABASE 7 477 #define IWI_FW_ERROR_ALLOC_FAIL 8 478 #define IWI_FW_ERROR_DMA_UNDERRUN 9 479 #define IWI_FW_ERROR_DMA_STATUS 10 480 #define IWI_FW_ERROR_DINOSTATUS_ERROR 11 481 #define IWI_FW_ERROR_EEPROMSTATUS_ERROR 12 482 #define IWI_FW_ERROR_SYSASSERT 13 483 #define IWI_FW_ERROR_FATAL_ERROR 14 484 485 486 #define IWI_FW_EVENT_ELEM_SIZE (3 * sizeof(u_int32_t)) 487 #define IWI_FW_EVENT_START_OFFSET (sizeof(u_int32_t) + 2 * sizeof(u_int16_t)) 488 #define IWI_FW_ERROR_ELEM_SIZE (7 * sizeof(u_int32_t)) 489 #define IWI_FW_ERROR_START_OFFSET (1 * sizeof(u_int32_t)) 490 491 492 #define IWI_FW_MAX_STATIONS 32 493 494 struct iwi_fw_station { 495 u_int8_t mac[ETHER_ADDR_LEN]; 496 u_int8_t reserved; 497 u_int8_t support_mode; 498 } __packed; 499 500 501 502 /* 503 * EEPROM access macro 504 */ 505 #define IWI_EEPROM_CTL(sc, val) do { \ 506 MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ 507 DELAY(IWI_EEPROM_DELAY); \ 508 } while (/* CONSTCOND */0) 509