1 /* 2 * Copyright (c) 2004-2006 3 * Damien Bergamini <damien.bergamini@free.fr>. 4 * Copyright (c) 2004, 2005 5 * Andrew Atrens <atrens@nortelnetworks.com>. 6 * 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice unmodified, this list of conditions, and the following 14 * disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/iwi/if_iwireg.h,v 1.2.2.2 2006/01/29 13:54:19 damien Exp $ 32 * $DragonFly: src/sys/dev/netif/iwi/if_iwireg.h,v 1.3 2006/12/23 09:44:26 sephe Exp $ 33 */ 34 35 #define IWI_CMD_RING_COUNT 16 36 #define IWI_TX_RING_COUNT 64 37 #define IWI_RX_RING_COUNT 32 38 39 #define IWI_TX_DESC_SIZE (sizeof (struct iwi_tx_desc)) 40 #define IWI_CMD_DESC_SIZE (sizeof (struct iwi_cmd_desc)) 41 42 #define IWI_CSR_INTR 0x0008 43 #define IWI_CSR_INTR_MASK 0x000c 44 #define IWI_CSR_INDIRECT_ADDR 0x0010 45 #define IWI_CSR_INDIRECT_DATA 0x0014 46 #define IWI_CSR_AUTOINC_ADDR 0x0018 47 #define IWI_CSR_AUTOINC_DATA 0x001c 48 #define IWI_CSR_RST 0x0020 49 #define IWI_CSR_CTL 0x0024 50 #define IWI_CSR_IO 0x0030 51 #define IWI_CSR_CMD_BASE 0x0200 52 #define IWI_CSR_CMD_SIZE 0x0204 53 #define IWI_CSR_TX1_BASE 0x0208 54 #define IWI_CSR_TX1_SIZE 0x020c 55 #define IWI_CSR_TX2_BASE 0x0210 56 #define IWI_CSR_TX2_SIZE 0x0214 57 #define IWI_CSR_TX3_BASE 0x0218 58 #define IWI_CSR_TX3_SIZE 0x021c 59 #define IWI_CSR_TX4_BASE 0x0220 60 #define IWI_CSR_TX4_SIZE 0x0224 61 #define IWI_CSR_CMD_RIDX 0x0280 62 #define IWI_CSR_TX1_RIDX 0x0284 63 #define IWI_CSR_TX2_RIDX 0x0288 64 #define IWI_CSR_TX3_RIDX 0x028c 65 #define IWI_CSR_TX4_RIDX 0x0290 66 #define IWI_CSR_RX_RIDX 0x02a0 67 #define IWI_CSR_RX_BASE 0x0500 68 #define IWI_CSR_TABLE0_SIZE 0x0700 69 #define IWI_CSR_TABLE0_BASE 0x0704 70 #define IWI_CSR_NODE_BASE 0x0c0c 71 #define IWI_CSR_CMD_WIDX 0x0f80 72 #define IWI_CSR_TX1_WIDX 0x0f84 73 #define IWI_CSR_TX2_WIDX 0x0f88 74 #define IWI_CSR_TX3_WIDX 0x0f8c 75 #define IWI_CSR_TX4_WIDX 0x0f90 76 #define IWI_CSR_RX_WIDX 0x0fa0 77 #define IWI_CSR_READ_INT 0x0ff4 78 79 /* aliases */ 80 #define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE 81 82 /* flags for IWI_CSR_INTR */ 83 #define IWI_INTR_RX_DONE 0x00000002 84 #define IWI_INTR_CMD_DONE 0x00000800 85 #define IWI_INTR_TX1_DONE 0x00001000 86 #define IWI_INTR_TX2_DONE 0x00002000 87 #define IWI_INTR_TX3_DONE 0x00004000 88 #define IWI_INTR_TX4_DONE 0x00008000 89 #define IWI_INTR_FW_INITED 0x01000000 90 #define IWI_INTR_RADIO_OFF 0x04000000 91 #define IWI_INTR_FATAL_ERROR 0x40000000 92 #define IWI_INTR_PARITY_ERROR 0x80000000 93 94 #define IWI_INTR_MASK \ 95 (IWI_INTR_RX_DONE | IWI_INTR_CMD_DONE | IWI_INTR_TX1_DONE | \ 96 IWI_INTR_TX2_DONE | IWI_INTR_TX3_DONE | IWI_INTR_TX4_DONE | \ 97 IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \ 98 IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR) 99 100 /* flags for IWI_CSR_RST */ 101 #define IWI_RST_PRINCETON_RESET 0x00000001 102 #define IWI_RST_SOFT_RESET 0x00000080 103 #define IWI_RST_MASTER_DISABLED 0x00000100 104 #define IWI_RST_STOP_MASTER 0x00000200 105 106 /* flags for IWI_CSR_CTL */ 107 #define IWI_CTL_CLOCK_READY 0x00000001 108 #define IWI_CTL_ALLOW_STANDBY 0x00000002 109 #define IWI_CTL_INIT 0x00000004 110 111 /* flags for IWI_CSR_IO */ 112 #define IWI_IO_RADIO_ENABLED 0x00010000 113 114 /* flags for IWI_CSR_READ_INT */ 115 #define IWI_READ_INT_INIT_HOST 0x20000000 116 117 /* constants for command blocks */ 118 #define IWI_CB_DEFAULT_CTL 0x8cea0000 119 #define IWI_CB_MAXDATALEN 8191 120 121 /* supported rates */ 122 #define IWI_RATE_DS1 10 123 #define IWI_RATE_DS2 20 124 #define IWI_RATE_DS5 55 125 #define IWI_RATE_DS11 110 126 #define IWI_RATE_OFDM6 13 127 #define IWI_RATE_OFDM9 15 128 #define IWI_RATE_OFDM12 5 129 #define IWI_RATE_OFDM18 7 130 #define IWI_RATE_OFDM24 9 131 #define IWI_RATE_OFDM36 11 132 #define IWI_RATE_OFDM48 1 133 #define IWI_RATE_OFDM54 3 134 135 struct iwi_hdr { 136 uint8_t type; 137 #define IWI_HDR_TYPE_DATA 0 138 #define IWI_HDR_TYPE_COMMAND 1 139 #define IWI_HDR_TYPE_NOTIF 3 140 #define IWI_HDR_TYPE_FRAME 9 141 142 uint8_t seq; 143 uint8_t flags; 144 #define IWI_HDR_FLAG_IRQ 0x04 145 146 uint8_t reserved; 147 } __packed; 148 149 struct iwi_notif { 150 uint32_t reserved[2]; 151 uint8_t type; 152 #define IWI_NOTIF_TYPE_ASSOCIATION 10 153 #define IWI_NOTIF_TYPE_AUTHENTICATION 11 154 #define IWI_NOTIF_TYPE_SCAN_CHANNEL 12 155 #define IWI_NOTIF_TYPE_SCAN_COMPLETE 13 156 #define IWI_NOTIF_TYPE_BEACON 17 157 #define IWI_NOTIF_TYPE_CALIBRATION 20 158 #define IWI_NOTIF_TYPE_NOISE 25 159 160 uint8_t flags; 161 uint16_t len; 162 } __packed; 163 164 /* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */ 165 struct iwi_notif_authentication { 166 uint8_t state; 167 #define IWI_DEAUTHENTICATED 0 168 #define IWI_AUTHENTICATED 9 169 } __packed; 170 171 /* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */ 172 struct iwi_notif_association { 173 uint8_t state; 174 #define IWI_DEASSOCIATED 0 175 #define IWI_ASSOCIATED 12 176 177 struct ieee80211_frame frame; 178 uint16_t capinfo; 179 uint16_t status; 180 uint16_t associd; 181 } __packed; 182 183 /* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */ 184 struct iwi_notif_scan_channel { 185 uint8_t nchan; 186 uint8_t reserved[47]; 187 } __packed; 188 189 /* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */ 190 struct iwi_notif_scan_complete { 191 uint8_t type; 192 uint8_t nchan; 193 uint8_t status; 194 uint8_t reserved; 195 } __packed; 196 197 /* received frame header */ 198 struct iwi_frame { 199 uint32_t reserved1[2]; 200 uint8_t chan; 201 uint8_t status; 202 uint8_t rate; 203 uint8_t rssi; 204 uint8_t agc; 205 uint8_t rssi_dbm; 206 uint16_t signal; 207 uint16_t noise; 208 uint8_t antenna; 209 uint8_t control; 210 uint8_t reserved2[2]; 211 uint16_t len; 212 } __packed; 213 214 /* header for transmission */ 215 struct iwi_tx_desc { 216 struct iwi_hdr hdr; 217 uint32_t reserved1; 218 uint8_t station; 219 uint8_t reserved2[3]; 220 uint8_t cmd; 221 #define IWI_DATA_CMD_TX 0x0b 222 223 uint8_t seq; 224 uint16_t len; 225 uint8_t priority; 226 uint8_t flags; 227 #define IWI_DATA_FLAG_SHPREAMBLE 0x04 228 #define IWI_DATA_FLAG_NO_WEP 0x20 229 #define IWI_DATA_FLAG_NEED_ACK 0x80 230 231 uint8_t xflags; 232 #define IWI_DATA_XFLAG_QOS 0x10 233 234 uint8_t weptxkey; 235 uint8_t wepkey[IEEE80211_KEYBUF_SIZE]; 236 uint8_t rate; 237 uint8_t antenna; 238 uint8_t reserved3[10]; 239 struct ieee80211_qosframe_addr4 wh; 240 uint32_t iv; 241 uint32_t eiv; 242 uint32_t nseg; 243 #define IWI_MAX_NSEG 6 244 245 uint32_t seg_addr[IWI_MAX_NSEG]; 246 uint16_t seg_len[IWI_MAX_NSEG]; 247 } __packed; 248 249 /* command */ 250 struct iwi_cmd_desc { 251 struct iwi_hdr hdr; 252 uint8_t type; 253 #define IWI_CMD_ENABLE 2 254 #define IWI_CMD_SET_CONFIG 6 255 #define IWI_CMD_SET_ESSID 8 256 #define IWI_CMD_SET_MAC_ADDRESS 11 257 #define IWI_CMD_SET_RTS_THRESHOLD 15 258 #define IWI_CMD_SET_FRAG_THRESHOLD 16 259 #define IWI_CMD_SET_POWER_MODE 17 260 #define IWI_CMD_SET_WEP_KEY 18 261 #define IWI_CMD_ASSOCIATE 21 262 #define IWI_CMD_SET_RATES 22 263 #define IWI_CMD_ABORT_SCAN 23 264 #define IWI_CMD_SET_WME_PARAMS 25 265 #define IWI_CMD_SCAN 26 266 #define IWI_CMD_SET_OPTIE 31 267 #define IWI_CMD_DISABLE 33 268 #define IWI_CMD_SET_IV 34 269 #define IWI_CMD_SET_TX_POWER 35 270 #define IWI_CMD_SET_SENSITIVITY 42 271 #define IWI_CMD_SET_WMEIE 84 272 273 uint8_t len; 274 uint16_t reserved; 275 uint8_t data[120]; 276 } __packed; 277 278 /* node information (IBSS) */ 279 struct iwi_ibssnode { 280 uint8_t bssid[IEEE80211_ADDR_LEN]; 281 uint8_t reserved[2]; 282 } __packed; 283 284 /* constants for 'mode' fields */ 285 #define IWI_MODE_11A 0 286 #define IWI_MODE_11B 1 287 #define IWI_MODE_11G 2 288 289 /* possible values for command IWI_CMD_SET_POWER_MODE */ 290 #define IWI_POWER_MODE_CAM 0 291 292 /* structure for command IWI_CMD_SET_RATES */ 293 struct iwi_rateset { 294 uint8_t mode; 295 uint8_t nrates; 296 uint8_t type; 297 #define IWI_RATESET_TYPE_NEGOTIATED 0 298 #define IWI_RATESET_TYPE_SUPPORTED 1 299 300 uint8_t reserved; 301 302 #define IWI_RATESET_MAXSIZE 12 303 uint8_t rates[IWI_RATESET_MAXSIZE]; 304 } __packed; 305 306 /* structure for command IWI_CMD_SET_TX_POWER */ 307 struct iwi_txpower { 308 uint8_t nchan; 309 uint8_t mode; 310 struct { 311 uint8_t chan; 312 uint8_t power; 313 #define IWI_TXPOWER_MAX 20 314 #define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX) 315 } __packed chan[37]; 316 } __packed; 317 318 /* structure for command IWI_CMD_ASSOCIATE */ 319 struct iwi_associate { 320 uint8_t chan; 321 uint8_t auth; 322 #define IWI_AUTH_OPEN 0 323 #define IWI_AUTH_SHARED 1 324 #define IWI_AUTH_NONE 3 325 326 uint8_t type; 327 uint8_t reserved1; 328 uint16_t policy; 329 #define IWI_POLICY_WME 1 330 #define IWI_POLICY_WPA 2 331 332 uint8_t plen; 333 uint8_t mode; 334 uint8_t bssid[IEEE80211_ADDR_LEN]; 335 uint8_t tstamp[8]; 336 uint16_t capinfo; 337 uint16_t lintval; 338 uint16_t intval; 339 uint8_t dst[IEEE80211_ADDR_LEN]; 340 uint32_t reserved3; 341 uint16_t reserved4; 342 } __packed; 343 344 /* structure for command IWI_CMD_SCAN */ 345 struct iwi_scan { 346 uint32_t index; 347 uint8_t channels[54]; 348 #define IWI_CHAN_5GHZ (0 << 6) 349 #define IWI_CHAN_2GHZ (1 << 6) 350 351 uint8_t type[27]; 352 #define IWI_SCAN_TYPE_PASSIVE 0x11 353 #define IWI_SCAN_TYPE_DIRECTED 0x22 354 #define IWI_SCAN_TYPE_BROADCAST 0x33 355 #define IWI_SCAN_TYPE_BDIRECTED 0x44 356 357 uint8_t reserved1; 358 uint16_t reserved2; 359 uint16_t passive; /* dwell time */ 360 uint16_t directed; /* dwell time */ 361 uint16_t broadcast; /* dwell time */ 362 uint16_t bdirected; /* dwell time */ 363 } __packed; 364 365 /* structure for command IWI_CMD_SET_CONFIG */ 366 struct iwi_configuration { 367 uint8_t bluetooth_coexistence; 368 uint8_t reserved1; 369 uint8_t answer_pbreq; 370 uint8_t allow_invalid_frames; 371 uint8_t multicast_enabled; 372 uint8_t drop_unicast_unencrypted; 373 uint8_t disable_unicast_decryption; 374 uint8_t drop_multicast_unencrypted; 375 uint8_t disable_multicast_decryption; 376 uint8_t antenna; 377 uint8_t reserved2; 378 uint8_t use_protection; 379 uint8_t protection_ctsonly; 380 uint8_t enable_multicast_filtering; 381 uint8_t bluetooth_threshold; 382 uint8_t reserved4; 383 uint8_t allow_beacon_and_probe_resp; 384 uint8_t allow_mgt; 385 uint8_t noise_reported; 386 uint8_t reserved5; 387 } __packed; 388 389 /* structure for command IWI_CMD_SET_WEP_KEY */ 390 struct iwi_wep_key { 391 uint8_t cmd; 392 #define IWI_WEP_KEY_CMD_SETKEY 0x08 393 394 uint8_t seq; 395 uint8_t idx; 396 uint8_t len; 397 uint8_t key[IEEE80211_KEYBUF_SIZE]; 398 } __packed; 399 400 /* structure for command IWI_CMD_SET_WME_PARAMS */ 401 struct iwi_wme_params { 402 uint16_t cwmin[WME_NUM_AC]; 403 uint16_t cwmax[WME_NUM_AC]; 404 uint8_t aifsn[WME_NUM_AC]; 405 uint8_t acm[WME_NUM_AC]; 406 uint16_t burst[WME_NUM_AC]; 407 } __packed; 408 409 #define IWI_MEM_EVENT_CTL 0x00300004 410 #define IWI_MEM_EEPROM_CTL 0x00300040 411 412 /* possible flags for register IWI_MEM_EVENT */ 413 #define IWI_LED_ASSOC (1 << 5) 414 #define IWI_LED_MASK 0xd9fffffb 415 416 #define IWI_EEPROM_MAC 0x21 417 418 #define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 419 420 #define IWI_EEPROM_C (1 << 0) /* Serial Clock */ 421 #define IWI_EEPROM_S (1 << 1) /* Chip Select */ 422 #define IWI_EEPROM_D (1 << 2) /* Serial data input */ 423 #define IWI_EEPROM_Q (1 << 4) /* Serial data output */ 424 425 #define IWI_EEPROM_SHIFT_D 2 426 #define IWI_EEPROM_SHIFT_Q 4 427 428 /* 429 * control and status registers access macros 430 */ 431 #define CSR_READ_1(sc, reg) \ 432 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 433 434 #define CSR_READ_2(sc, reg) \ 435 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 436 437 #define CSR_READ_4(sc, reg) \ 438 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 439 440 #define CSR_READ_REGION_4(sc, offset, datap, count) \ 441 bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 442 (datap), (count)) 443 444 #define CSR_WRITE_1(sc, reg, val) \ 445 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 446 447 #define CSR_WRITE_2(sc, reg, val) \ 448 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 449 450 #define CSR_WRITE_4(sc, reg, val) \ 451 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 452 453 #define CSR_WRITE_REGION_1(sc, offset, datap, count) \ 454 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 455 (datap), (count)) 456 457 /* 458 * indirect memory space access macros 459 */ 460 #define MEM_READ_1(sc, addr) \ 461 (CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)), \ 462 CSR_READ_1((sc), IWI_CSR_INDIRECT_DATA)) 463 464 #define MEM_READ_4(sc, addr) \ 465 (CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)), \ 466 CSR_READ_4((sc), IWI_CSR_INDIRECT_DATA)) 467 468 #define MEM_WRITE_1(sc, addr, val) do { \ 469 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 470 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 471 } while (/* CONSTCOND */0) 472 473 #define MEM_WRITE_2(sc, addr, val) do { \ 474 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 475 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 476 } while (/* CONSTCOND */0) 477 478 #define MEM_WRITE_4(sc, addr, val) do { \ 479 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 480 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \ 481 } while (/* CONSTCOND */0) 482 483 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 484 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \ 485 CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \ 486 } while (/* CONSTCOND */0) 487 488 /* 489 * EEPROM access macro 490 */ 491 #define IWI_EEPROM_CTL(sc, val) do { \ 492 MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \ 493 DELAY(IWI_EEPROM_DELAY); \ 494 } while (/* CONSTCOND */0) 495