1 /* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90 /*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105 #include <sys/cdefs.h> 106 __FBSDID("$FreeBSD$"); 107 108 #include <sys/param.h> 109 #include <sys/bus.h> 110 #include <sys/endian.h> 111 #include <sys/firmware.h> 112 #include <sys/kernel.h> 113 #include <sys/malloc.h> 114 #include <sys/mbuf.h> 115 #include <sys/mutex.h> 116 #include <sys/module.h> 117 #include <sys/proc.h> 118 #include <sys/rman.h> 119 #include <sys/socket.h> 120 #include <sys/sockio.h> 121 #include <sys/sysctl.h> 122 #include <sys/linker.h> 123 124 #include <machine/endian.h> 125 126 #include <bus/pci/pcivar.h> 127 #include <bus/pci/pcireg.h> 128 129 #include <net/bpf.h> 130 131 #include <net/if.h> 132 #include <net/if_var.h> 133 #include <net/if_arp.h> 134 #include <net/ethernet.h> 135 #include <net/if_dl.h> 136 #include <net/if_media.h> 137 #include <net/if_types.h> 138 #include <net/ifq_var.h> 139 140 #include <netinet/in.h> 141 #include <netinet/in_systm.h> 142 #include <netinet/if_ether.h> 143 #include <netinet/ip.h> 144 145 #include <netproto/802_11/ieee80211_var.h> 146 #include <netproto/802_11/ieee80211_regdomain.h> 147 #include <netproto/802_11/ieee80211_ratectl.h> 148 #include <netproto/802_11/ieee80211_radiotap.h> 149 150 #include "if_iwmreg.h" 151 #include "if_iwmvar.h" 152 #include "if_iwm_debug.h" 153 #include "if_iwm_pcie_trans.h" 154 155 /* 156 * This is a subset of what's in linux iwlwifi/pcie/trans.c. 157 * The rest can be migrated out into here once they're no longer in 158 * if_iwm.c. 159 */ 160 161 /* 162 * basic device access 163 */ 164 165 uint32_t 166 iwm_read_prph(struct iwm_softc *sc, uint32_t addr) 167 { 168 IWM_WRITE(sc, 169 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24))); 170 IWM_BARRIER_READ_WRITE(sc); 171 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT); 172 } 173 174 void 175 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val) 176 { 177 IWM_WRITE(sc, 178 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24))); 179 IWM_BARRIER_WRITE(sc); 180 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val); 181 } 182 183 #ifdef IWM_DEBUG 184 int 185 iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) 186 { 187 int offs, ret = 0; 188 uint32_t *vals = buf; 189 190 if (iwm_nic_lock(sc)) { 191 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr); 192 for (offs = 0; offs < dwords; offs++) 193 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT); 194 iwm_nic_unlock(sc); 195 } else { 196 ret = EBUSY; 197 } 198 return ret; 199 } 200 #endif 201 202 int 203 iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) 204 { 205 int offs; 206 const uint32_t *vals = buf; 207 208 if (iwm_nic_lock(sc)) { 209 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr); 210 /* WADDR auto-increments */ 211 for (offs = 0; offs < dwords; offs++) { 212 uint32_t val = vals ? vals[offs] : 0; 213 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val); 214 } 215 iwm_nic_unlock(sc); 216 } else { 217 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, 218 "%s: write_mem failed\n", __func__); 219 return EBUSY; 220 } 221 return 0; 222 } 223 224 int 225 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val) 226 { 227 return iwm_write_mem(sc, addr, &val, 1); 228 } 229 230 int 231 iwm_poll_bit(struct iwm_softc *sc, int reg, 232 uint32_t bits, uint32_t mask, int timo) 233 { 234 for (;;) { 235 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) { 236 return 1; 237 } 238 if (timo < 10) { 239 return 0; 240 } 241 timo -= 10; 242 DELAY(10); 243 } 244 } 245 246 int 247 iwm_nic_lock(struct iwm_softc *sc) 248 { 249 int rv = 0; 250 251 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 252 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 253 254 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 255 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 256 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 257 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 258 rv = 1; 259 } else { 260 /* jolt */ 261 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 262 } 263 264 return rv; 265 } 266 267 void 268 iwm_nic_unlock(struct iwm_softc *sc) 269 { 270 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 271 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 272 } 273 274 void 275 iwm_set_bits_mask_prph(struct iwm_softc *sc, 276 uint32_t reg, uint32_t bits, uint32_t mask) 277 { 278 uint32_t val; 279 280 /* XXX: no error path? */ 281 if (iwm_nic_lock(sc)) { 282 val = iwm_read_prph(sc, reg) & mask; 283 val |= bits; 284 iwm_write_prph(sc, reg, val); 285 iwm_nic_unlock(sc); 286 } 287 } 288 289 void 290 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 291 { 292 iwm_set_bits_mask_prph(sc, reg, bits, ~0); 293 } 294 295 void 296 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 297 { 298 iwm_set_bits_mask_prph(sc, reg, 0, ~bits); 299 } 300 301 /* 302 * High-level hardware frobbing routines 303 */ 304 305 void 306 iwm_enable_rfkill_int(struct iwm_softc *sc) 307 { 308 sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL; 309 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 310 } 311 312 int 313 iwm_check_rfkill(struct iwm_softc *sc) 314 { 315 uint32_t v; 316 int rv; 317 318 /* 319 * "documentation" is not really helpful here: 320 * 27: HW_RF_KILL_SW 321 * Indicates state of (platform's) hardware RF-Kill switch 322 * 323 * But apparently when it's off, it's on ... 324 */ 325 v = IWM_READ(sc, IWM_CSR_GP_CNTRL); 326 rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0; 327 if (rv) { 328 sc->sc_flags |= IWM_FLAG_RFKILL; 329 } else { 330 sc->sc_flags &= ~IWM_FLAG_RFKILL; 331 } 332 333 return rv; 334 } 335 336 337 #define IWM_HW_READY_TIMEOUT 50 338 int 339 iwm_set_hw_ready(struct iwm_softc *sc) 340 { 341 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 342 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 343 344 return iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG, 345 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 346 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 347 IWM_HW_READY_TIMEOUT); 348 } 349 #undef IWM_HW_READY_TIMEOUT 350 351 int 352 iwm_prepare_card_hw(struct iwm_softc *sc) 353 { 354 int rv = 0; 355 int t = 0; 356 357 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__); 358 if (iwm_set_hw_ready(sc)) 359 goto out; 360 361 /* If HW is not ready, prepare the conditions to check again */ 362 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 363 IWM_CSR_HW_IF_CONFIG_REG_PREPARE); 364 365 do { 366 if (iwm_set_hw_ready(sc)) 367 goto out; 368 DELAY(200); 369 t += 200; 370 } while (t < 150000); 371 372 rv = ETIMEDOUT; 373 374 out: 375 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__); 376 return rv; 377 } 378 379 void 380 iwm_apm_config(struct iwm_softc *sc) 381 { 382 uint16_t reg; 383 384 #if defined(__DragonFly__) 385 reg = pci_read_config(sc->sc_dev, PCIER_LINKCTRL, sizeof(reg)); 386 if (reg & PCIEM_LNKCTL_ASPM_L1) { 387 #else 388 reg = pci_read_config(sc->sc_dev, PCIER_LINK_CTL, sizeof(reg)); 389 if (reg & PCIEM_LINK_CTL_ASPMC_L1) { 390 #endif 391 /* Um the Linux driver prints "Disabling L0S for this one ... */ 392 IWM_SETBITS(sc, IWM_CSR_GIO_REG, 393 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 394 } else { 395 /* ... and "Enabling" here */ 396 IWM_CLRBITS(sc, IWM_CSR_GIO_REG, 397 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 398 } 399 } 400 401 /* 402 * Start up NIC's basic functionality after it has been reset 403 * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop()) 404 * NOTE: This does not load uCode nor start the embedded processor 405 */ 406 int 407 iwm_apm_init(struct iwm_softc *sc) 408 { 409 int error = 0; 410 411 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n"); 412 413 /* Disable L0S exit timer (platform NMI Work/Around) */ 414 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 415 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 416 417 /* 418 * Disable L0s without affecting L1; 419 * don't wait for ICH L0s (ICH bug W/A) 420 */ 421 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 422 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 423 424 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 425 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL); 426 427 /* 428 * Enable HAP INTA (interrupt from management bus) to 429 * wake device's PCI Express link L1a -> L0s 430 */ 431 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 432 IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 433 434 iwm_apm_config(sc); 435 436 #if 0 /* not for 7k */ 437 /* Configure analog phase-lock-loop before activating to D0A */ 438 if (trans->cfg->base_params->pll_cfg_val) 439 IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG, 440 trans->cfg->base_params->pll_cfg_val); 441 #endif 442 443 /* 444 * Set "initialization complete" bit to move adapter from 445 * D0U* --> D0A* (powered-up active) state. 446 */ 447 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 448 449 /* 450 * Wait for clock stabilization; once stabilized, access to 451 * device-internal resources is supported, e.g. iwm_write_prph() 452 * and accesses to uCode SRAM. 453 */ 454 if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 455 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 456 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) { 457 device_printf(sc->sc_dev, 458 "timeout waiting for clock stabilization\n"); 459 460 goto out; 461 } 462 463 if (sc->host_interrupt_operation_mode) { 464 /* 465 * This is a bit of an abuse - This is needed for 7260 / 3160 466 * only check host_interrupt_operation_mode even if this is 467 * not related to host_interrupt_operation_mode. 468 * 469 * Enable the oscillator to count wake up time for L1 exit. This 470 * consumes slightly more power (100uA) - but allows to be sure 471 * that we wake up from L1 on time. 472 * 473 * This looks weird: read twice the same register, discard the 474 * value, set a bit, and yet again, read that same register 475 * just to discard the value. But that's the way the hardware 476 * seems to like it. 477 */ 478 iwm_read_prph(sc, IWM_OSC_CLK); 479 iwm_read_prph(sc, IWM_OSC_CLK); 480 iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL); 481 iwm_read_prph(sc, IWM_OSC_CLK); 482 iwm_read_prph(sc, IWM_OSC_CLK); 483 } 484 485 /* 486 * Enable DMA clock and wait for it to stabilize. 487 * 488 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits 489 * do not disable clocks. This preserves any hardware bits already 490 * set by default in "CLK_CTRL_REG" after reset. 491 */ 492 iwm_write_prph(sc, IWM_APMG_CLK_EN_REG, IWM_APMG_CLK_VAL_DMA_CLK_RQT); 493 //kpause("iwmapm", 0, mstohz(20), NULL); 494 DELAY(20); 495 496 /* Disable L1-Active */ 497 iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 498 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 499 500 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 501 iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG, 502 IWM_APMG_RTC_INT_STT_RFKILL); 503 504 out: 505 if (error) 506 device_printf(sc->sc_dev, "apm init error %d\n", error); 507 return error; 508 } 509 510 void 511 iwm_apm_stop(struct iwm_softc *sc) 512 { 513 /* stop device's busmaster DMA activity */ 514 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER); 515 516 if (!iwm_poll_bit(sc, IWM_CSR_RESET, 517 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 518 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100)) 519 device_printf(sc->sc_dev, "timeout waiting for master\n"); 520 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__); 521 } 522 523 int 524 iwm_start_hw(struct iwm_softc *sc) 525 { 526 int error; 527 528 if ((error = iwm_prepare_card_hw(sc)) != 0) 529 return error; 530 531 /* Reset the entire device */ 532 IWM_WRITE(sc, IWM_CSR_RESET, 533 IWM_CSR_RESET_REG_FLAG_SW_RESET | 534 IWM_CSR_RESET_REG_FLAG_NEVO_RESET); 535 DELAY(10); 536 537 if ((error = iwm_apm_init(sc)) != 0) 538 return error; 539 540 iwm_enable_rfkill_int(sc); 541 iwm_check_rfkill(sc); 542 543 return 0; 544 } 545 546 void 547 iwm_set_pwr(struct iwm_softc *sc) 548 { 549 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 550 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC); 551 } 552 553 int 554 iwm_pcie_rx_stop(struct iwm_softc *sc) 555 { 556 557 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 558 return (iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG, 559 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 560 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 561 1000)); 562 } 563