1 /* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90 /*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105 #include <sys/cdefs.h> 106 __FBSDID("$FreeBSD$"); 107 108 #include <sys/param.h> 109 #include <sys/bus.h> 110 #include <sys/endian.h> 111 #include <sys/firmware.h> 112 #include <sys/kernel.h> 113 #include <sys/malloc.h> 114 #include <sys/mbuf.h> 115 #include <sys/rman.h> 116 #include <sys/sysctl.h> 117 #include <sys/linker.h> 118 119 #include <machine/endian.h> 120 121 #include <bus/pci/pcivar.h> 122 #include <bus/pci/pcireg.h> 123 124 #include <net/bpf.h> 125 126 #include <net/if.h> 127 #include <net/if_var.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_media.h> 131 #include <net/if_types.h> 132 133 #include <netinet/in.h> 134 #include <netinet/in_systm.h> 135 #include <netinet/if_ether.h> 136 #include <netinet/ip.h> 137 138 #include <netproto/802_11/ieee80211_var.h> 139 #include <netproto/802_11/ieee80211_regdomain.h> 140 #include <netproto/802_11/ieee80211_ratectl.h> 141 #include <netproto/802_11/ieee80211_radiotap.h> 142 143 #include "if_iwmreg.h" 144 #include "if_iwmvar.h" 145 #include "if_iwm_config.h" 146 #include "if_iwm_debug.h" 147 #include "if_iwm_pcie_trans.h" 148 149 /* 150 * This is a subset of what's in linux iwlwifi/pcie/trans.c. 151 * The rest can be migrated out into here once they're no longer in 152 * if_iwm.c. 153 */ 154 155 /* 156 * basic device access 157 */ 158 159 uint32_t 160 iwm_read_prph(struct iwm_softc *sc, uint32_t addr) 161 { 162 IWM_WRITE(sc, 163 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24))); 164 IWM_BARRIER_READ_WRITE(sc); 165 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT); 166 } 167 168 void 169 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val) 170 { 171 IWM_WRITE(sc, 172 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24))); 173 IWM_BARRIER_WRITE(sc); 174 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val); 175 } 176 177 #ifdef IWM_DEBUG 178 int 179 iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) 180 { 181 int offs, ret = 0; 182 uint32_t *vals = buf; 183 184 if (iwm_nic_lock(sc)) { 185 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr); 186 for (offs = 0; offs < dwords; offs++) 187 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT); 188 iwm_nic_unlock(sc); 189 } else { 190 ret = EBUSY; 191 } 192 return ret; 193 } 194 #endif 195 196 int 197 iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) 198 { 199 int offs; 200 const uint32_t *vals = buf; 201 202 if (iwm_nic_lock(sc)) { 203 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr); 204 /* WADDR auto-increments */ 205 for (offs = 0; offs < dwords; offs++) { 206 uint32_t val = vals ? vals[offs] : 0; 207 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val); 208 } 209 iwm_nic_unlock(sc); 210 } else { 211 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, 212 "%s: write_mem failed\n", __func__); 213 return EBUSY; 214 } 215 return 0; 216 } 217 218 int 219 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val) 220 { 221 return iwm_write_mem(sc, addr, &val, 1); 222 } 223 224 int 225 iwm_poll_bit(struct iwm_softc *sc, int reg, 226 uint32_t bits, uint32_t mask, int timo) 227 { 228 for (;;) { 229 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) { 230 return 1; 231 } 232 if (timo < 10) { 233 return 0; 234 } 235 timo -= 10; 236 DELAY(10); 237 } 238 } 239 240 int 241 iwm_nic_lock(struct iwm_softc *sc) 242 { 243 int rv = 0; 244 245 if (sc->cmd_hold_nic_awake) 246 return 1; 247 248 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 249 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 250 251 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_8000) 252 DELAY(2); 253 254 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 255 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 256 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 257 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 258 rv = 1; 259 } else { 260 /* jolt */ 261 IWM_DPRINTF(sc, IWM_DEBUG_RESET, 262 "%s: resetting device via NMI\n", __func__); 263 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 264 } 265 266 return rv; 267 } 268 269 void 270 iwm_nic_unlock(struct iwm_softc *sc) 271 { 272 if (sc->cmd_hold_nic_awake) 273 return; 274 275 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 276 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 277 } 278 279 void 280 iwm_set_bits_mask_prph(struct iwm_softc *sc, 281 uint32_t reg, uint32_t bits, uint32_t mask) 282 { 283 uint32_t val; 284 285 /* XXX: no error path? */ 286 if (iwm_nic_lock(sc)) { 287 val = iwm_read_prph(sc, reg) & mask; 288 val |= bits; 289 iwm_write_prph(sc, reg, val); 290 iwm_nic_unlock(sc); 291 } 292 } 293 294 void 295 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 296 { 297 iwm_set_bits_mask_prph(sc, reg, bits, ~0); 298 } 299 300 void 301 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 302 { 303 iwm_set_bits_mask_prph(sc, reg, 0, ~bits); 304 } 305 306 /* 307 * High-level hardware frobbing routines 308 */ 309 310 void 311 iwm_enable_rfkill_int(struct iwm_softc *sc) 312 { 313 sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL; 314 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 315 } 316 317 int 318 iwm_check_rfkill(struct iwm_softc *sc) 319 { 320 uint32_t v; 321 int rv; 322 323 /* 324 * "documentation" is not really helpful here: 325 * 27: HW_RF_KILL_SW 326 * Indicates state of (platform's) hardware RF-Kill switch 327 * 328 * But apparently when it's off, it's on ... 329 */ 330 v = IWM_READ(sc, IWM_CSR_GP_CNTRL); 331 rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0; 332 if (rv) { 333 sc->sc_flags |= IWM_FLAG_RFKILL; 334 } else { 335 sc->sc_flags &= ~IWM_FLAG_RFKILL; 336 } 337 338 return rv; 339 } 340 341 342 #define IWM_HW_READY_TIMEOUT 50 343 int 344 iwm_set_hw_ready(struct iwm_softc *sc) 345 { 346 int ready; 347 348 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 349 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 350 351 ready = iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG, 352 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 353 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 354 IWM_HW_READY_TIMEOUT); 355 if (ready) { 356 IWM_SETBITS(sc, IWM_CSR_MBOX_SET_REG, 357 IWM_CSR_MBOX_SET_REG_OS_ALIVE); 358 } 359 return ready; 360 } 361 #undef IWM_HW_READY_TIMEOUT 362 363 int 364 iwm_prepare_card_hw(struct iwm_softc *sc) 365 { 366 int rv = 0; 367 int t = 0; 368 369 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__); 370 if (iwm_set_hw_ready(sc)) 371 goto out; 372 373 DELAY(100); 374 375 /* If HW is not ready, prepare the conditions to check again */ 376 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 377 IWM_CSR_HW_IF_CONFIG_REG_PREPARE); 378 379 do { 380 if (iwm_set_hw_ready(sc)) 381 goto out; 382 DELAY(200); 383 t += 200; 384 } while (t < 150000); 385 386 rv = ETIMEDOUT; 387 388 out: 389 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__); 390 return rv; 391 } 392 393 void 394 iwm_apm_config(struct iwm_softc *sc) 395 { 396 uint16_t lctl, cap; 397 int pcie_ptr; 398 399 /* 400 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 401 * Check if BIOS (or OS) enabled L1-ASPM on this device. 402 * If so (likely), disable L0S, so device moves directly L0->L1; 403 * costs negligible amount of power savings. 404 * If not (unlikely), enable L0S, so there is at least some 405 * power savings, even without L1. 406 */ 407 #if defined(__DragonFly__) 408 pcie_ptr = pci_get_pciecap_ptr(sc->sc_dev); 409 if (pcie_ptr == 0) 410 return; 411 lctl = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_LINKCTRL, 412 sizeof(lctl)); 413 if (lctl & PCIEM_LNKCTL_ASPM_L1) { 414 #else 415 int error; 416 417 error = pci_find_cap(sc->sc_dev, PCIY_EXPRESS, &pcie_ptr); 418 if (error != 0) 419 return; 420 lctl = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_LINK_CTL, 421 sizeof(lctl)); 422 if (lctl & PCIEM_LINK_CTL_ASPMC_L1) { 423 #endif 424 IWM_SETBITS(sc, IWM_CSR_GIO_REG, 425 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 426 } else { 427 IWM_CLRBITS(sc, IWM_CSR_GIO_REG, 428 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 429 } 430 431 #if defined(__DragonFly__) 432 cap = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_DEVCTRL2, 433 sizeof(cap)); 434 sc->sc_ltr_enabled = (cap & PCIEM_DEVCTL2_LTR_ENABLE) ? 1 : 0; 435 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_PWRSAVE, 436 "L1 %sabled - LTR %sabled\n", 437 (lctl & PCIEM_LNKCTL_ASPM_L1) ? "En" : "Dis", 438 #else 439 cap = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_DEVICE_CTL2, 440 sizeof(cap)); 441 sc->sc_ltr_enabled = (cap & PCIEM_CTL2_LTR_ENABLE) ? 1 : 0; 442 IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_PWRSAVE, 443 "L1 %sabled - LTR %sabled\n", 444 (lctl & PCIEM_LINK_CTL_ASPMC_L1) ? "En" : "Dis", 445 #endif 446 sc->sc_ltr_enabled ? "En" : "Dis"); 447 } 448 449 /* 450 * Start up NIC's basic functionality after it has been reset 451 * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop()) 452 * NOTE: This does not load uCode nor start the embedded processor 453 */ 454 int 455 iwm_apm_init(struct iwm_softc *sc) 456 { 457 int error = 0; 458 459 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n"); 460 461 /* Disable L0S exit timer (platform NMI Work/Around) */ 462 if (sc->cfg->device_family != IWM_DEVICE_FAMILY_8000) { 463 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 464 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 465 } 466 467 /* 468 * Disable L0s without affecting L1; 469 * don't wait for ICH L0s (ICH bug W/A) 470 */ 471 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 472 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 473 474 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 475 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL); 476 477 /* 478 * Enable HAP INTA (interrupt from management bus) to 479 * wake device's PCI Express link L1a -> L0s 480 */ 481 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 482 IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 483 484 iwm_apm_config(sc); 485 486 #if 0 /* not for 7k/8k */ 487 /* Configure analog phase-lock-loop before activating to D0A */ 488 if (trans->cfg->base_params->pll_cfg_val) 489 IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG, 490 trans->cfg->base_params->pll_cfg_val); 491 #endif 492 493 /* 494 * Set "initialization complete" bit to move adapter from 495 * D0U* --> D0A* (powered-up active) state. 496 */ 497 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 498 499 /* 500 * Wait for clock stabilization; once stabilized, access to 501 * device-internal resources is supported, e.g. iwm_write_prph() 502 * and accesses to uCode SRAM. 503 */ 504 if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 505 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 506 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) { 507 device_printf(sc->sc_dev, 508 "timeout waiting for clock stabilization\n"); 509 error = ETIMEDOUT; 510 goto out; 511 } 512 513 if (sc->cfg->host_interrupt_operation_mode) { 514 /* 515 * This is a bit of an abuse - This is needed for 7260 / 3160 516 * only check host_interrupt_operation_mode even if this is 517 * not related to host_interrupt_operation_mode. 518 * 519 * Enable the oscillator to count wake up time for L1 exit. This 520 * consumes slightly more power (100uA) - but allows to be sure 521 * that we wake up from L1 on time. 522 * 523 * This looks weird: read twice the same register, discard the 524 * value, set a bit, and yet again, read that same register 525 * just to discard the value. But that's the way the hardware 526 * seems to like it. 527 */ 528 if (iwm_nic_lock(sc)) { 529 iwm_read_prph(sc, IWM_OSC_CLK); 530 iwm_read_prph(sc, IWM_OSC_CLK); 531 iwm_nic_unlock(sc); 532 } 533 iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL); 534 if (iwm_nic_lock(sc)) { 535 iwm_read_prph(sc, IWM_OSC_CLK); 536 iwm_read_prph(sc, IWM_OSC_CLK); 537 iwm_nic_unlock(sc); 538 } 539 } 540 541 /* 542 * Enable DMA clock and wait for it to stabilize. 543 * 544 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits 545 * do not disable clocks. This preserves any hardware bits already 546 * set by default in "CLK_CTRL_REG" after reset. 547 */ 548 if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) { 549 if (iwm_nic_lock(sc)) { 550 iwm_write_prph(sc, IWM_APMG_CLK_EN_REG, 551 IWM_APMG_CLK_VAL_DMA_CLK_RQT); 552 iwm_nic_unlock(sc); 553 } 554 DELAY(20); 555 556 /* Disable L1-Active */ 557 iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 558 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 559 560 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 561 if (iwm_nic_lock(sc)) { 562 iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG, 563 IWM_APMG_RTC_INT_STT_RFKILL); 564 iwm_nic_unlock(sc); 565 } 566 } 567 out: 568 if (error) 569 device_printf(sc->sc_dev, "apm init error %d\n", error); 570 return error; 571 } 572 573 void 574 iwm_apm_stop(struct iwm_softc *sc) 575 { 576 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__); 577 578 /* stop device's busmaster DMA activity */ 579 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER); 580 581 if (!iwm_poll_bit(sc, IWM_CSR_RESET, 582 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 583 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100)) 584 device_printf(sc->sc_dev, "timeout waiting for master\n"); 585 586 /* Reset the entire device */ 587 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET); 588 DELAY(1000); 589 590 /* 591 * Clear "initialization complete" bit to move adapter from 592 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 593 */ 594 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 595 IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 596 } 597 598 int 599 iwm_start_hw(struct iwm_softc *sc) 600 { 601 int error; 602 603 if ((error = iwm_prepare_card_hw(sc)) != 0) 604 return error; 605 606 /* Reset the entire device */ 607 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET); 608 DELAY(1000); 609 610 if ((error = iwm_apm_init(sc)) != 0) 611 return error; 612 613 iwm_enable_rfkill_int(sc); 614 iwm_check_rfkill(sc); 615 616 return 0; 617 } 618 619 void 620 iwm_set_pwr(struct iwm_softc *sc) 621 { 622 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 623 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC); 624 } 625 626 int 627 iwm_pcie_rx_stop(struct iwm_softc *sc) 628 { 629 int ret = 0; 630 if (iwm_nic_lock(sc)) { 631 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 632 ret = iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG, 633 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 634 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 635 1000); 636 iwm_nic_unlock(sc); 637 } 638 return ret; 639 } 640 641 void 642 iwm_pcie_clear_cmd_in_flight(struct iwm_softc *sc) 643 { 644 if (!sc->cfg->apmg_wake_up_wa) 645 return; 646 647 if (!sc->cmd_hold_nic_awake) { 648 device_printf(sc->sc_dev, 649 "%s: cmd_hold_nic_awake not set\n", __func__); 650 return; 651 } 652 653 sc->cmd_hold_nic_awake = 0; 654 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 655 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 656 } 657 658 int 659 iwm_pcie_set_cmd_in_flight(struct iwm_softc *sc) 660 { 661 int ret; 662 663 /* 664 * wake up the NIC to make sure that the firmware will see the host 665 * command - we will let the NIC sleep once all the host commands 666 * returned. This needs to be done only on NICs that have 667 * apmg_wake_up_wa set. 668 */ 669 if (sc->cfg->apmg_wake_up_wa && 670 !sc->cmd_hold_nic_awake) { 671 672 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 673 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 674 675 ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 676 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 677 (IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 678 IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 679 15000); 680 if (ret == 0) { 681 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 682 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 683 device_printf(sc->sc_dev, 684 "%s: Failed to wake NIC for hcmd\n", __func__); 685 return EIO; 686 } 687 sc->cmd_hold_nic_awake = 1; 688 } 689 690 return 0; 691 } 692