1 /*	$OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $	*/
2 
3 /*
4  * Copyright (c) 2014 genua mbh <info@genua.de>
5  * Copyright (c) 2014 Fixup Software Ltd.
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 /*-
21  * Based on BSD-licensed source modules in the Linux iwlwifi driver,
22  * which were used as the reference documentation for this implementation.
23  *
24  * Driver version we are currently based off of is
25  * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd)
26  *
27  ***********************************************************************
28  *
29  * This file is provided under a dual BSD/GPLv2 license.  When using or
30  * redistributing this file, you may do so under either license.
31  *
32  * GPL LICENSE SUMMARY
33  *
34  * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
35  *
36  * This program is free software; you can redistribute it and/or modify
37  * it under the terms of version 2 of the GNU General Public License as
38  * published by the Free Software Foundation.
39  *
40  * This program is distributed in the hope that it will be useful, but
41  * WITHOUT ANY WARRANTY; without even the implied warranty of
42  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
43  * General Public License for more details.
44  *
45  * You should have received a copy of the GNU General Public License
46  * along with this program; if not, write to the Free Software
47  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
48  * USA
49  *
50  * The full GNU General Public License is included in this distribution
51  * in the file called COPYING.
52  *
53  * Contact Information:
54  *  Intel Linux Wireless <ilw@linux.intel.com>
55  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
56  *
57  *
58  * BSD LICENSE
59  *
60  * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
61  * All rights reserved.
62  *
63  * Redistribution and use in source and binary forms, with or without
64  * modification, are permitted provided that the following conditions
65  * are met:
66  *
67  *  * Redistributions of source code must retain the above copyright
68  *    notice, this list of conditions and the following disclaimer.
69  *  * Redistributions in binary form must reproduce the above copyright
70  *    notice, this list of conditions and the following disclaimer in
71  *    the documentation and/or other materials provided with the
72  *    distribution.
73  *  * Neither the name Intel Corporation nor the names of its
74  *    contributors may be used to endorse or promote products derived
75  *    from this software without specific prior written permission.
76  *
77  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
78  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
79  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
80  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
81  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
82  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
83  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
84  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
85  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
86  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
87  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
88  */
89 
90 /*-
91  * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
92  *
93  * Permission to use, copy, modify, and distribute this software for any
94  * purpose with or without fee is hereby granted, provided that the above
95  * copyright notice and this permission notice appear in all copies.
96  *
97  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
98  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
99  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
100  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
101  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
102  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
103  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
104  */
105 #include <sys/cdefs.h>
106 __FBSDID("$FreeBSD$");
107 
108 #include <sys/param.h>
109 #include <sys/bus.h>
110 #include <sys/endian.h>
111 #include <sys/firmware.h>
112 #include <sys/kernel.h>
113 #include <sys/malloc.h>
114 #include <sys/mbuf.h>
115 #include <sys/rman.h>
116 #include <sys/sysctl.h>
117 #include <sys/linker.h>
118 
119 #include <machine/endian.h>
120 
121 #include <bus/pci/pcivar.h>
122 #include <bus/pci/pcireg.h>
123 
124 #include <net/bpf.h>
125 
126 #include <net/if.h>
127 #include <net/if_var.h>
128 #include <net/if_arp.h>
129 #include <net/if_dl.h>
130 #include <net/if_media.h>
131 #include <net/if_types.h>
132 
133 #include <netinet/in.h>
134 #include <netinet/in_systm.h>
135 #include <netinet/if_ether.h>
136 #include <netinet/ip.h>
137 
138 #include <netproto/802_11/ieee80211_var.h>
139 #include <netproto/802_11/ieee80211_regdomain.h>
140 #include <netproto/802_11/ieee80211_ratectl.h>
141 #include <netproto/802_11/ieee80211_radiotap.h>
142 
143 #include "if_iwmreg.h"
144 #include "if_iwmvar.h"
145 #include "if_iwm_debug.h"
146 #include "if_iwm_pcie_trans.h"
147 
148 /*
149  * This is a subset of what's in linux iwlwifi/pcie/trans.c.
150  * The rest can be migrated out into here once they're no longer in
151  * if_iwm.c.
152  */
153 
154 /*
155  * basic device access
156  */
157 
158 uint32_t
159 iwm_read_prph(struct iwm_softc *sc, uint32_t addr)
160 {
161 	IWM_WRITE(sc,
162 	    IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24)));
163 	IWM_BARRIER_READ_WRITE(sc);
164 	return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT);
165 }
166 
167 void
168 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val)
169 {
170 	IWM_WRITE(sc,
171 	    IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24)));
172 	IWM_BARRIER_WRITE(sc);
173 	IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val);
174 }
175 
176 #ifdef IWM_DEBUG
177 int
178 iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords)
179 {
180 	int offs, ret = 0;
181 	uint32_t *vals = buf;
182 
183 	if (iwm_nic_lock(sc)) {
184 		IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr);
185 		for (offs = 0; offs < dwords; offs++)
186 			vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT);
187 		iwm_nic_unlock(sc);
188 	} else {
189 		ret = EBUSY;
190 	}
191 	return ret;
192 }
193 #endif
194 
195 int
196 iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords)
197 {
198 	int offs;
199 	const uint32_t *vals = buf;
200 
201 	if (iwm_nic_lock(sc)) {
202 		IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr);
203 		/* WADDR auto-increments */
204 		for (offs = 0; offs < dwords; offs++) {
205 			uint32_t val = vals ? vals[offs] : 0;
206 			IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val);
207 		}
208 		iwm_nic_unlock(sc);
209 	} else {
210 		IWM_DPRINTF(sc, IWM_DEBUG_TRANS,
211 		    "%s: write_mem failed\n", __func__);
212 		return EBUSY;
213 	}
214 	return 0;
215 }
216 
217 int
218 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val)
219 {
220 	return iwm_write_mem(sc, addr, &val, 1);
221 }
222 
223 int
224 iwm_poll_bit(struct iwm_softc *sc, int reg,
225 	uint32_t bits, uint32_t mask, int timo)
226 {
227 	for (;;) {
228 		if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {
229 			return 1;
230 		}
231 		if (timo < 10) {
232 			return 0;
233 		}
234 		timo -= 10;
235 		DELAY(10);
236 	}
237 }
238 
239 int
240 iwm_nic_lock(struct iwm_softc *sc)
241 {
242 	int rv = 0;
243 
244 	IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
245 	    IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
246 
247 	if (sc->cfg->device_family == IWM_DEVICE_FAMILY_8000)
248 		DELAY(2);
249 
250 	if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
251 	    IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
252 	    IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
253 	     | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) {
254 		rv = 1;
255 	} else {
256 		/* jolt */
257 		IWM_DPRINTF(sc, IWM_DEBUG_RESET,
258 		    "%s: resetting device via NMI\n", __func__);
259 		IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI);
260 	}
261 
262 	return rv;
263 }
264 
265 void
266 iwm_nic_unlock(struct iwm_softc *sc)
267 {
268 	IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
269 	    IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
270 }
271 
272 void
273 iwm_set_bits_mask_prph(struct iwm_softc *sc,
274 	uint32_t reg, uint32_t bits, uint32_t mask)
275 {
276 	uint32_t val;
277 
278 	/* XXX: no error path? */
279 	if (iwm_nic_lock(sc)) {
280 		val = iwm_read_prph(sc, reg) & mask;
281 		val |= bits;
282 		iwm_write_prph(sc, reg, val);
283 		iwm_nic_unlock(sc);
284 	}
285 }
286 
287 void
288 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
289 {
290 	iwm_set_bits_mask_prph(sc, reg, bits, ~0);
291 }
292 
293 void
294 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
295 {
296 	iwm_set_bits_mask_prph(sc, reg, 0, ~bits);
297 }
298 
299 /*
300  * High-level hardware frobbing routines
301  */
302 
303 void
304 iwm_enable_rfkill_int(struct iwm_softc *sc)
305 {
306 	sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL;
307 	IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);
308 }
309 
310 int
311 iwm_check_rfkill(struct iwm_softc *sc)
312 {
313 	uint32_t v;
314 	int rv;
315 
316 	/*
317 	 * "documentation" is not really helpful here:
318 	 *  27:	HW_RF_KILL_SW
319 	 *	Indicates state of (platform's) hardware RF-Kill switch
320 	 *
321 	 * But apparently when it's off, it's on ...
322 	 */
323 	v = IWM_READ(sc, IWM_CSR_GP_CNTRL);
324 	rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0;
325 	if (rv) {
326 		sc->sc_flags |= IWM_FLAG_RFKILL;
327 	} else {
328 		sc->sc_flags &= ~IWM_FLAG_RFKILL;
329 	}
330 
331 	return rv;
332 }
333 
334 
335 #define IWM_HW_READY_TIMEOUT 50
336 int
337 iwm_set_hw_ready(struct iwm_softc *sc)
338 {
339 	int ready;
340 
341 	IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
342 	    IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
343 
344 	ready = iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG,
345 	    IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
346 	    IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
347 	    IWM_HW_READY_TIMEOUT);
348 	if (ready) {
349 		IWM_SETBITS(sc, IWM_CSR_MBOX_SET_REG,
350 		    IWM_CSR_MBOX_SET_REG_OS_ALIVE);
351 	}
352 	return ready;
353 }
354 #undef IWM_HW_READY_TIMEOUT
355 
356 int
357 iwm_prepare_card_hw(struct iwm_softc *sc)
358 {
359 	int rv = 0;
360 	int t = 0;
361 
362 	IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__);
363 	if (iwm_set_hw_ready(sc))
364 		goto out;
365 
366 	DELAY(100);
367 
368 	/* If HW is not ready, prepare the conditions to check again */
369 	IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
370 	    IWM_CSR_HW_IF_CONFIG_REG_PREPARE);
371 
372 	do {
373 		if (iwm_set_hw_ready(sc))
374 			goto out;
375 		DELAY(200);
376 		t += 200;
377 	} while (t < 150000);
378 
379 	rv = ETIMEDOUT;
380 
381  out:
382 	IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__);
383 	return rv;
384 }
385 
386 void
387 iwm_apm_config(struct iwm_softc *sc)
388 {
389 	uint16_t reg;
390 
391 #if defined(__DragonFly__)
392 	reg = pci_read_config(sc->sc_dev, PCIER_LINKCTRL, sizeof(reg));
393 	if (reg & PCIEM_LNKCTL_ASPM_L1)  {
394 #else
395 	reg = pci_read_config(sc->sc_dev, PCIER_LINK_CTL, sizeof(reg));
396 	if (reg & PCIEM_LINK_CTL_ASPMC_L1)  {
397 #endif
398 		/* Um the Linux driver prints "Disabling L0S for this one ... */
399 		IWM_SETBITS(sc, IWM_CSR_GIO_REG,
400 		    IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
401 	} else {
402 		/* ... and "Enabling" here */
403 		IWM_CLRBITS(sc, IWM_CSR_GIO_REG,
404 		    IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
405 	}
406 }
407 
408 /*
409  * Start up NIC's basic functionality after it has been reset
410  * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop())
411  * NOTE:  This does not load uCode nor start the embedded processor
412  */
413 int
414 iwm_apm_init(struct iwm_softc *sc)
415 {
416 	int error = 0;
417 
418 	IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n");
419 
420 	/* Disable L0S exit timer (platform NMI Work/Around) */
421 	if (sc->cfg->device_family != IWM_DEVICE_FAMILY_8000) {
422 		IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
423 		    IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
424 	}
425 
426 	/*
427 	 * Disable L0s without affecting L1;
428 	 *  don't wait for ICH L0s (ICH bug W/A)
429 	 */
430 	IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
431 	    IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
432 
433 	/* Set FH wait threshold to maximum (HW error during stress W/A) */
434 	IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL);
435 
436 	/*
437 	 * Enable HAP INTA (interrupt from management bus) to
438 	 * wake device's PCI Express link L1a -> L0s
439 	 */
440 	IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
441 	    IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
442 
443 	iwm_apm_config(sc);
444 
445 #if 0 /* not for 7k/8k */
446 	/* Configure analog phase-lock-loop before activating to D0A */
447 	if (trans->cfg->base_params->pll_cfg_val)
448 		IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG,
449 		    trans->cfg->base_params->pll_cfg_val);
450 #endif
451 
452 	/*
453 	 * Set "initialization complete" bit to move adapter from
454 	 * D0U* --> D0A* (powered-up active) state.
455 	 */
456 	IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
457 
458 	/*
459 	 * Wait for clock stabilization; once stabilized, access to
460 	 * device-internal resources is supported, e.g. iwm_write_prph()
461 	 * and accesses to uCode SRAM.
462 	 */
463 	if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
464 	    IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
465 	    IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) {
466 		device_printf(sc->sc_dev,
467 		    "timeout waiting for clock stabilization\n");
468 		error = ETIMEDOUT;
469 		goto out;
470 	}
471 
472 	if (sc->cfg->host_interrupt_operation_mode) {
473 		/*
474 		 * This is a bit of an abuse - This is needed for 7260 / 3160
475 		 * only check host_interrupt_operation_mode even if this is
476 		 * not related to host_interrupt_operation_mode.
477 		 *
478 		 * Enable the oscillator to count wake up time for L1 exit. This
479 		 * consumes slightly more power (100uA) - but allows to be sure
480 		 * that we wake up from L1 on time.
481 		 *
482 		 * This looks weird: read twice the same register, discard the
483 		 * value, set a bit, and yet again, read that same register
484 		 * just to discard the value. But that's the way the hardware
485 		 * seems to like it.
486 		 */
487 		iwm_read_prph(sc, IWM_OSC_CLK);
488 		iwm_read_prph(sc, IWM_OSC_CLK);
489 		iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL);
490 		iwm_read_prph(sc, IWM_OSC_CLK);
491 		iwm_read_prph(sc, IWM_OSC_CLK);
492 	}
493 
494 	/*
495 	 * Enable DMA clock and wait for it to stabilize.
496 	 *
497 	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
498 	 * do not disable clocks.  This preserves any hardware bits already
499 	 * set by default in "CLK_CTRL_REG" after reset.
500 	 */
501 	if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) {
502 		iwm_write_prph(sc, IWM_APMG_CLK_EN_REG,
503 		    IWM_APMG_CLK_VAL_DMA_CLK_RQT);
504 		DELAY(20);
505 
506 		/* Disable L1-Active */
507 		iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG,
508 		    IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
509 
510 		/* Clear the interrupt in APMG if the NIC is in RFKILL */
511 		iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG,
512 		    IWM_APMG_RTC_INT_STT_RFKILL);
513 	}
514  out:
515 	if (error)
516 		device_printf(sc->sc_dev, "apm init error %d\n", error);
517 	return error;
518 }
519 
520 void
521 iwm_apm_stop(struct iwm_softc *sc)
522 {
523 	IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__);
524 
525 	/* stop device's busmaster DMA activity */
526 	IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER);
527 
528 	if (!iwm_poll_bit(sc, IWM_CSR_RESET,
529 	    IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED,
530 	    IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100))
531 		device_printf(sc->sc_dev, "timeout waiting for master\n");
532 
533 	/* Reset the entire device */
534 	IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET);
535 	DELAY(1000);
536 
537 	/*
538 	 * Clear "initialization complete" bit to move adapter from
539 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
540 	 */
541 	IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
542 		    IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
543 }
544 
545 int
546 iwm_start_hw(struct iwm_softc *sc)
547 {
548 	int error;
549 
550 	if ((error = iwm_prepare_card_hw(sc)) != 0)
551 		return error;
552 
553 	/* Reset the entire device */
554 	IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET);
555 	DELAY(1000);
556 
557 	if ((error = iwm_apm_init(sc)) != 0)
558 		return error;
559 
560 	iwm_enable_rfkill_int(sc);
561 	iwm_check_rfkill(sc);
562 
563 	return 0;
564 }
565 
566 void
567 iwm_set_pwr(struct iwm_softc *sc)
568 {
569 	iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG,
570 	    IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC);
571 }
572 
573 int
574 iwm_pcie_rx_stop(struct iwm_softc *sc)
575 {
576 	int ret = 0;
577 	if (iwm_nic_lock(sc)) {
578 		IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
579 		ret = iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG,
580 		    IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
581 		    IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
582 		    1000);
583 		iwm_nic_unlock(sc);
584 	}
585 	return ret;
586 }
587