1 /* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2014 genua mbh <info@genua.de> 5 * Copyright (c) 2014 Fixup Software Ltd. 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 22 * which were used as the reference documentation for this implementation. 23 * 24 * Driver version we are currently based off of is 25 * Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd) 26 * 27 *********************************************************************** 28 * 29 * This file is provided under a dual BSD/GPLv2 license. When using or 30 * redistributing this file, you may do so under either license. 31 * 32 * GPL LICENSE SUMMARY 33 * 34 * Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved. 35 * 36 * This program is free software; you can redistribute it and/or modify 37 * it under the terms of version 2 of the GNU General Public License as 38 * published by the Free Software Foundation. 39 * 40 * This program is distributed in the hope that it will be useful, but 41 * WITHOUT ANY WARRANTY; without even the implied warranty of 42 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 43 * General Public License for more details. 44 * 45 * You should have received a copy of the GNU General Public License 46 * along with this program; if not, write to the Free Software 47 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 48 * USA 49 * 50 * The full GNU General Public License is included in this distribution 51 * in the file called COPYING. 52 * 53 * Contact Information: 54 * Intel Linux Wireless <ilw@linux.intel.com> 55 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 56 * 57 * 58 * BSD LICENSE 59 * 60 * Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved. 61 * All rights reserved. 62 * 63 * Redistribution and use in source and binary forms, with or without 64 * modification, are permitted provided that the following conditions 65 * are met: 66 * 67 * * Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * * Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in 71 * the documentation and/or other materials provided with the 72 * distribution. 73 * * Neither the name Intel Corporation nor the names of its 74 * contributors may be used to endorse or promote products derived 75 * from this software without specific prior written permission. 76 * 77 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 78 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 79 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 80 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 81 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 82 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 83 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 84 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 85 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 86 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 87 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 88 */ 89 90 /*- 91 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 92 * 93 * Permission to use, copy, modify, and distribute this software for any 94 * purpose with or without fee is hereby granted, provided that the above 95 * copyright notice and this permission notice appear in all copies. 96 * 97 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 98 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 99 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 100 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 101 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 102 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 103 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 104 */ 105 #include <sys/cdefs.h> 106 __FBSDID("$FreeBSD$"); 107 108 #include <sys/param.h> 109 #include <sys/bus.h> 110 #include <sys/endian.h> 111 #include <sys/firmware.h> 112 #include <sys/kernel.h> 113 #include <sys/malloc.h> 114 #include <sys/mbuf.h> 115 #include <sys/mutex.h> 116 #include <sys/module.h> 117 #include <sys/proc.h> 118 #include <sys/rman.h> 119 #include <sys/socket.h> 120 #include <sys/sockio.h> 121 #include <sys/sysctl.h> 122 #include <sys/linker.h> 123 124 #include <machine/endian.h> 125 126 #include <bus/pci/pcivar.h> 127 #include <bus/pci/pcireg.h> 128 129 #include <net/bpf.h> 130 131 #include <net/if.h> 132 #include <net/if_var.h> 133 #include <net/if_arp.h> 134 #include <net/if_dl.h> 135 #include <net/if_media.h> 136 #include <net/if_types.h> 137 138 #include <netinet/in.h> 139 #include <netinet/in_systm.h> 140 #include <netinet/if_ether.h> 141 #include <netinet/ip.h> 142 143 #include <netproto/802_11/ieee80211_var.h> 144 #include <netproto/802_11/ieee80211_regdomain.h> 145 #include <netproto/802_11/ieee80211_ratectl.h> 146 #include <netproto/802_11/ieee80211_radiotap.h> 147 148 #include "if_iwmreg.h" 149 #include "if_iwmvar.h" 150 #include "if_iwm_debug.h" 151 #include "if_iwm_pcie_trans.h" 152 153 /* 154 * This is a subset of what's in linux iwlwifi/pcie/trans.c. 155 * The rest can be migrated out into here once they're no longer in 156 * if_iwm.c. 157 */ 158 159 /* 160 * basic device access 161 */ 162 163 uint32_t 164 iwm_read_prph(struct iwm_softc *sc, uint32_t addr) 165 { 166 IWM_WRITE(sc, 167 IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24))); 168 IWM_BARRIER_READ_WRITE(sc); 169 return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT); 170 } 171 172 void 173 iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val) 174 { 175 IWM_WRITE(sc, 176 IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24))); 177 IWM_BARRIER_WRITE(sc); 178 IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val); 179 } 180 181 #ifdef IWM_DEBUG 182 int 183 iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) 184 { 185 int offs, ret = 0; 186 uint32_t *vals = buf; 187 188 if (iwm_nic_lock(sc)) { 189 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr); 190 for (offs = 0; offs < dwords; offs++) 191 vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT); 192 iwm_nic_unlock(sc); 193 } else { 194 ret = EBUSY; 195 } 196 return ret; 197 } 198 #endif 199 200 int 201 iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) 202 { 203 int offs; 204 const uint32_t *vals = buf; 205 206 if (iwm_nic_lock(sc)) { 207 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr); 208 /* WADDR auto-increments */ 209 for (offs = 0; offs < dwords; offs++) { 210 uint32_t val = vals ? vals[offs] : 0; 211 IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val); 212 } 213 iwm_nic_unlock(sc); 214 } else { 215 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, 216 "%s: write_mem failed\n", __func__); 217 return EBUSY; 218 } 219 return 0; 220 } 221 222 int 223 iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val) 224 { 225 return iwm_write_mem(sc, addr, &val, 1); 226 } 227 228 int 229 iwm_poll_bit(struct iwm_softc *sc, int reg, 230 uint32_t bits, uint32_t mask, int timo) 231 { 232 for (;;) { 233 if ((IWM_READ(sc, reg) & mask) == (bits & mask)) { 234 return 1; 235 } 236 if (timo < 10) { 237 return 0; 238 } 239 timo -= 10; 240 DELAY(10); 241 } 242 } 243 244 int 245 iwm_nic_lock(struct iwm_softc *sc) 246 { 247 int rv = 0; 248 249 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, 250 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 251 252 if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 253 IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 254 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY 255 | IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) { 256 rv = 1; 257 } else { 258 /* jolt */ 259 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI); 260 } 261 262 return rv; 263 } 264 265 void 266 iwm_nic_unlock(struct iwm_softc *sc) 267 { 268 IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL, 269 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 270 } 271 272 void 273 iwm_set_bits_mask_prph(struct iwm_softc *sc, 274 uint32_t reg, uint32_t bits, uint32_t mask) 275 { 276 uint32_t val; 277 278 /* XXX: no error path? */ 279 if (iwm_nic_lock(sc)) { 280 val = iwm_read_prph(sc, reg) & mask; 281 val |= bits; 282 iwm_write_prph(sc, reg, val); 283 iwm_nic_unlock(sc); 284 } 285 } 286 287 void 288 iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 289 { 290 iwm_set_bits_mask_prph(sc, reg, bits, ~0); 291 } 292 293 void 294 iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits) 295 { 296 iwm_set_bits_mask_prph(sc, reg, 0, ~bits); 297 } 298 299 /* 300 * High-level hardware frobbing routines 301 */ 302 303 void 304 iwm_enable_rfkill_int(struct iwm_softc *sc) 305 { 306 sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL; 307 IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask); 308 } 309 310 int 311 iwm_check_rfkill(struct iwm_softc *sc) 312 { 313 uint32_t v; 314 int rv; 315 316 /* 317 * "documentation" is not really helpful here: 318 * 27: HW_RF_KILL_SW 319 * Indicates state of (platform's) hardware RF-Kill switch 320 * 321 * But apparently when it's off, it's on ... 322 */ 323 v = IWM_READ(sc, IWM_CSR_GP_CNTRL); 324 rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0; 325 if (rv) { 326 sc->sc_flags |= IWM_FLAG_RFKILL; 327 } else { 328 sc->sc_flags &= ~IWM_FLAG_RFKILL; 329 } 330 331 return rv; 332 } 333 334 335 #define IWM_HW_READY_TIMEOUT 50 336 int 337 iwm_set_hw_ready(struct iwm_softc *sc) 338 { 339 int ready; 340 341 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 342 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 343 344 ready = iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG, 345 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 346 IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 347 IWM_HW_READY_TIMEOUT); 348 if (ready) { 349 IWM_SETBITS(sc, IWM_CSR_MBOX_SET_REG, 350 IWM_CSR_MBOX_SET_REG_OS_ALIVE); 351 } 352 return ready; 353 } 354 #undef IWM_HW_READY_TIMEOUT 355 356 int 357 iwm_prepare_card_hw(struct iwm_softc *sc) 358 { 359 int rv = 0; 360 int t = 0; 361 362 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__); 363 if (iwm_set_hw_ready(sc)) 364 goto out; 365 366 DELAY(100); 367 368 /* If HW is not ready, prepare the conditions to check again */ 369 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 370 IWM_CSR_HW_IF_CONFIG_REG_PREPARE); 371 372 do { 373 if (iwm_set_hw_ready(sc)) 374 goto out; 375 DELAY(200); 376 t += 200; 377 } while (t < 150000); 378 379 rv = ETIMEDOUT; 380 381 out: 382 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__); 383 return rv; 384 } 385 386 void 387 iwm_apm_config(struct iwm_softc *sc) 388 { 389 uint16_t reg; 390 391 #if defined(__DragonFly__) 392 reg = pci_read_config(sc->sc_dev, PCIER_LINKCTRL, sizeof(reg)); 393 if (reg & PCIEM_LNKCTL_ASPM_L1) { 394 #else 395 reg = pci_read_config(sc->sc_dev, PCIER_LINK_CTL, sizeof(reg)); 396 if (reg & PCIEM_LINK_CTL_ASPMC_L1) { 397 #endif 398 /* Um the Linux driver prints "Disabling L0S for this one ... */ 399 IWM_SETBITS(sc, IWM_CSR_GIO_REG, 400 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 401 } else { 402 /* ... and "Enabling" here */ 403 IWM_CLRBITS(sc, IWM_CSR_GIO_REG, 404 IWM_CSR_GIO_REG_VAL_L0S_ENABLED); 405 } 406 } 407 408 /* 409 * Start up NIC's basic functionality after it has been reset 410 * (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop()) 411 * NOTE: This does not load uCode nor start the embedded processor 412 */ 413 int 414 iwm_apm_init(struct iwm_softc *sc) 415 { 416 int error = 0; 417 418 IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n"); 419 420 /* Disable L0S exit timer (platform NMI Work/Around) */ 421 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 422 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 423 424 /* 425 * Disable L0s without affecting L1; 426 * don't wait for ICH L0s (ICH bug W/A) 427 */ 428 IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS, 429 IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 430 431 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 432 IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL); 433 434 /* 435 * Enable HAP INTA (interrupt from management bus) to 436 * wake device's PCI Express link L1a -> L0s 437 */ 438 IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, 439 IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 440 441 iwm_apm_config(sc); 442 443 #if 0 /* not for 7k */ 444 /* Configure analog phase-lock-loop before activating to D0A */ 445 if (trans->cfg->base_params->pll_cfg_val) 446 IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG, 447 trans->cfg->base_params->pll_cfg_val); 448 #endif 449 450 /* 451 * Set "initialization complete" bit to move adapter from 452 * D0U* --> D0A* (powered-up active) state. 453 */ 454 IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 455 456 /* 457 * Wait for clock stabilization; once stabilized, access to 458 * device-internal resources is supported, e.g. iwm_write_prph() 459 * and accesses to uCode SRAM. 460 */ 461 if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL, 462 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 463 IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) { 464 device_printf(sc->sc_dev, 465 "timeout waiting for clock stabilization\n"); 466 error = ETIMEDOUT; 467 goto out; 468 } 469 470 if (sc->host_interrupt_operation_mode) { 471 /* 472 * This is a bit of an abuse - This is needed for 7260 / 3160 473 * only check host_interrupt_operation_mode even if this is 474 * not related to host_interrupt_operation_mode. 475 * 476 * Enable the oscillator to count wake up time for L1 exit. This 477 * consumes slightly more power (100uA) - but allows to be sure 478 * that we wake up from L1 on time. 479 * 480 * This looks weird: read twice the same register, discard the 481 * value, set a bit, and yet again, read that same register 482 * just to discard the value. But that's the way the hardware 483 * seems to like it. 484 */ 485 iwm_read_prph(sc, IWM_OSC_CLK); 486 iwm_read_prph(sc, IWM_OSC_CLK); 487 iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL); 488 iwm_read_prph(sc, IWM_OSC_CLK); 489 iwm_read_prph(sc, IWM_OSC_CLK); 490 } 491 492 /* 493 * Enable DMA clock and wait for it to stabilize. 494 * 495 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits 496 * do not disable clocks. This preserves any hardware bits already 497 * set by default in "CLK_CTRL_REG" after reset. 498 */ 499 iwm_write_prph(sc, IWM_APMG_CLK_EN_REG, IWM_APMG_CLK_VAL_DMA_CLK_RQT); 500 //kpause("iwmapm", 0, mstohz(20), NULL); 501 DELAY(20); 502 503 /* Disable L1-Active */ 504 iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG, 505 IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 506 507 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 508 iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG, 509 IWM_APMG_RTC_INT_STT_RFKILL); 510 511 out: 512 if (error) 513 device_printf(sc->sc_dev, "apm init error %d\n", error); 514 return error; 515 } 516 517 void 518 iwm_apm_stop(struct iwm_softc *sc) 519 { 520 /* stop device's busmaster DMA activity */ 521 IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER); 522 523 if (!iwm_poll_bit(sc, IWM_CSR_RESET, 524 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 525 IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100)) 526 device_printf(sc->sc_dev, "timeout waiting for master\n"); 527 IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__); 528 } 529 530 int 531 iwm_start_hw(struct iwm_softc *sc) 532 { 533 int error; 534 535 if ((error = iwm_prepare_card_hw(sc)) != 0) 536 return error; 537 538 /* Reset the entire device */ 539 IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET); 540 DELAY(10); 541 542 if ((error = iwm_apm_init(sc)) != 0) 543 return error; 544 545 iwm_enable_rfkill_int(sc); 546 iwm_check_rfkill(sc); 547 548 return 0; 549 } 550 551 void 552 iwm_set_pwr(struct iwm_softc *sc) 553 { 554 iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG, 555 IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC); 556 } 557 558 int 559 iwm_pcie_rx_stop(struct iwm_softc *sc) 560 { 561 562 IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 563 return (iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG, 564 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 565 IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 566 1000)); 567 } 568