1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2 /* $FreeBSD$ */ 3 4 /****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * CSR (control and status registers) 74 * 75 * CSR registers are mapped directly into PCI bus space, and are accessible 76 * whenever platform supplies power to device, even when device is in 77 * low power states due to driver-invoked device resets 78 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 79 * 80 * Use iwl_write32() and iwl_read32() family to access these registers; 81 * these provide simple PCI bus access, without waking up the MAC. 82 * Do not use iwl_write_direct32() family for these registers; 83 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 84 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 85 * the CSR registers. 86 * 87 * NOTE: Device does need to be awake in order to read this memory 88 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 89 */ 90 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 91 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 92 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 93 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 94 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 95 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 96 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 97 #define IWM_CSR_GP_CNTRL (0x024) 98 99 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 100 #define IWM_CSR_INT_PERIODIC_REG (0x005) 101 102 /* 103 * Hardware revision info 104 * Bit fields: 105 * 31-16: Reserved 106 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 108 * 1-0: "Dash" (-) value, as in A-1, etc. 109 */ 110 #define IWM_CSR_HW_REV (0x028) 111 112 /* 113 * EEPROM and OTP (one-time-programmable) memory reads 114 * 115 * NOTE: Device must be awake, initialized via apm_ops.init(), 116 * in order to read. 117 */ 118 #define IWM_CSR_EEPROM_REG (0x02c) 119 #define IWM_CSR_EEPROM_GP (0x030) 120 #define IWM_CSR_OTP_GP_REG (0x034) 121 122 #define IWM_CSR_GIO_REG (0x03C) 123 #define IWM_CSR_GP_UCODE_REG (0x048) 124 #define IWM_CSR_GP_DRIVER_REG (0x050) 125 126 /* 127 * UCODE-DRIVER GP (general purpose) mailbox registers. 128 * SET/CLR registers set/clear bit(s) if "1" is written. 129 */ 130 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 131 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 132 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 133 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 134 135 #define IWM_CSR_MBOX_SET_REG (0x088) 136 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 137 138 #define IWM_CSR_LED_REG (0x094) 139 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 140 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 141 142 143 /* GIO Chicken Bits (PCI Express bus link power management) */ 144 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 145 146 /* Analog phase-lock-loop configuration */ 147 #define IWM_CSR_ANA_PLL_CFG (0x20c) 148 149 /* 150 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 151 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 152 * See also IWM_CSR_HW_REV register. 153 * Bit fields: 154 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 155 * 1-0: "Dash" (-) value, as in C-1, etc. 156 */ 157 #define IWM_CSR_HW_REV_WA_REG (0x22C) 158 159 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 160 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 161 162 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 163 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 164 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 166 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 167 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 171 172 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 173 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 178 179 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 180 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 183 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 184 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 186 187 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 188 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 189 190 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 191 * acknowledged (reset) by host writing "1" to flagged bits. */ 192 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 193 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 194 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 195 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 196 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 197 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 198 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 199 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 200 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 201 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 202 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 203 204 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 205 IWM_CSR_INT_BIT_HW_ERR | \ 206 IWM_CSR_INT_BIT_FH_TX | \ 207 IWM_CSR_INT_BIT_SW_ERR | \ 208 IWM_CSR_INT_BIT_RF_KILL | \ 209 IWM_CSR_INT_BIT_SW_RX | \ 210 IWM_CSR_INT_BIT_WAKEUP | \ 211 IWM_CSR_INT_BIT_ALIVE | \ 212 IWM_CSR_INT_BIT_RX_PERIODIC) 213 214 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 215 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 216 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 217 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 218 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 219 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 220 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 221 222 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 223 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 224 IWM_CSR_FH_INT_BIT_RX_CHNL0) 225 226 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 227 IWM_CSR_FH_INT_BIT_TX_CHNL0) 228 229 /* GPIO */ 230 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 231 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 232 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 233 234 /* RESET */ 235 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 236 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 237 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 238 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 239 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 240 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 241 242 /* 243 * GP (general purpose) CONTROL REGISTER 244 * Bit fields: 245 * 27: HW_RF_KILL_SW 246 * Indicates state of (platform's) hardware RF-Kill switch 247 * 26-24: POWER_SAVE_TYPE 248 * Indicates current power-saving mode: 249 * 000 -- No power saving 250 * 001 -- MAC power-down 251 * 010 -- PHY (radio) power-down 252 * 011 -- Error 253 * 9-6: SYS_CONFIG 254 * Indicates current system configuration, reflecting pins on chip 255 * as forced high/low by device circuit board. 256 * 4: GOING_TO_SLEEP 257 * Indicates MAC is entering a power-saving sleep power-down. 258 * Not a good time to access device-internal resources. 259 * 3: MAC_ACCESS_REQ 260 * Host sets this to request and maintain MAC wakeup, to allow host 261 * access to device-internal resources. Host must wait for 262 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 263 * device registers. 264 * 2: INIT_DONE 265 * Host sets this to put device into fully operational D0 power mode. 266 * Host resets this after SW_RESET to put device into low power mode. 267 * 0: MAC_CLOCK_READY 268 * Indicates MAC (ucode processor, etc.) is powered up and can run. 269 * Internal resources are accessible. 270 * NOTE: This does not indicate that the processor is actually running. 271 * NOTE: This does not indicate that device has completed 272 * init or post-power-down restore of internal SRAM memory. 273 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 274 * SRAM is restored and uCode is in normal operation mode. 275 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 276 * do not need to save/restore it. 277 * NOTE: After device reset, this bit remains "0" until host sets 278 * INIT_DONE 279 */ 280 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 281 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 283 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 284 285 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 286 287 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 288 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 289 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 290 291 292 /* HW REV */ 293 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 294 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 295 296 /** 297 * hw_rev values 298 */ 299 enum { 300 IWM_SILICON_A_STEP = 0, 301 IWM_SILICON_B_STEP, 302 IWM_SILICON_C_STEP, 303 }; 304 305 306 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 307 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 308 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 309 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 310 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 311 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 312 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 313 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 314 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 315 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 316 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 317 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 318 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 319 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 320 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 321 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 322 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 323 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 324 325 /* EEPROM REG */ 326 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 327 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 328 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 329 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 330 331 /* EEPROM GP */ 332 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 333 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 334 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 335 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 336 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 337 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 338 339 /* One-time-programmable memory general purpose reg */ 340 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 341 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 342 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 343 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 344 345 /* GP REG */ 346 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 347 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 348 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 349 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 350 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 351 352 353 /* CSR GIO */ 354 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 355 356 /* 357 * UCODE-DRIVER GP (general purpose) mailbox register 1 358 * Host driver and uCode write and/or read this register to communicate with 359 * each other. 360 * Bit fields: 361 * 4: UCODE_DISABLE 362 * Host sets this to request permanent halt of uCode, same as 363 * sending CARD_STATE command with "halt" bit set. 364 * 3: CT_KILL_EXIT 365 * Host sets this to request exit from CT_KILL state, i.e. host thinks 366 * device temperature is low enough to continue normal operation. 367 * 2: CMD_BLOCKED 368 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 369 * to release uCode to clear all Tx and command queues, enter 370 * unassociated mode, and power down. 371 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 372 * 1: SW_BIT_RFKILL 373 * Host sets this when issuing CARD_STATE command to request 374 * device sleep. 375 * 0: MAC_SLEEP 376 * uCode sets this when preparing a power-saving power-down. 377 * uCode resets this when power-up is complete and SRAM is sane. 378 * NOTE: device saves internal SRAM data to host when powering down, 379 * and must restore this data after powering back up. 380 * MAC_SLEEP is the best indication that restore is complete. 381 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 382 * do not need to save/restore it. 383 */ 384 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 385 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 386 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 387 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 388 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 389 390 /* GP Driver */ 391 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 392 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 393 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 394 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 395 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 396 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 397 398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 399 400 /* GIO Chicken Bits (PCI Express bus link power management) */ 401 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 402 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 403 404 /* LED */ 405 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 406 #define IWM_CSR_LED_REG_TURN_ON (0x60) 407 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 408 409 /* ANA_PLL */ 410 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 411 412 /* HPET MEM debug */ 413 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 414 415 /* DRAM INT TABLE */ 416 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 417 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 418 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 419 420 /* SECURE boot registers */ 421 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 422 enum iwm_secure_boot_config_reg { 423 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 424 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 425 }; 426 427 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 428 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 429 enum iwm_secure_boot_status_reg { 430 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 431 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 432 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 433 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 435 }; 436 437 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 438 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 439 440 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 441 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 442 443 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 444 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 445 446 #define IWM_CSR_SECURE_TIME_OUT (100) 447 448 /* extended range in FW SRAM */ 449 #define IWM_FW_MEM_EXTENDED_START 0x40000 450 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 451 452 /* FW chicken bits */ 453 #define IWM_LMPM_CHICK 0xa01ff8 454 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 455 456 #define IWM_FH_TCSR_0_REG0 (0x1D00) 457 458 /* 459 * HBUS (Host-side Bus) 460 * 461 * HBUS registers are mapped directly into PCI bus space, but are used 462 * to indirectly access device's internal memory or registers that 463 * may be powered-down. 464 * 465 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 466 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 467 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 468 * internal resources. 469 * 470 * Do not use iwl_write32()/iwl_read32() family to access these registers; 471 * these provide only simple PCI bus access, without waking up the MAC. 472 */ 473 #define IWM_HBUS_BASE (0x400) 474 475 /* 476 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 477 * structures, error log, event log, verifying uCode load). 478 * First write to address register, then read from or write to data register 479 * to complete the job. Once the address register is set up, accesses to 480 * data registers auto-increment the address by one dword. 481 * Bit usage for address registers (read or write): 482 * 0-31: memory address within device 483 */ 484 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 485 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 486 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 487 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 488 489 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 490 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 491 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 492 493 /* 494 * Registers for accessing device's internal peripheral registers 495 * (e.g. SCD, BSM, etc.). First write to address register, 496 * then read from or write to data register to complete the job. 497 * Bit usage for address registers (read or write): 498 * 0-15: register address (offset) within device 499 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 500 */ 501 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 502 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 503 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 504 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 505 506 /* enable the ID buf for read */ 507 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 508 #define IWM_WFMP_MAC_ADDR_0 0xa03080 509 #define IWM_WFMP_MAC_ADDR_1 0xa03084 510 #define IWM_LMPM_PMG_EN 0xa01cec 511 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 512 #define IWM_RFIC_REG_RD 0xad0470 513 #define IWM_WFPM_CTRL_REG 0xa03030 514 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 515 #define IWM_ENABLE_WFPM 0x80000000 516 517 #define IWM_AUX_MISC_REG 0xa200b0 518 #define IWM_HW_STEP_LOCATION_BITS 24 519 520 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 521 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 522 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 523 #define IWM_RSA_ENABLE 0xa24b08 524 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 525 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 526 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 527 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 528 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 529 #define IWM_SB_CPU_1_STATUS 0xa01e30 530 #define IWM_SB_CPU_2_STATUS 0Xa01e34 531 532 /* Used to enable DBGM */ 533 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 534 535 /* 536 * Per-Tx-queue write pointer (index, really!) 537 * Indicates index to next TFD that driver will fill (1 past latest filled). 538 * Bit usage: 539 * 0-7: queue write index 540 * 11-8: queue selector 541 */ 542 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 543 544 /********************************************************** 545 * CSR values 546 **********************************************************/ 547 /* 548 * host interrupt timeout value 549 * used with setting interrupt coalescing timer 550 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 551 * 552 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 553 */ 554 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 555 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 556 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 557 #define IWM_HOST_INT_OPER_MODE (1 << 31) 558 559 /***************************************************************************** 560 * 7000/3000 series SHR DTS addresses * 561 *****************************************************************************/ 562 563 /* Diode Results Register Structure: */ 564 enum iwm_dtd_diode_reg { 565 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 566 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 567 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 568 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 569 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 570 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 571 /* Those are the masks INSIDE the flags bit-field: */ 572 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 573 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 574 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 575 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 576 }; 577 578 /** 579 * enum iwm_ucode_tlv_flag - ucode API flags 580 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 581 * was a separate TLV but moved here to save space. 582 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 583 * treats good CRC threshold as a boolean 584 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 585 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 586 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 587 * offload profile config command. 588 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 589 * (rather than two) IPv6 addresses 590 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 591 * from the probe request template. 592 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 593 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 594 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 595 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 596 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 597 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 598 */ 599 enum iwm_ucode_tlv_flag { 600 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 601 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 602 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 603 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 604 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 605 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 606 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 607 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 608 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 609 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 610 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 611 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 612 }; 613 614 #define IWM_UCODE_TLV_FLAG_BITS \ 615 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 616 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 617 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 618 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 619 620 /** 621 * enum iwm_ucode_tlv_api - ucode api 622 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 623 * longer than the passive one, which is essential for fragmented scan. 624 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 625 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 626 * 627 * @IWM_NUM_UCODE_TLV_API: number of bits used 628 */ 629 enum iwm_ucode_tlv_api { 630 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8, 631 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9, 632 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18, 633 634 IWM_NUM_UCODE_TLV_API = 32 635 }; 636 637 #define IWM_UCODE_TLV_API_BITS \ 638 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 639 640 /** 641 * enum iwm_ucode_tlv_capa - ucode capabilities 642 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 643 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 644 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 645 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 646 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 647 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 648 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 649 * tx power value into TPC Report action frame and Link Measurement Report 650 * action frame 651 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 652 * channel in DS parameter set element in probe requests. 653 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 654 * probe requests. 655 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 656 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 657 * which also implies support for the scheduler configuration command 658 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 659 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 660 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 661 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 662 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 663 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 664 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 665 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 666 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 667 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 668 * sources for the MCC. This TLV bit is a future replacement to 669 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 670 * is supported. 671 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 672 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 673 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 674 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 675 * 0=no support) 676 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 677 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 678 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 679 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 680 * antenna the beacon should be transmitted 681 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 682 * from AP and will send it upon d0i3 exit. 683 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 684 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 685 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 686 * thresholds reporting 687 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 688 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 689 * regular image. 690 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 691 * memory addresses from the firmware. 692 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 693 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 694 * 0=no support) 695 * 696 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 697 */ 698 enum iwm_ucode_tlv_capa { 699 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 700 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 701 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 702 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 703 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 704 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 705 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 706 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 707 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 708 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 709 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 710 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 711 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 712 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 713 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 714 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 715 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 716 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 717 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 718 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 719 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 720 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 721 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 722 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 723 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 724 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 725 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 726 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 727 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 728 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 729 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 730 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 731 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 732 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 733 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 734 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 735 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 736 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 737 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 738 739 IWM_NUM_UCODE_TLV_CAPA = 128 740 }; 741 742 /* The default calibrate table size if not specified by firmware file */ 743 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 744 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 745 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 746 747 /* The default max probe length if not specified by the firmware file */ 748 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 749 750 /* 751 * enumeration of ucode section. 752 * This enumeration is used directly for older firmware (before 16.0). 753 * For new firmware, there can be up to 4 sections (see below) but the 754 * first one packaged into the firmware file is the DATA section and 755 * some debugging code accesses that. 756 */ 757 enum iwm_ucode_sec { 758 IWM_UCODE_SECTION_DATA, 759 IWM_UCODE_SECTION_INST, 760 }; 761 /* 762 * For 16.0 uCode and above, there is no differentiation between sections, 763 * just an offset to the HW address. 764 */ 765 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 766 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 767 768 /* uCode version contains 4 values: Major/Minor/API/Serial */ 769 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 770 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 771 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 772 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 773 774 /* 775 * Calibration control struct. 776 * Sent as part of the phy configuration command. 777 * @flow_trigger: bitmap for which calibrations to perform according to 778 * flow triggers. 779 * @event_trigger: bitmap for which calibrations to perform according to 780 * event triggers. 781 */ 782 struct iwm_tlv_calib_ctrl { 783 uint32_t flow_trigger; 784 uint32_t event_trigger; 785 } __packed; 786 787 enum iwm_fw_phy_cfg { 788 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 789 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 790 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 791 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 792 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 793 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 794 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 795 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 796 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 797 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 798 }; 799 800 #define IWM_UCODE_MAX_CS 1 801 802 /** 803 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 804 * @cipher: a cipher suite selector 805 * @flags: cipher scheme flags (currently reserved for a future use) 806 * @hdr_len: a size of MPDU security header 807 * @pn_len: a size of PN 808 * @pn_off: an offset of pn from the beginning of the security header 809 * @key_idx_off: an offset of key index byte in the security header 810 * @key_idx_mask: a bit mask of key_idx bits 811 * @key_idx_shift: bit shift needed to get key_idx 812 * @mic_len: mic length in bytes 813 * @hw_cipher: a HW cipher index used in host commands 814 */ 815 struct iwm_fw_cipher_scheme { 816 uint32_t cipher; 817 uint8_t flags; 818 uint8_t hdr_len; 819 uint8_t pn_len; 820 uint8_t pn_off; 821 uint8_t key_idx_off; 822 uint8_t key_idx_mask; 823 uint8_t key_idx_shift; 824 uint8_t mic_len; 825 uint8_t hw_cipher; 826 } __packed; 827 828 /** 829 * struct iwm_fw_cscheme_list - a cipher scheme list 830 * @size: a number of entries 831 * @cs: cipher scheme entries 832 */ 833 struct iwm_fw_cscheme_list { 834 uint8_t size; 835 struct iwm_fw_cipher_scheme cs[]; 836 } __packed; 837 838 /* v1/v2 uCode file layout */ 839 struct iwm_ucode_header { 840 uint32_t ver; /* major/minor/API/serial */ 841 union { 842 struct { 843 uint32_t inst_size; /* bytes of runtime code */ 844 uint32_t data_size; /* bytes of runtime data */ 845 uint32_t init_size; /* bytes of init code */ 846 uint32_t init_data_size; /* bytes of init data */ 847 uint32_t boot_size; /* bytes of bootstrap code */ 848 uint8_t data[0]; /* in same order as sizes */ 849 } v1; 850 struct { 851 uint32_t build; /* build number */ 852 uint32_t inst_size; /* bytes of runtime code */ 853 uint32_t data_size; /* bytes of runtime data */ 854 uint32_t init_size; /* bytes of init code */ 855 uint32_t init_data_size; /* bytes of init data */ 856 uint32_t boot_size; /* bytes of bootstrap code */ 857 uint8_t data[0]; /* in same order as sizes */ 858 } v2; 859 } u; 860 }; 861 862 /* 863 * new TLV uCode file layout 864 * 865 * The new TLV file format contains TLVs, that each specify 866 * some piece of data. 867 */ 868 869 enum iwm_ucode_tlv_type { 870 IWM_UCODE_TLV_INVALID = 0, /* unused */ 871 IWM_UCODE_TLV_INST = 1, 872 IWM_UCODE_TLV_DATA = 2, 873 IWM_UCODE_TLV_INIT = 3, 874 IWM_UCODE_TLV_INIT_DATA = 4, 875 IWM_UCODE_TLV_BOOT = 5, 876 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 877 IWM_UCODE_TLV_PAN = 7, 878 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 879 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 880 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 881 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 882 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 883 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 884 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 885 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 886 IWM_UCODE_TLV_WOWLAN_INST = 16, 887 IWM_UCODE_TLV_WOWLAN_DATA = 17, 888 IWM_UCODE_TLV_FLAGS = 18, 889 IWM_UCODE_TLV_SEC_RT = 19, 890 IWM_UCODE_TLV_SEC_INIT = 20, 891 IWM_UCODE_TLV_SEC_WOWLAN = 21, 892 IWM_UCODE_TLV_DEF_CALIB = 22, 893 IWM_UCODE_TLV_PHY_SKU = 23, 894 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 895 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 896 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 897 IWM_UCODE_TLV_NUM_OF_CPU = 27, 898 IWM_UCODE_TLV_CSCHEME = 28, 899 900 /* 901 * Following two are not in our base tag, but allow 902 * handling ucode version 9. 903 */ 904 IWM_UCODE_TLV_API_CHANGES_SET = 29, 905 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 906 907 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 908 IWM_UCODE_TLV_PAGING = 32, 909 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 910 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 911 IWM_UCODE_TLV_FW_VERSION = 36, 912 IWM_UCODE_TLV_FW_DBG_DEST = 38, 913 IWM_UCODE_TLV_FW_DBG_CONF = 39, 914 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 915 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 916 IWM_UCODE_TLV_FW_MEM_SEG = 51, 917 }; 918 919 struct iwm_ucode_tlv { 920 uint32_t type; /* see above */ 921 uint32_t length; /* not including type/length fields */ 922 uint8_t data[0]; 923 }; 924 925 struct iwm_ucode_api { 926 uint32_t api_index; 927 uint32_t api_flags; 928 } __packed; 929 930 struct iwm_ucode_capa { 931 uint32_t api_index; 932 uint32_t api_capa; 933 } __packed; 934 935 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 936 937 struct iwm_tlv_ucode_header { 938 /* 939 * The TLV style ucode header is distinguished from 940 * the v1/v2 style header by first four bytes being 941 * zero, as such is an invalid combination of 942 * major/minor/API/serial versions. 943 */ 944 uint32_t zero; 945 uint32_t magic; 946 uint8_t human_readable[64]; 947 uint32_t ver; /* major/minor/API/serial */ 948 uint32_t build; 949 uint64_t ignore; 950 /* 951 * The data contained herein has a TLV layout, 952 * see above for the TLV header and types. 953 * Note that each TLV is padded to a length 954 * that is a multiple of 4 for alignment. 955 */ 956 uint8_t data[0]; 957 }; 958 959 /* 960 * Registers in this file are internal, not PCI bus memory mapped. 961 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 962 */ 963 #define IWM_PRPH_BASE (0x00000) 964 #define IWM_PRPH_END (0xFFFFF) 965 966 /* APMG (power management) constants */ 967 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 968 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 969 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 970 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 971 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 972 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 973 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 974 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 975 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 976 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 977 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 978 979 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 980 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 981 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 982 983 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 984 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 985 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 986 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 987 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 988 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 989 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 990 991 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 992 993 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 994 995 /* Device system time */ 996 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 997 998 /* Device NMI register */ 999 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1000 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1001 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1002 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1003 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1004 1005 /* 1006 * Device reset for family 8000 1007 * write to bit 24 in order to reset the CPU 1008 */ 1009 #define IWM_RELEASE_CPU_RESET 0x300c 1010 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1011 1012 1013 /***************************************************************************** 1014 * 7000/3000 series SHR DTS addresses * 1015 *****************************************************************************/ 1016 1017 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1018 #define IWM_DTSC_CFG_MODE (0x00a10604) 1019 #define IWM_DTSC_VREF_AVG (0x00a10648) 1020 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1021 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1022 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1023 1024 1025 /** 1026 * Tx Scheduler 1027 * 1028 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1029 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1030 * host DRAM. It steers each frame's Tx command (which contains the frame 1031 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1032 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1033 * but one DMA channel may take input from several queues. 1034 * 1035 * Tx DMA FIFOs have dedicated purposes. 1036 * 1037 * For 5000 series and up, they are used differently 1038 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1039 * 1040 * 0 -- EDCA BK (background) frames, lowest priority 1041 * 1 -- EDCA BE (best effort) frames, normal priority 1042 * 2 -- EDCA VI (video) frames, higher priority 1043 * 3 -- EDCA VO (voice) and management frames, highest priority 1044 * 4 -- unused 1045 * 5 -- unused 1046 * 6 -- unused 1047 * 7 -- Commands 1048 * 1049 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1050 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1051 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1052 * 1053 * The driver sets up each queue to work in one of two modes: 1054 * 1055 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1056 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1057 * contains TFDs for a unique combination of Recipient Address (RA) 1058 * and Traffic Identifier (TID), that is, traffic of a given 1059 * Quality-Of-Service (QOS) priority, destined for a single station. 1060 * 1061 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1062 * each frame within the BA window, including whether it's been transmitted, 1063 * and whether it's been acknowledged by the receiving station. The device 1064 * automatically processes block-acks received from the receiving STA, 1065 * and reschedules un-acked frames to be retransmitted (successful 1066 * Tx completion may end up being out-of-order). 1067 * 1068 * The driver must maintain the queue's Byte Count table in host DRAM 1069 * for this mode. 1070 * This mode does not support fragmentation. 1071 * 1072 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1073 * The device may automatically retry Tx, but will retry only one frame 1074 * at a time, until receiving ACK from receiving station, or reaching 1075 * retry limit and giving up. 1076 * 1077 * The command queue (#4/#9) must use this mode! 1078 * This mode does not require use of the Byte Count table in host DRAM. 1079 * 1080 * Driver controls scheduler operation via 3 means: 1081 * 1) Scheduler registers 1082 * 2) Shared scheduler data base in internal SRAM 1083 * 3) Shared data in host DRAM 1084 * 1085 * Initialization: 1086 * 1087 * When loading, driver should allocate memory for: 1088 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1089 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1090 * (1024 bytes for each queue). 1091 * 1092 * After receiving "Alive" response from uCode, driver must initialize 1093 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1094 * the driver can't issue commands!): 1095 */ 1096 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1097 1098 /** 1099 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1100 * can keep track of at one time when creating block-ack chains of frames. 1101 * Note that "64" matches the number of ack bits in a block-ack packet. 1102 */ 1103 #define IWM_SCD_WIN_SIZE 64 1104 #define IWM_SCD_FRAME_LIMIT 64 1105 1106 #define IWM_SCD_TXFIFO_POS_TID (0) 1107 #define IWM_SCD_TXFIFO_POS_RA (4) 1108 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1109 1110 /* agn SCD */ 1111 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1112 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1113 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1114 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1115 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1116 1117 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1118 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1119 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1120 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1121 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1122 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1123 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1124 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1125 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1126 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1127 1128 /* Context Data */ 1129 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1130 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1131 1132 /* Tx status */ 1133 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1134 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1135 1136 /* Translation Data */ 1137 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1138 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1139 1140 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1141 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1142 1143 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1144 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1145 1146 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1147 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1148 1149 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1150 1151 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1152 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1153 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1154 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1155 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1156 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1157 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1158 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1159 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1160 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1161 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1162 1163 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1164 { 1165 if (chnl < 20) 1166 return IWM_SCD_BASE + 0x18 + chnl * 4; 1167 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1168 } 1169 1170 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1171 { 1172 if (chnl < 20) 1173 return IWM_SCD_BASE + 0x68 + chnl * 4; 1174 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1175 } 1176 1177 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1178 { 1179 if (chnl < 20) 1180 return IWM_SCD_BASE + 0x10c + chnl * 4; 1181 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1182 } 1183 1184 /*********************** END TX SCHEDULER *************************************/ 1185 1186 /* Oscillator clock */ 1187 #define IWM_OSC_CLK (0xa04068) 1188 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1189 1190 /****************************/ 1191 /* Flow Handler Definitions */ 1192 /****************************/ 1193 1194 /** 1195 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1196 * Addresses are offsets from device's PCI hardware base address. 1197 */ 1198 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1199 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1200 1201 /** 1202 * Keep-Warm (KW) buffer base address. 1203 * 1204 * Driver must allocate a 4KByte buffer that is for keeping the 1205 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1206 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1207 * from going into a power-savings mode that would cause higher DRAM latency, 1208 * and possible data over/under-runs, before all Tx/Rx is complete. 1209 * 1210 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1211 * of the buffer, which must be 4K aligned. Once this is set up, the device 1212 * automatically invokes keep-warm accesses when normal accesses might not 1213 * be sufficient to maintain fast DRAM response. 1214 * 1215 * Bit fields: 1216 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1217 */ 1218 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1219 1220 1221 /** 1222 * TFD Circular Buffers Base (CBBC) addresses 1223 * 1224 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1225 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1226 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1227 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1228 * aligned (address bits 0-7 must be 0). 1229 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1230 * for them are in different places. 1231 * 1232 * Bit fields in each pointer register: 1233 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1234 */ 1235 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1236 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1237 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1238 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1239 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1240 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1241 1242 /* Find TFD CB base pointer for given queue */ 1243 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1244 { 1245 if (chnl < 16) 1246 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1247 if (chnl < 20) 1248 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1249 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1250 } 1251 1252 1253 /** 1254 * Rx SRAM Control and Status Registers (RSCSR) 1255 * 1256 * These registers provide handshake between driver and device for the Rx queue 1257 * (this queue handles *all* command responses, notifications, Rx data, etc. 1258 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1259 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1260 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1261 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1262 * mapping between RBDs and RBs. 1263 * 1264 * Driver must allocate host DRAM memory for the following, and set the 1265 * physical address of each into device registers: 1266 * 1267 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1268 * entries (although any power of 2, up to 4096, is selectable by driver). 1269 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1270 * (typically 4K, although 8K or 16K are also selectable by driver). 1271 * Driver sets up RB size and number of RBDs in the CB via Rx config 1272 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1273 * 1274 * Bit fields within one RBD: 1275 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1276 * 1277 * Driver sets physical address [35:8] of base of RBD circular buffer 1278 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1279 * 1280 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1281 * (RBs) have been filled, via a "write pointer", actually the index of 1282 * the RB's corresponding RBD within the circular buffer. Driver sets 1283 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1284 * 1285 * Bit fields in lower dword of Rx status buffer (upper dword not used 1286 * by driver: 1287 * 31-12: Not used by driver 1288 * 11- 0: Index of last filled Rx buffer descriptor 1289 * (device writes, driver reads this value) 1290 * 1291 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1292 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1293 * and update the device's "write" index register, 1294 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1295 * 1296 * This "write" index corresponds to the *next* RBD that the driver will make 1297 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1298 * the circular buffer. This value should initially be 0 (before preparing any 1299 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1300 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1301 * "read" index has advanced past 1! See below). 1302 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1303 * 1304 * As the device fills RBs (referenced from contiguous RBDs within the circular 1305 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1306 * to tell the driver the index of the latest filled RBD. The driver must 1307 * read this "read" index from DRAM after receiving an Rx interrupt from device 1308 * 1309 * The driver must also internally keep track of a third index, which is the 1310 * next RBD to process. When receiving an Rx interrupt, driver should process 1311 * all filled but unprocessed RBs up to, but not including, the RB 1312 * corresponding to the "read" index. For example, if "read" index becomes "1", 1313 * driver may process the RB pointed to by RBD 0. Depending on volume of 1314 * traffic, there may be many RBs to process. 1315 * 1316 * If read index == write index, device thinks there is no room to put new data. 1317 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1318 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1319 * and "read" indexes; that is, make sure that there are no more than 254 1320 * buffers waiting to be filled. 1321 */ 1322 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1323 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1324 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1325 1326 /** 1327 * Physical base address of 8-byte Rx Status buffer. 1328 * Bit fields: 1329 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1330 */ 1331 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1332 1333 /** 1334 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1335 * Bit fields: 1336 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1337 */ 1338 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1339 1340 /** 1341 * Rx write pointer (index, really!). 1342 * Bit fields: 1343 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1344 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1345 */ 1346 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1347 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1348 1349 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1350 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1351 1352 /** 1353 * Rx Config/Status Registers (RCSR) 1354 * Rx Config Reg for channel 0 (only channel used) 1355 * 1356 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1357 * normal operation (see bit fields). 1358 * 1359 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1360 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1361 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1362 * 1363 * Bit fields: 1364 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1365 * '10' operate normally 1366 * 29-24: reserved 1367 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1368 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1369 * 19-18: reserved 1370 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1371 * '10' 12K, '11' 16K. 1372 * 15-14: reserved 1373 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1374 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1375 * typical value 0x10 (about 1/2 msec) 1376 * 3- 0: reserved 1377 */ 1378 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1379 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1380 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1381 1382 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1383 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1384 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1385 1386 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1387 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1388 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1389 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1390 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1391 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1392 1393 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1394 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1395 #define IWM_RX_RB_TIMEOUT (0x11) 1396 1397 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1398 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1399 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1400 1401 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1402 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1403 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1404 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1405 1406 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1407 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1408 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1409 1410 /** 1411 * Rx Shared Status Registers (RSSR) 1412 * 1413 * After stopping Rx DMA channel (writing 0 to 1414 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1415 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1416 * 1417 * Bit fields: 1418 * 24: 1 = Channel 0 is idle 1419 * 1420 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1421 * contain default values that should not be altered by the driver. 1422 */ 1423 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1424 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1425 1426 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1427 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1428 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1429 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1430 1431 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1432 1433 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1434 1435 /* TFDB Area - TFDs buffer table */ 1436 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1437 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1438 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1439 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1440 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1441 1442 /** 1443 * Transmit DMA Channel Control/Status Registers (TCSR) 1444 * 1445 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1446 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1447 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1448 * 1449 * To use a Tx DMA channel, driver must initialize its 1450 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1451 * 1452 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1453 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1454 * 1455 * All other bits should be 0. 1456 * 1457 * Bit fields: 1458 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1459 * '10' operate normally 1460 * 29- 4: Reserved, set to "0" 1461 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1462 * 2- 0: Reserved, set to "0" 1463 */ 1464 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1465 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1466 1467 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1468 #define IWM_FH_TCSR_CHNL_NUM (8) 1469 1470 /* TCSR: tx_config register values */ 1471 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1472 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1473 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1474 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1475 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1476 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1477 1478 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1479 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1480 1481 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1482 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1483 1484 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1485 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1486 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1487 1488 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1489 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1490 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1491 1492 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1493 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1494 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1495 1496 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1497 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1498 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1499 1500 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1501 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1502 1503 /** 1504 * Tx Shared Status Registers (TSSR) 1505 * 1506 * After stopping Tx DMA channel (writing 0 to 1507 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1508 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1509 * (channel's buffers empty | no pending requests). 1510 * 1511 * Bit fields: 1512 * 31-24: 1 = Channel buffers empty (channel 7:0) 1513 * 23-16: 1 = No pending requests (channel 7:0) 1514 */ 1515 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1516 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1517 1518 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1519 1520 /** 1521 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1522 * 31: Indicates an address error when accessed to internal memory 1523 * uCode/driver must write "1" in order to clear this flag 1524 * 30: Indicates that Host did not send the expected number of dwords to FH 1525 * uCode/driver must write "1" in order to clear this flag 1526 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1527 * command was received from the scheduler while the TRB was already full 1528 * with previous command 1529 * uCode/driver must write "1" in order to clear this flag 1530 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1531 * bit is set, it indicates that the FH has received a full indication 1532 * from the RTC TxFIFO and the current value of the TxCredit counter was 1533 * not equal to zero. This mean that the credit mechanism was not 1534 * synchronized to the TxFIFO status 1535 * uCode/driver must write "1" in order to clear this flag 1536 */ 1537 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1538 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1539 1540 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1541 1542 /* Tx service channels */ 1543 #define IWM_FH_SRVC_CHNL (9) 1544 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1545 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1546 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1547 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1548 1549 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1550 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1551 (_chan) * 4) 1552 1553 /* Instruct FH to increment the retry count of a packet when 1554 * it is brought from the memory to TX-FIFO 1555 */ 1556 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1557 1558 #define IWM_RX_QUEUE_SIZE 256 1559 #define IWM_RX_QUEUE_MASK 255 1560 #define IWM_RX_QUEUE_SIZE_LOG 8 1561 1562 /* 1563 * RX related structures and functions 1564 */ 1565 #define IWM_RX_FREE_BUFFERS 64 1566 #define IWM_RX_LOW_WATERMARK 8 1567 1568 /** 1569 * struct iwm_rb_status - reseve buffer status 1570 * host memory mapped FH registers 1571 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1572 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1573 * @finished_rb_num [0:11] - Indicates the index of the current RB 1574 * in which the last frame was written to 1575 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1576 * which was transferred 1577 */ 1578 struct iwm_rb_status { 1579 uint16_t closed_rb_num; 1580 uint16_t closed_fr_num; 1581 uint16_t finished_rb_num; 1582 uint16_t finished_fr_nam; 1583 uint32_t unused; 1584 } __packed; 1585 1586 1587 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1588 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1589 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1590 IWM_TFD_QUEUE_SIZE_BC_DUP) 1591 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1592 #define IWM_NUM_OF_TBS 20 1593 1594 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1595 { 1596 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1597 } 1598 /** 1599 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1600 * 1601 * This structure contains dma address and length of transmission address 1602 * 1603 * @lo: low [31:0] portion of the dma address of TX buffer 1604 * every even is unaligned on 16 bit boundary 1605 * @hi_n_len 0-3 [35:32] portion of dma 1606 * 4-15 length of the tx buffer 1607 */ 1608 struct iwm_tfd_tb { 1609 uint32_t lo; 1610 uint16_t hi_n_len; 1611 } __packed; 1612 1613 /** 1614 * struct iwm_tfd 1615 * 1616 * Transmit Frame Descriptor (TFD) 1617 * 1618 * @ __reserved1[3] reserved 1619 * @ num_tbs 0-4 number of active tbs 1620 * 5 reserved 1621 * 6-7 padding (not used) 1622 * @ tbs[20] transmit frame buffer descriptors 1623 * @ __pad padding 1624 * 1625 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1626 * Both driver and device share these circular buffers, each of which must be 1627 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1628 * 1629 * Driver must indicate the physical address of the base of each 1630 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1631 * 1632 * Each TFD contains pointer/size information for up to 20 data buffers 1633 * in host DRAM. These buffers collectively contain the (one) frame described 1634 * by the TFD. Each buffer must be a single contiguous block of memory within 1635 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1636 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1637 * Tx frame, up to 8 KBytes in size. 1638 * 1639 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1640 */ 1641 struct iwm_tfd { 1642 uint8_t __reserved1[3]; 1643 uint8_t num_tbs; 1644 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1645 uint32_t __pad; 1646 } __packed; 1647 1648 /* Keep Warm Size */ 1649 #define IWM_KW_SIZE 0x1000 /* 4k */ 1650 1651 /* Fixed (non-configurable) rx data from phy */ 1652 1653 /** 1654 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1655 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1656 * @tfd_offset 0-12 - tx command byte count 1657 * 12-16 - station index 1658 */ 1659 struct iwm_agn_scd_bc_tbl { 1660 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1661 } __packed; 1662 1663 /* Maximum number of Tx queues. */ 1664 #define IWM_MVM_MAX_QUEUES 31 1665 1666 /* Tx queue numbers */ 1667 enum { 1668 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1669 IWM_MVM_CMD_QUEUE = 9, 1670 IWM_MVM_AUX_QUEUE = 15, 1671 }; 1672 1673 enum iwm_mvm_tx_fifo { 1674 IWM_MVM_TX_FIFO_BK = 0, 1675 IWM_MVM_TX_FIFO_BE, 1676 IWM_MVM_TX_FIFO_VI, 1677 IWM_MVM_TX_FIFO_VO, 1678 IWM_MVM_TX_FIFO_MCAST = 5, 1679 IWM_MVM_TX_FIFO_CMD = 7, 1680 }; 1681 1682 #define IWM_MVM_STATION_COUNT 16 1683 1684 /* commands */ 1685 enum { 1686 IWM_MVM_ALIVE = 0x1, 1687 IWM_REPLY_ERROR = 0x2, 1688 1689 IWM_INIT_COMPLETE_NOTIF = 0x4, 1690 1691 /* PHY context commands */ 1692 IWM_PHY_CONTEXT_CMD = 0x8, 1693 IWM_DBG_CFG = 0x9, 1694 1695 /* UMAC scan commands */ 1696 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1697 IWM_SCAN_CFG_CMD = 0xc, 1698 IWM_SCAN_REQ_UMAC = 0xd, 1699 IWM_SCAN_ABORT_UMAC = 0xe, 1700 IWM_SCAN_COMPLETE_UMAC = 0xf, 1701 1702 /* station table */ 1703 IWM_ADD_STA_KEY = 0x17, 1704 IWM_ADD_STA = 0x18, 1705 IWM_REMOVE_STA = 0x19, 1706 1707 /* TX */ 1708 IWM_TX_CMD = 0x1c, 1709 IWM_TXPATH_FLUSH = 0x1e, 1710 IWM_MGMT_MCAST_KEY = 0x1f, 1711 1712 /* scheduler config */ 1713 IWM_SCD_QUEUE_CFG = 0x1d, 1714 1715 /* global key */ 1716 IWM_WEP_KEY = 0x20, 1717 1718 /* MAC and Binding commands */ 1719 IWM_MAC_CONTEXT_CMD = 0x28, 1720 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1721 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1722 IWM_BINDING_CONTEXT_CMD = 0x2b, 1723 IWM_TIME_QUOTA_CMD = 0x2c, 1724 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1725 1726 IWM_LQ_CMD = 0x4e, 1727 1728 /* paging block to FW cpu2 */ 1729 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1730 1731 /* Scan offload */ 1732 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1733 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1734 IWM_HOT_SPOT_CMD = 0x53, 1735 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1736 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1737 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1738 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1739 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1740 1741 /* Phy */ 1742 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1743 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1744 IWM_PHY_DB_CMD = 0x6c, 1745 1746 /* Power - legacy power table command */ 1747 IWM_POWER_TABLE_CMD = 0x77, 1748 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1749 1750 /* Thermal Throttling*/ 1751 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1752 1753 /* Scanning */ 1754 IWM_SCAN_ABORT_CMD = 0x81, 1755 IWM_SCAN_START_NOTIFICATION = 0x82, 1756 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1757 1758 /* NVM */ 1759 IWM_NVM_ACCESS_CMD = 0x88, 1760 1761 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1762 1763 IWM_BEACON_NOTIFICATION = 0x90, 1764 IWM_BEACON_TEMPLATE_CMD = 0x91, 1765 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1766 IWM_BT_CONFIG = 0x9b, 1767 IWM_STATISTICS_NOTIFICATION = 0x9d, 1768 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1769 1770 /* RF-KILL commands and notifications */ 1771 IWM_CARD_STATE_CMD = 0xa0, 1772 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1773 1774 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1775 1776 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1777 1778 /* Power - new power table command */ 1779 IWM_MAC_PM_POWER_TABLE = 0xa9, 1780 1781 IWM_REPLY_RX_PHY_CMD = 0xc0, 1782 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1783 IWM_BA_NOTIF = 0xc5, 1784 1785 /* Location Aware Regulatory */ 1786 IWM_MCC_UPDATE_CMD = 0xc8, 1787 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1788 1789 /* BT Coex */ 1790 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1791 IWM_BT_COEX_PROT_ENV = 0xcd, 1792 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1793 IWM_BT_COEX_CI = 0x5d, 1794 1795 IWM_REPLY_SF_CFG_CMD = 0xd1, 1796 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1797 1798 /* DTS measurements */ 1799 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1800 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1801 1802 IWM_REPLY_DEBUG_CMD = 0xf0, 1803 IWM_DEBUG_LOG_MSG = 0xf7, 1804 1805 IWM_MCAST_FILTER_CMD = 0xd0, 1806 1807 /* D3 commands/notifications */ 1808 IWM_D3_CONFIG_CMD = 0xd3, 1809 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1810 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1811 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1812 1813 /* for WoWLAN in particular */ 1814 IWM_WOWLAN_PATTERNS = 0xe0, 1815 IWM_WOWLAN_CONFIGURATION = 0xe1, 1816 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1817 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1818 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1819 IWM_WOWLAN_GET_STATUSES = 0xe5, 1820 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1821 1822 /* and for NetDetect */ 1823 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1824 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1825 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1826 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1827 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1828 1829 IWM_REPLY_MAX = 0xff, 1830 }; 1831 1832 enum iwm_phy_ops_subcmd_ids { 1833 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1834 IWM_CTDP_CONFIG_CMD = 0x03, 1835 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1836 IWM_CT_KILL_NOTIFICATION = 0xFE, 1837 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1838 }; 1839 1840 /* command groups */ 1841 enum { 1842 IWM_LEGACY_GROUP = 0x0, 1843 IWM_LONG_GROUP = 0x1, 1844 IWM_SYSTEM_GROUP = 0x2, 1845 IWM_MAC_CONF_GROUP = 0x3, 1846 IWM_PHY_OPS_GROUP = 0x4, 1847 IWM_DATA_PATH_GROUP = 0x5, 1848 IWM_PROT_OFFLOAD_GROUP = 0xb, 1849 }; 1850 1851 /** 1852 * struct iwm_cmd_response - generic response struct for most commands 1853 * @status: status of the command asked, changes for each one 1854 */ 1855 struct iwm_cmd_response { 1856 uint32_t status; 1857 }; 1858 1859 /* 1860 * struct iwm_tx_ant_cfg_cmd 1861 * @valid: valid antenna configuration 1862 */ 1863 struct iwm_tx_ant_cfg_cmd { 1864 uint32_t valid; 1865 } __packed; 1866 1867 /** 1868 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1869 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1870 * @flags: (reserved for future implementation) 1871 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1872 * @pwr_restriction: TX power restriction in dBms. 1873 */ 1874 struct iwm_reduce_tx_power_cmd { 1875 uint8_t flags; 1876 uint8_t mac_context_id; 1877 uint16_t pwr_restriction; 1878 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1879 1880 /* 1881 * Calibration control struct. 1882 * Sent as part of the phy configuration command. 1883 * @flow_trigger: bitmap for which calibrations to perform according to 1884 * flow triggers. 1885 * @event_trigger: bitmap for which calibrations to perform according to 1886 * event triggers. 1887 */ 1888 struct iwm_calib_ctrl { 1889 uint32_t flow_trigger; 1890 uint32_t event_trigger; 1891 } __packed; 1892 1893 /* This enum defines the bitmap of various calibrations to enable in both 1894 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1895 */ 1896 enum iwm_calib_cfg { 1897 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1898 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1899 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1900 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1901 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1902 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1903 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1904 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1905 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1906 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1907 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1908 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1909 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1910 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1911 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1912 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1913 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1914 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1915 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1916 }; 1917 1918 /* 1919 * Phy configuration command. 1920 */ 1921 struct iwm_phy_cfg_cmd { 1922 uint32_t phy_cfg; 1923 struct iwm_calib_ctrl calib_control; 1924 } __packed; 1925 1926 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1927 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1928 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1929 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1930 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1931 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1932 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1933 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1934 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 1935 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 1936 1937 1938 /* Target of the IWM_NVM_ACCESS_CMD */ 1939 enum { 1940 IWM_NVM_ACCESS_TARGET_CACHE = 0, 1941 IWM_NVM_ACCESS_TARGET_OTP = 1, 1942 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 1943 }; 1944 1945 /* Section types for IWM_NVM_ACCESS_CMD */ 1946 enum { 1947 IWM_NVM_SECTION_TYPE_SW = 1, 1948 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 1949 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 1950 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 1951 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 1952 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 1953 IWM_NVM_MAX_NUM_SECTIONS = 13, 1954 }; 1955 1956 /** 1957 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 1958 * @op_code: 0 - read, 1 - write 1959 * @target: IWM_NVM_ACCESS_TARGET_* 1960 * @type: IWM_NVM_SECTION_TYPE_* 1961 * @offset: offset in bytes into the section 1962 * @length: in bytes, to read/write 1963 * @data: if write operation, the data to write. On read its empty 1964 */ 1965 struct iwm_nvm_access_cmd { 1966 uint8_t op_code; 1967 uint8_t target; 1968 uint16_t type; 1969 uint16_t offset; 1970 uint16_t length; 1971 uint8_t data[]; 1972 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 1973 1974 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 1975 1976 /* 1977 * struct iwm_fw_paging_cmd - paging layout 1978 * 1979 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 1980 * 1981 * Send to FW the paging layout in the driver. 1982 * 1983 * @flags: various flags for the command 1984 * @block_size: the block size in powers of 2 1985 * @block_num: number of blocks specified in the command. 1986 * @device_phy_addr: virtual addresses from device side 1987 */ 1988 struct iwm_fw_paging_cmd { 1989 uint32_t flags; 1990 uint32_t block_size; 1991 uint32_t block_num; 1992 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 1993 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 1994 1995 /* 1996 * Fw items ID's 1997 * 1998 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 1999 * download 2000 */ 2001 enum iwm_fw_item_id { 2002 IWM_FW_ITEM_ID_PAGING = 3, 2003 }; 2004 2005 /* 2006 * struct iwm_fw_get_item_cmd - get an item from the fw 2007 */ 2008 struct iwm_fw_get_item_cmd { 2009 uint32_t item_id; 2010 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2011 2012 /** 2013 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2014 * @offset: offset in bytes into the section 2015 * @length: in bytes, either how much was written or read 2016 * @type: IWM_NVM_SECTION_TYPE_* 2017 * @status: 0 for success, fail otherwise 2018 * @data: if read operation, the data returned. Empty on write. 2019 */ 2020 struct iwm_nvm_access_resp { 2021 uint16_t offset; 2022 uint16_t length; 2023 uint16_t type; 2024 uint16_t status; 2025 uint8_t data[]; 2026 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2027 2028 /* IWM_MVM_ALIVE 0x1 */ 2029 2030 /* alive response is_valid values */ 2031 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2032 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2033 2034 /* alive response ver_type values */ 2035 enum { 2036 IWM_FW_TYPE_HW = 0, 2037 IWM_FW_TYPE_PROT = 1, 2038 IWM_FW_TYPE_AP = 2, 2039 IWM_FW_TYPE_WOWLAN = 3, 2040 IWM_FW_TYPE_TIMING = 4, 2041 IWM_FW_TYPE_WIPAN = 5 2042 }; 2043 2044 /* alive response ver_subtype values */ 2045 enum { 2046 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2047 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2048 IWM_FW_SUBTYPE_REDUCED = 2, 2049 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2050 IWM_FW_SUBTYPE_WOWLAN = 4, 2051 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2052 IWM_FW_SUBTYPE_WIPAN = 6, 2053 IWM_FW_SUBTYPE_INITIALIZE = 9 2054 }; 2055 2056 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2057 #define IWM_ALIVE_STATUS_OK 0xCAFE 2058 2059 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2060 2061 struct iwm_mvm_alive_resp_ver1 { 2062 uint16_t status; 2063 uint16_t flags; 2064 uint8_t ucode_minor; 2065 uint8_t ucode_major; 2066 uint16_t id; 2067 uint8_t api_minor; 2068 uint8_t api_major; 2069 uint8_t ver_subtype; 2070 uint8_t ver_type; 2071 uint8_t mac; 2072 uint8_t opt; 2073 uint16_t reserved2; 2074 uint32_t timestamp; 2075 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2076 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2077 uint32_t cpu_register_ptr; 2078 uint32_t dbgm_config_ptr; 2079 uint32_t alive_counter_ptr; 2080 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2081 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2082 2083 struct iwm_mvm_alive_resp_ver2 { 2084 uint16_t status; 2085 uint16_t flags; 2086 uint8_t ucode_minor; 2087 uint8_t ucode_major; 2088 uint16_t id; 2089 uint8_t api_minor; 2090 uint8_t api_major; 2091 uint8_t ver_subtype; 2092 uint8_t ver_type; 2093 uint8_t mac; 2094 uint8_t opt; 2095 uint16_t reserved2; 2096 uint32_t timestamp; 2097 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2098 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2099 uint32_t cpu_register_ptr; 2100 uint32_t dbgm_config_ptr; 2101 uint32_t alive_counter_ptr; 2102 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2103 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2104 uint32_t st_fwrd_size; 2105 uint8_t umac_minor; /* UMAC version: minor */ 2106 uint8_t umac_major; /* UMAC version: major */ 2107 uint16_t umac_id; /* UMAC version: id */ 2108 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2109 uint32_t dbg_print_buff_addr; 2110 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2111 2112 struct iwm_mvm_alive_resp { 2113 uint16_t status; 2114 uint16_t flags; 2115 uint32_t ucode_minor; 2116 uint32_t ucode_major; 2117 uint8_t ver_subtype; 2118 uint8_t ver_type; 2119 uint8_t mac; 2120 uint8_t opt; 2121 uint32_t timestamp; 2122 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2123 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2124 uint32_t cpu_register_ptr; 2125 uint32_t dbgm_config_ptr; 2126 uint32_t alive_counter_ptr; 2127 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2128 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2129 uint32_t st_fwrd_size; 2130 uint32_t umac_minor; /* UMAC version: minor */ 2131 uint32_t umac_major; /* UMAC version: major */ 2132 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2133 uint32_t dbg_print_buff_addr; 2134 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2135 2136 /* Error response/notification */ 2137 enum { 2138 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2139 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2140 IWM_FW_ERR_SERVICE = 0x2, 2141 IWM_FW_ERR_ARC_MEMORY = 0x3, 2142 IWM_FW_ERR_ARC_CODE = 0x4, 2143 IWM_FW_ERR_WATCH_DOG = 0x5, 2144 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2145 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2146 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2147 IWM_FW_ERR_UNEXPECTED = 0xFE, 2148 IWM_FW_ERR_FATAL = 0xFF 2149 }; 2150 2151 /** 2152 * struct iwm_error_resp - FW error indication 2153 * ( IWM_REPLY_ERROR = 0x2 ) 2154 * @error_type: one of IWM_FW_ERR_* 2155 * @cmd_id: the command ID for which the error occurred 2156 * @bad_cmd_seq_num: sequence number of the erroneous command 2157 * @error_service: which service created the error, applicable only if 2158 * error_type = 2, otherwise 0 2159 * @timestamp: TSF in usecs. 2160 */ 2161 struct iwm_error_resp { 2162 uint32_t error_type; 2163 uint8_t cmd_id; 2164 uint8_t reserved1; 2165 uint16_t bad_cmd_seq_num; 2166 uint32_t error_service; 2167 uint64_t timestamp; 2168 } __packed; 2169 2170 2171 /* Common PHY, MAC and Bindings definitions */ 2172 2173 #define IWM_MAX_MACS_IN_BINDING (3) 2174 #define IWM_MAX_BINDINGS (4) 2175 #define IWM_AUX_BINDING_INDEX (3) 2176 #define IWM_MAX_PHYS (4) 2177 2178 /* Used to extract ID and color from the context dword */ 2179 #define IWM_FW_CTXT_ID_POS (0) 2180 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2181 #define IWM_FW_CTXT_COLOR_POS (8) 2182 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2183 #define IWM_FW_CTXT_INVALID (0xffffffff) 2184 2185 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2186 (_color << IWM_FW_CTXT_COLOR_POS)) 2187 2188 /* Possible actions on PHYs, MACs and Bindings */ 2189 enum { 2190 IWM_FW_CTXT_ACTION_STUB = 0, 2191 IWM_FW_CTXT_ACTION_ADD, 2192 IWM_FW_CTXT_ACTION_MODIFY, 2193 IWM_FW_CTXT_ACTION_REMOVE, 2194 IWM_FW_CTXT_ACTION_NUM 2195 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2196 2197 /* Time Events */ 2198 2199 /* Time Event types, according to MAC type */ 2200 enum iwm_time_event_type { 2201 /* BSS Station Events */ 2202 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2203 IWM_TE_BSS_STA_ASSOC, 2204 IWM_TE_BSS_EAP_DHCP_PROT, 2205 IWM_TE_BSS_QUIET_PERIOD, 2206 2207 /* P2P Device Events */ 2208 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2209 IWM_TE_P2P_DEVICE_LISTEN, 2210 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2211 IWM_TE_P2P_DEVICE_FULL_SCAN, 2212 2213 /* P2P Client Events */ 2214 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2215 IWM_TE_P2P_CLIENT_ASSOC, 2216 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2217 2218 /* P2P GO Events */ 2219 IWM_TE_P2P_GO_ASSOC_PROT, 2220 IWM_TE_P2P_GO_REPETITIVE_NOA, 2221 IWM_TE_P2P_GO_CT_WINDOW, 2222 2223 /* WiDi Sync Events */ 2224 IWM_TE_WIDI_TX_SYNC, 2225 2226 IWM_TE_MAX 2227 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2228 2229 2230 2231 /* Time event - defines for command API v1 */ 2232 2233 /* 2234 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2235 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2236 * the first fragment is scheduled. 2237 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2238 * the first 2 fragments are scheduled. 2239 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2240 * number of fragments are valid. 2241 * 2242 * Other than the constant defined above, specifying a fragmentation value 'x' 2243 * means that the event can be fragmented but only the first 'x' will be 2244 * scheduled. 2245 */ 2246 enum { 2247 IWM_TE_V1_FRAG_NONE = 0, 2248 IWM_TE_V1_FRAG_SINGLE = 1, 2249 IWM_TE_V1_FRAG_DUAL = 2, 2250 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2251 }; 2252 2253 /* If a Time Event can be fragmented, this is the max number of fragments */ 2254 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2255 /* Repeat the time event endlessly (until removed) */ 2256 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2257 /* If a Time Event has bounded repetitions, this is the maximal value */ 2258 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2259 2260 /* Time Event dependencies: none, on another TE, or in a specific time */ 2261 enum { 2262 IWM_TE_V1_INDEPENDENT = 0, 2263 IWM_TE_V1_DEP_OTHER = (1 << 0), 2264 IWM_TE_V1_DEP_TSF = (1 << 1), 2265 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2266 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2267 2268 /* 2269 * @IWM_TE_V1_NOTIF_NONE: no notifications 2270 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2271 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2272 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2273 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2274 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2275 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2276 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2277 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2278 * 2279 * Supported Time event notifications configuration. 2280 * A notification (both event and fragment) includes a status indicating weather 2281 * the FW was able to schedule the event or not. For fragment start/end 2282 * notification the status is always success. There is no start/end fragment 2283 * notification for monolithic events. 2284 */ 2285 enum { 2286 IWM_TE_V1_NOTIF_NONE = 0, 2287 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2288 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2289 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2290 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2291 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2292 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2293 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2294 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2295 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2296 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2297 2298 /* Time event - defines for command API */ 2299 2300 /* 2301 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2302 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2303 * the first fragment is scheduled. 2304 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2305 * the first 2 fragments are scheduled. 2306 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2307 * number of fragments are valid. 2308 * 2309 * Other than the constant defined above, specifying a fragmentation value 'x' 2310 * means that the event can be fragmented but only the first 'x' will be 2311 * scheduled. 2312 */ 2313 enum { 2314 IWM_TE_V2_FRAG_NONE = 0, 2315 IWM_TE_V2_FRAG_SINGLE = 1, 2316 IWM_TE_V2_FRAG_DUAL = 2, 2317 IWM_TE_V2_FRAG_MAX = 0xfe, 2318 IWM_TE_V2_FRAG_ENDLESS = 0xff 2319 }; 2320 2321 /* Repeat the time event endlessly (until removed) */ 2322 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2323 /* If a Time Event has bounded repetitions, this is the maximal value */ 2324 #define IWM_TE_V2_REPEAT_MAX 0xfe 2325 2326 #define IWM_TE_V2_PLACEMENT_POS 12 2327 #define IWM_TE_V2_ABSENCE_POS 15 2328 2329 /* Time event policy values 2330 * A notification (both event and fragment) includes a status indicating weather 2331 * the FW was able to schedule the event or not. For fragment start/end 2332 * notification the status is always success. There is no start/end fragment 2333 * notification for monolithic events. 2334 * 2335 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2336 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2337 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2338 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2339 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2340 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2341 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2342 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2343 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2344 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2345 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2346 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2347 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2348 */ 2349 enum { 2350 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2351 2352 /* notifications (event start/stop, fragment start/stop) */ 2353 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2354 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2355 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2356 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2357 2358 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2359 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2360 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2361 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2362 2363 IWM_TE_V2_NOTIF_MSK = 0xff, 2364 2365 /* placement characteristics */ 2366 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2367 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2368 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2369 2370 /* are we present or absent during the Time Event. */ 2371 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2372 }; 2373 2374 /** 2375 * struct iwm_time_event_cmd_api - configuring Time Events 2376 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2377 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2378 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2379 * @id_and_color: ID and color of the relevant MAC 2380 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2381 * @id: this field has two meanings, depending on the action: 2382 * If the action is ADD, then it means the type of event to add. 2383 * For all other actions it is the unique event ID assigned when the 2384 * event was added by the FW. 2385 * @apply_time: When to start the Time Event (in GP2) 2386 * @max_delay: maximum delay to event's start (apply time), in TU 2387 * @depends_on: the unique ID of the event we depend on (if any) 2388 * @interval: interval between repetitions, in TU 2389 * @duration: duration of event in TU 2390 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2391 * @max_frags: maximal number of fragments the Time Event can be divided to 2392 * @policy: defines whether uCode shall notify the host or other uCode modules 2393 * on event and/or fragment start and/or end 2394 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2395 * IWM_TE_EVENT_SOCIOPATHIC 2396 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2397 */ 2398 struct iwm_time_event_cmd { 2399 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2400 uint32_t id_and_color; 2401 uint32_t action; 2402 uint32_t id; 2403 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2404 uint32_t apply_time; 2405 uint32_t max_delay; 2406 uint32_t depends_on; 2407 uint32_t interval; 2408 uint32_t duration; 2409 uint8_t repeat; 2410 uint8_t max_frags; 2411 uint16_t policy; 2412 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2413 2414 /** 2415 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2416 * @status: bit 0 indicates success, all others specify errors 2417 * @id: the Time Event type 2418 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2419 * @id_and_color: ID and color of the relevant MAC 2420 */ 2421 struct iwm_time_event_resp { 2422 uint32_t status; 2423 uint32_t id; 2424 uint32_t unique_id; 2425 uint32_t id_and_color; 2426 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2427 2428 /** 2429 * struct iwm_time_event_notif - notifications of time event start/stop 2430 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2431 * @timestamp: action timestamp in GP2 2432 * @session_id: session's unique id 2433 * @unique_id: unique id of the Time Event itself 2434 * @id_and_color: ID and color of the relevant MAC 2435 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2436 * @status: true if scheduled, false otherwise (not executed) 2437 */ 2438 struct iwm_time_event_notif { 2439 uint32_t timestamp; 2440 uint32_t session_id; 2441 uint32_t unique_id; 2442 uint32_t id_and_color; 2443 uint32_t action; 2444 uint32_t status; 2445 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2446 2447 2448 /* Bindings and Time Quota */ 2449 2450 /** 2451 * struct iwm_binding_cmd - configuring bindings 2452 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2453 * @id_and_color: ID and color of the relevant Binding 2454 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2455 * @macs: array of MAC id and colors which belong to the binding 2456 * @phy: PHY id and color which belongs to the binding 2457 */ 2458 struct iwm_binding_cmd { 2459 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2460 uint32_t id_and_color; 2461 uint32_t action; 2462 /* IWM_BINDING_DATA_API_S_VER_1 */ 2463 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2464 uint32_t phy; 2465 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2466 2467 /* The maximal number of fragments in the FW's schedule session */ 2468 #define IWM_MVM_MAX_QUOTA 128 2469 2470 /** 2471 * struct iwm_time_quota_data - configuration of time quota per binding 2472 * @id_and_color: ID and color of the relevant Binding 2473 * @quota: absolute time quota in TU. The scheduler will try to divide the 2474 * remainig quota (after Time Events) according to this quota. 2475 * @max_duration: max uninterrupted context duration in TU 2476 */ 2477 struct iwm_time_quota_data { 2478 uint32_t id_and_color; 2479 uint32_t quota; 2480 uint32_t max_duration; 2481 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2482 2483 /** 2484 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2485 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2486 * @quotas: allocations per binding 2487 */ 2488 struct iwm_time_quota_cmd { 2489 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2490 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2491 2492 2493 /* PHY context */ 2494 2495 /* Supported bands */ 2496 #define IWM_PHY_BAND_5 (0) 2497 #define IWM_PHY_BAND_24 (1) 2498 2499 /* Supported channel width, vary if there is VHT support */ 2500 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2501 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2502 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2503 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2504 2505 /* 2506 * Control channel position: 2507 * For legacy set bit means upper channel, otherwise lower. 2508 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2509 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2510 * center_freq 2511 * | 2512 * 40Mhz |_______|_______| 2513 * 80Mhz |_______|_______|_______|_______| 2514 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2515 * code 011 010 001 000 | 100 101 110 111 2516 */ 2517 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2518 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2519 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2520 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2521 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2522 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2523 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2524 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2525 2526 /* 2527 * @band: IWM_PHY_BAND_* 2528 * @channel: channel number 2529 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2530 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2531 */ 2532 struct iwm_fw_channel_info { 2533 uint8_t band; 2534 uint8_t channel; 2535 uint8_t width; 2536 uint8_t ctrl_pos; 2537 } __packed; 2538 2539 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2540 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2541 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2542 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2543 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2544 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2545 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2546 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2547 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2548 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2549 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2550 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2551 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2552 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2553 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2554 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2555 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2556 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2557 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2558 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2559 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2560 2561 /* TODO: fix the value, make it depend on firmware at runtime? */ 2562 #define IWM_NUM_PHY_CTX 3 2563 2564 /* TODO: complete missing documentation */ 2565 /** 2566 * struct iwm_phy_context_cmd - config of the PHY context 2567 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2568 * @id_and_color: ID and color of the relevant Binding 2569 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2570 * @apply_time: 0 means immediate apply and context switch. 2571 * other value means apply new params after X usecs 2572 * @tx_param_color: ??? 2573 * @channel_info: 2574 * @txchain_info: ??? 2575 * @rxchain_info: ??? 2576 * @acquisition_data: ??? 2577 * @dsp_cfg_flags: set to 0 2578 */ 2579 struct iwm_phy_context_cmd { 2580 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2581 uint32_t id_and_color; 2582 uint32_t action; 2583 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2584 uint32_t apply_time; 2585 uint32_t tx_param_color; 2586 struct iwm_fw_channel_info ci; 2587 uint32_t txchain_info; 2588 uint32_t rxchain_info; 2589 uint32_t acquisition_data; 2590 uint32_t dsp_cfg_flags; 2591 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2592 2593 #define IWM_RX_INFO_PHY_CNT 8 2594 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2595 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2596 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2597 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2598 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2599 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2600 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2601 2602 #define IWM_RX_INFO_AGC_IDX 1 2603 #define IWM_RX_INFO_RSSI_AB_IDX 2 2604 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2605 #define IWM_OFDM_AGC_A_POS 0 2606 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2607 #define IWM_OFDM_AGC_B_POS 7 2608 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2609 #define IWM_OFDM_AGC_CODE_POS 20 2610 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2611 #define IWM_OFDM_RSSI_A_POS 0 2612 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2613 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2614 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2615 #define IWM_OFDM_RSSI_B_POS 16 2616 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2617 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2618 2619 /** 2620 * struct iwm_rx_phy_info - phy info 2621 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2622 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2623 * @cfg_phy_cnt: configurable DSP phy data byte count 2624 * @stat_id: configurable DSP phy data set ID 2625 * @reserved1: 2626 * @system_timestamp: GP2 at on air rise 2627 * @timestamp: TSF at on air rise 2628 * @beacon_time_stamp: beacon at on-air rise 2629 * @phy_flags: general phy flags: band, modulation, ... 2630 * @channel: channel number 2631 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2632 * @rate_n_flags: IWM_RATE_MCS_* 2633 * @byte_count: frame's byte-count 2634 * @frame_time: frame's time on the air, based on byte count and frame rate 2635 * calculation 2636 * @mac_active_msk: what MACs were active when the frame was received 2637 * 2638 * Before each Rx, the device sends this data. It contains PHY information 2639 * about the reception of the packet. 2640 */ 2641 struct iwm_rx_phy_info { 2642 uint8_t non_cfg_phy_cnt; 2643 uint8_t cfg_phy_cnt; 2644 uint8_t stat_id; 2645 uint8_t reserved1; 2646 uint32_t system_timestamp; 2647 uint64_t timestamp; 2648 uint32_t beacon_time_stamp; 2649 uint16_t phy_flags; 2650 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2651 uint16_t channel; 2652 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2653 uint8_t rate; 2654 uint8_t rflags; 2655 uint16_t xrflags; 2656 uint32_t byte_count; 2657 uint16_t mac_active_msk; 2658 uint16_t frame_time; 2659 } __packed; 2660 2661 struct iwm_rx_mpdu_res_start { 2662 uint16_t byte_count; 2663 uint16_t reserved; 2664 } __packed; 2665 2666 /** 2667 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2668 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2669 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2670 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2671 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2672 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2673 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2674 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2675 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2676 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2677 */ 2678 enum iwm_rx_phy_flags { 2679 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2680 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2681 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2682 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2683 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2684 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2685 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2686 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2687 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2688 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2689 }; 2690 2691 /** 2692 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2693 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2694 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2695 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2696 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2697 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2698 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2699 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2700 * in the driver. 2701 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2702 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2703 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2704 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2705 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2706 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2707 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2708 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2709 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2710 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2711 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2712 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2713 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2714 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2715 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2716 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2717 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2718 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2719 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2720 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2721 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2722 */ 2723 enum iwm_mvm_rx_status { 2724 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2725 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2726 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2727 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2728 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2729 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2730 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2731 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2732 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2733 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2734 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2735 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2736 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2737 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2738 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2739 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2740 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2741 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2742 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2743 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2744 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2745 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2746 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2747 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2748 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2749 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2750 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2751 }; 2752 2753 /** 2754 * struct iwm_radio_version_notif - information on the radio version 2755 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2756 * @radio_flavor: 2757 * @radio_step: 2758 * @radio_dash: 2759 */ 2760 struct iwm_radio_version_notif { 2761 uint32_t radio_flavor; 2762 uint32_t radio_step; 2763 uint32_t radio_dash; 2764 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2765 2766 enum iwm_card_state_flags { 2767 IWM_CARD_ENABLED = 0x00, 2768 IWM_HW_CARD_DISABLED = 0x01, 2769 IWM_SW_CARD_DISABLED = 0x02, 2770 IWM_CT_KILL_CARD_DISABLED = 0x04, 2771 IWM_HALT_CARD_DISABLED = 0x08, 2772 IWM_CARD_DISABLED_MSK = 0x0f, 2773 IWM_CARD_IS_RX_ON = 0x10, 2774 }; 2775 2776 /** 2777 * struct iwm_radio_version_notif - information on the radio version 2778 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2779 * @flags: %iwm_card_state_flags 2780 */ 2781 struct iwm_card_state_notif { 2782 uint32_t flags; 2783 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2784 2785 /** 2786 * struct iwm_missed_beacons_notif - information on missed beacons 2787 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2788 * @mac_id: interface ID 2789 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2790 * beacons since last RX. 2791 * @consec_missed_beacons: number of consecutive missed beacons 2792 * @num_expected_beacons: 2793 * @num_recvd_beacons: 2794 */ 2795 struct iwm_missed_beacons_notif { 2796 uint32_t mac_id; 2797 uint32_t consec_missed_beacons_since_last_rx; 2798 uint32_t consec_missed_beacons; 2799 uint32_t num_expected_beacons; 2800 uint32_t num_recvd_beacons; 2801 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2802 2803 /** 2804 * struct iwm_mfuart_load_notif - mfuart image version & status 2805 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2806 * @installed_ver: installed image version 2807 * @external_ver: external image version 2808 * @status: MFUART loading status 2809 * @duration: MFUART loading time 2810 */ 2811 struct iwm_mfuart_load_notif { 2812 uint32_t installed_ver; 2813 uint32_t external_ver; 2814 uint32_t status; 2815 uint32_t duration; 2816 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2817 2818 /** 2819 * struct iwm_set_calib_default_cmd - set default value for calibration. 2820 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2821 * @calib_index: the calibration to set value for 2822 * @length: of data 2823 * @data: the value to set for the calibration result 2824 */ 2825 struct iwm_set_calib_default_cmd { 2826 uint16_t calib_index; 2827 uint16_t length; 2828 uint8_t data[0]; 2829 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2830 2831 #define IWM_MAX_PORT_ID_NUM 2 2832 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2833 2834 /** 2835 * struct iwm_mcast_filter_cmd - configure multicast filter. 2836 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2837 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2838 * to identify network interface adopted in host-device IF. 2839 * It is used by FW as index in array of addresses. This array has 2840 * IWM_MAX_PORT_ID_NUM members. 2841 * @count: Number of MAC addresses in the array 2842 * @pass_all: Set 1 to pass all multicast packets. 2843 * @bssid: current association BSSID. 2844 * @addr_list: Place holder for array of MAC addresses. 2845 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2846 */ 2847 struct iwm_mcast_filter_cmd { 2848 uint8_t filter_own; 2849 uint8_t port_id; 2850 uint8_t count; 2851 uint8_t pass_all; 2852 uint8_t bssid[6]; 2853 uint8_t reserved[2]; 2854 uint8_t addr_list[0]; 2855 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2856 2857 /* 2858 * The first MAC indices (starting from 0) 2859 * are available to the driver, AUX follows 2860 */ 2861 #define IWM_MAC_INDEX_AUX 4 2862 #define IWM_MAC_INDEX_MIN_DRIVER 0 2863 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 2864 #define IWM_NUM_MAC_INDEX (IWM_MAC_INDEX_AUX + 1) 2865 2866 /*********************************** 2867 * Statistics API 2868 ***********************************/ 2869 struct iwm_mvm_statistics_dbg { 2870 uint32_t burst_check; 2871 uint32_t burst_count; 2872 uint32_t wait_for_silence_timeout_cnt; 2873 uint32_t reserved[3]; 2874 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2875 2876 struct iwm_mvm_statistics_div { 2877 uint32_t tx_on_a; 2878 uint32_t tx_on_b; 2879 uint32_t exec_time; 2880 uint32_t probe_time; 2881 uint32_t rssi_ant; 2882 uint32_t reserved2; 2883 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2884 2885 struct iwm_mvm_statistics_rx_non_phy { 2886 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2887 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2888 uint32_t non_bssid_frames; /* number of frames with BSSID that 2889 * doesn't belong to the STA BSSID */ 2890 uint32_t filtered_frames; /* count frames that were dumped in the 2891 * filtering process */ 2892 uint32_t non_channel_beacons; /* beacons with our bss id but not on 2893 * our serving channel */ 2894 uint32_t channel_beacons; /* beacons with our bss id and in our 2895 * serving channel */ 2896 uint32_t num_missed_bcon; /* number of missed beacons */ 2897 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2898 * ADC was in saturation */ 2899 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2900 * for INA */ 2901 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2902 uint32_t interference_data_flag; /* flag for interference data 2903 * availability. 1 when data is 2904 * available. */ 2905 uint32_t channel_load; /* counts RX Enable time in uSec */ 2906 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2907 * and CCK) counter */ 2908 uint32_t beacon_rssi_a; 2909 uint32_t beacon_rssi_b; 2910 uint32_t beacon_rssi_c; 2911 uint32_t beacon_energy_a; 2912 uint32_t beacon_energy_b; 2913 uint32_t beacon_energy_c; 2914 uint32_t num_bt_kills; 2915 uint32_t mac_id; 2916 uint32_t directed_data_mpdu; 2917 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 2918 2919 struct iwm_mvm_statistics_rx_phy { 2920 uint32_t ina_cnt; 2921 uint32_t fina_cnt; 2922 uint32_t plcp_err; 2923 uint32_t crc32_err; 2924 uint32_t overrun_err; 2925 uint32_t early_overrun_err; 2926 uint32_t crc32_good; 2927 uint32_t false_alarm_cnt; 2928 uint32_t fina_sync_err_cnt; 2929 uint32_t sfd_timeout; 2930 uint32_t fina_timeout; 2931 uint32_t unresponded_rts; 2932 uint32_t rxe_frame_limit_overrun; 2933 uint32_t sent_ack_cnt; 2934 uint32_t sent_cts_cnt; 2935 uint32_t sent_ba_rsp_cnt; 2936 uint32_t dsp_self_kill; 2937 uint32_t mh_format_err; 2938 uint32_t re_acq_main_rssi_sum; 2939 uint32_t reserved; 2940 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 2941 2942 struct iwm_mvm_statistics_rx_ht_phy { 2943 uint32_t plcp_err; 2944 uint32_t overrun_err; 2945 uint32_t early_overrun_err; 2946 uint32_t crc32_good; 2947 uint32_t crc32_err; 2948 uint32_t mh_format_err; 2949 uint32_t agg_crc32_good; 2950 uint32_t agg_mpdu_cnt; 2951 uint32_t agg_cnt; 2952 uint32_t unsupport_mcs; 2953 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 2954 2955 struct iwm_mvm_statistics_tx_non_phy { 2956 uint32_t preamble_cnt; 2957 uint32_t rx_detected_cnt; 2958 uint32_t bt_prio_defer_cnt; 2959 uint32_t bt_prio_kill_cnt; 2960 uint32_t few_bytes_cnt; 2961 uint32_t cts_timeout; 2962 uint32_t ack_timeout; 2963 uint32_t expected_ack_cnt; 2964 uint32_t actual_ack_cnt; 2965 uint32_t dump_msdu_cnt; 2966 uint32_t burst_abort_next_frame_mismatch_cnt; 2967 uint32_t burst_abort_missing_next_frame_cnt; 2968 uint32_t cts_timeout_collision; 2969 uint32_t ack_or_ba_timeout_collision; 2970 } __packed; /* IWM_STATISTICS_TX_NON_PHY_API_S_VER_3 */ 2971 2972 #define IWM_MAX_CHAINS 3 2973 2974 struct iwm_mvm_statistics_tx_non_phy_agg { 2975 uint32_t ba_timeout; 2976 uint32_t ba_reschedule_frames; 2977 uint32_t scd_query_agg_frame_cnt; 2978 uint32_t scd_query_no_agg; 2979 uint32_t scd_query_agg; 2980 uint32_t scd_query_mismatch; 2981 uint32_t frame_not_ready; 2982 uint32_t underrun; 2983 uint32_t bt_prio_kill; 2984 uint32_t rx_ba_rsp_cnt; 2985 int8_t txpower[IWM_MAX_CHAINS]; 2986 int8_t reserved; 2987 uint32_t reserved2; 2988 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 2989 2990 struct iwm_mvm_statistics_tx_channel_width { 2991 uint32_t ext_cca_narrow_ch20[1]; 2992 uint32_t ext_cca_narrow_ch40[2]; 2993 uint32_t ext_cca_narrow_ch80[3]; 2994 uint32_t ext_cca_narrow_ch160[4]; 2995 uint32_t last_tx_ch_width_indx; 2996 uint32_t rx_detected_per_ch_width[4]; 2997 uint32_t success_per_ch_width[4]; 2998 uint32_t fail_per_ch_width[4]; 2999 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3000 3001 struct iwm_mvm_statistics_tx { 3002 struct iwm_mvm_statistics_tx_non_phy general; 3003 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3004 struct iwm_mvm_statistics_tx_channel_width channel_width; 3005 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3006 3007 3008 struct iwm_mvm_statistics_bt_activity { 3009 uint32_t hi_priority_tx_req_cnt; 3010 uint32_t hi_priority_tx_denied_cnt; 3011 uint32_t lo_priority_tx_req_cnt; 3012 uint32_t lo_priority_tx_denied_cnt; 3013 uint32_t hi_priority_rx_req_cnt; 3014 uint32_t hi_priority_rx_denied_cnt; 3015 uint32_t lo_priority_rx_req_cnt; 3016 uint32_t lo_priority_rx_denied_cnt; 3017 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3018 3019 struct iwm_mvm_statistics_general_v8 { 3020 uint32_t radio_temperature; 3021 uint32_t radio_voltage; 3022 struct iwm_mvm_statistics_dbg dbg; 3023 uint32_t sleep_time; 3024 uint32_t slots_out; 3025 uint32_t slots_idle; 3026 uint32_t ttl_timestamp; 3027 struct iwm_mvm_statistics_div slow_div; 3028 uint32_t rx_enable_counter; 3029 /* 3030 * num_of_sos_states: 3031 * count the number of times we have to re-tune 3032 * in order to get out of bad PHY status 3033 */ 3034 uint32_t num_of_sos_states; 3035 uint32_t beacon_filtered; 3036 uint32_t missed_beacons; 3037 uint8_t beacon_filter_average_energy; 3038 uint8_t beacon_filter_reason; 3039 uint8_t beacon_filter_current_energy; 3040 uint8_t beacon_filter_reserved; 3041 uint32_t beacon_filter_delta_time; 3042 struct iwm_mvm_statistics_bt_activity bt_activity; 3043 uint64_t rx_time; 3044 uint64_t on_time_rf; 3045 uint64_t on_time_scan; 3046 uint64_t tx_time; 3047 uint32_t beacon_counter[IWM_NUM_MAC_INDEX]; 3048 uint8_t beacon_average_energy[IWM_NUM_MAC_INDEX]; 3049 uint8_t reserved[4 - (IWM_NUM_MAC_INDEX % 4)]; 3050 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_8 */ 3051 3052 struct iwm_mvm_statistics_rx { 3053 struct iwm_mvm_statistics_rx_phy ofdm; 3054 struct iwm_mvm_statistics_rx_phy cck; 3055 struct iwm_mvm_statistics_rx_non_phy general; 3056 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3057 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3058 3059 /* 3060 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3061 * 3062 * By default, uCode issues this notification after receiving a beacon 3063 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3064 * IWM_STATISTICS_CMD (0x9c), below. 3065 */ 3066 3067 struct iwm_notif_statistics_v10 { 3068 uint32_t flag; 3069 struct iwm_mvm_statistics_rx rx; 3070 struct iwm_mvm_statistics_tx tx; 3071 struct iwm_mvm_statistics_general_v8 general; 3072 } __packed; /* IWM_STATISTICS_NTFY_API_S_VER_10 */ 3073 3074 #define IWM_STATISTICS_FLG_CLEAR 0x1 3075 #define IWM_STATISTICS_FLG_DISABLE_NOTIF 0x2 3076 3077 struct iwm_statistics_cmd { 3078 uint32_t flags; 3079 } __packed; /* IWM_STATISTICS_CMD_API_S_VER_1 */ 3080 3081 /*********************************** 3082 * Smart Fifo API 3083 ***********************************/ 3084 /* Smart Fifo state */ 3085 enum iwm_sf_state { 3086 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3087 IWM_SF_FULL_ON, 3088 IWM_SF_UNINIT, 3089 IWM_SF_INIT_OFF, 3090 IWM_SF_HW_NUM_STATES 3091 }; 3092 3093 /* Smart Fifo possible scenario */ 3094 enum iwm_sf_scenario { 3095 IWM_SF_SCENARIO_SINGLE_UNICAST, 3096 IWM_SF_SCENARIO_AGG_UNICAST, 3097 IWM_SF_SCENARIO_MULTICAST, 3098 IWM_SF_SCENARIO_BA_RESP, 3099 IWM_SF_SCENARIO_TX_RESP, 3100 IWM_SF_NUM_SCENARIO 3101 }; 3102 3103 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3104 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3105 3106 /* smart FIFO default values */ 3107 #define IWM_SF_W_MARK_SISO 4096 3108 #define IWM_SF_W_MARK_MIMO2 8192 3109 #define IWM_SF_W_MARK_MIMO3 6144 3110 #define IWM_SF_W_MARK_LEGACY 4096 3111 #define IWM_SF_W_MARK_SCAN 4096 3112 3113 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3114 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3115 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3116 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3117 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3118 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3119 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3120 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3121 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3122 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3123 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3124 3125 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3126 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3127 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3128 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3129 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3130 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3131 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3132 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3133 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3134 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3135 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3136 3137 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3138 3139 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3140 3141 /** 3142 * Smart Fifo configuration command. 3143 * @state: smart fifo state, types listed in enum %iwm_sf_state. 3144 * @watermark: Minimum allowed available free space in RXF for transient state. 3145 * @long_delay_timeouts: aging and idle timer values for each scenario 3146 * in long delay state. 3147 * @full_on_timeouts: timer values for each scenario in full on state. 3148 */ 3149 struct iwm_sf_cfg_cmd { 3150 uint32_t state; 3151 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3152 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3153 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3154 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3155 3156 enum iwm_ac { 3157 IWM_AC_BK, 3158 IWM_AC_BE, 3159 IWM_AC_VI, 3160 IWM_AC_VO, 3161 IWM_AC_NUM, 3162 }; 3163 3164 /** 3165 * enum iwm_mac_protection_flags - MAC context flags 3166 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3167 * this will require CCK RTS/CTS2self. 3168 * RTS/CTS will protect full burst time. 3169 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3170 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3171 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3172 */ 3173 enum iwm_mac_protection_flags { 3174 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3175 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3176 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3177 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3178 }; 3179 3180 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3181 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3182 3183 /** 3184 * enum iwm_mac_types - Supported MAC types 3185 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3186 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3187 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3188 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3189 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3190 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3191 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3192 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3193 * @IWM_FW_MAC_TYPE_GO: P2P GO 3194 * @IWM_FW_MAC_TYPE_TEST: ? 3195 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3196 */ 3197 enum iwm_mac_types { 3198 IWM_FW_MAC_TYPE_FIRST = 1, 3199 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3200 IWM_FW_MAC_TYPE_LISTENER, 3201 IWM_FW_MAC_TYPE_PIBSS, 3202 IWM_FW_MAC_TYPE_IBSS, 3203 IWM_FW_MAC_TYPE_BSS_STA, 3204 IWM_FW_MAC_TYPE_P2P_DEVICE, 3205 IWM_FW_MAC_TYPE_P2P_STA, 3206 IWM_FW_MAC_TYPE_GO, 3207 IWM_FW_MAC_TYPE_TEST, 3208 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3209 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3210 3211 /** 3212 * enum iwm_tsf_id - TSF hw timer ID 3213 * @IWM_TSF_ID_A: use TSF A 3214 * @IWM_TSF_ID_B: use TSF B 3215 * @IWM_TSF_ID_C: use TSF C 3216 * @IWM_TSF_ID_D: use TSF D 3217 * @IWM_NUM_TSF_IDS: number of TSF timers available 3218 */ 3219 enum iwm_tsf_id { 3220 IWM_TSF_ID_A = 0, 3221 IWM_TSF_ID_B = 1, 3222 IWM_TSF_ID_C = 2, 3223 IWM_TSF_ID_D = 3, 3224 IWM_NUM_TSF_IDS = 4, 3225 }; /* IWM_TSF_ID_API_E_VER_1 */ 3226 3227 /** 3228 * struct iwm_mac_data_ap - configuration data for AP MAC context 3229 * @beacon_time: beacon transmit time in system time 3230 * @beacon_tsf: beacon transmit time in TSF 3231 * @bi: beacon interval in TU 3232 * @bi_reciprocal: 2^32 / bi 3233 * @dtim_interval: dtim transmit time in TU 3234 * @dtim_reciprocal: 2^32 / dtim_interval 3235 * @mcast_qid: queue ID for multicast traffic 3236 * @beacon_template: beacon template ID 3237 */ 3238 struct iwm_mac_data_ap { 3239 uint32_t beacon_time; 3240 uint64_t beacon_tsf; 3241 uint32_t bi; 3242 uint32_t bi_reciprocal; 3243 uint32_t dtim_interval; 3244 uint32_t dtim_reciprocal; 3245 uint32_t mcast_qid; 3246 uint32_t beacon_template; 3247 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3248 3249 /** 3250 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3251 * @beacon_time: beacon transmit time in system time 3252 * @beacon_tsf: beacon transmit time in TSF 3253 * @bi: beacon interval in TU 3254 * @bi_reciprocal: 2^32 / bi 3255 * @beacon_template: beacon template ID 3256 */ 3257 struct iwm_mac_data_ibss { 3258 uint32_t beacon_time; 3259 uint64_t beacon_tsf; 3260 uint32_t bi; 3261 uint32_t bi_reciprocal; 3262 uint32_t beacon_template; 3263 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3264 3265 /** 3266 * struct iwm_mac_data_sta - configuration data for station MAC context 3267 * @is_assoc: 1 for associated state, 0 otherwise 3268 * @dtim_time: DTIM arrival time in system time 3269 * @dtim_tsf: DTIM arrival time in TSF 3270 * @bi: beacon interval in TU, applicable only when associated 3271 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3272 * @dtim_interval: DTIM interval in TU, applicable only when associated 3273 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3274 * @listen_interval: in beacon intervals, applicable only when associated 3275 * @assoc_id: unique ID assigned by the AP during association 3276 */ 3277 struct iwm_mac_data_sta { 3278 uint32_t is_assoc; 3279 uint32_t dtim_time; 3280 uint64_t dtim_tsf; 3281 uint32_t bi; 3282 uint32_t bi_reciprocal; 3283 uint32_t dtim_interval; 3284 uint32_t dtim_reciprocal; 3285 uint32_t listen_interval; 3286 uint32_t assoc_id; 3287 uint32_t assoc_beacon_arrive_time; 3288 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3289 3290 /** 3291 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3292 * @ap: iwm_mac_data_ap struct with most config data 3293 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3294 * 0 indicates that there is no CT window. 3295 * @opp_ps_enabled: indicate that opportunistic PS allowed 3296 */ 3297 struct iwm_mac_data_go { 3298 struct iwm_mac_data_ap ap; 3299 uint32_t ctwin; 3300 uint32_t opp_ps_enabled; 3301 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3302 3303 /** 3304 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3305 * @sta: iwm_mac_data_sta struct with most config data 3306 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3307 * 0 indicates that there is no CT window. 3308 */ 3309 struct iwm_mac_data_p2p_sta { 3310 struct iwm_mac_data_sta sta; 3311 uint32_t ctwin; 3312 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3313 3314 /** 3315 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3316 * @stats_interval: interval in TU between statistics notifications to host. 3317 */ 3318 struct iwm_mac_data_pibss { 3319 uint32_t stats_interval; 3320 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3321 3322 /* 3323 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3324 * context. 3325 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3326 * other channels as well. This should be to true only in case that the 3327 * device is discoverable and there is an active GO. Note that setting this 3328 * field when not needed, will increase the number of interrupts and have 3329 * effect on the platform power, as this setting opens the Rx filters on 3330 * all macs. 3331 */ 3332 struct iwm_mac_data_p2p_dev { 3333 uint32_t is_disc_extended; 3334 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3335 3336 /** 3337 * enum iwm_mac_filter_flags - MAC context filter flags 3338 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3339 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3340 * control frames to the host 3341 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3342 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3343 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3344 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3345 * (in station mode when associated) 3346 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3347 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3348 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3349 */ 3350 enum iwm_mac_filter_flags { 3351 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3352 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3353 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3354 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3355 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3356 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3357 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3358 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3359 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3360 }; 3361 3362 /** 3363 * enum iwm_mac_qos_flags - QoS flags 3364 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3365 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3366 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3367 * 3368 */ 3369 enum iwm_mac_qos_flags { 3370 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3371 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3372 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3373 }; 3374 3375 /** 3376 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3377 * @cw_min: Contention window, start value in numbers of slots. 3378 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3379 * @cw_max: Contention window, max value in numbers of slots. 3380 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3381 * @aifsn: Number of slots in Arbitration Interframe Space (before 3382 * performing random backoff timing prior to Tx). Device default 1. 3383 * @fifos_mask: FIFOs used by this MAC for this AC 3384 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3385 * 3386 * One instance of this config struct for each of 4 EDCA access categories 3387 * in struct iwm_qosparam_cmd. 3388 * 3389 * Device will automatically increase contention window by (2*CW) + 1 for each 3390 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3391 * value, to cap the CW value. 3392 */ 3393 struct iwm_ac_qos { 3394 uint16_t cw_min; 3395 uint16_t cw_max; 3396 uint8_t aifsn; 3397 uint8_t fifos_mask; 3398 uint16_t edca_txop; 3399 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3400 3401 /** 3402 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3403 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3404 * @id_and_color: ID and color of the MAC 3405 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3406 * @mac_type: one of IWM_FW_MAC_TYPE_* 3407 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3408 * @node_addr: MAC address 3409 * @bssid_addr: BSSID 3410 * @cck_rates: basic rates available for CCK 3411 * @ofdm_rates: basic rates available for OFDM 3412 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3413 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3414 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3415 * @filter_flags: combination of IWM_MAC_FILTER_* 3416 * @qos_flags: from IWM_MAC_QOS_FLG_* 3417 * @ac: one iwm_mac_qos configuration for each AC 3418 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3419 */ 3420 struct iwm_mac_ctx_cmd { 3421 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3422 uint32_t id_and_color; 3423 uint32_t action; 3424 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3425 uint32_t mac_type; 3426 uint32_t tsf_id; 3427 uint8_t node_addr[6]; 3428 uint16_t reserved_for_node_addr; 3429 uint8_t bssid_addr[6]; 3430 uint16_t reserved_for_bssid_addr; 3431 uint32_t cck_rates; 3432 uint32_t ofdm_rates; 3433 uint32_t protection_flags; 3434 uint32_t cck_short_preamble; 3435 uint32_t short_slot; 3436 uint32_t filter_flags; 3437 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3438 uint32_t qos_flags; 3439 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3440 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3441 union { 3442 struct iwm_mac_data_ap ap; 3443 struct iwm_mac_data_go go; 3444 struct iwm_mac_data_sta sta; 3445 struct iwm_mac_data_p2p_sta p2p_sta; 3446 struct iwm_mac_data_p2p_dev p2p_dev; 3447 struct iwm_mac_data_pibss pibss; 3448 struct iwm_mac_data_ibss ibss; 3449 }; 3450 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3451 3452 static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3453 { 3454 if (!v) 3455 return 0; 3456 return 0xFFFFFFFF / v; 3457 } 3458 3459 #define IWM_NONQOS_SEQ_GET 0x1 3460 #define IWM_NONQOS_SEQ_SET 0x2 3461 struct iwm_nonqos_seq_query_cmd { 3462 uint32_t get_set_flag; 3463 uint32_t mac_id_n_color; 3464 uint16_t value; 3465 uint16_t reserved; 3466 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3467 3468 /* Power Management Commands, Responses, Notifications */ 3469 3470 /* Radio LP RX Energy Threshold measured in dBm */ 3471 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3472 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3473 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3474 3475 /** 3476 * enum iwm_scan_flags - masks for power table command flags 3477 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3478 * receiver and transmitter. '0' - does not allow. 3479 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3480 * '1' Driver enables PM (use rest of parameters) 3481 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3482 * '1' PM could sleep over DTIM till listen Interval. 3483 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3484 * access categories are both delivery and trigger enabled. 3485 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3486 * PBW Snoozing enabled 3487 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3488 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3489 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3490 * detection enablement 3491 */ 3492 enum iwm_power_flags { 3493 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3494 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3495 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3496 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3497 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3498 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3499 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3500 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3501 }; 3502 3503 #define IWM_POWER_VEC_SIZE 5 3504 3505 /** 3506 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3507 * is used also with a new power API for device wide power settings. 3508 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3509 * 3510 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3511 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3512 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3513 * set regardless of power scheme or current power state. 3514 * FW use this value also when PM is disabled. 3515 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3516 * PSM transition - legacy PM 3517 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3518 * PSM transition - legacy PM 3519 * @sleep_interval: not in use 3520 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3521 * is set. For example, if it is required to skip over 3522 * one DTIM, this value need to be set to 2 (DTIM periods). 3523 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3524 * Default: 80dbm 3525 */ 3526 struct iwm_powertable_cmd { 3527 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3528 uint16_t flags; 3529 uint8_t keep_alive_seconds; 3530 uint8_t debug_flags; 3531 uint32_t rx_data_timeout; 3532 uint32_t tx_data_timeout; 3533 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3534 uint32_t skip_dtim_periods; 3535 uint32_t lprx_rssi_threshold; 3536 } __packed; 3537 3538 /** 3539 * enum iwm_device_power_flags - masks for device power command flags 3540 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3541 * receiver and transmitter. '0' - does not allow. 3542 */ 3543 enum iwm_device_power_flags { 3544 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3545 }; 3546 3547 /** 3548 * struct iwm_device_power_cmd - device wide power command. 3549 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3550 * 3551 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3552 */ 3553 struct iwm_device_power_cmd { 3554 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3555 uint16_t flags; 3556 uint16_t reserved; 3557 } __packed; 3558 3559 /** 3560 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3561 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3562 * @id_and_color: MAC contex identifier 3563 * @flags: Power table command flags from POWER_FLAGS_* 3564 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3565 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3566 * set regardless of power scheme or current power state. 3567 * FW use this value also when PM is disabled. 3568 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3569 * PSM transition - legacy PM 3570 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3571 * PSM transition - legacy PM 3572 * @sleep_interval: not in use 3573 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3574 * is set. For example, if it is required to skip over 3575 * one DTIM, this value need to be set to 2 (DTIM periods). 3576 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3577 * PSM transition - uAPSD 3578 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3579 * PSM transition - uAPSD 3580 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3581 * Default: 80dbm 3582 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3583 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3584 * from the AP [msec] 3585 * @snooze_window: A window of time in which PBW snoozing insures that all 3586 * packets received. It is also the minimum time from last 3587 * received unicast RX packet, before client stops snoozing 3588 * for data. [msec] 3589 * @snooze_step: TBD 3590 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3591 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3592 * each corresponding AC. 3593 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3594 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3595 * values. 3596 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3597 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3598 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3599 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3600 * @limited_ps_threshold: 3601 */ 3602 struct iwm_mac_power_cmd { 3603 /* CONTEXT_DESC_API_T_VER_1 */ 3604 uint32_t id_and_color; 3605 3606 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3607 uint16_t flags; 3608 uint16_t keep_alive_seconds; 3609 uint32_t rx_data_timeout; 3610 uint32_t tx_data_timeout; 3611 uint32_t rx_data_timeout_uapsd; 3612 uint32_t tx_data_timeout_uapsd; 3613 uint8_t lprx_rssi_threshold; 3614 uint8_t skip_dtim_periods; 3615 uint16_t snooze_interval; 3616 uint16_t snooze_window; 3617 uint8_t snooze_step; 3618 uint8_t qndp_tid; 3619 uint8_t uapsd_ac_flags; 3620 uint8_t uapsd_max_sp; 3621 uint8_t heavy_tx_thld_packets; 3622 uint8_t heavy_rx_thld_packets; 3623 uint8_t heavy_tx_thld_percentage; 3624 uint8_t heavy_rx_thld_percentage; 3625 uint8_t limited_ps_threshold; 3626 uint8_t reserved; 3627 } __packed; 3628 3629 /* 3630 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3631 * associated AP is identified as improperly implementing uAPSD protocol. 3632 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3633 * @sta_id: index of station in uCode's station table - associated AP ID in 3634 * this context. 3635 */ 3636 struct iwm_uapsd_misbehaving_ap_notif { 3637 uint32_t sta_id; 3638 uint8_t mac_id; 3639 uint8_t reserved[3]; 3640 } __packed; 3641 3642 /** 3643 * struct iwm_beacon_filter_cmd 3644 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3645 * @id_and_color: MAC contex identifier 3646 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3647 * to driver if delta in Energy values calculated for this and last 3648 * passed beacon is greater than this threshold. Zero value means that 3649 * the Energy change is ignored for beacon filtering, and beacon will 3650 * not be forced to be sent to driver regardless of this delta. Typical 3651 * energy delta 5dB. 3652 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3653 * Send beacon to driver if delta in Energy values calculated for this 3654 * and last passed beacon is greater than this threshold. Zero value 3655 * means that the Energy change is ignored for beacon filtering while in 3656 * Roaming state, typical energy delta 1dB. 3657 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3658 * calculated for current beacon is less than the threshold, use 3659 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3660 * Threshold. Typical energy threshold is -72dBm. 3661 * @bf_temp_threshold: This threshold determines the type of temperature 3662 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3663 * If the current temperature is above this threshold - Fast filter 3664 * will be used, If the current temperature is below this threshold - 3665 * Slow filter will be used. 3666 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3667 * calculated for this and the last passed beacon is greater than this 3668 * threshold. Zero value means that the temperature change is ignored for 3669 * beacon filtering; beacons will not be forced to be sent to driver 3670 * regardless of whether its temperature has been changed. 3671 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3672 * calculated for this and the last passed beacon is greater than this 3673 * threshold. Zero value means that the temperature change is ignored for 3674 * beacon filtering; beacons will not be forced to be sent to driver 3675 * regardless of whether its temperature has been changed. 3676 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3677 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3678 * for a specific period of time. Units: Beacons. 3679 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3680 * for a longer period of time then this escape-timeout. Units: Beacons. 3681 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3682 */ 3683 struct iwm_beacon_filter_cmd { 3684 uint32_t bf_energy_delta; 3685 uint32_t bf_roaming_energy_delta; 3686 uint32_t bf_roaming_state; 3687 uint32_t bf_temp_threshold; 3688 uint32_t bf_temp_fast_filter; 3689 uint32_t bf_temp_slow_filter; 3690 uint32_t bf_enable_beacon_filter; 3691 uint32_t bf_debug_flag; 3692 uint32_t bf_escape_timer; 3693 uint32_t ba_escape_timer; 3694 uint32_t ba_enable_beacon_abort; 3695 } __packed; 3696 3697 /* Beacon filtering and beacon abort */ 3698 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3699 #define IWM_BF_ENERGY_DELTA_MAX 255 3700 #define IWM_BF_ENERGY_DELTA_MIN 0 3701 3702 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3703 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3704 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3705 3706 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3707 #define IWM_BF_ROAMING_STATE_MAX 255 3708 #define IWM_BF_ROAMING_STATE_MIN 0 3709 3710 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3711 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3712 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3713 3714 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3715 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3716 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3717 3718 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3719 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3720 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3721 3722 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3723 3724 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3725 3726 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3727 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3728 #define IWM_BF_ESCAPE_TIMER_MIN 0 3729 3730 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3731 #define IWM_BA_ESCAPE_TIMER_D3 9 3732 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3733 #define IWM_BA_ESCAPE_TIMER_MIN 0 3734 3735 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3736 3737 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3738 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3739 .bf_roaming_energy_delta = \ 3740 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3741 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3742 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3743 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3744 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3745 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3746 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3747 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3748 3749 /* 3750 * These serve as indexes into 3751 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3752 * TODO: avoid overlap between legacy and HT rates 3753 */ 3754 enum { 3755 IWM_RATE_1M_INDEX = 0, 3756 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3757 IWM_RATE_2M_INDEX, 3758 IWM_RATE_5M_INDEX, 3759 IWM_RATE_11M_INDEX, 3760 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3761 IWM_RATE_6M_INDEX, 3762 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3763 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3764 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3765 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3766 IWM_RATE_9M_INDEX, 3767 IWM_RATE_12M_INDEX, 3768 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3769 IWM_RATE_18M_INDEX, 3770 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3771 IWM_RATE_24M_INDEX, 3772 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3773 IWM_RATE_36M_INDEX, 3774 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3775 IWM_RATE_48M_INDEX, 3776 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3777 IWM_RATE_54M_INDEX, 3778 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3779 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3780 IWM_RATE_60M_INDEX, 3781 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3782 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3783 IWM_RATE_MCS_8_INDEX, 3784 IWM_RATE_MCS_9_INDEX, 3785 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3786 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3787 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3788 }; 3789 3790 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3791 3792 /* fw API values for legacy bit rates, both OFDM and CCK */ 3793 enum { 3794 IWM_RATE_6M_PLCP = 13, 3795 IWM_RATE_9M_PLCP = 15, 3796 IWM_RATE_12M_PLCP = 5, 3797 IWM_RATE_18M_PLCP = 7, 3798 IWM_RATE_24M_PLCP = 9, 3799 IWM_RATE_36M_PLCP = 11, 3800 IWM_RATE_48M_PLCP = 1, 3801 IWM_RATE_54M_PLCP = 3, 3802 IWM_RATE_1M_PLCP = 10, 3803 IWM_RATE_2M_PLCP = 20, 3804 IWM_RATE_5M_PLCP = 55, 3805 IWM_RATE_11M_PLCP = 110, 3806 IWM_RATE_INVM_PLCP = -1, 3807 }; 3808 3809 /* 3810 * rate_n_flags bit fields 3811 * 3812 * The 32-bit value has different layouts in the low 8 bites depending on the 3813 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3814 * for CCK and OFDM). 3815 * 3816 * High-throughput (HT) rate format 3817 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3818 * Very High-throughput (VHT) rate format 3819 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3820 * Legacy OFDM rate format for bits 7:0 3821 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3822 * Legacy CCK rate format for bits 7:0: 3823 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3824 */ 3825 3826 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3827 #define IWM_RATE_MCS_HT_POS 8 3828 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3829 3830 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3831 #define IWM_RATE_MCS_CCK_POS 9 3832 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3833 3834 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3835 #define IWM_RATE_MCS_VHT_POS 26 3836 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3837 3838 3839 /* 3840 * High-throughput (HT) rate format for bits 7:0 3841 * 3842 * 2-0: MCS rate base 3843 * 0) 6 Mbps 3844 * 1) 12 Mbps 3845 * 2) 18 Mbps 3846 * 3) 24 Mbps 3847 * 4) 36 Mbps 3848 * 5) 48 Mbps 3849 * 6) 54 Mbps 3850 * 7) 60 Mbps 3851 * 4-3: 0) Single stream (SISO) 3852 * 1) Dual stream (MIMO) 3853 * 2) Triple stream (MIMO) 3854 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3855 * (bits 7-6 are zero) 3856 * 3857 * Together the low 5 bits work out to the MCS index because we don't 3858 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3859 * streams and 16-23 have three streams. We could also support MCS 32 3860 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3861 */ 3862 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3863 #define IWM_RATE_HT_MCS_NSS_POS 3 3864 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3865 3866 /* Bit 10: (1) Use Green Field preamble */ 3867 #define IWM_RATE_HT_MCS_GF_POS 10 3868 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3869 3870 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3871 3872 /* 3873 * Very High-throughput (VHT) rate format for bits 7:0 3874 * 3875 * 3-0: VHT MCS (0-9) 3876 * 5-4: number of streams - 1: 3877 * 0) Single stream (SISO) 3878 * 1) Dual stream (MIMO) 3879 * 2) Triple stream (MIMO) 3880 */ 3881 3882 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3883 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3884 #define IWM_RATE_VHT_MCS_NSS_POS 4 3885 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3886 3887 /* 3888 * Legacy OFDM rate format for bits 7:0 3889 * 3890 * 3-0: 0xD) 6 Mbps 3891 * 0xF) 9 Mbps 3892 * 0x5) 12 Mbps 3893 * 0x7) 18 Mbps 3894 * 0x9) 24 Mbps 3895 * 0xB) 36 Mbps 3896 * 0x1) 48 Mbps 3897 * 0x3) 54 Mbps 3898 * (bits 7-4 are 0) 3899 * 3900 * Legacy CCK rate format for bits 7:0: 3901 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3902 * 3903 * 6-0: 10) 1 Mbps 3904 * 20) 2 Mbps 3905 * 55) 5.5 Mbps 3906 * 110) 11 Mbps 3907 * (bit 7 is 0) 3908 */ 3909 #define IWM_RATE_LEGACY_RATE_MSK 0xff 3910 3911 3912 /* 3913 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 3914 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 3915 */ 3916 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 3917 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3918 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3919 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3920 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3921 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3922 3923 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 3924 #define IWM_RATE_MCS_SGI_POS 13 3925 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 3926 3927 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 3928 #define IWM_RATE_MCS_ANT_POS 14 3929 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 3930 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 3931 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 3932 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 3933 IWM_RATE_MCS_ANT_B_MSK) 3934 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 3935 IWM_RATE_MCS_ANT_C_MSK) 3936 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 3937 #define IWM_RATE_MCS_ANT_NUM 3 3938 3939 /* Bit 17-18: (0) SS, (1) SS*2 */ 3940 #define IWM_RATE_MCS_STBC_POS 17 3941 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 3942 3943 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 3944 #define IWM_RATE_MCS_BF_POS 19 3945 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 3946 3947 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 3948 #define IWM_RATE_MCS_ZLF_POS 20 3949 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 3950 3951 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 3952 #define IWM_RATE_MCS_DUP_POS 24 3953 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 3954 3955 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 3956 #define IWM_RATE_MCS_LDPC_POS 27 3957 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 3958 3959 3960 /* Link Quality definitions */ 3961 3962 /* # entries in rate scale table to support Tx retries */ 3963 #define IWM_LQ_MAX_RETRY_NUM 16 3964 3965 /* Link quality command flags bit fields */ 3966 3967 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 3968 #define IWM_LQ_FLAG_USE_RTS_POS 0 3969 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 3970 3971 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 3972 #define IWM_LQ_FLAG_COLOR_POS 1 3973 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 3974 3975 /* Bit 4-5: Tx RTS BW Signalling 3976 * (0) No RTS BW signalling 3977 * (1) Static BW signalling 3978 * (2) Dynamic BW signalling 3979 */ 3980 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 3981 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 3982 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 3983 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 3984 3985 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 3986 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 3987 */ 3988 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 3989 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 3990 3991 /* Single Stream Tx Parameters (lq_cmd->ss_params) 3992 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 3993 * used for single stream Tx. 3994 */ 3995 3996 /* Bit 0-1: Max STBC streams allowed. Can be 0-3. 3997 * (0) - No STBC allowed 3998 * (1) - 2x1 STBC allowed (HT/VHT) 3999 * (2) - 4x2 STBC allowed (HT/VHT) 4000 * (3) - 3x2 STBC allowed (HT only) 4001 * All our chips are at most 2 antennas so only (1) is valid for now. 4002 */ 4003 #define IWM_LQ_SS_STBC_ALLOWED_POS 0 4004 #define IWM_LQ_SS_STBC_ALLOWED_MSK (3 << IWM_LQ_SS_STBC_ALLOWED_MSK) 4005 4006 /* 2x1 STBC is allowed */ 4007 #define IWM_LQ_SS_STBC_1SS_ALLOWED (1 << IWM_LQ_SS_STBC_ALLOWED_POS) 4008 4009 /* Bit 2: Beamformer (VHT only) is allowed */ 4010 #define IWM_LQ_SS_BFER_ALLOWED_POS 2 4011 #define IWM_LQ_SS_BFER_ALLOWED (1 << IWM_LQ_SS_BFER_ALLOWED_POS) 4012 4013 /* Bit 3: Force BFER or STBC for testing 4014 * If this is set: 4015 * If BFER is allowed then force the ucode to choose BFER else 4016 * If STBC is allowed then force the ucode to choose STBC over SISO 4017 */ 4018 #define IWM_LQ_SS_FORCE_POS 3 4019 #define IWM_LQ_SS_FORCE (1 << IWM_LQ_SS_FORCE_POS) 4020 4021 /* Bit 31: ss_params field is valid. Used for FW backward compatibility 4022 * with other drivers which don't support the ss_params API yet 4023 */ 4024 #define IWM_LQ_SS_PARAMS_VALID_POS 31 4025 #define IWM_LQ_SS_PARAMS_VALID (1 << IWM_LQ_SS_PARAMS_VALID_POS) 4026 4027 /** 4028 * struct iwm_lq_cmd - link quality command 4029 * @sta_id: station to update 4030 * @control: not used 4031 * @flags: combination of IWM_LQ_FLAG_* 4032 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4033 * and SISO rates 4034 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4035 * Should be ANT_[ABC] 4036 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4037 * @initial_rate_index: first index from rs_table per AC category 4038 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4039 * value of 100 is one usec. Range is 100 to 8000 4040 * @agg_disable_start_th: try-count threshold for starting aggregation. 4041 * If a frame has higher try-count, it should not be selected for 4042 * starting an aggregation sequence. 4043 * @agg_frame_cnt_limit: max frame count in an aggregation. 4044 * 0: no limit 4045 * 1: no aggregation (one frame per aggregation) 4046 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4047 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4048 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4049 * @ss_params: single stream features. declare whether STBC or BFER are allowed. 4050 */ 4051 struct iwm_lq_cmd { 4052 uint8_t sta_id; 4053 uint8_t reduced_tpc; 4054 uint16_t control; 4055 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4056 uint8_t flags; 4057 uint8_t mimo_delim; 4058 uint8_t single_stream_ant_msk; 4059 uint8_t dual_stream_ant_msk; 4060 uint8_t initial_rate_index[IWM_AC_NUM]; 4061 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4062 uint16_t agg_time_limit; 4063 uint8_t agg_disable_start_th; 4064 uint8_t agg_frame_cnt_limit; 4065 uint32_t reserved2; 4066 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4067 uint32_t ss_params; 4068 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4069 4070 /** 4071 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4072 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4073 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4074 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4075 * Otherwise, use rate_n_flags from the TX command 4076 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4077 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4078 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4079 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4080 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4081 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4082 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4083 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4084 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4085 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4086 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4087 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4088 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4089 * Should be set for beacons and probe responses 4090 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4091 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4092 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4093 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4094 * Should be set for 26/30 length MAC headers 4095 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4096 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4097 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4098 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4099 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4100 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4101 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4102 */ 4103 enum iwm_tx_flags { 4104 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4105 IWM_TX_CMD_FLG_ACK = (1 << 3), 4106 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4107 IWM_TX_CMD_FLG_BA = (1 << 5), 4108 IWM_TX_CMD_FLG_BAR = (1 << 6), 4109 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4110 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4111 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4112 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4113 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4114 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4115 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4116 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4117 IWM_TX_CMD_FLG_TSF = (1 << 16), 4118 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4119 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4120 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4121 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4122 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4123 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4124 IWM_TX_CMD_FLG_DUR = (1 << 25), 4125 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4126 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4127 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4128 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4129 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4130 4131 /** 4132 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4133 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4134 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4135 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4136 */ 4137 enum iwm_tx_pm_timeouts { 4138 IWM_PM_FRAME_NONE = 0, 4139 IWM_PM_FRAME_MGMT = 2, 4140 IWM_PM_FRAME_ASSOC = 3, 4141 }; 4142 4143 /* 4144 * TX command security control 4145 */ 4146 #define IWM_TX_CMD_SEC_WEP 0x01 4147 #define IWM_TX_CMD_SEC_CCM 0x02 4148 #define IWM_TX_CMD_SEC_TKIP 0x03 4149 #define IWM_TX_CMD_SEC_EXT 0x04 4150 #define IWM_TX_CMD_SEC_MSK 0x07 4151 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4152 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4153 #define IWM_TX_CMD_SEC_KEY128 0x08 4154 4155 /* TODO: how does these values are OK with only 16 bit variable??? */ 4156 /* 4157 * TX command next frame info 4158 * 4159 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4160 * bit 3 - immediate ACK required 4161 * bit 4 - rate is taken from STA table 4162 * bit 5 - frame belongs to BA stream 4163 * bit 6 - immediate BA response expected 4164 * bit 7 - unused 4165 * bits 8:15 - Station ID 4166 * bits 16:31 - rate 4167 */ 4168 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4169 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4170 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4171 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4172 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4173 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4174 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4175 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4176 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4177 4178 /* 4179 * TX command Frame life time in us - to be written in pm_frame_timeout 4180 */ 4181 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4182 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4183 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4184 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4185 4186 /* 4187 * TID for non QoS frames - to be written in tid_tspec 4188 */ 4189 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4190 4191 /* 4192 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4193 */ 4194 #define IWM_DEFAULT_TX_RETRY 15 4195 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4196 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4197 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4198 #define IWM_LOW_RETRY_LIMIT 7 4199 4200 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4201 /** 4202 * struct iwm_tx_cmd - TX command struct to FW 4203 * ( IWM_TX_CMD = 0x1c ) 4204 * @len: in bytes of the payload, see below for details 4205 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4206 * Used for fragmentation and bursting, but not in 11n aggregation. 4207 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4208 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4209 * cleared. Combination of IWM_RATE_MCS_* 4210 * @sta_id: index of destination station in FW station table 4211 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4212 * @initial_rate_index: index into the rate table for initial TX attempt. 4213 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4214 * @key: security key 4215 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4216 * @life_time: frame life time (usecs??) 4217 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4218 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4219 * @dram_msb_ptr: upper bits of the scratch physical address 4220 * @rts_retry_limit: max attempts for RTS 4221 * @data_retry_limit: max attempts to send the data packet 4222 * @tid_spec: TID/tspec 4223 * @pm_frame_timeout: PM TX frame timeout 4224 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4225 * specified by HCCA protocol 4226 * 4227 * The byte count (both len and next_frame_len) includes MAC header 4228 * (24/26/30/32 bytes) 4229 * + 2 bytes pad if 26/30 header size 4230 * + 8 byte IV for CCM or TKIP (not used for WEP) 4231 * + Data payload 4232 * + 8-byte MIC (not used for CCM/WEP) 4233 * It does not include post-MAC padding, i.e., 4234 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4235 * Range of len: 14-2342 bytes. 4236 * 4237 * After the struct fields the MAC header is placed, plus any padding, 4238 * and then the actial payload. 4239 */ 4240 struct iwm_tx_cmd { 4241 uint16_t len; 4242 uint16_t next_frame_len; 4243 uint32_t tx_flags; 4244 struct { 4245 uint8_t try_cnt; 4246 uint8_t btkill_cnt; 4247 uint16_t reserved; 4248 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4249 uint32_t rate_n_flags; 4250 uint8_t sta_id; 4251 uint8_t sec_ctl; 4252 uint8_t initial_rate_index; 4253 uint8_t reserved2; 4254 uint8_t key[16]; 4255 uint16_t next_frame_flags; 4256 uint16_t reserved3; 4257 uint32_t life_time; 4258 uint32_t dram_lsb_ptr; 4259 uint8_t dram_msb_ptr; 4260 uint8_t rts_retry_limit; 4261 uint8_t data_retry_limit; 4262 uint8_t tid_tspec; 4263 uint16_t pm_frame_timeout; 4264 uint16_t driver_txop; 4265 uint8_t payload[0]; 4266 struct ieee80211_frame hdr[0]; 4267 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4268 4269 /* 4270 * TX response related data 4271 */ 4272 4273 /* 4274 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4275 * @IWM_TX_STATUS_SUCCESS: 4276 * @IWM_TX_STATUS_DIRECT_DONE: 4277 * @IWM_TX_STATUS_POSTPONE_DELAY: 4278 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4279 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4280 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4281 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4282 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4283 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4284 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4285 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4286 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4287 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4288 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4289 * @IWM_TX_STATUS_FAIL_DEST_PS: 4290 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4291 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4292 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4293 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4294 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4295 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4296 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4297 * @IWM_TX_STATUS_FAIL_FW_DROP: 4298 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4299 * STA table 4300 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4301 * @IWM_TX_MODE_MSK: 4302 * @IWM_TX_MODE_NO_BURST: 4303 * @IWM_TX_MODE_IN_BURST_SEQ: 4304 * @IWM_TX_MODE_FIRST_IN_BURST: 4305 * @IWM_TX_QUEUE_NUM_MSK: 4306 * 4307 * Valid only if frame_count =1 4308 * TODO: complete documentation 4309 */ 4310 enum iwm_tx_status { 4311 IWM_TX_STATUS_MSK = 0x000000ff, 4312 IWM_TX_STATUS_SUCCESS = 0x01, 4313 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4314 /* postpone TX */ 4315 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4316 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4317 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4318 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4319 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4320 /* abort TX */ 4321 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4322 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4323 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4324 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4325 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4326 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4327 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4328 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4329 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4330 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4331 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4332 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4333 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4334 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4335 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4336 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4337 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4338 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4339 IWM_TX_MODE_MSK = 0x00000f00, 4340 IWM_TX_MODE_NO_BURST = 0x00000000, 4341 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4342 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4343 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4344 IWM_TX_NARROW_BW_MSK = 0x00060000, 4345 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4346 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4347 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4348 }; 4349 4350 /* 4351 * enum iwm_tx_agg_status - TX aggregation status 4352 * @IWM_AGG_TX_STATE_STATUS_MSK: 4353 * @IWM_AGG_TX_STATE_TRANSMITTED: 4354 * @IWM_AGG_TX_STATE_UNDERRUN: 4355 * @IWM_AGG_TX_STATE_BT_PRIO: 4356 * @IWM_AGG_TX_STATE_FEW_BYTES: 4357 * @IWM_AGG_TX_STATE_ABORT: 4358 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4359 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4360 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4361 * @IWM_AGG_TX_STATE_SCD_QUERY: 4362 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4363 * @IWM_AGG_TX_STATE_RESPONSE: 4364 * @IWM_AGG_TX_STATE_DUMP_TX: 4365 * @IWM_AGG_TX_STATE_DELAY_TX: 4366 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4367 * occur if tx failed for this frame when it was a member of a previous 4368 * aggregation block). If rate scaling is used, retry count indicates the 4369 * rate table entry used for all frames in the new agg. 4370 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4371 * this frame 4372 * 4373 * TODO: complete documentation 4374 */ 4375 enum iwm_tx_agg_status { 4376 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4377 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4378 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4379 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4380 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4381 IWM_AGG_TX_STATE_ABORT = 0x008, 4382 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4383 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4384 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4385 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4386 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4387 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4388 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4389 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4390 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4391 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4392 }; 4393 4394 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4395 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4396 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4397 4398 /* 4399 * The mask below describes a status where we are absolutely sure that the MPDU 4400 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4401 * written the bytes to the TXE, but we know nothing about what the DSP did. 4402 */ 4403 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4404 IWM_AGG_TX_STATE_ABORT | \ 4405 IWM_AGG_TX_STATE_SCD_QUERY) 4406 4407 /* 4408 * IWM_REPLY_TX = 0x1c (response) 4409 * 4410 * This response may be in one of two slightly different formats, indicated 4411 * by the frame_count field: 4412 * 4413 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4414 * frame. Multiple attempts, at various bit rates, may have been made for 4415 * this frame. 4416 * 4417 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4418 * frames that used block-acknowledge. All frames were transmitted at 4419 * same rate. Rate scaling may have been used if first frame in this new 4420 * agg block failed in previous agg block(s). 4421 * 4422 * Note that, for aggregation, ACK (block-ack) status is not delivered 4423 * here; block-ack has not been received by the time the device records 4424 * this status. 4425 * This status relates to reasons the tx might have been blocked or aborted 4426 * within the device, rather than whether it was received successfully by 4427 * the destination station. 4428 */ 4429 4430 /** 4431 * struct iwm_agg_tx_status - per packet TX aggregation status 4432 * @status: enum iwm_tx_agg_status 4433 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4434 */ 4435 struct iwm_agg_tx_status { 4436 uint16_t status; 4437 uint16_t sequence; 4438 } __packed; 4439 4440 /* 4441 * definitions for initial rate index field 4442 * bits [3:0] initial rate index 4443 * bits [6:4] rate table color, used for the initial rate 4444 * bit-7 invalid rate indication 4445 */ 4446 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4447 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4448 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4449 4450 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4451 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4452 4453 /** 4454 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4455 * ( IWM_REPLY_TX = 0x1c ) 4456 * @frame_count: 1 no aggregation, >1 aggregation 4457 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4458 * @failure_rts: num of failures due to unsuccessful RTS 4459 * @failure_frame: num failures due to no ACK (unused for agg) 4460 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4461 * Tx of all the batch. IWM_RATE_MCS_* 4462 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4463 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4464 * in usec. 4465 * @pa_status: tx power info 4466 * @pa_integ_res_a: tx power info 4467 * @pa_integ_res_b: tx power info 4468 * @pa_integ_res_c: tx power info 4469 * @measurement_req_id: tx power info 4470 * @tfd_info: TFD information set by the FH 4471 * @seq_ctl: sequence control from the Tx cmd 4472 * @byte_cnt: byte count from the Tx cmd 4473 * @tlc_info: TLC rate info 4474 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4475 * @frame_ctrl: frame control 4476 * @status: for non-agg: frame status IWM_TX_STATUS_* 4477 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4478 * follow this one, up to frame_count. 4479 * 4480 * After the array of statuses comes the SSN of the SCD. Look at 4481 * %iwm_mvm_get_scd_ssn for more details. 4482 */ 4483 struct iwm_mvm_tx_resp { 4484 uint8_t frame_count; 4485 uint8_t bt_kill_count; 4486 uint8_t failure_rts; 4487 uint8_t failure_frame; 4488 uint32_t initial_rate; 4489 uint16_t wireless_media_time; 4490 4491 uint8_t pa_status; 4492 uint8_t pa_integ_res_a[3]; 4493 uint8_t pa_integ_res_b[3]; 4494 uint8_t pa_integ_res_c[3]; 4495 uint16_t measurement_req_id; 4496 uint8_t reduced_tpc; 4497 uint8_t reserved; 4498 4499 uint32_t tfd_info; 4500 uint16_t seq_ctl; 4501 uint16_t byte_cnt; 4502 uint8_t tlc_info; 4503 uint8_t ra_tid; 4504 uint16_t frame_ctrl; 4505 4506 struct iwm_agg_tx_status status; 4507 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4508 4509 /** 4510 * struct iwm_mvm_ba_notif - notifies about reception of BA 4511 * ( IWM_BA_NOTIF = 0xc5 ) 4512 * @sta_addr_lo32: lower 32 bits of the MAC address 4513 * @sta_addr_hi16: upper 16 bits of the MAC address 4514 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4515 * @tid: tid of the session 4516 * @seq_ctl: 4517 * @bitmap: the bitmap of the BA notification as seen in the air 4518 * @scd_flow: the tx queue this BA relates to 4519 * @scd_ssn: the index of the last contiguously sent packet 4520 * @txed: number of Txed frames in this batch 4521 * @txed_2_done: number of Acked frames in this batch 4522 */ 4523 struct iwm_mvm_ba_notif { 4524 uint32_t sta_addr_lo32; 4525 uint16_t sta_addr_hi16; 4526 uint16_t reserved; 4527 4528 uint8_t sta_id; 4529 uint8_t tid; 4530 uint16_t seq_ctl; 4531 uint64_t bitmap; 4532 uint16_t scd_flow; 4533 uint16_t scd_ssn; 4534 uint8_t txed; 4535 uint8_t txed_2_done; 4536 uint16_t reserved1; 4537 } __packed; 4538 4539 /* 4540 * struct iwm_mac_beacon_cmd - beacon template command 4541 * @tx: the tx commands associated with the beacon frame 4542 * @template_id: currently equal to the mac context id of the coresponding 4543 * mac. 4544 * @tim_idx: the offset of the tim IE in the beacon 4545 * @tim_size: the length of the tim IE 4546 * @frame: the template of the beacon frame 4547 */ 4548 struct iwm_mac_beacon_cmd { 4549 struct iwm_tx_cmd tx; 4550 uint32_t template_id; 4551 uint32_t tim_idx; 4552 uint32_t tim_size; 4553 struct ieee80211_frame frame[0]; 4554 } __packed; 4555 4556 struct iwm_beacon_notif { 4557 struct iwm_mvm_tx_resp beacon_notify_hdr; 4558 uint64_t tsf; 4559 uint32_t ibss_mgr_status; 4560 } __packed; 4561 4562 /** 4563 * enum iwm_dump_control - dump (flush) control flags 4564 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4565 * and the TFD queues are empty. 4566 */ 4567 enum iwm_dump_control { 4568 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4569 }; 4570 4571 /** 4572 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4573 * @queues_ctl: bitmap of queues to flush 4574 * @flush_ctl: control flags 4575 * @reserved: reserved 4576 */ 4577 struct iwm_tx_path_flush_cmd { 4578 uint32_t queues_ctl; 4579 uint16_t flush_ctl; 4580 uint16_t reserved; 4581 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4582 4583 /** 4584 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4585 * @tx_resp: the Tx response from the fw (agg or non-agg) 4586 * 4587 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4588 * it can't know that everything will go well until the end of the AMPDU, it 4589 * can't know in advance the number of MPDUs that will be sent in the current 4590 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4591 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4592 * of the batch. This is why the SSN of the SCD is written at the end of the 4593 * whole struct at a variable offset. This function knows how to cope with the 4594 * variable offset and returns the SSN of the SCD. 4595 */ 4596 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4597 { 4598 return le32_to_cpup((uint32_t *)&tx_resp->status + 4599 tx_resp->frame_count) & 0xfff; 4600 } 4601 4602 /** 4603 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4604 * @token: 4605 * @sta_id: station id 4606 * @tid: 4607 * @scd_queue: scheduler queue to confiug 4608 * @enable: 1 queue enable, 0 queue disable 4609 * @aggregate: 1 aggregated queue, 0 otherwise 4610 * @tx_fifo: %enum iwm_mvm_tx_fifo 4611 * @window: BA window size 4612 * @ssn: SSN for the BA agreement 4613 */ 4614 struct iwm_scd_txq_cfg_cmd { 4615 uint8_t token; 4616 uint8_t sta_id; 4617 uint8_t tid; 4618 uint8_t scd_queue; 4619 uint8_t enable; 4620 uint8_t aggregate; 4621 uint8_t tx_fifo; 4622 uint8_t window; 4623 uint16_t ssn; 4624 uint16_t reserved; 4625 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4626 4627 /** 4628 * struct iwm_scd_txq_cfg_rsp 4629 * @token: taken from the command 4630 * @sta_id: station id from the command 4631 * @tid: tid from the command 4632 * @scd_queue: scd_queue from the command 4633 */ 4634 struct iwm_scd_txq_cfg_rsp { 4635 uint8_t token; 4636 uint8_t sta_id; 4637 uint8_t tid; 4638 uint8_t scd_queue; 4639 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4640 4641 4642 /* Scan Commands, Responses, Notifications */ 4643 4644 /* Max number of IEs for direct SSID scans in a command */ 4645 #define IWM_PROBE_OPTION_MAX 20 4646 4647 /** 4648 * struct iwm_ssid_ie - directed scan network information element 4649 * 4650 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4651 * selected by "type" bit field in struct iwm_scan_channel; 4652 * each channel may select different ssids from among the 20 entries. 4653 * SSID IEs get transmitted in reverse order of entry. 4654 */ 4655 struct iwm_ssid_ie { 4656 uint8_t id; 4657 uint8_t len; 4658 uint8_t ssid[IEEE80211_NWID_LEN]; 4659 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4660 4661 /* scan offload */ 4662 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4663 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4664 #define IWM_SCAN_MAX_PROFILES 11 4665 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4666 4667 /* Default watchdog (in MS) for scheduled scan iteration */ 4668 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4669 4670 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4671 #define IWM_CAN_ABORT_STATUS 1 4672 4673 #define IWM_FULL_SCAN_MULTIPLIER 5 4674 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4675 #define IWM_MAX_SCHED_SCAN_PLANS 2 4676 4677 /** 4678 * iwm_scan_schedule_lmac - schedule of scan offload 4679 * @delay: delay between iterations, in seconds. 4680 * @iterations: num of scan iterations 4681 * @full_scan_mul: number of partial scans before each full scan 4682 */ 4683 struct iwm_scan_schedule_lmac { 4684 uint16_t delay; 4685 uint8_t iterations; 4686 uint8_t full_scan_mul; 4687 } __packed; /* SCAN_SCHEDULE_API_S */ 4688 4689 /** 4690 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4691 * @tx_flags: combination of TX_CMD_FLG_* 4692 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4693 * cleared. Combination of RATE_MCS_* 4694 * @sta_id: index of destination station in FW station table 4695 * @reserved: for alignment and future use 4696 */ 4697 struct iwm_scan_req_tx_cmd { 4698 uint32_t tx_flags; 4699 uint32_t rate_n_flags; 4700 uint8_t sta_id; 4701 uint8_t reserved[3]; 4702 } __packed; 4703 4704 enum iwm_scan_channel_flags_lmac { 4705 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4706 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4707 }; 4708 4709 /** 4710 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4711 * @flags: bits 1-20: directed scan to i'th ssid 4712 * other bits &enum iwm_scan_channel_flags_lmac 4713 * @channel_number: channel number 1-13 etc 4714 * @iter_count: scan iteration on this channel 4715 * @iter_interval: interval in seconds between iterations on one channel 4716 */ 4717 struct iwm_scan_channel_cfg_lmac { 4718 uint32_t flags; 4719 uint16_t channel_num; 4720 uint16_t iter_count; 4721 uint32_t iter_interval; 4722 } __packed; 4723 4724 /* 4725 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4726 * @offset: offset in the data block 4727 * @len: length of the segment 4728 */ 4729 struct iwm_scan_probe_segment { 4730 uint16_t offset; 4731 uint16_t len; 4732 } __packed; 4733 4734 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4735 * @mac_header: first (and common) part of the probe 4736 * @band_data: band specific data 4737 * @common_data: last (and common) part of the probe 4738 * @buf: raw data block 4739 */ 4740 struct iwm_scan_probe_req { 4741 struct iwm_scan_probe_segment mac_header; 4742 struct iwm_scan_probe_segment band_data[2]; 4743 struct iwm_scan_probe_segment common_data; 4744 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4745 } __packed; 4746 4747 enum iwm_scan_channel_flags { 4748 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4749 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4750 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4751 }; 4752 4753 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4754 * @flags: enum iwm_scan_channel_flags 4755 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4756 * involved. 4757 * 1 - EBS is disabled. 4758 * 2 - every second scan will be full scan(and so on). 4759 */ 4760 struct iwm_scan_channel_opt { 4761 uint16_t flags; 4762 uint16_t non_ebs_ratio; 4763 } __packed; 4764 4765 /** 4766 * iwm_mvm_lmac_scan_flags 4767 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4768 * without filtering. 4769 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4770 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4771 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4772 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4773 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4774 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4775 * and DS parameter set IEs into probe requests. 4776 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4777 * 1, 6 and 11. 4778 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4779 */ 4780 enum iwm_mvm_lmac_scan_flags { 4781 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4782 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4783 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4784 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4785 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4786 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4787 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4788 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4789 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4790 }; 4791 4792 enum iwm_scan_priority { 4793 IWM_SCAN_PRIORITY_LOW, 4794 IWM_SCAN_PRIORITY_MEDIUM, 4795 IWM_SCAN_PRIORITY_HIGH, 4796 }; 4797 4798 /** 4799 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4800 * @reserved1: for alignment and future use 4801 * @channel_num: num of channels to scan 4802 * @active-dwell: dwell time for active channels 4803 * @passive-dwell: dwell time for passive channels 4804 * @fragmented-dwell: dwell time for fragmented passive scan 4805 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4806 * @reserved2: for alignment and future use 4807 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4808 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4809 * @max_out_time: max time (in TU) to be out of associated channel 4810 * @suspend_time: pause scan this long (TUs) when returning to service channel 4811 * @flags: RXON flags 4812 * @filter_flags: RXON filter 4813 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4814 * @direct_scan: list of SSIDs for directed active scan 4815 * @scan_prio: enum iwm_scan_priority 4816 * @iter_num: number of scan iterations 4817 * @delay: delay in seconds before first iteration 4818 * @schedule: two scheduling plans. The first one is finite, the second one can 4819 * be infinite. 4820 * @channel_opt: channel optimization options, for full and partial scan 4821 * @data: channel configuration and probe request packet. 4822 */ 4823 struct iwm_scan_req_lmac { 4824 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4825 uint32_t reserved1; 4826 uint8_t n_channels; 4827 uint8_t active_dwell; 4828 uint8_t passive_dwell; 4829 uint8_t fragmented_dwell; 4830 uint8_t extended_dwell; 4831 uint8_t reserved2; 4832 uint16_t rx_chain_select; 4833 uint32_t scan_flags; 4834 uint32_t max_out_time; 4835 uint32_t suspend_time; 4836 /* RX_ON_FLAGS_API_S_VER_1 */ 4837 uint32_t flags; 4838 uint32_t filter_flags; 4839 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4840 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4841 uint32_t scan_prio; 4842 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4843 uint32_t iter_num; 4844 uint32_t delay; 4845 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4846 struct iwm_scan_channel_opt channel_opt[2]; 4847 uint8_t data[]; 4848 } __packed; 4849 4850 /** 4851 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4852 * @last_schedule_line: last schedule line executed (fast or regular) 4853 * @last_schedule_iteration: last scan iteration executed before scan abort 4854 * @status: enum iwm_scan_offload_complete_status 4855 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4856 * @time_after_last_iter; time in seconds elapsed after last iteration 4857 */ 4858 struct iwm_periodic_scan_complete { 4859 uint8_t last_schedule_line; 4860 uint8_t last_schedule_iteration; 4861 uint8_t status; 4862 uint8_t ebs_status; 4863 uint32_t time_after_last_iter; 4864 uint32_t reserved; 4865 } __packed; 4866 4867 /* How many statistics are gathered for each channel */ 4868 #define IWM_SCAN_RESULTS_STATISTICS 1 4869 4870 /** 4871 * enum iwm_scan_complete_status - status codes for scan complete notifications 4872 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 4873 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 4874 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 4875 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 4876 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 4877 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 4878 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 4879 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 4880 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 4881 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 4882 * (not an error!) 4883 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 4884 * asked for 4885 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 4886 */ 4887 enum iwm_scan_complete_status { 4888 IWM_SCAN_COMP_STATUS_OK = 0x1, 4889 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 4890 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 4891 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 4892 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 4893 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 4894 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 4895 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 4896 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 4897 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 4898 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 4899 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 4900 }; 4901 4902 /** 4903 * struct iwm_scan_results_notif - scan results for one channel 4904 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 4905 * @channel: which channel the results are from 4906 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4907 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4908 * @num_probe_not_sent: # of request that weren't sent due to not enough time 4909 * @duration: duration spent in channel, in usecs 4910 * @statistics: statistics gathered for this channel 4911 */ 4912 struct iwm_scan_results_notif { 4913 uint8_t channel; 4914 uint8_t band; 4915 uint8_t probe_status; 4916 uint8_t num_probe_not_sent; 4917 uint32_t duration; 4918 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 4919 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 4920 4921 enum iwm_scan_framework_client { 4922 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 4923 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 4924 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 4925 }; 4926 4927 /** 4928 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 4929 * @ssid: MAC address to filter out 4930 * @reported_rssi: AP rssi reported to the host 4931 * @client_bitmap: clients ignore this entry - enum scan_framework_client 4932 */ 4933 struct iwm_scan_offload_blacklist { 4934 uint8_t ssid[IEEE80211_ADDR_LEN]; 4935 uint8_t reported_rssi; 4936 uint8_t client_bitmap; 4937 } __packed; 4938 4939 enum iwm_scan_offload_network_type { 4940 IWM_NETWORK_TYPE_BSS = 1, 4941 IWM_NETWORK_TYPE_IBSS = 2, 4942 IWM_NETWORK_TYPE_ANY = 3, 4943 }; 4944 4945 enum iwm_scan_offload_band_selection { 4946 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 4947 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 4948 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 4949 }; 4950 4951 /** 4952 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 4953 * @ssid_index: index to ssid list in fixed part 4954 * @unicast_cipher: encryption olgorithm to match - bitmap 4955 * @aut_alg: authentication olgorithm to match - bitmap 4956 * @network_type: enum iwm_scan_offload_network_type 4957 * @band_selection: enum iwm_scan_offload_band_selection 4958 * @client_bitmap: clients waiting for match - enum scan_framework_client 4959 */ 4960 struct iwm_scan_offload_profile { 4961 uint8_t ssid_index; 4962 uint8_t unicast_cipher; 4963 uint8_t auth_alg; 4964 uint8_t network_type; 4965 uint8_t band_selection; 4966 uint8_t client_bitmap; 4967 uint8_t reserved[2]; 4968 } __packed; 4969 4970 /** 4971 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 4972 * @blaclist: AP list to filter off from scan results 4973 * @profiles: profiles to search for match 4974 * @blacklist_len: length of blacklist 4975 * @num_profiles: num of profiles in the list 4976 * @match_notify: clients waiting for match found notification 4977 * @pass_match: clients waiting for the results 4978 * @active_clients: active clients bitmap - enum scan_framework_client 4979 * @any_beacon_notify: clients waiting for match notification without match 4980 */ 4981 struct iwm_scan_offload_profile_cfg { 4982 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 4983 uint8_t blacklist_len; 4984 uint8_t num_profiles; 4985 uint8_t match_notify; 4986 uint8_t pass_match; 4987 uint8_t active_clients; 4988 uint8_t any_beacon_notify; 4989 uint8_t reserved[2]; 4990 } __packed; 4991 4992 enum iwm_scan_offload_complete_status { 4993 IWM_SCAN_OFFLOAD_COMPLETED = 1, 4994 IWM_SCAN_OFFLOAD_ABORTED = 2, 4995 }; 4996 4997 enum iwm_scan_ebs_status { 4998 IWM_SCAN_EBS_SUCCESS, 4999 IWM_SCAN_EBS_FAILED, 5000 IWM_SCAN_EBS_CHAN_NOT_FOUND, 5001 IWM_SCAN_EBS_INACTIVE, 5002 }; 5003 5004 /** 5005 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5006 * SCAN_COMPLETE_NTF_API_S_VER_3 5007 * @scanned_channels: number of channels scanned (and number of valid results) 5008 * @status: one of SCAN_COMP_STATUS_* 5009 * @bt_status: BT on/off status 5010 * @last_channel: last channel that was scanned 5011 * @tsf_low: TSF timer (lower half) in usecs 5012 * @tsf_high: TSF timer (higher half) in usecs 5013 * @results: an array of scan results, only "scanned_channels" of them are valid 5014 */ 5015 struct iwm_lmac_scan_complete_notif { 5016 uint8_t scanned_channels; 5017 uint8_t status; 5018 uint8_t bt_status; 5019 uint8_t last_channel; 5020 uint32_t tsf_low; 5021 uint32_t tsf_high; 5022 struct iwm_scan_results_notif results[]; 5023 } __packed; 5024 5025 5026 /* UMAC Scan API */ 5027 5028 /* The maximum of either of these cannot exceed 8, because we use an 5029 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5030 */ 5031 #define IWM_MVM_MAX_UMAC_SCANS 8 5032 #define IWM_MVM_MAX_LMAC_SCANS 1 5033 5034 enum iwm_scan_config_flags { 5035 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5036 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5037 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5038 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5039 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5040 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5041 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5042 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5043 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5044 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5045 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5046 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5047 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5048 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5049 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5050 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5051 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5052 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5053 5054 /* Bits 26-31 are for num of channels in channel_array */ 5055 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5056 }; 5057 5058 enum iwm_scan_config_rates { 5059 /* OFDM basic rates */ 5060 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5061 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5062 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5063 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5064 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5065 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5066 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5067 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5068 /* CCK basic rates */ 5069 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5070 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5071 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5072 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5073 5074 /* Bits 16-27 are for supported rates */ 5075 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5076 }; 5077 5078 enum iwm_channel_flags { 5079 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5080 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5081 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5082 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5083 }; 5084 5085 /** 5086 * struct iwm_scan_config 5087 * @flags: enum scan_config_flags 5088 * @tx_chains: valid_tx antenna - ANT_* definitions 5089 * @rx_chains: valid_rx antenna - ANT_* definitions 5090 * @legacy_rates: default legacy rates - enum scan_config_rates 5091 * @out_of_channel_time: default max out of serving channel time 5092 * @suspend_time: default max suspend time 5093 * @dwell_active: default dwell time for active scan 5094 * @dwell_passive: default dwell time for passive scan 5095 * @dwell_fragmented: default dwell time for fragmented scan 5096 * @dwell_extended: default dwell time for channels 1, 6 and 11 5097 * @mac_addr: default mac address to be used in probes 5098 * @bcast_sta_id: the index of the station in the fw 5099 * @channel_flags: default channel flags - enum iwm_channel_flags 5100 * scan_config_channel_flag 5101 * @channel_array: default supported channels 5102 */ 5103 struct iwm_scan_config { 5104 uint32_t flags; 5105 uint32_t tx_chains; 5106 uint32_t rx_chains; 5107 uint32_t legacy_rates; 5108 uint32_t out_of_channel_time; 5109 uint32_t suspend_time; 5110 uint8_t dwell_active; 5111 uint8_t dwell_passive; 5112 uint8_t dwell_fragmented; 5113 uint8_t dwell_extended; 5114 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5115 uint8_t bcast_sta_id; 5116 uint8_t channel_flags; 5117 uint8_t channel_array[]; 5118 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5119 5120 /** 5121 * iwm_umac_scan_flags 5122 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5123 * can be preempted by other scan requests with higher priority. 5124 * The low priority scan will be resumed when the higher proirity scan is 5125 * completed. 5126 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5127 * when scan starts. 5128 */ 5129 enum iwm_umac_scan_flags { 5130 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5131 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5132 }; 5133 5134 enum iwm_umac_scan_uid_offsets { 5135 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5136 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5137 }; 5138 5139 enum iwm_umac_scan_general_flags { 5140 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5141 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5142 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5143 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5144 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5145 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5146 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5147 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5148 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5149 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5150 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5151 }; 5152 5153 /** 5154 * struct iwm_scan_channel_cfg_umac 5155 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5156 * @channel_num: channel number 1-13 etc. 5157 * @iter_count: repetition count for the channel. 5158 * @iter_interval: interval between two scan iterations on one channel. 5159 */ 5160 struct iwm_scan_channel_cfg_umac { 5161 uint32_t flags; 5162 uint8_t channel_num; 5163 uint8_t iter_count; 5164 uint16_t iter_interval; 5165 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5166 5167 /** 5168 * struct iwm_scan_umac_schedule 5169 * @interval: interval in seconds between scan iterations 5170 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5171 * @reserved: for alignment and future use 5172 */ 5173 struct iwm_scan_umac_schedule { 5174 uint16_t interval; 5175 uint8_t iter_count; 5176 uint8_t reserved; 5177 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5178 5179 /** 5180 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5181 * parameters following channels configuration array. 5182 * @schedule: two scheduling plans. 5183 * @delay: delay in TUs before starting the first scan iteration 5184 * @reserved: for future use and alignment 5185 * @preq: probe request with IEs blocks 5186 * @direct_scan: list of SSIDs for directed active scan 5187 */ 5188 struct iwm_scan_req_umac_tail { 5189 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5190 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5191 uint16_t delay; 5192 uint16_t reserved; 5193 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5194 struct iwm_scan_probe_req preq; 5195 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5196 } __packed; 5197 5198 /** 5199 * struct iwm_scan_req_umac 5200 * @flags: &enum iwm_umac_scan_flags 5201 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5202 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5203 * @general_flags: &enum iwm_umac_scan_general_flags 5204 * @extended_dwell: dwell time for channels 1, 6 and 11 5205 * @active_dwell: dwell time for active scan 5206 * @passive_dwell: dwell time for passive scan 5207 * @fragmented_dwell: dwell time for fragmented passive scan 5208 * @max_out_time: max out of serving channel time 5209 * @suspend_time: max suspend time 5210 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5211 * @channel_flags: &enum iwm_scan_channel_flags 5212 * @n_channels: num of channels in scan request 5213 * @reserved: for future use and alignment 5214 * @data: &struct iwm_scan_channel_cfg_umac and 5215 * &struct iwm_scan_req_umac_tail 5216 */ 5217 struct iwm_scan_req_umac { 5218 uint32_t flags; 5219 uint32_t uid; 5220 uint32_t ooc_priority; 5221 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5222 uint32_t general_flags; 5223 uint8_t extended_dwell; 5224 uint8_t active_dwell; 5225 uint8_t passive_dwell; 5226 uint8_t fragmented_dwell; 5227 uint32_t max_out_time; 5228 uint32_t suspend_time; 5229 uint32_t scan_priority; 5230 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5231 uint8_t channel_flags; 5232 uint8_t n_channels; 5233 uint16_t reserved; 5234 uint8_t data[]; 5235 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5236 5237 /** 5238 * struct iwm_umac_scan_abort 5239 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5240 * @flags: reserved 5241 */ 5242 struct iwm_umac_scan_abort { 5243 uint32_t uid; 5244 uint32_t flags; 5245 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5246 5247 /** 5248 * struct iwm_umac_scan_complete 5249 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5250 * @last_schedule: last scheduling line 5251 * @last_iter: last scan iteration number 5252 * @scan status: &enum iwm_scan_offload_complete_status 5253 * @ebs_status: &enum iwm_scan_ebs_status 5254 * @time_from_last_iter: time elapsed from last iteration 5255 * @reserved: for future use 5256 */ 5257 struct iwm_umac_scan_complete { 5258 uint32_t uid; 5259 uint8_t last_schedule; 5260 uint8_t last_iter; 5261 uint8_t status; 5262 uint8_t ebs_status; 5263 uint32_t time_from_last_iter; 5264 uint32_t reserved; 5265 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5266 5267 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5268 /** 5269 * struct iwm_scan_offload_profile_match - match information 5270 * @bssid: matched bssid 5271 * @channel: channel where the match occurred 5272 * @energy: 5273 * @matching_feature: 5274 * @matching_channels: bitmap of channels that matched, referencing 5275 * the channels passed in tue scan offload request 5276 */ 5277 struct iwm_scan_offload_profile_match { 5278 uint8_t bssid[IEEE80211_ADDR_LEN]; 5279 uint16_t reserved; 5280 uint8_t channel; 5281 uint8_t energy; 5282 uint8_t matching_feature; 5283 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5284 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5285 5286 /** 5287 * struct iwm_scan_offload_profiles_query - match results query response 5288 * @matched_profiles: bitmap of matched profiles, referencing the 5289 * matches passed in the scan offload request 5290 * @last_scan_age: age of the last offloaded scan 5291 * @n_scans_done: number of offloaded scans done 5292 * @gp2_d0u: GP2 when D0U occurred 5293 * @gp2_invoked: GP2 when scan offload was invoked 5294 * @resume_while_scanning: not used 5295 * @self_recovery: obsolete 5296 * @reserved: reserved 5297 * @matches: array of match information, one for each match 5298 */ 5299 struct iwm_scan_offload_profiles_query { 5300 uint32_t matched_profiles; 5301 uint32_t last_scan_age; 5302 uint32_t n_scans_done; 5303 uint32_t gp2_d0u; 5304 uint32_t gp2_invoked; 5305 uint8_t resume_while_scanning; 5306 uint8_t self_recovery; 5307 uint16_t reserved; 5308 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5309 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5310 5311 /** 5312 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5313 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5314 * @scanned_channels: number of channels scanned and number of valid elements in 5315 * results array 5316 * @status: one of SCAN_COMP_STATUS_* 5317 * @bt_status: BT on/off status 5318 * @last_channel: last channel that was scanned 5319 * @tsf_low: TSF timer (lower half) in usecs 5320 * @tsf_high: TSF timer (higher half) in usecs 5321 * @results: array of scan results, only "scanned_channels" of them are valid 5322 */ 5323 struct iwm_umac_scan_iter_complete_notif { 5324 uint32_t uid; 5325 uint8_t scanned_channels; 5326 uint8_t status; 5327 uint8_t bt_status; 5328 uint8_t last_channel; 5329 uint32_t tsf_low; 5330 uint32_t tsf_high; 5331 struct iwm_scan_results_notif results[]; 5332 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5333 5334 /* Please keep this enum *SORTED* by hex value. 5335 * Needed for binary search, otherwise a warning will be triggered. 5336 */ 5337 enum iwm_scan_subcmd_ids { 5338 IWM_GSCAN_START_CMD = 0x0, 5339 IWM_GSCAN_STOP_CMD = 0x1, 5340 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5341 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5342 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5343 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5344 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5345 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5346 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5347 }; 5348 5349 /* STA API */ 5350 5351 /** 5352 * enum iwm_sta_flags - flags for the ADD_STA host command 5353 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5354 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5355 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5356 * @IWM_STA_FLG_PS: set if STA is in Power Save 5357 * @IWM_STA_FLG_INVALID: set if STA is invalid 5358 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5359 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5360 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5361 * @IWM_STA_FLG_PAN: STA is for PAN interface 5362 * @IWM_STA_FLG_CLASS_AUTH: 5363 * @IWM_STA_FLG_CLASS_ASSOC: 5364 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5365 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5366 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5367 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5368 * initialised by driver and can be updated by fw upon reception of 5369 * action frames that can change the channel width. When cleared the fw 5370 * will send all the frames in 20MHz even when FAT channel is requested. 5371 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5372 * driver and can be updated by fw upon reception of action frames. 5373 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5374 */ 5375 enum iwm_sta_flags { 5376 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5377 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5378 5379 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5380 5381 IWM_STA_FLG_PS = (1 << 8), 5382 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5383 IWM_STA_FLG_PAN = (1 << 13), 5384 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5385 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5386 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5387 5388 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5389 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5390 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5391 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5392 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5393 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5394 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5395 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5396 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5397 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5398 5399 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5400 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5401 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5402 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5403 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5404 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5405 5406 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5407 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5408 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5409 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5410 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5411 5412 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5413 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5414 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5415 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5416 }; 5417 5418 /** 5419 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5420 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5421 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5422 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5423 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5424 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5425 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5426 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5427 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5428 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5429 * station info array (1 - n 1X mode) 5430 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5431 * @IWM_STA_KEY_NOT_VALID: key is invalid 5432 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5433 * @IWM_STA_KEY_MULTICAST: set for multical key 5434 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5435 */ 5436 enum iwm_sta_key_flag { 5437 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5438 IWM_STA_KEY_FLG_WEP = (1 << 0), 5439 IWM_STA_KEY_FLG_CCM = (2 << 0), 5440 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5441 IWM_STA_KEY_FLG_EXT = (4 << 0), 5442 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5443 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5444 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5445 5446 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5447 IWM_STA_KEY_FLG_KEYID_POS = 8, 5448 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5449 IWM_STA_KEY_NOT_VALID = (1 << 11), 5450 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5451 IWM_STA_KEY_MULTICAST = (1 << 14), 5452 IWM_STA_KEY_MFP = (1 << 15), 5453 }; 5454 5455 /** 5456 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5457 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5458 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5459 * @IWM_STA_MODIFY_TX_RATE: unused 5460 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5461 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5462 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5463 * @IWM_STA_MODIFY_PROT_TH: 5464 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5465 */ 5466 enum iwm_sta_modify_flag { 5467 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5468 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5469 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5470 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5471 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5472 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5473 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5474 IWM_STA_MODIFY_QUEUES = (1 << 7), 5475 }; 5476 5477 #define IWM_STA_MODE_MODIFY 1 5478 5479 /** 5480 * enum iwm_sta_sleep_flag - type of sleep of the station 5481 * @IWM_STA_SLEEP_STATE_AWAKE: 5482 * @IWM_STA_SLEEP_STATE_PS_POLL: 5483 * @IWM_STA_SLEEP_STATE_UAPSD: 5484 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5485 * (last) released frame 5486 */ 5487 enum iwm_sta_sleep_flag { 5488 IWM_STA_SLEEP_STATE_AWAKE = 0, 5489 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5490 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5491 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5492 }; 5493 5494 /* STA ID and color bits definitions */ 5495 #define IWM_STA_ID_SEED (0x0f) 5496 #define IWM_STA_ID_POS (0) 5497 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5498 5499 #define IWM_STA_COLOR_SEED (0x7) 5500 #define IWM_STA_COLOR_POS (4) 5501 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5502 5503 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5504 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5505 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5506 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5507 5508 #define IWM_STA_KEY_MAX_NUM (16) 5509 #define IWM_STA_KEY_IDX_INVALID (0xff) 5510 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5511 #define IWM_MAX_GLOBAL_KEYS (4) 5512 #define IWM_STA_KEY_LEN_WEP40 (5) 5513 #define IWM_STA_KEY_LEN_WEP104 (13) 5514 5515 /** 5516 * struct iwm_mvm_keyinfo - key information 5517 * @key_flags: type %iwm_sta_key_flag 5518 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5519 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5520 * @key_offset: key offset in the fw's key table 5521 * @key: 16-byte unicast decryption key 5522 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5523 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5524 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5525 */ 5526 struct iwm_mvm_keyinfo { 5527 uint16_t key_flags; 5528 uint8_t tkip_rx_tsc_byte2; 5529 uint8_t reserved1; 5530 uint16_t tkip_rx_ttak[5]; 5531 uint8_t key_offset; 5532 uint8_t reserved2; 5533 uint8_t key[16]; 5534 uint64_t tx_secur_seq_cnt; 5535 uint64_t hw_tkip_mic_rx_key; 5536 uint64_t hw_tkip_mic_tx_key; 5537 } __packed; 5538 5539 #define IWM_ADD_STA_STATUS_MASK 0xFF 5540 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5541 #define IWM_ADD_STA_BAID_MASK 0x7F00 5542 #define IWM_ADD_STA_BAID_SHIFT 8 5543 5544 /** 5545 * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table. 5546 * ( REPLY_ADD_STA = 0x18 ) 5547 * @add_modify: 1: modify existing, 0: add new station 5548 * @awake_acs: 5549 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5550 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5551 * @mac_id_n_color: the Mac context this station belongs to 5552 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5553 * @sta_id: index of station in uCode's station table 5554 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5555 * alone. 1 - modify, 0 - don't change. 5556 * @station_flags: look at %iwm_sta_flags 5557 * @station_flags_msk: what of %station_flags have changed 5558 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5559 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5560 * add_immediate_ba_ssn. 5561 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5562 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5563 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5564 * add_immediate_ba_tid. 5565 * @sleep_tx_count: number of packets to transmit to station even though it is 5566 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5567 * keeps track of STA sleep state. 5568 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5569 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5570 * mac-addr. 5571 * @beamform_flags: beam forming controls 5572 * @tfd_queue_msk: tfd queues used by this station 5573 * 5574 * The device contains an internal table of per-station information, with info 5575 * on security keys, aggregation parameters, and Tx rates for initial Tx 5576 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5577 * 5578 * ADD_STA sets up the table entry for one station, either creating a new 5579 * entry, or modifying a pre-existing one. 5580 */ 5581 struct iwm_mvm_add_sta_cmd { 5582 uint8_t add_modify; 5583 uint8_t awake_acs; 5584 uint16_t tid_disable_tx; 5585 uint32_t mac_id_n_color; 5586 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5587 uint16_t reserved2; 5588 uint8_t sta_id; 5589 uint8_t modify_mask; 5590 uint16_t reserved3; 5591 uint32_t station_flags; 5592 uint32_t station_flags_msk; 5593 uint8_t add_immediate_ba_tid; 5594 uint8_t remove_immediate_ba_tid; 5595 uint16_t add_immediate_ba_ssn; 5596 uint16_t sleep_tx_count; 5597 uint16_t sleep_state_flags; 5598 uint16_t assoc_id; 5599 uint16_t beamform_flags; 5600 uint32_t tfd_queue_msk; 5601 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5602 5603 /** 5604 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5605 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5606 * @sta_id: index of station in uCode's station table 5607 * @key_offset: key offset in key storage 5608 * @key_flags: type %iwm_sta_key_flag 5609 * @key: key material data 5610 * @key2: key material data 5611 * @rx_secur_seq_cnt: RX security sequence counter for the key 5612 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5613 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5614 */ 5615 struct iwm_mvm_add_sta_key_cmd { 5616 uint8_t sta_id; 5617 uint8_t key_offset; 5618 uint16_t key_flags; 5619 uint8_t key[16]; 5620 uint8_t key2[16]; 5621 uint8_t rx_secur_seq_cnt[16]; 5622 uint8_t tkip_rx_tsc_byte2; 5623 uint8_t reserved; 5624 uint16_t tkip_rx_ttak[5]; 5625 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5626 5627 /** 5628 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5629 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5630 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5631 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5632 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5633 * that doesn't exist. 5634 */ 5635 enum iwm_mvm_add_sta_rsp_status { 5636 IWM_ADD_STA_SUCCESS = 0x1, 5637 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5638 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5639 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5640 }; 5641 5642 /** 5643 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5644 * ( IWM_REMOVE_STA = 0x19 ) 5645 * @sta_id: the station id of the station to be removed 5646 */ 5647 struct iwm_mvm_rm_sta_cmd { 5648 uint8_t sta_id; 5649 uint8_t reserved[3]; 5650 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5651 5652 /** 5653 * struct iwm_mvm_mgmt_mcast_key_cmd 5654 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5655 * @ctrl_flags: %iwm_sta_key_flag 5656 * @IGTK: 5657 * @K1: IGTK master key 5658 * @K2: IGTK sub key 5659 * @sta_id: station ID that support IGTK 5660 * @key_id: 5661 * @receive_seq_cnt: initial RSC/PN needed for replay check 5662 */ 5663 struct iwm_mvm_mgmt_mcast_key_cmd { 5664 uint32_t ctrl_flags; 5665 uint8_t IGTK[16]; 5666 uint8_t K1[16]; 5667 uint8_t K2[16]; 5668 uint32_t key_id; 5669 uint32_t sta_id; 5670 uint64_t receive_seq_cnt; 5671 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5672 5673 struct iwm_mvm_wep_key { 5674 uint8_t key_index; 5675 uint8_t key_offset; 5676 uint16_t reserved1; 5677 uint8_t key_size; 5678 uint8_t reserved2[3]; 5679 uint8_t key[16]; 5680 } __packed; 5681 5682 struct iwm_mvm_wep_key_cmd { 5683 uint32_t mac_id_n_color; 5684 uint8_t num_keys; 5685 uint8_t decryption_type; 5686 uint8_t flags; 5687 uint8_t reserved; 5688 struct iwm_mvm_wep_key wep_key[0]; 5689 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5690 5691 /* 5692 * BT coex 5693 */ 5694 5695 enum iwm_bt_coex_mode { 5696 IWM_BT_COEX_DISABLE = 0x0, 5697 IWM_BT_COEX_NW = 0x1, 5698 IWM_BT_COEX_BT = 0x2, 5699 IWM_BT_COEX_WIFI = 0x3, 5700 }; /* BT_COEX_MODES_E */ 5701 5702 enum iwm_bt_coex_enabled_modules { 5703 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5704 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5705 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5706 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5707 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5708 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5709 5710 /** 5711 * struct iwm_bt_coex_cmd - bt coex configuration command 5712 * @mode: enum %iwm_bt_coex_mode 5713 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5714 * 5715 * The structure is used for the BT_COEX command. 5716 */ 5717 struct iwm_bt_coex_cmd { 5718 uint32_t mode; 5719 uint32_t enabled_modules; 5720 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5721 5722 5723 /* 5724 * Location Aware Regulatory (LAR) API - MCC updates 5725 */ 5726 5727 /** 5728 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5729 * regulatory profile according to the given MCC (Mobile Country Code). 5730 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5731 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5732 * MCC in the cmd response will be the relevant MCC in the NVM. 5733 * @mcc: given mobile country code 5734 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5735 * @reserved: reserved for alignment 5736 */ 5737 struct iwm_mcc_update_cmd_v1 { 5738 uint16_t mcc; 5739 uint8_t source_id; 5740 uint8_t reserved; 5741 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5742 5743 /** 5744 * struct iwm_mcc_update_cmd - Request the device to update geographic 5745 * regulatory profile according to the given MCC (Mobile Country Code). 5746 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5747 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5748 * MCC in the cmd response will be the relevant MCC in the NVM. 5749 * @mcc: given mobile country code 5750 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5751 * @reserved: reserved for alignment 5752 * @key: integrity key for MCC API OEM testing 5753 * @reserved2: reserved 5754 */ 5755 struct iwm_mcc_update_cmd { 5756 uint16_t mcc; 5757 uint8_t source_id; 5758 uint8_t reserved; 5759 uint32_t key; 5760 uint32_t reserved2[5]; 5761 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5762 5763 /** 5764 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5765 * Contains the new channel control profile map, if changed, and the new MCC 5766 * (mobile country code). 5767 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5768 * @status: see &enum iwm_mcc_update_status 5769 * @mcc: the new applied MCC 5770 * @cap: capabilities for all channels which matches the MCC 5771 * @source_id: the MCC source, see iwm_mcc_source 5772 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5773 * channels, depending on platform) 5774 * @channels: channel control data map, DWORD for each channel. Only the first 5775 * 16bits are used. 5776 */ 5777 struct iwm_mcc_update_resp_v1 { 5778 uint32_t status; 5779 uint16_t mcc; 5780 uint8_t cap; 5781 uint8_t source_id; 5782 uint32_t n_channels; 5783 uint32_t channels[0]; 5784 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5785 5786 /** 5787 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5788 * Contains the new channel control profile map, if changed, and the new MCC 5789 * (mobile country code). 5790 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5791 * @status: see &enum iwm_mcc_update_status 5792 * @mcc: the new applied MCC 5793 * @cap: capabilities for all channels which matches the MCC 5794 * @source_id: the MCC source, see iwm_mcc_source 5795 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5796 * @reserved: reserved. 5797 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5798 * channels, depending on platform) 5799 * @channels: channel control data map, DWORD for each channel. Only the first 5800 * 16bits are used. 5801 */ 5802 struct iwm_mcc_update_resp { 5803 uint32_t status; 5804 uint16_t mcc; 5805 uint8_t cap; 5806 uint8_t source_id; 5807 uint16_t time; 5808 uint16_t reserved; 5809 uint32_t n_channels; 5810 uint32_t channels[0]; 5811 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5812 5813 /** 5814 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5815 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5816 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5817 * the cellular and connectivity cores that gets updates of the mcc, and 5818 * notifies the ucode directly of any mcc change. 5819 * The ucode requests the driver to request the device to update geographic 5820 * regulatory profile according to the given MCC (Mobile Country Code). 5821 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5822 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5823 * MCC in the cmd response will be the relevant MCC in the NVM. 5824 * @mcc: given mobile country code 5825 * @source_id: identity of the change originator, see iwm_mcc_source 5826 * @reserved1: reserved for alignment 5827 */ 5828 struct iwm_mcc_chub_notif { 5829 uint16_t mcc; 5830 uint8_t source_id; 5831 uint8_t reserved1; 5832 } __packed; /* LAR_MCC_NOTIFY_S */ 5833 5834 enum iwm_mcc_update_status { 5835 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5836 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5837 IWM_MCC_RESP_INVALID, 5838 IWM_MCC_RESP_NVM_DISABLED, 5839 IWM_MCC_RESP_ILLEGAL, 5840 IWM_MCC_RESP_LOW_PRIORITY, 5841 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5842 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5843 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5844 }; 5845 5846 enum iwm_mcc_source { 5847 IWM_MCC_SOURCE_OLD_FW = 0, 5848 IWM_MCC_SOURCE_ME = 1, 5849 IWM_MCC_SOURCE_BIOS = 2, 5850 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5851 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5852 IWM_MCC_SOURCE_WIFI = 5, 5853 IWM_MCC_SOURCE_RESERVED = 6, 5854 IWM_MCC_SOURCE_DEFAULT = 7, 5855 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5856 IWM_MCC_SOURCE_MCC_API = 9, 5857 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5858 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5859 }; 5860 5861 /** 5862 * struct iwm_dts_measurement_notif_v1 - measurements notification 5863 * 5864 * @temp: the measured temperature 5865 * @voltage: the measured voltage 5866 */ 5867 struct iwm_dts_measurement_notif_v1 { 5868 int32_t temp; 5869 int32_t voltage; 5870 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5871 5872 /** 5873 * struct iwm_dts_measurement_notif_v2 - measurements notification 5874 * 5875 * @temp: the measured temperature 5876 * @voltage: the measured voltage 5877 * @threshold_idx: the trip index that was crossed 5878 */ 5879 struct iwm_dts_measurement_notif_v2 { 5880 int32_t temp; 5881 int32_t voltage; 5882 int32_t threshold_idx; 5883 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5884 5885 /* 5886 * Some cherry-picked definitions 5887 */ 5888 5889 #define IWM_FRAME_LIMIT 64 5890 5891 /* 5892 * These functions retrieve specific information from the id field in 5893 * the iwm_host_cmd struct which contains the command id, the group id, 5894 * and the version of the command and vice versa. 5895 */ 5896 static inline uint8_t 5897 iwm_cmd_opcode(uint32_t cmdid) 5898 { 5899 return cmdid & 0xff; 5900 } 5901 5902 static inline uint8_t 5903 iwm_cmd_groupid(uint32_t cmdid) 5904 { 5905 return ((cmdid & 0xff00) >> 8); 5906 } 5907 5908 static inline uint8_t 5909 iwm_cmd_version(uint32_t cmdid) 5910 { 5911 return ((cmdid & 0xff0000) >> 16); 5912 } 5913 5914 static inline uint32_t 5915 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 5916 { 5917 return opcode + (groupid << 8) + (version << 16); 5918 } 5919 5920 /* make uint16_t wide id out of uint8_t group and opcode */ 5921 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 5922 5923 /* due to the conversion, this group is special */ 5924 #define IWM_ALWAYS_LONG_GROUP 1 5925 5926 struct iwm_cmd_header { 5927 uint8_t code; 5928 uint8_t flags; 5929 uint8_t idx; 5930 uint8_t qid; 5931 } __packed; 5932 5933 struct iwm_cmd_header_wide { 5934 uint8_t opcode; 5935 uint8_t group_id; 5936 uint8_t idx; 5937 uint8_t qid; 5938 uint16_t length; 5939 uint8_t reserved; 5940 uint8_t version; 5941 } __packed; 5942 5943 /** 5944 * enum iwm_power_scheme 5945 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 5946 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 5947 * @IWM_POWER_LEVEL_LP - Low Power 5948 */ 5949 enum iwm_power_scheme { 5950 IWM_POWER_SCHEME_CAM = 1, 5951 IWM_POWER_SCHEME_BPS, 5952 IWM_POWER_SCHEME_LP 5953 }; 5954 5955 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 5956 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 5957 #define IWM_CMD_FAILED_MSK 0x40 5958 5959 /** 5960 * struct iwm_device_cmd 5961 * 5962 * For allocation of the command and tx queues, this establishes the overall 5963 * size of the largest command we send to uCode, except for commands that 5964 * aren't fully copied and use other TFD space. 5965 */ 5966 struct iwm_device_cmd { 5967 union { 5968 struct { 5969 struct iwm_cmd_header hdr; 5970 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 5971 }; 5972 struct { 5973 struct iwm_cmd_header_wide hdr_wide; 5974 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 5975 sizeof(struct iwm_cmd_header_wide) + 5976 sizeof(struct iwm_cmd_header)]; 5977 }; 5978 }; 5979 } __packed; 5980 5981 struct iwm_rx_packet { 5982 /* 5983 * The first 4 bytes of the RX frame header contain both the RX frame 5984 * size and some flags. 5985 * Bit fields: 5986 * 31: flag flush RB request 5987 * 30: flag ignore TC (terminal counter) request 5988 * 29: flag fast IRQ request 5989 * 28-14: Reserved 5990 * 13-00: RX frame size 5991 */ 5992 uint32_t len_n_flags; 5993 struct iwm_cmd_header hdr; 5994 uint8_t data[]; 5995 } __packed; 5996 5997 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 5998 #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 5999 #define IWM_FH_RSCSR_FRAME_ALIGN 0x40 6000 6001 static inline uint32_t 6002 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6003 { 6004 6005 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6006 } 6007 6008 static inline uint32_t 6009 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6010 { 6011 6012 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6013 } 6014 6015 6016 #define IWM_MIN_DBM -100 6017 #define IWM_MAX_DBM -33 /* realistic guess */ 6018 6019 #define IWM_READ(sc, reg) \ 6020 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6021 6022 #define IWM_WRITE(sc, reg, val) \ 6023 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6024 6025 #define IWM_WRITE_1(sc, reg, val) \ 6026 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6027 6028 #define IWM_SETBITS(sc, reg, mask) \ 6029 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6030 6031 #define IWM_CLRBITS(sc, reg, mask) \ 6032 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6033 6034 #define IWM_BARRIER_WRITE(sc) \ 6035 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6036 BUS_SPACE_BARRIER_WRITE) 6037 6038 #define IWM_BARRIER_READ_WRITE(sc) \ 6039 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6040 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6041 6042 #endif /* __IF_IWM_REG_H__ */ 6043