1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2 /* $FreeBSD$ */ 3 4 /****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * CSR (control and status registers) 74 * 75 * CSR registers are mapped directly into PCI bus space, and are accessible 76 * whenever platform supplies power to device, even when device is in 77 * low power states due to driver-invoked device resets 78 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 79 * 80 * Use iwl_write32() and iwl_read32() family to access these registers; 81 * these provide simple PCI bus access, without waking up the MAC. 82 * Do not use iwl_write_direct32() family for these registers; 83 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 84 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 85 * the CSR registers. 86 * 87 * NOTE: Device does need to be awake in order to read this memory 88 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 89 */ 90 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 91 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 92 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 93 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 94 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 95 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 96 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 97 #define IWM_CSR_GP_CNTRL (0x024) 98 99 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 100 #define IWM_CSR_INT_PERIODIC_REG (0x005) 101 102 /* 103 * Hardware revision info 104 * Bit fields: 105 * 31-16: Reserved 106 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 108 * 1-0: "Dash" (-) value, as in A-1, etc. 109 */ 110 #define IWM_CSR_HW_REV (0x028) 111 112 /* 113 * EEPROM and OTP (one-time-programmable) memory reads 114 * 115 * NOTE: Device must be awake, initialized via apm_ops.init(), 116 * in order to read. 117 */ 118 #define IWM_CSR_EEPROM_REG (0x02c) 119 #define IWM_CSR_EEPROM_GP (0x030) 120 #define IWM_CSR_OTP_GP_REG (0x034) 121 122 #define IWM_CSR_GIO_REG (0x03C) 123 #define IWM_CSR_GP_UCODE_REG (0x048) 124 #define IWM_CSR_GP_DRIVER_REG (0x050) 125 126 /* 127 * UCODE-DRIVER GP (general purpose) mailbox registers. 128 * SET/CLR registers set/clear bit(s) if "1" is written. 129 */ 130 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 131 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 132 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 133 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 134 135 #define IWM_CSR_MBOX_SET_REG (0x088) 136 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 137 138 #define IWM_CSR_LED_REG (0x094) 139 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 140 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 141 142 143 /* GIO Chicken Bits (PCI Express bus link power management) */ 144 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 145 146 /* Analog phase-lock-loop configuration */ 147 #define IWM_CSR_ANA_PLL_CFG (0x20c) 148 149 /* 150 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 151 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 152 * See also IWM_CSR_HW_REV register. 153 * Bit fields: 154 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 155 * 1-0: "Dash" (-) value, as in C-1, etc. 156 */ 157 #define IWM_CSR_HW_REV_WA_REG (0x22C) 158 159 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 160 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 161 162 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 163 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 164 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 166 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 167 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 171 172 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 173 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 178 179 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 180 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 183 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 184 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 186 187 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 188 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 189 190 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 191 * acknowledged (reset) by host writing "1" to flagged bits. */ 192 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 193 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 194 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 195 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 196 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 197 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 198 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 199 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 200 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 201 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 202 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 203 204 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 205 IWM_CSR_INT_BIT_HW_ERR | \ 206 IWM_CSR_INT_BIT_FH_TX | \ 207 IWM_CSR_INT_BIT_SW_ERR | \ 208 IWM_CSR_INT_BIT_RF_KILL | \ 209 IWM_CSR_INT_BIT_SW_RX | \ 210 IWM_CSR_INT_BIT_WAKEUP | \ 211 IWM_CSR_INT_BIT_ALIVE | \ 212 IWM_CSR_INT_BIT_RX_PERIODIC) 213 214 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 215 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 216 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 217 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 218 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 219 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 220 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 221 222 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 223 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 224 IWM_CSR_FH_INT_BIT_RX_CHNL0) 225 226 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 227 IWM_CSR_FH_INT_BIT_TX_CHNL0) 228 229 /* GPIO */ 230 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 231 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 232 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 233 234 /* RESET */ 235 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 236 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 237 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 238 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 239 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 240 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 241 242 /* 243 * GP (general purpose) CONTROL REGISTER 244 * Bit fields: 245 * 27: HW_RF_KILL_SW 246 * Indicates state of (platform's) hardware RF-Kill switch 247 * 26-24: POWER_SAVE_TYPE 248 * Indicates current power-saving mode: 249 * 000 -- No power saving 250 * 001 -- MAC power-down 251 * 010 -- PHY (radio) power-down 252 * 011 -- Error 253 * 9-6: SYS_CONFIG 254 * Indicates current system configuration, reflecting pins on chip 255 * as forced high/low by device circuit board. 256 * 4: GOING_TO_SLEEP 257 * Indicates MAC is entering a power-saving sleep power-down. 258 * Not a good time to access device-internal resources. 259 * 3: MAC_ACCESS_REQ 260 * Host sets this to request and maintain MAC wakeup, to allow host 261 * access to device-internal resources. Host must wait for 262 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 263 * device registers. 264 * 2: INIT_DONE 265 * Host sets this to put device into fully operational D0 power mode. 266 * Host resets this after SW_RESET to put device into low power mode. 267 * 0: MAC_CLOCK_READY 268 * Indicates MAC (ucode processor, etc.) is powered up and can run. 269 * Internal resources are accessible. 270 * NOTE: This does not indicate that the processor is actually running. 271 * NOTE: This does not indicate that device has completed 272 * init or post-power-down restore of internal SRAM memory. 273 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 274 * SRAM is restored and uCode is in normal operation mode. 275 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 276 * do not need to save/restore it. 277 * NOTE: After device reset, this bit remains "0" until host sets 278 * INIT_DONE 279 */ 280 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 281 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 283 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 284 285 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 286 287 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 288 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 289 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 290 291 292 /* HW REV */ 293 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 294 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 295 296 /** 297 * hw_rev values 298 */ 299 enum { 300 IWM_SILICON_A_STEP = 0, 301 IWM_SILICON_B_STEP, 302 IWM_SILICON_C_STEP, 303 }; 304 305 306 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 307 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 308 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 309 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 310 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 311 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 312 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 313 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 314 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 315 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 316 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 317 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 318 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 319 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 320 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 321 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 322 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 323 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 324 325 /* EEPROM REG */ 326 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 327 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 328 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 329 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 330 331 /* EEPROM GP */ 332 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 333 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 334 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 335 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 336 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 337 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 338 339 /* One-time-programmable memory general purpose reg */ 340 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 341 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 342 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 343 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 344 345 /* GP REG */ 346 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 347 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 348 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 349 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 350 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 351 352 353 /* CSR GIO */ 354 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 355 356 /* 357 * UCODE-DRIVER GP (general purpose) mailbox register 1 358 * Host driver and uCode write and/or read this register to communicate with 359 * each other. 360 * Bit fields: 361 * 4: UCODE_DISABLE 362 * Host sets this to request permanent halt of uCode, same as 363 * sending CARD_STATE command with "halt" bit set. 364 * 3: CT_KILL_EXIT 365 * Host sets this to request exit from CT_KILL state, i.e. host thinks 366 * device temperature is low enough to continue normal operation. 367 * 2: CMD_BLOCKED 368 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 369 * to release uCode to clear all Tx and command queues, enter 370 * unassociated mode, and power down. 371 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 372 * 1: SW_BIT_RFKILL 373 * Host sets this when issuing CARD_STATE command to request 374 * device sleep. 375 * 0: MAC_SLEEP 376 * uCode sets this when preparing a power-saving power-down. 377 * uCode resets this when power-up is complete and SRAM is sane. 378 * NOTE: device saves internal SRAM data to host when powering down, 379 * and must restore this data after powering back up. 380 * MAC_SLEEP is the best indication that restore is complete. 381 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 382 * do not need to save/restore it. 383 */ 384 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 385 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 386 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 387 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 388 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 389 390 /* GP Driver */ 391 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 392 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 393 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 394 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 395 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 396 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 397 398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 399 400 /* GIO Chicken Bits (PCI Express bus link power management) */ 401 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 402 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 403 404 /* LED */ 405 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 406 #define IWM_CSR_LED_REG_TURN_ON (0x60) 407 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 408 409 /* ANA_PLL */ 410 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 411 412 /* HPET MEM debug */ 413 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 414 415 /* DRAM INT TABLE */ 416 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 417 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 418 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 419 420 /* SECURE boot registers */ 421 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 422 enum iwm_secure_boot_config_reg { 423 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 424 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 425 }; 426 427 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 428 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 429 enum iwm_secure_boot_status_reg { 430 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 431 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 432 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 433 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 435 }; 436 437 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 438 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70 439 enum iwm_secure_load_status_reg { 440 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001, 441 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003, 442 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007, 443 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8, 444 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00, 445 }; 446 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 447 448 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38 449 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c 450 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 451 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 452 453 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000 454 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000 455 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 456 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 457 458 #define IWM_CSR_SECURE_TIME_OUT (100) 459 460 /* extended range in FW SRAM */ 461 #define IWM_FW_MEM_EXTENDED_START 0x40000 462 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 463 464 /* FW chicken bits */ 465 #define IWM_LMPM_CHICK 0xa01ff8 466 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 467 468 #define IWM_FH_TCSR_0_REG0 (0x1D00) 469 470 /* 471 * HBUS (Host-side Bus) 472 * 473 * HBUS registers are mapped directly into PCI bus space, but are used 474 * to indirectly access device's internal memory or registers that 475 * may be powered-down. 476 * 477 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 478 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 479 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 480 * internal resources. 481 * 482 * Do not use iwl_write32()/iwl_read32() family to access these registers; 483 * these provide only simple PCI bus access, without waking up the MAC. 484 */ 485 #define IWM_HBUS_BASE (0x400) 486 487 /* 488 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 489 * structures, error log, event log, verifying uCode load). 490 * First write to address register, then read from or write to data register 491 * to complete the job. Once the address register is set up, accesses to 492 * data registers auto-increment the address by one dword. 493 * Bit usage for address registers (read or write): 494 * 0-31: memory address within device 495 */ 496 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 497 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 498 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 499 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 500 501 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 502 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 503 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 504 505 /* 506 * Registers for accessing device's internal peripheral registers 507 * (e.g. SCD, BSM, etc.). First write to address register, 508 * then read from or write to data register to complete the job. 509 * Bit usage for address registers (read or write): 510 * 0-15: register address (offset) within device 511 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 512 */ 513 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 514 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 515 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 516 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 517 518 /* enable the ID buf for read */ 519 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 520 #define IWM_WFMP_MAC_ADDR_0 0xa03080 521 #define IWM_WFMP_MAC_ADDR_1 0xa03084 522 #define IWM_LMPM_PMG_EN 0xa01cec 523 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 524 #define IWM_RFIC_REG_RD 0xad0470 525 #define IWM_WFPM_CTRL_REG 0xa03030 526 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 527 #define IWM_ENABLE_WFPM 0x80000000 528 529 #define IWM_AUX_MISC_REG 0xa200b0 530 #define IWM_HW_STEP_LOCATION_BITS 24 531 532 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 533 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 534 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 535 #define IWM_RSA_ENABLE 0xa24b08 536 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 537 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 538 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 539 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 540 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 541 #define IWM_SB_CPU_1_STATUS 0xa01e30 542 #define IWM_SB_CPU_2_STATUS 0Xa01e34 543 544 /* Used to enable DBGM */ 545 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 546 547 /* 548 * Per-Tx-queue write pointer (index, really!) 549 * Indicates index to next TFD that driver will fill (1 past latest filled). 550 * Bit usage: 551 * 0-7: queue write index 552 * 11-8: queue selector 553 */ 554 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 555 556 /********************************************************** 557 * CSR values 558 **********************************************************/ 559 /* 560 * host interrupt timeout value 561 * used with setting interrupt coalescing timer 562 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 563 * 564 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 565 */ 566 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 567 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 568 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 569 #define IWM_HOST_INT_OPER_MODE (1 << 31) 570 571 /***************************************************************************** 572 * 7000/3000 series SHR DTS addresses * 573 *****************************************************************************/ 574 575 /* Diode Results Register Structure: */ 576 enum iwm_dtd_diode_reg { 577 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 578 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 579 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 580 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 581 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 582 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 583 /* Those are the masks INSIDE the flags bit-field: */ 584 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 585 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 586 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 587 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 588 }; 589 590 /** 591 * enum iwm_ucode_tlv_flag - ucode API flags 592 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 593 * was a separate TLV but moved here to save space. 594 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 595 * treats good CRC threshold as a boolean 596 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 597 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 598 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 599 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 600 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 601 * offload profile config command. 602 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api 603 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API. 604 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 605 * (rather than two) IPv6 addresses 606 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API 607 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 608 * from the probe request template. 609 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping 610 * connection when going back to D0 611 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 612 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 613 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan. 614 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API 615 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command 616 * containing CAM (Continuous Active Mode) indication. 617 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 618 * single bound interface). 619 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 620 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 621 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 622 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 623 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 624 * 625 */ 626 enum iwm_ucode_tlv_flag { 627 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 628 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 629 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 630 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3), 631 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4), 632 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5), 633 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6), 634 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 635 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8), 636 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9), 637 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 638 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11), 639 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 640 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14), 641 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 642 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 643 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17), 644 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19), 645 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20), 646 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21), 647 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22), 648 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23), 649 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 650 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 651 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 652 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 653 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30), 654 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31), 655 }; 656 657 #define IWM_UCODE_TLV_FLAG_BITS \ 658 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 659 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 660 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 661 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 662 663 /** 664 * enum iwm_ucode_tlv_api - ucode api 665 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 666 * longer than the passive one, which is essential for fragmented scan. 667 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 668 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 669 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 670 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 671 * instead of 3. 672 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 673 * (command version 3) that supports per-chain limits 674 * 675 * @IWM_NUM_UCODE_TLV_API: number of bits used 676 */ 677 enum iwm_ucode_tlv_api { 678 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8), 679 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9), 680 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14), 681 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18), 682 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24), 683 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27), 684 685 IWM_NUM_UCODE_TLV_API = 32 686 }; 687 688 #define IWM_UCODE_TLV_API_BITS \ 689 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 690 691 /** 692 * enum iwm_ucode_tlv_capa - ucode capabilities 693 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 694 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 695 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 696 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 697 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 698 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 699 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 700 * tx power value into TPC Report action frame and Link Measurement Report 701 * action frame 702 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 703 * channel in DS parameter set element in probe requests. 704 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 705 * probe requests. 706 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 707 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 708 * which also implies support for the scheduler configuration command 709 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 710 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 711 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 712 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 713 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 714 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 715 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 716 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 717 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 718 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 719 * sources for the MCC. This TLV bit is a future replacement to 720 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 721 * is supported. 722 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 723 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 724 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 725 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 726 * 0=no support) 727 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 728 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 729 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 730 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 731 * antenna the beacon should be transmitted 732 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 733 * from AP and will send it upon d0i3 exit. 734 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 735 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 736 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 737 * thresholds reporting 738 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 739 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 740 * regular image. 741 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 742 * memory addresses from the firmware. 743 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 744 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 745 * 0=no support) 746 * 747 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 748 */ 749 enum iwm_ucode_tlv_capa { 750 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 751 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 752 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 753 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 754 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 755 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 756 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 757 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 758 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 759 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 760 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 761 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 762 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 763 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 764 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 765 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 766 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 767 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 768 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 769 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 770 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 771 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 772 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 773 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 774 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 775 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 776 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 777 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 778 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 779 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 780 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 781 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 782 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 783 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 784 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 785 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 786 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79, 787 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 788 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 789 790 IWM_NUM_UCODE_TLV_CAPA = 128 791 }; 792 793 /* The default calibrate table size if not specified by firmware file */ 794 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 795 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 796 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 797 798 /* The default max probe length if not specified by the firmware file */ 799 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 800 801 /* 802 * enumeration of ucode section. 803 * This enumeration is used directly for older firmware (before 16.0). 804 * For new firmware, there can be up to 4 sections (see below) but the 805 * first one packaged into the firmware file is the DATA section and 806 * some debugging code accesses that. 807 */ 808 enum iwm_ucode_sec { 809 IWM_UCODE_SECTION_DATA, 810 IWM_UCODE_SECTION_INST, 811 }; 812 /* 813 * For 16.0 uCode and above, there is no differentiation between sections, 814 * just an offset to the HW address. 815 */ 816 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 817 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 818 819 /* uCode version contains 4 values: Major/Minor/API/Serial */ 820 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 821 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 822 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 823 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 824 825 /* 826 * Calibration control struct. 827 * Sent as part of the phy configuration command. 828 * @flow_trigger: bitmap for which calibrations to perform according to 829 * flow triggers. 830 * @event_trigger: bitmap for which calibrations to perform according to 831 * event triggers. 832 */ 833 struct iwm_tlv_calib_ctrl { 834 uint32_t flow_trigger; 835 uint32_t event_trigger; 836 } __packed; 837 838 enum iwm_fw_phy_cfg { 839 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 840 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 841 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 842 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 843 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 844 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 845 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 846 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 847 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 848 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 849 }; 850 851 #define IWM_UCODE_MAX_CS 1 852 853 /** 854 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 855 * @cipher: a cipher suite selector 856 * @flags: cipher scheme flags (currently reserved for a future use) 857 * @hdr_len: a size of MPDU security header 858 * @pn_len: a size of PN 859 * @pn_off: an offset of pn from the beginning of the security header 860 * @key_idx_off: an offset of key index byte in the security header 861 * @key_idx_mask: a bit mask of key_idx bits 862 * @key_idx_shift: bit shift needed to get key_idx 863 * @mic_len: mic length in bytes 864 * @hw_cipher: a HW cipher index used in host commands 865 */ 866 struct iwm_fw_cipher_scheme { 867 uint32_t cipher; 868 uint8_t flags; 869 uint8_t hdr_len; 870 uint8_t pn_len; 871 uint8_t pn_off; 872 uint8_t key_idx_off; 873 uint8_t key_idx_mask; 874 uint8_t key_idx_shift; 875 uint8_t mic_len; 876 uint8_t hw_cipher; 877 } __packed; 878 879 /** 880 * struct iwm_fw_cscheme_list - a cipher scheme list 881 * @size: a number of entries 882 * @cs: cipher scheme entries 883 */ 884 struct iwm_fw_cscheme_list { 885 uint8_t size; 886 struct iwm_fw_cipher_scheme cs[]; 887 } __packed; 888 889 /* v1/v2 uCode file layout */ 890 struct iwm_ucode_header { 891 uint32_t ver; /* major/minor/API/serial */ 892 union { 893 struct { 894 uint32_t inst_size; /* bytes of runtime code */ 895 uint32_t data_size; /* bytes of runtime data */ 896 uint32_t init_size; /* bytes of init code */ 897 uint32_t init_data_size; /* bytes of init data */ 898 uint32_t boot_size; /* bytes of bootstrap code */ 899 uint8_t data[0]; /* in same order as sizes */ 900 } v1; 901 struct { 902 uint32_t build; /* build number */ 903 uint32_t inst_size; /* bytes of runtime code */ 904 uint32_t data_size; /* bytes of runtime data */ 905 uint32_t init_size; /* bytes of init code */ 906 uint32_t init_data_size; /* bytes of init data */ 907 uint32_t boot_size; /* bytes of bootstrap code */ 908 uint8_t data[0]; /* in same order as sizes */ 909 } v2; 910 } u; 911 }; 912 913 /* 914 * new TLV uCode file layout 915 * 916 * The new TLV file format contains TLVs, that each specify 917 * some piece of data. 918 */ 919 920 enum iwm_ucode_tlv_type { 921 IWM_UCODE_TLV_INVALID = 0, /* unused */ 922 IWM_UCODE_TLV_INST = 1, 923 IWM_UCODE_TLV_DATA = 2, 924 IWM_UCODE_TLV_INIT = 3, 925 IWM_UCODE_TLV_INIT_DATA = 4, 926 IWM_UCODE_TLV_BOOT = 5, 927 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 928 IWM_UCODE_TLV_PAN = 7, 929 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 930 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 931 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 932 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 933 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 934 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 935 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 936 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 937 IWM_UCODE_TLV_WOWLAN_INST = 16, 938 IWM_UCODE_TLV_WOWLAN_DATA = 17, 939 IWM_UCODE_TLV_FLAGS = 18, 940 IWM_UCODE_TLV_SEC_RT = 19, 941 IWM_UCODE_TLV_SEC_INIT = 20, 942 IWM_UCODE_TLV_SEC_WOWLAN = 21, 943 IWM_UCODE_TLV_DEF_CALIB = 22, 944 IWM_UCODE_TLV_PHY_SKU = 23, 945 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 946 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 947 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 948 IWM_UCODE_TLV_NUM_OF_CPU = 27, 949 IWM_UCODE_TLV_CSCHEME = 28, 950 951 /* 952 * Following two are not in our base tag, but allow 953 * handling ucode version 9. 954 */ 955 IWM_UCODE_TLV_API_CHANGES_SET = 29, 956 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 957 958 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 959 IWM_UCODE_TLV_PAGING = 32, 960 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 961 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 962 IWM_UCODE_TLV_FW_VERSION = 36, 963 IWM_UCODE_TLV_FW_DBG_DEST = 38, 964 IWM_UCODE_TLV_FW_DBG_CONF = 39, 965 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 966 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 967 IWM_UCODE_TLV_FW_MEM_SEG = 51, 968 }; 969 970 struct iwm_ucode_tlv { 971 uint32_t type; /* see above */ 972 uint32_t length; /* not including type/length fields */ 973 uint8_t data[0]; 974 }; 975 976 struct iwm_ucode_api { 977 uint32_t api_index; 978 uint32_t api_flags; 979 } __packed; 980 981 struct iwm_ucode_capa { 982 uint32_t api_index; 983 uint32_t api_capa; 984 } __packed; 985 986 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 987 988 struct iwm_tlv_ucode_header { 989 /* 990 * The TLV style ucode header is distinguished from 991 * the v1/v2 style header by first four bytes being 992 * zero, as such is an invalid combination of 993 * major/minor/API/serial versions. 994 */ 995 uint32_t zero; 996 uint32_t magic; 997 uint8_t human_readable[64]; 998 uint32_t ver; /* major/minor/API/serial */ 999 uint32_t build; 1000 uint64_t ignore; 1001 /* 1002 * The data contained herein has a TLV layout, 1003 * see above for the TLV header and types. 1004 * Note that each TLV is padded to a length 1005 * that is a multiple of 4 for alignment. 1006 */ 1007 uint8_t data[0]; 1008 }; 1009 1010 /* 1011 * Registers in this file are internal, not PCI bus memory mapped. 1012 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 1013 */ 1014 #define IWM_PRPH_BASE (0x00000) 1015 #define IWM_PRPH_END (0xFFFFF) 1016 1017 /* APMG (power management) constants */ 1018 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 1019 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 1020 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 1021 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 1022 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 1023 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 1024 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 1025 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 1026 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 1027 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 1028 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 1029 1030 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 1031 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 1032 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 1033 1034 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 1035 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 1036 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 1037 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 1038 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 1039 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 1040 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 1041 1042 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 1043 1044 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 1045 1046 /* Device system time */ 1047 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 1048 1049 /* Device NMI register */ 1050 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1051 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1052 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1053 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1054 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1055 1056 /* 1057 * Device reset for family 8000 1058 * write to bit 24 in order to reset the CPU 1059 */ 1060 #define IWM_RELEASE_CPU_RESET 0x300c 1061 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1062 1063 1064 /***************************************************************************** 1065 * 7000/3000 series SHR DTS addresses * 1066 *****************************************************************************/ 1067 1068 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1069 #define IWM_DTSC_CFG_MODE (0x00a10604) 1070 #define IWM_DTSC_VREF_AVG (0x00a10648) 1071 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1072 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1073 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1074 1075 1076 /** 1077 * Tx Scheduler 1078 * 1079 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1080 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1081 * host DRAM. It steers each frame's Tx command (which contains the frame 1082 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1083 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1084 * but one DMA channel may take input from several queues. 1085 * 1086 * Tx DMA FIFOs have dedicated purposes. 1087 * 1088 * For 5000 series and up, they are used differently 1089 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1090 * 1091 * 0 -- EDCA BK (background) frames, lowest priority 1092 * 1 -- EDCA BE (best effort) frames, normal priority 1093 * 2 -- EDCA VI (video) frames, higher priority 1094 * 3 -- EDCA VO (voice) and management frames, highest priority 1095 * 4 -- unused 1096 * 5 -- unused 1097 * 6 -- unused 1098 * 7 -- Commands 1099 * 1100 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1101 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1102 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1103 * 1104 * The driver sets up each queue to work in one of two modes: 1105 * 1106 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1107 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1108 * contains TFDs for a unique combination of Recipient Address (RA) 1109 * and Traffic Identifier (TID), that is, traffic of a given 1110 * Quality-Of-Service (QOS) priority, destined for a single station. 1111 * 1112 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1113 * each frame within the BA window, including whether it's been transmitted, 1114 * and whether it's been acknowledged by the receiving station. The device 1115 * automatically processes block-acks received from the receiving STA, 1116 * and reschedules un-acked frames to be retransmitted (successful 1117 * Tx completion may end up being out-of-order). 1118 * 1119 * The driver must maintain the queue's Byte Count table in host DRAM 1120 * for this mode. 1121 * This mode does not support fragmentation. 1122 * 1123 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1124 * The device may automatically retry Tx, but will retry only one frame 1125 * at a time, until receiving ACK from receiving station, or reaching 1126 * retry limit and giving up. 1127 * 1128 * The command queue (#4/#9) must use this mode! 1129 * This mode does not require use of the Byte Count table in host DRAM. 1130 * 1131 * Driver controls scheduler operation via 3 means: 1132 * 1) Scheduler registers 1133 * 2) Shared scheduler data base in internal SRAM 1134 * 3) Shared data in host DRAM 1135 * 1136 * Initialization: 1137 * 1138 * When loading, driver should allocate memory for: 1139 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1140 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1141 * (1024 bytes for each queue). 1142 * 1143 * After receiving "Alive" response from uCode, driver must initialize 1144 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1145 * the driver can't issue commands!): 1146 */ 1147 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1148 1149 /** 1150 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1151 * can keep track of at one time when creating block-ack chains of frames. 1152 * Note that "64" matches the number of ack bits in a block-ack packet. 1153 */ 1154 #define IWM_SCD_WIN_SIZE 64 1155 #define IWM_SCD_FRAME_LIMIT 64 1156 1157 #define IWM_SCD_TXFIFO_POS_TID (0) 1158 #define IWM_SCD_TXFIFO_POS_RA (4) 1159 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1160 1161 /* agn SCD */ 1162 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1163 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1164 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1165 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1166 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1167 1168 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1169 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1170 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1171 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1172 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1173 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1174 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1175 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1176 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1177 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1178 1179 /* Context Data */ 1180 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1181 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1182 1183 /* Tx status */ 1184 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1185 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1186 1187 /* Translation Data */ 1188 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1189 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1190 1191 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1192 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1193 1194 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1195 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1196 1197 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1198 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1199 1200 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1201 1202 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1203 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1204 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1205 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1206 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1207 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1208 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1209 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1210 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1211 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1212 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1213 1214 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1215 { 1216 if (chnl < 20) 1217 return IWM_SCD_BASE + 0x18 + chnl * 4; 1218 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1219 } 1220 1221 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1222 { 1223 if (chnl < 20) 1224 return IWM_SCD_BASE + 0x68 + chnl * 4; 1225 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1226 } 1227 1228 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1229 { 1230 if (chnl < 20) 1231 return IWM_SCD_BASE + 0x10c + chnl * 4; 1232 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1233 } 1234 1235 /*********************** END TX SCHEDULER *************************************/ 1236 1237 /* Oscillator clock */ 1238 #define IWM_OSC_CLK (0xa04068) 1239 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1240 1241 /****************************/ 1242 /* Flow Handler Definitions */ 1243 /****************************/ 1244 1245 /** 1246 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1247 * Addresses are offsets from device's PCI hardware base address. 1248 */ 1249 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1250 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1251 1252 /** 1253 * Keep-Warm (KW) buffer base address. 1254 * 1255 * Driver must allocate a 4KByte buffer that is for keeping the 1256 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1257 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1258 * from going into a power-savings mode that would cause higher DRAM latency, 1259 * and possible data over/under-runs, before all Tx/Rx is complete. 1260 * 1261 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1262 * of the buffer, which must be 4K aligned. Once this is set up, the device 1263 * automatically invokes keep-warm accesses when normal accesses might not 1264 * be sufficient to maintain fast DRAM response. 1265 * 1266 * Bit fields: 1267 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1268 */ 1269 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1270 1271 1272 /** 1273 * TFD Circular Buffers Base (CBBC) addresses 1274 * 1275 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1276 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1277 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1278 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1279 * aligned (address bits 0-7 must be 0). 1280 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1281 * for them are in different places. 1282 * 1283 * Bit fields in each pointer register: 1284 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1285 */ 1286 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1287 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1288 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1289 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1290 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1291 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1292 1293 /* Find TFD CB base pointer for given queue */ 1294 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1295 { 1296 if (chnl < 16) 1297 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1298 if (chnl < 20) 1299 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1300 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1301 } 1302 1303 1304 /** 1305 * Rx SRAM Control and Status Registers (RSCSR) 1306 * 1307 * These registers provide handshake between driver and device for the Rx queue 1308 * (this queue handles *all* command responses, notifications, Rx data, etc. 1309 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1310 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1311 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1312 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1313 * mapping between RBDs and RBs. 1314 * 1315 * Driver must allocate host DRAM memory for the following, and set the 1316 * physical address of each into device registers: 1317 * 1318 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1319 * entries (although any power of 2, up to 4096, is selectable by driver). 1320 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1321 * (typically 4K, although 8K or 16K are also selectable by driver). 1322 * Driver sets up RB size and number of RBDs in the CB via Rx config 1323 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1324 * 1325 * Bit fields within one RBD: 1326 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1327 * 1328 * Driver sets physical address [35:8] of base of RBD circular buffer 1329 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1330 * 1331 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1332 * (RBs) have been filled, via a "write pointer", actually the index of 1333 * the RB's corresponding RBD within the circular buffer. Driver sets 1334 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1335 * 1336 * Bit fields in lower dword of Rx status buffer (upper dword not used 1337 * by driver: 1338 * 31-12: Not used by driver 1339 * 11- 0: Index of last filled Rx buffer descriptor 1340 * (device writes, driver reads this value) 1341 * 1342 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1343 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1344 * and update the device's "write" index register, 1345 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1346 * 1347 * This "write" index corresponds to the *next* RBD that the driver will make 1348 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1349 * the circular buffer. This value should initially be 0 (before preparing any 1350 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1351 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1352 * "read" index has advanced past 1! See below). 1353 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1354 * 1355 * As the device fills RBs (referenced from contiguous RBDs within the circular 1356 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1357 * to tell the driver the index of the latest filled RBD. The driver must 1358 * read this "read" index from DRAM after receiving an Rx interrupt from device 1359 * 1360 * The driver must also internally keep track of a third index, which is the 1361 * next RBD to process. When receiving an Rx interrupt, driver should process 1362 * all filled but unprocessed RBs up to, but not including, the RB 1363 * corresponding to the "read" index. For example, if "read" index becomes "1", 1364 * driver may process the RB pointed to by RBD 0. Depending on volume of 1365 * traffic, there may be many RBs to process. 1366 * 1367 * If read index == write index, device thinks there is no room to put new data. 1368 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1369 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1370 * and "read" indexes; that is, make sure that there are no more than 254 1371 * buffers waiting to be filled. 1372 */ 1373 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1374 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1375 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1376 1377 /** 1378 * Physical base address of 8-byte Rx Status buffer. 1379 * Bit fields: 1380 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1381 */ 1382 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1383 1384 /** 1385 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1386 * Bit fields: 1387 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1388 */ 1389 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1390 1391 /** 1392 * Rx write pointer (index, really!). 1393 * Bit fields: 1394 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1395 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1396 */ 1397 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1398 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1399 1400 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1401 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1402 1403 /** 1404 * Rx Config/Status Registers (RCSR) 1405 * Rx Config Reg for channel 0 (only channel used) 1406 * 1407 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1408 * normal operation (see bit fields). 1409 * 1410 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1411 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1412 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1413 * 1414 * Bit fields: 1415 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1416 * '10' operate normally 1417 * 29-24: reserved 1418 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1419 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1420 * 19-18: reserved 1421 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1422 * '10' 12K, '11' 16K. 1423 * 15-14: reserved 1424 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1425 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1426 * typical value 0x10 (about 1/2 msec) 1427 * 3- 0: reserved 1428 */ 1429 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1430 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1431 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1432 1433 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1434 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1435 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1436 1437 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1438 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1439 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1440 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1441 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1442 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1443 1444 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1445 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1446 #define IWM_RX_RB_TIMEOUT (0x11) 1447 1448 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1449 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1450 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1451 1452 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1453 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1454 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1455 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1456 1457 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1458 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1459 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1460 1461 /** 1462 * Rx Shared Status Registers (RSSR) 1463 * 1464 * After stopping Rx DMA channel (writing 0 to 1465 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1466 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1467 * 1468 * Bit fields: 1469 * 24: 1 = Channel 0 is idle 1470 * 1471 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1472 * contain default values that should not be altered by the driver. 1473 */ 1474 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1475 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1476 1477 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1478 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1479 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1480 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1481 1482 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1483 1484 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1485 1486 /* TFDB Area - TFDs buffer table */ 1487 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1488 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1489 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1490 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1491 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1492 1493 /** 1494 * Transmit DMA Channel Control/Status Registers (TCSR) 1495 * 1496 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1497 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1498 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1499 * 1500 * To use a Tx DMA channel, driver must initialize its 1501 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1502 * 1503 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1504 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1505 * 1506 * All other bits should be 0. 1507 * 1508 * Bit fields: 1509 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1510 * '10' operate normally 1511 * 29- 4: Reserved, set to "0" 1512 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1513 * 2- 0: Reserved, set to "0" 1514 */ 1515 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1516 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1517 1518 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1519 #define IWM_FH_TCSR_CHNL_NUM (8) 1520 1521 /* TCSR: tx_config register values */ 1522 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1523 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1524 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1525 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1526 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1527 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1528 1529 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1530 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1531 1532 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1533 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1534 1535 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1536 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1537 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1538 1539 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1540 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1541 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1542 1543 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1544 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1545 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1546 1547 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1548 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1549 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1550 1551 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1552 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1553 1554 /** 1555 * Tx Shared Status Registers (TSSR) 1556 * 1557 * After stopping Tx DMA channel (writing 0 to 1558 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1559 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1560 * (channel's buffers empty | no pending requests). 1561 * 1562 * Bit fields: 1563 * 31-24: 1 = Channel buffers empty (channel 7:0) 1564 * 23-16: 1 = No pending requests (channel 7:0) 1565 */ 1566 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1567 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1568 1569 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1570 1571 /** 1572 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1573 * 31: Indicates an address error when accessed to internal memory 1574 * uCode/driver must write "1" in order to clear this flag 1575 * 30: Indicates that Host did not send the expected number of dwords to FH 1576 * uCode/driver must write "1" in order to clear this flag 1577 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1578 * command was received from the scheduler while the TRB was already full 1579 * with previous command 1580 * uCode/driver must write "1" in order to clear this flag 1581 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1582 * bit is set, it indicates that the FH has received a full indication 1583 * from the RTC TxFIFO and the current value of the TxCredit counter was 1584 * not equal to zero. This mean that the credit mechanism was not 1585 * synchronized to the TxFIFO status 1586 * uCode/driver must write "1" in order to clear this flag 1587 */ 1588 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1589 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1590 1591 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1592 1593 /* Tx service channels */ 1594 #define IWM_FH_SRVC_CHNL (9) 1595 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1596 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1597 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1598 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1599 1600 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1601 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1602 (_chan) * 4) 1603 1604 /* Instruct FH to increment the retry count of a packet when 1605 * it is brought from the memory to TX-FIFO 1606 */ 1607 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1608 1609 #define IWM_RX_QUEUE_SIZE 256 1610 #define IWM_RX_QUEUE_MASK 255 1611 #define IWM_RX_QUEUE_SIZE_LOG 8 1612 1613 /* 1614 * RX related structures and functions 1615 */ 1616 #define IWM_RX_FREE_BUFFERS 64 1617 #define IWM_RX_LOW_WATERMARK 8 1618 1619 /** 1620 * struct iwm_rb_status - reseve buffer status 1621 * host memory mapped FH registers 1622 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1623 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1624 * @finished_rb_num [0:11] - Indicates the index of the current RB 1625 * in which the last frame was written to 1626 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1627 * which was transferred 1628 */ 1629 struct iwm_rb_status { 1630 uint16_t closed_rb_num; 1631 uint16_t closed_fr_num; 1632 uint16_t finished_rb_num; 1633 uint16_t finished_fr_nam; 1634 uint32_t unused; 1635 } __packed; 1636 1637 1638 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1639 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1640 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1641 IWM_TFD_QUEUE_SIZE_BC_DUP) 1642 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1643 #define IWM_NUM_OF_TBS 20 1644 1645 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1646 { 1647 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1648 } 1649 /** 1650 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1651 * 1652 * This structure contains dma address and length of transmission address 1653 * 1654 * @lo: low [31:0] portion of the dma address of TX buffer 1655 * every even is unaligned on 16 bit boundary 1656 * @hi_n_len 0-3 [35:32] portion of dma 1657 * 4-15 length of the tx buffer 1658 */ 1659 struct iwm_tfd_tb { 1660 uint32_t lo; 1661 uint16_t hi_n_len; 1662 } __packed; 1663 1664 /** 1665 * struct iwm_tfd 1666 * 1667 * Transmit Frame Descriptor (TFD) 1668 * 1669 * @ __reserved1[3] reserved 1670 * @ num_tbs 0-4 number of active tbs 1671 * 5 reserved 1672 * 6-7 padding (not used) 1673 * @ tbs[20] transmit frame buffer descriptors 1674 * @ __pad padding 1675 * 1676 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1677 * Both driver and device share these circular buffers, each of which must be 1678 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1679 * 1680 * Driver must indicate the physical address of the base of each 1681 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1682 * 1683 * Each TFD contains pointer/size information for up to 20 data buffers 1684 * in host DRAM. These buffers collectively contain the (one) frame described 1685 * by the TFD. Each buffer must be a single contiguous block of memory within 1686 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1687 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1688 * Tx frame, up to 8 KBytes in size. 1689 * 1690 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1691 */ 1692 struct iwm_tfd { 1693 uint8_t __reserved1[3]; 1694 uint8_t num_tbs; 1695 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1696 uint32_t __pad; 1697 } __packed; 1698 1699 /* Keep Warm Size */ 1700 #define IWM_KW_SIZE 0x1000 /* 4k */ 1701 1702 /* Fixed (non-configurable) rx data from phy */ 1703 1704 /** 1705 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1706 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1707 * @tfd_offset 0-12 - tx command byte count 1708 * 12-16 - station index 1709 */ 1710 struct iwm_agn_scd_bc_tbl { 1711 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1712 } __packed; 1713 1714 /* Maximum number of Tx queues. */ 1715 #define IWM_MVM_MAX_QUEUES 31 1716 1717 /* Tx queue numbers */ 1718 enum { 1719 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1720 IWM_MVM_CMD_QUEUE = 9, 1721 IWM_MVM_AUX_QUEUE = 15, 1722 }; 1723 1724 enum iwm_mvm_tx_fifo { 1725 IWM_MVM_TX_FIFO_BK = 0, 1726 IWM_MVM_TX_FIFO_BE, 1727 IWM_MVM_TX_FIFO_VI, 1728 IWM_MVM_TX_FIFO_VO, 1729 IWM_MVM_TX_FIFO_MCAST = 5, 1730 IWM_MVM_TX_FIFO_CMD = 7, 1731 }; 1732 1733 #define IWM_MVM_STATION_COUNT 16 1734 1735 /* commands */ 1736 enum { 1737 IWM_MVM_ALIVE = 0x1, 1738 IWM_REPLY_ERROR = 0x2, 1739 1740 IWM_INIT_COMPLETE_NOTIF = 0x4, 1741 1742 /* PHY context commands */ 1743 IWM_PHY_CONTEXT_CMD = 0x8, 1744 IWM_DBG_CFG = 0x9, 1745 1746 /* UMAC scan commands */ 1747 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1748 IWM_SCAN_CFG_CMD = 0xc, 1749 IWM_SCAN_REQ_UMAC = 0xd, 1750 IWM_SCAN_ABORT_UMAC = 0xe, 1751 IWM_SCAN_COMPLETE_UMAC = 0xf, 1752 1753 /* station table */ 1754 IWM_ADD_STA_KEY = 0x17, 1755 IWM_ADD_STA = 0x18, 1756 IWM_REMOVE_STA = 0x19, 1757 1758 /* TX */ 1759 IWM_TX_CMD = 0x1c, 1760 IWM_TXPATH_FLUSH = 0x1e, 1761 IWM_MGMT_MCAST_KEY = 0x1f, 1762 1763 /* scheduler config */ 1764 IWM_SCD_QUEUE_CFG = 0x1d, 1765 1766 /* global key */ 1767 IWM_WEP_KEY = 0x20, 1768 1769 /* MAC and Binding commands */ 1770 IWM_MAC_CONTEXT_CMD = 0x28, 1771 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1772 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1773 IWM_BINDING_CONTEXT_CMD = 0x2b, 1774 IWM_TIME_QUOTA_CMD = 0x2c, 1775 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1776 1777 IWM_LQ_CMD = 0x4e, 1778 1779 /* paging block to FW cpu2 */ 1780 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1781 1782 /* Scan offload */ 1783 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1784 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1785 IWM_HOT_SPOT_CMD = 0x53, 1786 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1787 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1788 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1789 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1790 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1791 1792 /* Phy */ 1793 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1794 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1795 /* IWM_PHY_DB_CMD = 0x6c, */ 1796 1797 /* Power - legacy power table command */ 1798 IWM_POWER_TABLE_CMD = 0x77, 1799 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1800 1801 /* Thermal Throttling*/ 1802 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1803 1804 /* Scanning */ 1805 IWM_SCAN_ABORT_CMD = 0x81, 1806 IWM_SCAN_START_NOTIFICATION = 0x82, 1807 IWM_SCAN_RESULTS_NOTIFICATION = 0x83, 1808 1809 /* NVM */ 1810 IWM_NVM_ACCESS_CMD = 0x88, 1811 1812 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1813 1814 IWM_BEACON_NOTIFICATION = 0x90, 1815 IWM_BEACON_TEMPLATE_CMD = 0x91, 1816 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1817 IWM_BT_CONFIG = 0x9b, 1818 IWM_STATISTICS_NOTIFICATION = 0x9d, 1819 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1820 1821 /* RF-KILL commands and notifications */ 1822 IWM_CARD_STATE_CMD = 0xa0, 1823 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1824 1825 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1826 1827 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1828 1829 /* Power - new power table command */ 1830 IWM_MAC_PM_POWER_TABLE = 0xa9, 1831 1832 IWM_REPLY_RX_PHY_CMD = 0xc0, 1833 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1834 IWM_BA_NOTIF = 0xc5, 1835 1836 /* Location Aware Regulatory */ 1837 IWM_MCC_UPDATE_CMD = 0xc8, 1838 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1839 1840 /* BT Coex */ 1841 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1842 IWM_BT_COEX_PROT_ENV = 0xcd, 1843 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1844 IWM_BT_COEX_CI = 0x5d, 1845 1846 IWM_REPLY_SF_CFG_CMD = 0xd1, 1847 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1848 1849 /* DTS measurements */ 1850 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1851 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1852 1853 IWM_REPLY_DEBUG_CMD = 0xf0, 1854 IWM_DEBUG_LOG_MSG = 0xf7, 1855 1856 IWM_MCAST_FILTER_CMD = 0xd0, 1857 1858 /* D3 commands/notifications */ 1859 IWM_D3_CONFIG_CMD = 0xd3, 1860 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1861 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1862 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1863 1864 /* for WoWLAN in particular */ 1865 IWM_WOWLAN_PATTERNS = 0xe0, 1866 IWM_WOWLAN_CONFIGURATION = 0xe1, 1867 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1868 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1869 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1870 IWM_WOWLAN_GET_STATUSES = 0xe5, 1871 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1872 1873 /* and for NetDetect */ 1874 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1875 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1876 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1877 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1878 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1879 1880 IWM_REPLY_MAX = 0xff, 1881 }; 1882 1883 enum iwm_phy_ops_subcmd_ids { 1884 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1885 IWM_CTDP_CONFIG_CMD = 0x03, 1886 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1887 IWM_CT_KILL_NOTIFICATION = 0xFE, 1888 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1889 }; 1890 1891 /* command groups */ 1892 enum { 1893 IWM_LEGACY_GROUP = 0x0, 1894 IWM_LONG_GROUP = 0x1, 1895 IWM_SYSTEM_GROUP = 0x2, 1896 IWM_MAC_CONF_GROUP = 0x3, 1897 IWM_PHY_OPS_GROUP = 0x4, 1898 IWM_DATA_PATH_GROUP = 0x5, 1899 IWM_PROT_OFFLOAD_GROUP = 0xb, 1900 }; 1901 1902 /** 1903 * struct iwm_cmd_response - generic response struct for most commands 1904 * @status: status of the command asked, changes for each one 1905 */ 1906 struct iwm_cmd_response { 1907 uint32_t status; 1908 }; 1909 1910 /* 1911 * struct iwm_tx_ant_cfg_cmd 1912 * @valid: valid antenna configuration 1913 */ 1914 struct iwm_tx_ant_cfg_cmd { 1915 uint32_t valid; 1916 } __packed; 1917 1918 /** 1919 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1920 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1921 * @flags: (reserved for future implementation) 1922 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1923 * @pwr_restriction: TX power restriction in dBms. 1924 */ 1925 struct iwm_reduce_tx_power_cmd { 1926 uint8_t flags; 1927 uint8_t mac_context_id; 1928 uint16_t pwr_restriction; 1929 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1930 1931 /* 1932 * Calibration control struct. 1933 * Sent as part of the phy configuration command. 1934 * @flow_trigger: bitmap for which calibrations to perform according to 1935 * flow triggers. 1936 * @event_trigger: bitmap for which calibrations to perform according to 1937 * event triggers. 1938 */ 1939 struct iwm_calib_ctrl { 1940 uint32_t flow_trigger; 1941 uint32_t event_trigger; 1942 } __packed; 1943 1944 /* This enum defines the bitmap of various calibrations to enable in both 1945 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1946 */ 1947 enum iwm_calib_cfg { 1948 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1949 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1950 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1951 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1952 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1953 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1954 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1955 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1956 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1957 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1958 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1959 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1960 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1961 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1962 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1963 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1964 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1965 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1966 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1967 }; 1968 1969 /* 1970 * Phy configuration command. 1971 */ 1972 struct iwm_phy_cfg_cmd { 1973 uint32_t phy_cfg; 1974 struct iwm_calib_ctrl calib_control; 1975 } __packed; 1976 1977 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1978 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1979 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1980 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1981 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1982 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1983 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1984 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1985 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 1986 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 1987 1988 1989 /* Target of the IWM_NVM_ACCESS_CMD */ 1990 enum { 1991 IWM_NVM_ACCESS_TARGET_CACHE = 0, 1992 IWM_NVM_ACCESS_TARGET_OTP = 1, 1993 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 1994 }; 1995 1996 /* Section types for IWM_NVM_ACCESS_CMD */ 1997 enum { 1998 IWM_NVM_SECTION_TYPE_SW = 1, 1999 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 2000 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 2001 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 2002 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 2003 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 2004 IWM_NVM_MAX_NUM_SECTIONS = 13, 2005 }; 2006 2007 /** 2008 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2009 * @op_code: 0 - read, 1 - write 2010 * @target: IWM_NVM_ACCESS_TARGET_* 2011 * @type: IWM_NVM_SECTION_TYPE_* 2012 * @offset: offset in bytes into the section 2013 * @length: in bytes, to read/write 2014 * @data: if write operation, the data to write. On read its empty 2015 */ 2016 struct iwm_nvm_access_cmd { 2017 uint8_t op_code; 2018 uint8_t target; 2019 uint16_t type; 2020 uint16_t offset; 2021 uint16_t length; 2022 uint8_t data[]; 2023 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2024 2025 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2026 2027 /* 2028 * struct iwm_fw_paging_cmd - paging layout 2029 * 2030 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2031 * 2032 * Send to FW the paging layout in the driver. 2033 * 2034 * @flags: various flags for the command 2035 * @block_size: the block size in powers of 2 2036 * @block_num: number of blocks specified in the command. 2037 * @device_phy_addr: virtual addresses from device side 2038 */ 2039 struct iwm_fw_paging_cmd { 2040 uint32_t flags; 2041 uint32_t block_size; 2042 uint32_t block_num; 2043 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2044 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2045 2046 /* 2047 * Fw items ID's 2048 * 2049 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2050 * download 2051 */ 2052 enum iwm_fw_item_id { 2053 IWM_FW_ITEM_ID_PAGING = 3, 2054 }; 2055 2056 /* 2057 * struct iwm_fw_get_item_cmd - get an item from the fw 2058 */ 2059 struct iwm_fw_get_item_cmd { 2060 uint32_t item_id; 2061 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2062 2063 /** 2064 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2065 * @offset: offset in bytes into the section 2066 * @length: in bytes, either how much was written or read 2067 * @type: IWM_NVM_SECTION_TYPE_* 2068 * @status: 0 for success, fail otherwise 2069 * @data: if read operation, the data returned. Empty on write. 2070 */ 2071 struct iwm_nvm_access_resp { 2072 uint16_t offset; 2073 uint16_t length; 2074 uint16_t type; 2075 uint16_t status; 2076 uint8_t data[]; 2077 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2078 2079 /* IWM_MVM_ALIVE 0x1 */ 2080 2081 /* alive response is_valid values */ 2082 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2083 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2084 2085 /* alive response ver_type values */ 2086 enum { 2087 IWM_FW_TYPE_HW = 0, 2088 IWM_FW_TYPE_PROT = 1, 2089 IWM_FW_TYPE_AP = 2, 2090 IWM_FW_TYPE_WOWLAN = 3, 2091 IWM_FW_TYPE_TIMING = 4, 2092 IWM_FW_TYPE_WIPAN = 5 2093 }; 2094 2095 /* alive response ver_subtype values */ 2096 enum { 2097 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2098 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2099 IWM_FW_SUBTYPE_REDUCED = 2, 2100 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2101 IWM_FW_SUBTYPE_WOWLAN = 4, 2102 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2103 IWM_FW_SUBTYPE_WIPAN = 6, 2104 IWM_FW_SUBTYPE_INITIALIZE = 9 2105 }; 2106 2107 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2108 #define IWM_ALIVE_STATUS_OK 0xCAFE 2109 2110 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2111 2112 struct iwm_mvm_alive_resp_ver1 { 2113 uint16_t status; 2114 uint16_t flags; 2115 uint8_t ucode_minor; 2116 uint8_t ucode_major; 2117 uint16_t id; 2118 uint8_t api_minor; 2119 uint8_t api_major; 2120 uint8_t ver_subtype; 2121 uint8_t ver_type; 2122 uint8_t mac; 2123 uint8_t opt; 2124 uint16_t reserved2; 2125 uint32_t timestamp; 2126 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2127 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2128 uint32_t cpu_register_ptr; 2129 uint32_t dbgm_config_ptr; 2130 uint32_t alive_counter_ptr; 2131 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2132 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2133 2134 struct iwm_mvm_alive_resp_ver2 { 2135 uint16_t status; 2136 uint16_t flags; 2137 uint8_t ucode_minor; 2138 uint8_t ucode_major; 2139 uint16_t id; 2140 uint8_t api_minor; 2141 uint8_t api_major; 2142 uint8_t ver_subtype; 2143 uint8_t ver_type; 2144 uint8_t mac; 2145 uint8_t opt; 2146 uint16_t reserved2; 2147 uint32_t timestamp; 2148 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2149 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2150 uint32_t cpu_register_ptr; 2151 uint32_t dbgm_config_ptr; 2152 uint32_t alive_counter_ptr; 2153 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2154 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2155 uint32_t st_fwrd_size; 2156 uint8_t umac_minor; /* UMAC version: minor */ 2157 uint8_t umac_major; /* UMAC version: major */ 2158 uint16_t umac_id; /* UMAC version: id */ 2159 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2160 uint32_t dbg_print_buff_addr; 2161 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2162 2163 struct iwm_mvm_alive_resp { 2164 uint16_t status; 2165 uint16_t flags; 2166 uint32_t ucode_minor; 2167 uint32_t ucode_major; 2168 uint8_t ver_subtype; 2169 uint8_t ver_type; 2170 uint8_t mac; 2171 uint8_t opt; 2172 uint32_t timestamp; 2173 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2174 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2175 uint32_t cpu_register_ptr; 2176 uint32_t dbgm_config_ptr; 2177 uint32_t alive_counter_ptr; 2178 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2179 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2180 uint32_t st_fwrd_size; 2181 uint32_t umac_minor; /* UMAC version: minor */ 2182 uint32_t umac_major; /* UMAC version: major */ 2183 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2184 uint32_t dbg_print_buff_addr; 2185 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2186 2187 /* Error response/notification */ 2188 enum { 2189 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2190 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2191 IWM_FW_ERR_SERVICE = 0x2, 2192 IWM_FW_ERR_ARC_MEMORY = 0x3, 2193 IWM_FW_ERR_ARC_CODE = 0x4, 2194 IWM_FW_ERR_WATCH_DOG = 0x5, 2195 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2196 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2197 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2198 IWM_FW_ERR_UNEXPECTED = 0xFE, 2199 IWM_FW_ERR_FATAL = 0xFF 2200 }; 2201 2202 /** 2203 * struct iwm_error_resp - FW error indication 2204 * ( IWM_REPLY_ERROR = 0x2 ) 2205 * @error_type: one of IWM_FW_ERR_* 2206 * @cmd_id: the command ID for which the error occurred 2207 * @bad_cmd_seq_num: sequence number of the erroneous command 2208 * @error_service: which service created the error, applicable only if 2209 * error_type = 2, otherwise 0 2210 * @timestamp: TSF in usecs. 2211 */ 2212 struct iwm_error_resp { 2213 uint32_t error_type; 2214 uint8_t cmd_id; 2215 uint8_t reserved1; 2216 uint16_t bad_cmd_seq_num; 2217 uint32_t error_service; 2218 uint64_t timestamp; 2219 } __packed; 2220 2221 2222 /* Common PHY, MAC and Bindings definitions */ 2223 2224 #define IWM_MAX_MACS_IN_BINDING (3) 2225 #define IWM_MAX_BINDINGS (4) 2226 #define IWM_AUX_BINDING_INDEX (3) 2227 #define IWM_MAX_PHYS (4) 2228 2229 /* Used to extract ID and color from the context dword */ 2230 #define IWM_FW_CTXT_ID_POS (0) 2231 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2232 #define IWM_FW_CTXT_COLOR_POS (8) 2233 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2234 #define IWM_FW_CTXT_INVALID (0xffffffff) 2235 2236 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2237 (_color << IWM_FW_CTXT_COLOR_POS)) 2238 2239 /* Possible actions on PHYs, MACs and Bindings */ 2240 enum { 2241 IWM_FW_CTXT_ACTION_STUB = 0, 2242 IWM_FW_CTXT_ACTION_ADD, 2243 IWM_FW_CTXT_ACTION_MODIFY, 2244 IWM_FW_CTXT_ACTION_REMOVE, 2245 IWM_FW_CTXT_ACTION_NUM 2246 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2247 2248 /* Time Events */ 2249 2250 /* Time Event types, according to MAC type */ 2251 enum iwm_time_event_type { 2252 /* BSS Station Events */ 2253 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2254 IWM_TE_BSS_STA_ASSOC, 2255 IWM_TE_BSS_EAP_DHCP_PROT, 2256 IWM_TE_BSS_QUIET_PERIOD, 2257 2258 /* P2P Device Events */ 2259 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2260 IWM_TE_P2P_DEVICE_LISTEN, 2261 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2262 IWM_TE_P2P_DEVICE_FULL_SCAN, 2263 2264 /* P2P Client Events */ 2265 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2266 IWM_TE_P2P_CLIENT_ASSOC, 2267 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2268 2269 /* P2P GO Events */ 2270 IWM_TE_P2P_GO_ASSOC_PROT, 2271 IWM_TE_P2P_GO_REPETITIVE_NOA, 2272 IWM_TE_P2P_GO_CT_WINDOW, 2273 2274 /* WiDi Sync Events */ 2275 IWM_TE_WIDI_TX_SYNC, 2276 2277 IWM_TE_MAX 2278 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2279 2280 2281 2282 /* Time event - defines for command API v1 */ 2283 2284 /* 2285 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2286 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2287 * the first fragment is scheduled. 2288 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2289 * the first 2 fragments are scheduled. 2290 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2291 * number of fragments are valid. 2292 * 2293 * Other than the constant defined above, specifying a fragmentation value 'x' 2294 * means that the event can be fragmented but only the first 'x' will be 2295 * scheduled. 2296 */ 2297 enum { 2298 IWM_TE_V1_FRAG_NONE = 0, 2299 IWM_TE_V1_FRAG_SINGLE = 1, 2300 IWM_TE_V1_FRAG_DUAL = 2, 2301 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2302 }; 2303 2304 /* If a Time Event can be fragmented, this is the max number of fragments */ 2305 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2306 /* Repeat the time event endlessly (until removed) */ 2307 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2308 /* If a Time Event has bounded repetitions, this is the maximal value */ 2309 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2310 2311 /* Time Event dependencies: none, on another TE, or in a specific time */ 2312 enum { 2313 IWM_TE_V1_INDEPENDENT = 0, 2314 IWM_TE_V1_DEP_OTHER = (1 << 0), 2315 IWM_TE_V1_DEP_TSF = (1 << 1), 2316 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2317 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2318 2319 /* 2320 * @IWM_TE_V1_NOTIF_NONE: no notifications 2321 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2322 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2323 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2324 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2325 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2326 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2327 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2328 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2329 * 2330 * Supported Time event notifications configuration. 2331 * A notification (both event and fragment) includes a status indicating weather 2332 * the FW was able to schedule the event or not. For fragment start/end 2333 * notification the status is always success. There is no start/end fragment 2334 * notification for monolithic events. 2335 */ 2336 enum { 2337 IWM_TE_V1_NOTIF_NONE = 0, 2338 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2339 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2340 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2341 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2342 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2343 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2344 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2345 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2346 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2347 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2348 2349 2350 /** 2351 * struct iwm_time_event_cmd_api_v1 - configuring Time Events 2352 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also 2353 * with version 2. determined by IWM_UCODE_TLV_FLAGS) 2354 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2355 * @id_and_color: ID and color of the relevant MAC 2356 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2357 * @id: this field has two meanings, depending on the action: 2358 * If the action is ADD, then it means the type of event to add. 2359 * For all other actions it is the unique event ID assigned when the 2360 * event was added by the FW. 2361 * @apply_time: When to start the Time Event (in GP2) 2362 * @max_delay: maximum delay to event's start (apply time), in TU 2363 * @depends_on: the unique ID of the event we depend on (if any) 2364 * @interval: interval between repetitions, in TU 2365 * @interval_reciprocal: 2^32 / interval 2366 * @duration: duration of event in TU 2367 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2368 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF 2369 * and IWM_TE_V1_EVENT_SOCIOPATHIC 2370 * @is_present: 0 or 1, are we present or absent during the Time Event 2371 * @max_frags: maximal number of fragments the Time Event can be divided to 2372 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when) 2373 */ 2374 struct iwm_time_event_cmd_v1 { 2375 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2376 uint32_t id_and_color; 2377 uint32_t action; 2378 uint32_t id; 2379 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */ 2380 uint32_t apply_time; 2381 uint32_t max_delay; 2382 uint32_t dep_policy; 2383 uint32_t depends_on; 2384 uint32_t is_present; 2385 uint32_t max_frags; 2386 uint32_t interval; 2387 uint32_t interval_reciprocal; 2388 uint32_t duration; 2389 uint32_t repeat; 2390 uint32_t notify; 2391 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */ 2392 2393 2394 /* Time event - defines for command API v2 */ 2395 2396 /* 2397 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2398 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2399 * the first fragment is scheduled. 2400 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2401 * the first 2 fragments are scheduled. 2402 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2403 * number of fragments are valid. 2404 * 2405 * Other than the constant defined above, specifying a fragmentation value 'x' 2406 * means that the event can be fragmented but only the first 'x' will be 2407 * scheduled. 2408 */ 2409 enum { 2410 IWM_TE_V2_FRAG_NONE = 0, 2411 IWM_TE_V2_FRAG_SINGLE = 1, 2412 IWM_TE_V2_FRAG_DUAL = 2, 2413 IWM_TE_V2_FRAG_MAX = 0xfe, 2414 IWM_TE_V2_FRAG_ENDLESS = 0xff 2415 }; 2416 2417 /* Repeat the time event endlessly (until removed) */ 2418 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2419 /* If a Time Event has bounded repetitions, this is the maximal value */ 2420 #define IWM_TE_V2_REPEAT_MAX 0xfe 2421 2422 #define IWM_TE_V2_PLACEMENT_POS 12 2423 #define IWM_TE_V2_ABSENCE_POS 15 2424 2425 /* Time event policy values (for time event cmd api v2) 2426 * A notification (both event and fragment) includes a status indicating weather 2427 * the FW was able to schedule the event or not. For fragment start/end 2428 * notification the status is always success. There is no start/end fragment 2429 * notification for monolithic events. 2430 * 2431 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2432 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2433 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2434 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2435 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2436 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2437 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2438 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2439 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2440 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2441 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2442 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2443 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2444 */ 2445 enum { 2446 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2447 2448 /* notifications (event start/stop, fragment start/stop) */ 2449 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2450 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2451 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2452 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2453 2454 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2455 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2456 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2457 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2458 2459 IWM_TE_V2_NOTIF_MSK = 0xff, 2460 2461 /* placement characteristics */ 2462 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2463 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2464 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2465 2466 /* are we present or absent during the Time Event. */ 2467 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2468 }; 2469 2470 /** 2471 * struct iwm_time_event_cmd_api_v2 - configuring Time Events 2472 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2473 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2474 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2475 * @id_and_color: ID and color of the relevant MAC 2476 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2477 * @id: this field has two meanings, depending on the action: 2478 * If the action is ADD, then it means the type of event to add. 2479 * For all other actions it is the unique event ID assigned when the 2480 * event was added by the FW. 2481 * @apply_time: When to start the Time Event (in GP2) 2482 * @max_delay: maximum delay to event's start (apply time), in TU 2483 * @depends_on: the unique ID of the event we depend on (if any) 2484 * @interval: interval between repetitions, in TU 2485 * @duration: duration of event in TU 2486 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2487 * @max_frags: maximal number of fragments the Time Event can be divided to 2488 * @policy: defines whether uCode shall notify the host or other uCode modules 2489 * on event and/or fragment start and/or end 2490 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2491 * IWM_TE_EVENT_SOCIOPATHIC 2492 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2493 */ 2494 struct iwm_time_event_cmd_v2 { 2495 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2496 uint32_t id_and_color; 2497 uint32_t action; 2498 uint32_t id; 2499 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2500 uint32_t apply_time; 2501 uint32_t max_delay; 2502 uint32_t depends_on; 2503 uint32_t interval; 2504 uint32_t duration; 2505 uint8_t repeat; 2506 uint8_t max_frags; 2507 uint16_t policy; 2508 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2509 2510 /** 2511 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2512 * @status: bit 0 indicates success, all others specify errors 2513 * @id: the Time Event type 2514 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2515 * @id_and_color: ID and color of the relevant MAC 2516 */ 2517 struct iwm_time_event_resp { 2518 uint32_t status; 2519 uint32_t id; 2520 uint32_t unique_id; 2521 uint32_t id_and_color; 2522 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2523 2524 /** 2525 * struct iwm_time_event_notif - notifications of time event start/stop 2526 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2527 * @timestamp: action timestamp in GP2 2528 * @session_id: session's unique id 2529 * @unique_id: unique id of the Time Event itself 2530 * @id_and_color: ID and color of the relevant MAC 2531 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2532 * @status: true if scheduled, false otherwise (not executed) 2533 */ 2534 struct iwm_time_event_notif { 2535 uint32_t timestamp; 2536 uint32_t session_id; 2537 uint32_t unique_id; 2538 uint32_t id_and_color; 2539 uint32_t action; 2540 uint32_t status; 2541 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2542 2543 2544 /* Bindings and Time Quota */ 2545 2546 /** 2547 * struct iwm_binding_cmd - configuring bindings 2548 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2549 * @id_and_color: ID and color of the relevant Binding 2550 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2551 * @macs: array of MAC id and colors which belong to the binding 2552 * @phy: PHY id and color which belongs to the binding 2553 */ 2554 struct iwm_binding_cmd { 2555 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2556 uint32_t id_and_color; 2557 uint32_t action; 2558 /* IWM_BINDING_DATA_API_S_VER_1 */ 2559 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2560 uint32_t phy; 2561 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2562 2563 /* The maximal number of fragments in the FW's schedule session */ 2564 #define IWM_MVM_MAX_QUOTA 128 2565 2566 /** 2567 * struct iwm_time_quota_data - configuration of time quota per binding 2568 * @id_and_color: ID and color of the relevant Binding 2569 * @quota: absolute time quota in TU. The scheduler will try to divide the 2570 * remainig quota (after Time Events) according to this quota. 2571 * @max_duration: max uninterrupted context duration in TU 2572 */ 2573 struct iwm_time_quota_data { 2574 uint32_t id_and_color; 2575 uint32_t quota; 2576 uint32_t max_duration; 2577 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2578 2579 /** 2580 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2581 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2582 * @quotas: allocations per binding 2583 */ 2584 struct iwm_time_quota_cmd { 2585 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2586 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2587 2588 2589 /* PHY context */ 2590 2591 /* Supported bands */ 2592 #define IWM_PHY_BAND_5 (0) 2593 #define IWM_PHY_BAND_24 (1) 2594 2595 /* Supported channel width, vary if there is VHT support */ 2596 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2597 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2598 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2599 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2600 2601 /* 2602 * Control channel position: 2603 * For legacy set bit means upper channel, otherwise lower. 2604 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2605 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2606 * center_freq 2607 * | 2608 * 40Mhz |_______|_______| 2609 * 80Mhz |_______|_______|_______|_______| 2610 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2611 * code 011 010 001 000 | 100 101 110 111 2612 */ 2613 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2614 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2615 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2616 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2617 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2618 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2619 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2620 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2621 2622 /* 2623 * @band: IWM_PHY_BAND_* 2624 * @channel: channel number 2625 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2626 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2627 */ 2628 struct iwm_fw_channel_info { 2629 uint8_t band; 2630 uint8_t channel; 2631 uint8_t width; 2632 uint8_t ctrl_pos; 2633 } __packed; 2634 2635 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2636 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2637 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2638 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2639 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2640 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2641 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2642 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2643 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2644 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2645 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2646 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2647 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2648 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2649 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2650 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2651 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2652 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2653 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2654 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2655 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2656 2657 /* TODO: fix the value, make it depend on firmware at runtime? */ 2658 #define IWM_NUM_PHY_CTX 3 2659 2660 /* TODO: complete missing documentation */ 2661 /** 2662 * struct iwm_phy_context_cmd - config of the PHY context 2663 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2664 * @id_and_color: ID and color of the relevant Binding 2665 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2666 * @apply_time: 0 means immediate apply and context switch. 2667 * other value means apply new params after X usecs 2668 * @tx_param_color: ??? 2669 * @channel_info: 2670 * @txchain_info: ??? 2671 * @rxchain_info: ??? 2672 * @acquisition_data: ??? 2673 * @dsp_cfg_flags: set to 0 2674 */ 2675 struct iwm_phy_context_cmd { 2676 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2677 uint32_t id_and_color; 2678 uint32_t action; 2679 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2680 uint32_t apply_time; 2681 uint32_t tx_param_color; 2682 struct iwm_fw_channel_info ci; 2683 uint32_t txchain_info; 2684 uint32_t rxchain_info; 2685 uint32_t acquisition_data; 2686 uint32_t dsp_cfg_flags; 2687 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2688 2689 #define IWM_RX_INFO_PHY_CNT 8 2690 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2691 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2692 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2693 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2694 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2695 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2696 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2697 2698 #define IWM_RX_INFO_AGC_IDX 1 2699 #define IWM_RX_INFO_RSSI_AB_IDX 2 2700 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2701 #define IWM_OFDM_AGC_A_POS 0 2702 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2703 #define IWM_OFDM_AGC_B_POS 7 2704 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2705 #define IWM_OFDM_AGC_CODE_POS 20 2706 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2707 #define IWM_OFDM_RSSI_A_POS 0 2708 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2709 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2710 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2711 #define IWM_OFDM_RSSI_B_POS 16 2712 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2713 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2714 2715 /** 2716 * struct iwm_rx_phy_info - phy info 2717 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2718 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2719 * @cfg_phy_cnt: configurable DSP phy data byte count 2720 * @stat_id: configurable DSP phy data set ID 2721 * @reserved1: 2722 * @system_timestamp: GP2 at on air rise 2723 * @timestamp: TSF at on air rise 2724 * @beacon_time_stamp: beacon at on-air rise 2725 * @phy_flags: general phy flags: band, modulation, ... 2726 * @channel: channel number 2727 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2728 * @rate_n_flags: IWM_RATE_MCS_* 2729 * @byte_count: frame's byte-count 2730 * @frame_time: frame's time on the air, based on byte count and frame rate 2731 * calculation 2732 * @mac_active_msk: what MACs were active when the frame was received 2733 * 2734 * Before each Rx, the device sends this data. It contains PHY information 2735 * about the reception of the packet. 2736 */ 2737 struct iwm_rx_phy_info { 2738 uint8_t non_cfg_phy_cnt; 2739 uint8_t cfg_phy_cnt; 2740 uint8_t stat_id; 2741 uint8_t reserved1; 2742 uint32_t system_timestamp; 2743 uint64_t timestamp; 2744 uint32_t beacon_time_stamp; 2745 uint16_t phy_flags; 2746 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2747 uint16_t channel; 2748 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2749 uint8_t rate; 2750 uint8_t rflags; 2751 uint16_t xrflags; 2752 uint32_t byte_count; 2753 uint16_t mac_active_msk; 2754 uint16_t frame_time; 2755 } __packed; 2756 2757 struct iwm_rx_mpdu_res_start { 2758 uint16_t byte_count; 2759 uint16_t reserved; 2760 } __packed; 2761 2762 /** 2763 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2764 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2765 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2766 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2767 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2768 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2769 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2770 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2771 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2772 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2773 */ 2774 enum iwm_rx_phy_flags { 2775 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2776 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2777 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2778 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2779 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2780 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2781 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2782 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2783 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2784 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2785 }; 2786 2787 /** 2788 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2789 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2790 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2791 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2792 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2793 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2794 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2795 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2796 * in the driver. 2797 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2798 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2799 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2800 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2801 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2802 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2803 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2804 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2805 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2806 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2807 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2808 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2809 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2810 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2811 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2812 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2813 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2814 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2815 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2816 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2817 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2818 */ 2819 enum iwm_mvm_rx_status { 2820 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2821 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2822 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2823 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2824 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2825 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2826 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2827 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2828 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2829 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2830 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2831 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2832 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2833 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2834 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2835 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2836 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2837 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2838 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2839 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2840 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2841 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2842 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2843 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2844 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2845 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2846 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2847 }; 2848 2849 /** 2850 * struct iwm_radio_version_notif - information on the radio version 2851 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2852 * @radio_flavor: 2853 * @radio_step: 2854 * @radio_dash: 2855 */ 2856 struct iwm_radio_version_notif { 2857 uint32_t radio_flavor; 2858 uint32_t radio_step; 2859 uint32_t radio_dash; 2860 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2861 2862 enum iwm_card_state_flags { 2863 IWM_CARD_ENABLED = 0x00, 2864 IWM_HW_CARD_DISABLED = 0x01, 2865 IWM_SW_CARD_DISABLED = 0x02, 2866 IWM_CT_KILL_CARD_DISABLED = 0x04, 2867 IWM_HALT_CARD_DISABLED = 0x08, 2868 IWM_CARD_DISABLED_MSK = 0x0f, 2869 IWM_CARD_IS_RX_ON = 0x10, 2870 }; 2871 2872 /** 2873 * struct iwm_radio_version_notif - information on the radio version 2874 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2875 * @flags: %iwm_card_state_flags 2876 */ 2877 struct iwm_card_state_notif { 2878 uint32_t flags; 2879 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2880 2881 /** 2882 * struct iwm_missed_beacons_notif - information on missed beacons 2883 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2884 * @mac_id: interface ID 2885 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2886 * beacons since last RX. 2887 * @consec_missed_beacons: number of consecutive missed beacons 2888 * @num_expected_beacons: 2889 * @num_recvd_beacons: 2890 */ 2891 struct iwm_missed_beacons_notif { 2892 uint32_t mac_id; 2893 uint32_t consec_missed_beacons_since_last_rx; 2894 uint32_t consec_missed_beacons; 2895 uint32_t num_expected_beacons; 2896 uint32_t num_recvd_beacons; 2897 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2898 2899 /** 2900 * struct iwm_mfuart_load_notif - mfuart image version & status 2901 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2902 * @installed_ver: installed image version 2903 * @external_ver: external image version 2904 * @status: MFUART loading status 2905 * @duration: MFUART loading time 2906 */ 2907 struct iwm_mfuart_load_notif { 2908 uint32_t installed_ver; 2909 uint32_t external_ver; 2910 uint32_t status; 2911 uint32_t duration; 2912 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2913 2914 /** 2915 * struct iwm_set_calib_default_cmd - set default value for calibration. 2916 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2917 * @calib_index: the calibration to set value for 2918 * @length: of data 2919 * @data: the value to set for the calibration result 2920 */ 2921 struct iwm_set_calib_default_cmd { 2922 uint16_t calib_index; 2923 uint16_t length; 2924 uint8_t data[0]; 2925 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2926 2927 #define IWM_MAX_PORT_ID_NUM 2 2928 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2929 2930 /** 2931 * struct iwm_mcast_filter_cmd - configure multicast filter. 2932 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2933 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2934 * to identify network interface adopted in host-device IF. 2935 * It is used by FW as index in array of addresses. This array has 2936 * IWM_MAX_PORT_ID_NUM members. 2937 * @count: Number of MAC addresses in the array 2938 * @pass_all: Set 1 to pass all multicast packets. 2939 * @bssid: current association BSSID. 2940 * @addr_list: Place holder for array of MAC addresses. 2941 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2942 */ 2943 struct iwm_mcast_filter_cmd { 2944 uint8_t filter_own; 2945 uint8_t port_id; 2946 uint8_t count; 2947 uint8_t pass_all; 2948 uint8_t bssid[6]; 2949 uint8_t reserved[2]; 2950 uint8_t addr_list[0]; 2951 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2952 2953 struct iwm_mvm_statistics_dbg { 2954 uint32_t burst_check; 2955 uint32_t burst_count; 2956 uint32_t wait_for_silence_timeout_cnt; 2957 uint32_t reserved[3]; 2958 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2959 2960 struct iwm_mvm_statistics_div { 2961 uint32_t tx_on_a; 2962 uint32_t tx_on_b; 2963 uint32_t exec_time; 2964 uint32_t probe_time; 2965 uint32_t rssi_ant; 2966 uint32_t reserved2; 2967 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2968 2969 struct iwm_mvm_statistics_general_common { 2970 uint32_t temperature; /* radio temperature */ 2971 uint32_t temperature_m; /* radio voltage */ 2972 struct iwm_mvm_statistics_dbg dbg; 2973 uint32_t sleep_time; 2974 uint32_t slots_out; 2975 uint32_t slots_idle; 2976 uint32_t ttl_timestamp; 2977 struct iwm_mvm_statistics_div div; 2978 uint32_t rx_enable_counter; 2979 /* 2980 * num_of_sos_states: 2981 * count the number of times we have to re-tune 2982 * in order to get out of bad PHY status 2983 */ 2984 uint32_t num_of_sos_states; 2985 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 2986 2987 struct iwm_mvm_statistics_rx_non_phy { 2988 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2989 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2990 uint32_t non_bssid_frames; /* number of frames with BSSID that 2991 * doesn't belong to the STA BSSID */ 2992 uint32_t filtered_frames; /* count frames that were dumped in the 2993 * filtering process */ 2994 uint32_t non_channel_beacons; /* beacons with our bss id but not on 2995 * our serving channel */ 2996 uint32_t channel_beacons; /* beacons with our bss id and in our 2997 * serving channel */ 2998 uint32_t num_missed_bcon; /* number of missed beacons */ 2999 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3000 * ADC was in saturation */ 3001 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3002 * for INA */ 3003 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3004 uint32_t interference_data_flag; /* flag for interference data 3005 * availability. 1 when data is 3006 * available. */ 3007 uint32_t channel_load; /* counts RX Enable time in uSec */ 3008 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3009 * and CCK) counter */ 3010 uint32_t beacon_rssi_a; 3011 uint32_t beacon_rssi_b; 3012 uint32_t beacon_rssi_c; 3013 uint32_t beacon_energy_a; 3014 uint32_t beacon_energy_b; 3015 uint32_t beacon_energy_c; 3016 uint32_t num_bt_kills; 3017 uint32_t mac_id; 3018 uint32_t directed_data_mpdu; 3019 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3020 3021 struct iwm_mvm_statistics_rx_phy { 3022 uint32_t ina_cnt; 3023 uint32_t fina_cnt; 3024 uint32_t plcp_err; 3025 uint32_t crc32_err; 3026 uint32_t overrun_err; 3027 uint32_t early_overrun_err; 3028 uint32_t crc32_good; 3029 uint32_t false_alarm_cnt; 3030 uint32_t fina_sync_err_cnt; 3031 uint32_t sfd_timeout; 3032 uint32_t fina_timeout; 3033 uint32_t unresponded_rts; 3034 uint32_t rxe_frame_limit_overrun; 3035 uint32_t sent_ack_cnt; 3036 uint32_t sent_cts_cnt; 3037 uint32_t sent_ba_rsp_cnt; 3038 uint32_t dsp_self_kill; 3039 uint32_t mh_format_err; 3040 uint32_t re_acq_main_rssi_sum; 3041 uint32_t reserved; 3042 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 3043 3044 struct iwm_mvm_statistics_rx_ht_phy { 3045 uint32_t plcp_err; 3046 uint32_t overrun_err; 3047 uint32_t early_overrun_err; 3048 uint32_t crc32_good; 3049 uint32_t crc32_err; 3050 uint32_t mh_format_err; 3051 uint32_t agg_crc32_good; 3052 uint32_t agg_mpdu_cnt; 3053 uint32_t agg_cnt; 3054 uint32_t unsupport_mcs; 3055 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3056 3057 #define IWM_MAX_CHAINS 3 3058 3059 struct iwm_mvm_statistics_tx_non_phy_agg { 3060 uint32_t ba_timeout; 3061 uint32_t ba_reschedule_frames; 3062 uint32_t scd_query_agg_frame_cnt; 3063 uint32_t scd_query_no_agg; 3064 uint32_t scd_query_agg; 3065 uint32_t scd_query_mismatch; 3066 uint32_t frame_not_ready; 3067 uint32_t underrun; 3068 uint32_t bt_prio_kill; 3069 uint32_t rx_ba_rsp_cnt; 3070 int8_t txpower[IWM_MAX_CHAINS]; 3071 int8_t reserved; 3072 uint32_t reserved2; 3073 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3074 3075 struct iwm_mvm_statistics_tx_channel_width { 3076 uint32_t ext_cca_narrow_ch20[1]; 3077 uint32_t ext_cca_narrow_ch40[2]; 3078 uint32_t ext_cca_narrow_ch80[3]; 3079 uint32_t ext_cca_narrow_ch160[4]; 3080 uint32_t last_tx_ch_width_indx; 3081 uint32_t rx_detected_per_ch_width[4]; 3082 uint32_t success_per_ch_width[4]; 3083 uint32_t fail_per_ch_width[4]; 3084 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3085 3086 struct iwm_mvm_statistics_tx { 3087 uint32_t preamble_cnt; 3088 uint32_t rx_detected_cnt; 3089 uint32_t bt_prio_defer_cnt; 3090 uint32_t bt_prio_kill_cnt; 3091 uint32_t few_bytes_cnt; 3092 uint32_t cts_timeout; 3093 uint32_t ack_timeout; 3094 uint32_t expected_ack_cnt; 3095 uint32_t actual_ack_cnt; 3096 uint32_t dump_msdu_cnt; 3097 uint32_t burst_abort_next_frame_mismatch_cnt; 3098 uint32_t burst_abort_missing_next_frame_cnt; 3099 uint32_t cts_timeout_collision; 3100 uint32_t ack_or_ba_timeout_collision; 3101 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3102 struct iwm_mvm_statistics_tx_channel_width channel_width; 3103 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3104 3105 3106 struct iwm_mvm_statistics_bt_activity { 3107 uint32_t hi_priority_tx_req_cnt; 3108 uint32_t hi_priority_tx_denied_cnt; 3109 uint32_t lo_priority_tx_req_cnt; 3110 uint32_t lo_priority_tx_denied_cnt; 3111 uint32_t hi_priority_rx_req_cnt; 3112 uint32_t hi_priority_rx_denied_cnt; 3113 uint32_t lo_priority_rx_req_cnt; 3114 uint32_t lo_priority_rx_denied_cnt; 3115 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3116 3117 struct iwm_mvm_statistics_general { 3118 struct iwm_mvm_statistics_general_common common; 3119 uint32_t beacon_filtered; 3120 uint32_t missed_beacons; 3121 int8_t beacon_filter_average_energy; 3122 int8_t beacon_filter_reason; 3123 int8_t beacon_filter_current_energy; 3124 int8_t beacon_filter_reserved; 3125 uint32_t beacon_filter_delta_time; 3126 struct iwm_mvm_statistics_bt_activity bt_activity; 3127 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */ 3128 3129 struct iwm_mvm_statistics_rx { 3130 struct iwm_mvm_statistics_rx_phy ofdm; 3131 struct iwm_mvm_statistics_rx_phy cck; 3132 struct iwm_mvm_statistics_rx_non_phy general; 3133 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3134 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3135 3136 /* 3137 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3138 * 3139 * By default, uCode issues this notification after receiving a beacon 3140 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3141 * IWM_REPLY_STATISTICS_CMD 0x9c, above. 3142 * 3143 * Statistics counters continue to increment beacon after beacon, but are 3144 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD 3145 * 0x9c with CLEAR_STATS bit set (see above). 3146 * 3147 * uCode also issues this notification during scans. uCode clears statistics 3148 * appropriately so that each notification contains statistics for only the 3149 * one channel that has just been scanned. 3150 */ 3151 3152 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */ 3153 uint32_t flag; 3154 struct iwm_mvm_statistics_rx rx; 3155 struct iwm_mvm_statistics_tx tx; 3156 struct iwm_mvm_statistics_general general; 3157 } __packed; 3158 3159 /*********************************** 3160 * Smart Fifo API 3161 ***********************************/ 3162 /* Smart Fifo state */ 3163 enum iwm_sf_state { 3164 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3165 IWM_SF_FULL_ON, 3166 IWM_SF_UNINIT, 3167 IWM_SF_INIT_OFF, 3168 IWM_SF_HW_NUM_STATES 3169 }; 3170 3171 /* Smart Fifo possible scenario */ 3172 enum iwm_sf_scenario { 3173 IWM_SF_SCENARIO_SINGLE_UNICAST, 3174 IWM_SF_SCENARIO_AGG_UNICAST, 3175 IWM_SF_SCENARIO_MULTICAST, 3176 IWM_SF_SCENARIO_BA_RESP, 3177 IWM_SF_SCENARIO_TX_RESP, 3178 IWM_SF_NUM_SCENARIO 3179 }; 3180 3181 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3182 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3183 3184 /* smart FIFO default values */ 3185 #define IWM_SF_W_MARK_SISO 4096 3186 #define IWM_SF_W_MARK_MIMO2 8192 3187 #define IWM_SF_W_MARK_MIMO3 6144 3188 #define IWM_SF_W_MARK_LEGACY 4096 3189 #define IWM_SF_W_MARK_SCAN 4096 3190 3191 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3192 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3193 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3194 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3195 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3196 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3197 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3198 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3199 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3200 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3201 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3202 3203 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3204 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3205 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3206 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3207 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3208 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3209 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3210 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3211 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3212 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3213 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3214 3215 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3216 3217 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3218 3219 /** 3220 * Smart Fifo configuration command. 3221 * @state: smart fifo state, types listed in enum %iwm_sf_state. 3222 * @watermark: Minimum allowed available free space in RXF for transient state. 3223 * @long_delay_timeouts: aging and idle timer values for each scenario 3224 * in long delay state. 3225 * @full_on_timeouts: timer values for each scenario in full on state. 3226 */ 3227 struct iwm_sf_cfg_cmd { 3228 uint32_t state; 3229 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3230 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3231 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3232 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3233 3234 /* 3235 * The first MAC indices (starting from 0) 3236 * are available to the driver, AUX follows 3237 */ 3238 #define IWM_MAC_INDEX_AUX 4 3239 #define IWM_MAC_INDEX_MIN_DRIVER 0 3240 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 3241 3242 enum iwm_ac { 3243 IWM_AC_BK, 3244 IWM_AC_BE, 3245 IWM_AC_VI, 3246 IWM_AC_VO, 3247 IWM_AC_NUM, 3248 }; 3249 3250 /** 3251 * enum iwm_mac_protection_flags - MAC context flags 3252 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3253 * this will require CCK RTS/CTS2self. 3254 * RTS/CTS will protect full burst time. 3255 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3256 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3257 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3258 */ 3259 enum iwm_mac_protection_flags { 3260 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3261 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3262 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3263 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3264 }; 3265 3266 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3267 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3268 3269 /** 3270 * enum iwm_mac_types - Supported MAC types 3271 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3272 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3273 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3274 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3275 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3276 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3277 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3278 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3279 * @IWM_FW_MAC_TYPE_GO: P2P GO 3280 * @IWM_FW_MAC_TYPE_TEST: ? 3281 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3282 */ 3283 enum iwm_mac_types { 3284 IWM_FW_MAC_TYPE_FIRST = 1, 3285 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3286 IWM_FW_MAC_TYPE_LISTENER, 3287 IWM_FW_MAC_TYPE_PIBSS, 3288 IWM_FW_MAC_TYPE_IBSS, 3289 IWM_FW_MAC_TYPE_BSS_STA, 3290 IWM_FW_MAC_TYPE_P2P_DEVICE, 3291 IWM_FW_MAC_TYPE_P2P_STA, 3292 IWM_FW_MAC_TYPE_GO, 3293 IWM_FW_MAC_TYPE_TEST, 3294 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3295 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3296 3297 /** 3298 * enum iwm_tsf_id - TSF hw timer ID 3299 * @IWM_TSF_ID_A: use TSF A 3300 * @IWM_TSF_ID_B: use TSF B 3301 * @IWM_TSF_ID_C: use TSF C 3302 * @IWM_TSF_ID_D: use TSF D 3303 * @IWM_NUM_TSF_IDS: number of TSF timers available 3304 */ 3305 enum iwm_tsf_id { 3306 IWM_TSF_ID_A = 0, 3307 IWM_TSF_ID_B = 1, 3308 IWM_TSF_ID_C = 2, 3309 IWM_TSF_ID_D = 3, 3310 IWM_NUM_TSF_IDS = 4, 3311 }; /* IWM_TSF_ID_API_E_VER_1 */ 3312 3313 /** 3314 * struct iwm_mac_data_ap - configuration data for AP MAC context 3315 * @beacon_time: beacon transmit time in system time 3316 * @beacon_tsf: beacon transmit time in TSF 3317 * @bi: beacon interval in TU 3318 * @bi_reciprocal: 2^32 / bi 3319 * @dtim_interval: dtim transmit time in TU 3320 * @dtim_reciprocal: 2^32 / dtim_interval 3321 * @mcast_qid: queue ID for multicast traffic 3322 * @beacon_template: beacon template ID 3323 */ 3324 struct iwm_mac_data_ap { 3325 uint32_t beacon_time; 3326 uint64_t beacon_tsf; 3327 uint32_t bi; 3328 uint32_t bi_reciprocal; 3329 uint32_t dtim_interval; 3330 uint32_t dtim_reciprocal; 3331 uint32_t mcast_qid; 3332 uint32_t beacon_template; 3333 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3334 3335 /** 3336 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3337 * @beacon_time: beacon transmit time in system time 3338 * @beacon_tsf: beacon transmit time in TSF 3339 * @bi: beacon interval in TU 3340 * @bi_reciprocal: 2^32 / bi 3341 * @beacon_template: beacon template ID 3342 */ 3343 struct iwm_mac_data_ibss { 3344 uint32_t beacon_time; 3345 uint64_t beacon_tsf; 3346 uint32_t bi; 3347 uint32_t bi_reciprocal; 3348 uint32_t beacon_template; 3349 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3350 3351 /** 3352 * struct iwm_mac_data_sta - configuration data for station MAC context 3353 * @is_assoc: 1 for associated state, 0 otherwise 3354 * @dtim_time: DTIM arrival time in system time 3355 * @dtim_tsf: DTIM arrival time in TSF 3356 * @bi: beacon interval in TU, applicable only when associated 3357 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3358 * @dtim_interval: DTIM interval in TU, applicable only when associated 3359 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3360 * @listen_interval: in beacon intervals, applicable only when associated 3361 * @assoc_id: unique ID assigned by the AP during association 3362 */ 3363 struct iwm_mac_data_sta { 3364 uint32_t is_assoc; 3365 uint32_t dtim_time; 3366 uint64_t dtim_tsf; 3367 uint32_t bi; 3368 uint32_t bi_reciprocal; 3369 uint32_t dtim_interval; 3370 uint32_t dtim_reciprocal; 3371 uint32_t listen_interval; 3372 uint32_t assoc_id; 3373 uint32_t assoc_beacon_arrive_time; 3374 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3375 3376 /** 3377 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3378 * @ap: iwm_mac_data_ap struct with most config data 3379 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3380 * 0 indicates that there is no CT window. 3381 * @opp_ps_enabled: indicate that opportunistic PS allowed 3382 */ 3383 struct iwm_mac_data_go { 3384 struct iwm_mac_data_ap ap; 3385 uint32_t ctwin; 3386 uint32_t opp_ps_enabled; 3387 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3388 3389 /** 3390 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3391 * @sta: iwm_mac_data_sta struct with most config data 3392 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3393 * 0 indicates that there is no CT window. 3394 */ 3395 struct iwm_mac_data_p2p_sta { 3396 struct iwm_mac_data_sta sta; 3397 uint32_t ctwin; 3398 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3399 3400 /** 3401 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3402 * @stats_interval: interval in TU between statistics notifications to host. 3403 */ 3404 struct iwm_mac_data_pibss { 3405 uint32_t stats_interval; 3406 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3407 3408 /* 3409 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3410 * context. 3411 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3412 * other channels as well. This should be to true only in case that the 3413 * device is discoverable and there is an active GO. Note that setting this 3414 * field when not needed, will increase the number of interrupts and have 3415 * effect on the platform power, as this setting opens the Rx filters on 3416 * all macs. 3417 */ 3418 struct iwm_mac_data_p2p_dev { 3419 uint32_t is_disc_extended; 3420 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3421 3422 /** 3423 * enum iwm_mac_filter_flags - MAC context filter flags 3424 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3425 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3426 * control frames to the host 3427 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3428 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3429 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3430 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3431 * (in station mode when associated) 3432 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3433 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3434 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3435 */ 3436 enum iwm_mac_filter_flags { 3437 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3438 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3439 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3440 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3441 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3442 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3443 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3444 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3445 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3446 }; 3447 3448 /** 3449 * enum iwm_mac_qos_flags - QoS flags 3450 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3451 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3452 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3453 * 3454 */ 3455 enum iwm_mac_qos_flags { 3456 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3457 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3458 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3459 }; 3460 3461 /** 3462 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3463 * @cw_min: Contention window, start value in numbers of slots. 3464 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3465 * @cw_max: Contention window, max value in numbers of slots. 3466 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3467 * @aifsn: Number of slots in Arbitration Interframe Space (before 3468 * performing random backoff timing prior to Tx). Device default 1. 3469 * @fifos_mask: FIFOs used by this MAC for this AC 3470 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3471 * 3472 * One instance of this config struct for each of 4 EDCA access categories 3473 * in struct iwm_qosparam_cmd. 3474 * 3475 * Device will automatically increase contention window by (2*CW) + 1 for each 3476 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3477 * value, to cap the CW value. 3478 */ 3479 struct iwm_ac_qos { 3480 uint16_t cw_min; 3481 uint16_t cw_max; 3482 uint8_t aifsn; 3483 uint8_t fifos_mask; 3484 uint16_t edca_txop; 3485 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3486 3487 /** 3488 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3489 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3490 * @id_and_color: ID and color of the MAC 3491 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3492 * @mac_type: one of IWM_FW_MAC_TYPE_* 3493 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3494 * @node_addr: MAC address 3495 * @bssid_addr: BSSID 3496 * @cck_rates: basic rates available for CCK 3497 * @ofdm_rates: basic rates available for OFDM 3498 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3499 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3500 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3501 * @filter_flags: combination of IWM_MAC_FILTER_* 3502 * @qos_flags: from IWM_MAC_QOS_FLG_* 3503 * @ac: one iwm_mac_qos configuration for each AC 3504 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3505 */ 3506 struct iwm_mac_ctx_cmd { 3507 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3508 uint32_t id_and_color; 3509 uint32_t action; 3510 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3511 uint32_t mac_type; 3512 uint32_t tsf_id; 3513 uint8_t node_addr[6]; 3514 uint16_t reserved_for_node_addr; 3515 uint8_t bssid_addr[6]; 3516 uint16_t reserved_for_bssid_addr; 3517 uint32_t cck_rates; 3518 uint32_t ofdm_rates; 3519 uint32_t protection_flags; 3520 uint32_t cck_short_preamble; 3521 uint32_t short_slot; 3522 uint32_t filter_flags; 3523 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3524 uint32_t qos_flags; 3525 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3526 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3527 union { 3528 struct iwm_mac_data_ap ap; 3529 struct iwm_mac_data_go go; 3530 struct iwm_mac_data_sta sta; 3531 struct iwm_mac_data_p2p_sta p2p_sta; 3532 struct iwm_mac_data_p2p_dev p2p_dev; 3533 struct iwm_mac_data_pibss pibss; 3534 struct iwm_mac_data_ibss ibss; 3535 }; 3536 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3537 3538 static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3539 { 3540 if (!v) 3541 return 0; 3542 return 0xFFFFFFFF / v; 3543 } 3544 3545 #define IWM_NONQOS_SEQ_GET 0x1 3546 #define IWM_NONQOS_SEQ_SET 0x2 3547 struct iwm_nonqos_seq_query_cmd { 3548 uint32_t get_set_flag; 3549 uint32_t mac_id_n_color; 3550 uint16_t value; 3551 uint16_t reserved; 3552 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3553 3554 /* Power Management Commands, Responses, Notifications */ 3555 3556 /* Radio LP RX Energy Threshold measured in dBm */ 3557 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3558 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3559 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3560 3561 /** 3562 * enum iwm_scan_flags - masks for power table command flags 3563 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3564 * receiver and transmitter. '0' - does not allow. 3565 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3566 * '1' Driver enables PM (use rest of parameters) 3567 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3568 * '1' PM could sleep over DTIM till listen Interval. 3569 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3570 * access categories are both delivery and trigger enabled. 3571 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3572 * PBW Snoozing enabled 3573 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3574 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3575 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3576 * detection enablement 3577 */ 3578 enum iwm_power_flags { 3579 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3580 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3581 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3582 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3583 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3584 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3585 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3586 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3587 }; 3588 3589 #define IWM_POWER_VEC_SIZE 5 3590 3591 /** 3592 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3593 * is used also with a new power API for device wide power settings. 3594 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3595 * 3596 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3597 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3598 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3599 * set regardless of power scheme or current power state. 3600 * FW use this value also when PM is disabled. 3601 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3602 * PSM transition - legacy PM 3603 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3604 * PSM transition - legacy PM 3605 * @sleep_interval: not in use 3606 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3607 * is set. For example, if it is required to skip over 3608 * one DTIM, this value need to be set to 2 (DTIM periods). 3609 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3610 * Default: 80dbm 3611 */ 3612 struct iwm_powertable_cmd { 3613 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3614 uint16_t flags; 3615 uint8_t keep_alive_seconds; 3616 uint8_t debug_flags; 3617 uint32_t rx_data_timeout; 3618 uint32_t tx_data_timeout; 3619 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3620 uint32_t skip_dtim_periods; 3621 uint32_t lprx_rssi_threshold; 3622 } __packed; 3623 3624 /** 3625 * enum iwm_device_power_flags - masks for device power command flags 3626 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3627 * receiver and transmitter. '0' - does not allow. This flag should be 3628 * always set to '1' unless one need to disable actual power down for debug 3629 * purposes. 3630 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning 3631 * that power management is disabled. '0' Power management is enabled, one 3632 * of power schemes is applied. 3633 */ 3634 enum iwm_device_power_flags { 3635 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3636 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13), 3637 }; 3638 3639 /** 3640 * struct iwm_device_power_cmd - device wide power command. 3641 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3642 * 3643 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3644 */ 3645 struct iwm_device_power_cmd { 3646 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3647 uint16_t flags; 3648 uint16_t reserved; 3649 } __packed; 3650 3651 /** 3652 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3653 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3654 * @id_and_color: MAC contex identifier 3655 * @flags: Power table command flags from POWER_FLAGS_* 3656 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3657 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3658 * set regardless of power scheme or current power state. 3659 * FW use this value also when PM is disabled. 3660 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3661 * PSM transition - legacy PM 3662 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3663 * PSM transition - legacy PM 3664 * @sleep_interval: not in use 3665 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3666 * is set. For example, if it is required to skip over 3667 * one DTIM, this value need to be set to 2 (DTIM periods). 3668 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3669 * PSM transition - uAPSD 3670 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3671 * PSM transition - uAPSD 3672 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3673 * Default: 80dbm 3674 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3675 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3676 * from the AP [msec] 3677 * @snooze_window: A window of time in which PBW snoozing insures that all 3678 * packets received. It is also the minimum time from last 3679 * received unicast RX packet, before client stops snoozing 3680 * for data. [msec] 3681 * @snooze_step: TBD 3682 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3683 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3684 * each corresponding AC. 3685 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3686 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3687 * values. 3688 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3689 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3690 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3691 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3692 * @limited_ps_threshold: 3693 */ 3694 struct iwm_mac_power_cmd { 3695 /* CONTEXT_DESC_API_T_VER_1 */ 3696 uint32_t id_and_color; 3697 3698 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3699 uint16_t flags; 3700 uint16_t keep_alive_seconds; 3701 uint32_t rx_data_timeout; 3702 uint32_t tx_data_timeout; 3703 uint32_t rx_data_timeout_uapsd; 3704 uint32_t tx_data_timeout_uapsd; 3705 uint8_t lprx_rssi_threshold; 3706 uint8_t skip_dtim_periods; 3707 uint16_t snooze_interval; 3708 uint16_t snooze_window; 3709 uint8_t snooze_step; 3710 uint8_t qndp_tid; 3711 uint8_t uapsd_ac_flags; 3712 uint8_t uapsd_max_sp; 3713 uint8_t heavy_tx_thld_packets; 3714 uint8_t heavy_rx_thld_packets; 3715 uint8_t heavy_tx_thld_percentage; 3716 uint8_t heavy_rx_thld_percentage; 3717 uint8_t limited_ps_threshold; 3718 uint8_t reserved; 3719 } __packed; 3720 3721 /* 3722 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3723 * associated AP is identified as improperly implementing uAPSD protocol. 3724 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3725 * @sta_id: index of station in uCode's station table - associated AP ID in 3726 * this context. 3727 */ 3728 struct iwm_uapsd_misbehaving_ap_notif { 3729 uint32_t sta_id; 3730 uint8_t mac_id; 3731 uint8_t reserved[3]; 3732 } __packed; 3733 3734 /** 3735 * struct iwm_beacon_filter_cmd 3736 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3737 * @id_and_color: MAC contex identifier 3738 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3739 * to driver if delta in Energy values calculated for this and last 3740 * passed beacon is greater than this threshold. Zero value means that 3741 * the Energy change is ignored for beacon filtering, and beacon will 3742 * not be forced to be sent to driver regardless of this delta. Typical 3743 * energy delta 5dB. 3744 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3745 * Send beacon to driver if delta in Energy values calculated for this 3746 * and last passed beacon is greater than this threshold. Zero value 3747 * means that the Energy change is ignored for beacon filtering while in 3748 * Roaming state, typical energy delta 1dB. 3749 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3750 * calculated for current beacon is less than the threshold, use 3751 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3752 * Threshold. Typical energy threshold is -72dBm. 3753 * @bf_temp_threshold: This threshold determines the type of temperature 3754 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3755 * If the current temperature is above this threshold - Fast filter 3756 * will be used, If the current temperature is below this threshold - 3757 * Slow filter will be used. 3758 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3759 * calculated for this and the last passed beacon is greater than this 3760 * threshold. Zero value means that the temperature change is ignored for 3761 * beacon filtering; beacons will not be forced to be sent to driver 3762 * regardless of whether its temperature has been changed. 3763 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3764 * calculated for this and the last passed beacon is greater than this 3765 * threshold. Zero value means that the temperature change is ignored for 3766 * beacon filtering; beacons will not be forced to be sent to driver 3767 * regardless of whether its temperature has been changed. 3768 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3769 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3770 * for a specific period of time. Units: Beacons. 3771 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3772 * for a longer period of time then this escape-timeout. Units: Beacons. 3773 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3774 */ 3775 struct iwm_beacon_filter_cmd { 3776 uint32_t bf_energy_delta; 3777 uint32_t bf_roaming_energy_delta; 3778 uint32_t bf_roaming_state; 3779 uint32_t bf_temp_threshold; 3780 uint32_t bf_temp_fast_filter; 3781 uint32_t bf_temp_slow_filter; 3782 uint32_t bf_enable_beacon_filter; 3783 uint32_t bf_debug_flag; 3784 uint32_t bf_escape_timer; 3785 uint32_t ba_escape_timer; 3786 uint32_t ba_enable_beacon_abort; 3787 } __packed; 3788 3789 /* Beacon filtering and beacon abort */ 3790 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3791 #define IWM_BF_ENERGY_DELTA_MAX 255 3792 #define IWM_BF_ENERGY_DELTA_MIN 0 3793 3794 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3795 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3796 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3797 3798 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3799 #define IWM_BF_ROAMING_STATE_MAX 255 3800 #define IWM_BF_ROAMING_STATE_MIN 0 3801 3802 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3803 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3804 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3805 3806 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3807 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3808 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3809 3810 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3811 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3812 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3813 3814 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3815 3816 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3817 3818 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3819 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3820 #define IWM_BF_ESCAPE_TIMER_MIN 0 3821 3822 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3823 #define IWM_BA_ESCAPE_TIMER_D3 9 3824 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3825 #define IWM_BA_ESCAPE_TIMER_MIN 0 3826 3827 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3828 3829 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3830 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3831 .bf_roaming_energy_delta = \ 3832 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3833 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3834 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3835 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3836 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3837 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3838 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3839 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3840 3841 /* 3842 * These serve as indexes into 3843 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3844 * TODO: avoid overlap between legacy and HT rates 3845 */ 3846 enum { 3847 IWM_RATE_1M_INDEX = 0, 3848 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3849 IWM_RATE_2M_INDEX, 3850 IWM_RATE_5M_INDEX, 3851 IWM_RATE_11M_INDEX, 3852 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3853 IWM_RATE_6M_INDEX, 3854 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3855 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3856 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3857 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3858 IWM_RATE_9M_INDEX, 3859 IWM_RATE_12M_INDEX, 3860 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3861 IWM_RATE_18M_INDEX, 3862 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3863 IWM_RATE_24M_INDEX, 3864 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3865 IWM_RATE_36M_INDEX, 3866 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3867 IWM_RATE_48M_INDEX, 3868 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3869 IWM_RATE_54M_INDEX, 3870 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3871 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3872 IWM_RATE_60M_INDEX, 3873 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3874 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3875 IWM_RATE_MCS_8_INDEX, 3876 IWM_RATE_MCS_9_INDEX, 3877 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3878 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3879 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3880 }; 3881 3882 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3883 3884 /* fw API values for legacy bit rates, both OFDM and CCK */ 3885 enum { 3886 IWM_RATE_6M_PLCP = 13, 3887 IWM_RATE_9M_PLCP = 15, 3888 IWM_RATE_12M_PLCP = 5, 3889 IWM_RATE_18M_PLCP = 7, 3890 IWM_RATE_24M_PLCP = 9, 3891 IWM_RATE_36M_PLCP = 11, 3892 IWM_RATE_48M_PLCP = 1, 3893 IWM_RATE_54M_PLCP = 3, 3894 IWM_RATE_1M_PLCP = 10, 3895 IWM_RATE_2M_PLCP = 20, 3896 IWM_RATE_5M_PLCP = 55, 3897 IWM_RATE_11M_PLCP = 110, 3898 IWM_RATE_INVM_PLCP = -1, 3899 }; 3900 3901 /* 3902 * rate_n_flags bit fields 3903 * 3904 * The 32-bit value has different layouts in the low 8 bites depending on the 3905 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3906 * for CCK and OFDM). 3907 * 3908 * High-throughput (HT) rate format 3909 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3910 * Very High-throughput (VHT) rate format 3911 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3912 * Legacy OFDM rate format for bits 7:0 3913 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3914 * Legacy CCK rate format for bits 7:0: 3915 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3916 */ 3917 3918 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3919 #define IWM_RATE_MCS_HT_POS 8 3920 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3921 3922 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3923 #define IWM_RATE_MCS_CCK_POS 9 3924 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3925 3926 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3927 #define IWM_RATE_MCS_VHT_POS 26 3928 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3929 3930 3931 /* 3932 * High-throughput (HT) rate format for bits 7:0 3933 * 3934 * 2-0: MCS rate base 3935 * 0) 6 Mbps 3936 * 1) 12 Mbps 3937 * 2) 18 Mbps 3938 * 3) 24 Mbps 3939 * 4) 36 Mbps 3940 * 5) 48 Mbps 3941 * 6) 54 Mbps 3942 * 7) 60 Mbps 3943 * 4-3: 0) Single stream (SISO) 3944 * 1) Dual stream (MIMO) 3945 * 2) Triple stream (MIMO) 3946 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3947 * (bits 7-6 are zero) 3948 * 3949 * Together the low 5 bits work out to the MCS index because we don't 3950 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3951 * streams and 16-23 have three streams. We could also support MCS 32 3952 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3953 */ 3954 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3955 #define IWM_RATE_HT_MCS_NSS_POS 3 3956 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3957 3958 /* Bit 10: (1) Use Green Field preamble */ 3959 #define IWM_RATE_HT_MCS_GF_POS 10 3960 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3961 3962 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3963 3964 /* 3965 * Very High-throughput (VHT) rate format for bits 7:0 3966 * 3967 * 3-0: VHT MCS (0-9) 3968 * 5-4: number of streams - 1: 3969 * 0) Single stream (SISO) 3970 * 1) Dual stream (MIMO) 3971 * 2) Triple stream (MIMO) 3972 */ 3973 3974 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3975 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3976 #define IWM_RATE_VHT_MCS_NSS_POS 4 3977 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3978 3979 /* 3980 * Legacy OFDM rate format for bits 7:0 3981 * 3982 * 3-0: 0xD) 6 Mbps 3983 * 0xF) 9 Mbps 3984 * 0x5) 12 Mbps 3985 * 0x7) 18 Mbps 3986 * 0x9) 24 Mbps 3987 * 0xB) 36 Mbps 3988 * 0x1) 48 Mbps 3989 * 0x3) 54 Mbps 3990 * (bits 7-4 are 0) 3991 * 3992 * Legacy CCK rate format for bits 7:0: 3993 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3994 * 3995 * 6-0: 10) 1 Mbps 3996 * 20) 2 Mbps 3997 * 55) 5.5 Mbps 3998 * 110) 11 Mbps 3999 * (bit 7 is 0) 4000 */ 4001 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4002 4003 4004 /* 4005 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4006 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4007 */ 4008 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4009 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4010 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4011 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4012 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4013 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4014 4015 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4016 #define IWM_RATE_MCS_SGI_POS 13 4017 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4018 4019 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4020 #define IWM_RATE_MCS_ANT_POS 14 4021 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4022 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4023 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4024 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4025 IWM_RATE_MCS_ANT_B_MSK) 4026 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4027 IWM_RATE_MCS_ANT_C_MSK) 4028 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4029 #define IWM_RATE_MCS_ANT_NUM 3 4030 4031 /* Bit 17-18: (0) SS, (1) SS*2 */ 4032 #define IWM_RATE_MCS_STBC_POS 17 4033 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4034 4035 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4036 #define IWM_RATE_MCS_BF_POS 19 4037 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4038 4039 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4040 #define IWM_RATE_MCS_ZLF_POS 20 4041 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4042 4043 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4044 #define IWM_RATE_MCS_DUP_POS 24 4045 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4046 4047 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4048 #define IWM_RATE_MCS_LDPC_POS 27 4049 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4050 4051 4052 /* Link Quality definitions */ 4053 4054 /* # entries in rate scale table to support Tx retries */ 4055 #define IWM_LQ_MAX_RETRY_NUM 16 4056 4057 /* Link quality command flags bit fields */ 4058 4059 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4060 #define IWM_LQ_FLAG_USE_RTS_POS 0 4061 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4062 4063 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4064 #define IWM_LQ_FLAG_COLOR_POS 1 4065 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4066 4067 /* Bit 4-5: Tx RTS BW Signalling 4068 * (0) No RTS BW signalling 4069 * (1) Static BW signalling 4070 * (2) Dynamic BW signalling 4071 */ 4072 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4073 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4074 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4075 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4076 4077 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4078 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4079 */ 4080 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4081 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4082 4083 /** 4084 * struct iwm_lq_cmd - link quality command 4085 * @sta_id: station to update 4086 * @control: not used 4087 * @flags: combination of IWM_LQ_FLAG_* 4088 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4089 * and SISO rates 4090 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4091 * Should be ANT_[ABC] 4092 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4093 * @initial_rate_index: first index from rs_table per AC category 4094 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4095 * value of 100 is one usec. Range is 100 to 8000 4096 * @agg_disable_start_th: try-count threshold for starting aggregation. 4097 * If a frame has higher try-count, it should not be selected for 4098 * starting an aggregation sequence. 4099 * @agg_frame_cnt_limit: max frame count in an aggregation. 4100 * 0: no limit 4101 * 1: no aggregation (one frame per aggregation) 4102 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4103 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4104 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4105 * @bf_params: beam forming params, currently not used 4106 */ 4107 struct iwm_lq_cmd { 4108 uint8_t sta_id; 4109 uint8_t reserved1; 4110 uint16_t control; 4111 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4112 uint8_t flags; 4113 uint8_t mimo_delim; 4114 uint8_t single_stream_ant_msk; 4115 uint8_t dual_stream_ant_msk; 4116 uint8_t initial_rate_index[IWM_AC_NUM]; 4117 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4118 uint16_t agg_time_limit; 4119 uint8_t agg_disable_start_th; 4120 uint8_t agg_frame_cnt_limit; 4121 uint32_t reserved2; 4122 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4123 uint32_t bf_params; 4124 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4125 4126 /** 4127 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4128 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4129 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4130 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4131 * Otherwise, use rate_n_flags from the TX command 4132 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4133 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4134 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4135 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4136 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4137 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4138 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4139 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4140 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4141 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4142 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4143 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4144 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4145 * Should be set for beacons and probe responses 4146 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4147 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4148 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4149 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4150 * Should be set for 26/30 length MAC headers 4151 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4152 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4153 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4154 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4155 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4156 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4157 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4158 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4159 */ 4160 enum iwm_tx_flags { 4161 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4162 IWM_TX_CMD_FLG_ACK = (1 << 3), 4163 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4164 IWM_TX_CMD_FLG_BA = (1 << 5), 4165 IWM_TX_CMD_FLG_BAR = (1 << 6), 4166 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4167 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4168 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4169 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4170 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4171 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4172 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4173 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4174 IWM_TX_CMD_FLG_TSF = (1 << 16), 4175 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4176 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4177 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4178 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4179 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4180 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22), 4181 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4182 IWM_TX_CMD_FLG_DUR = (1 << 25), 4183 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4184 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4185 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4186 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4187 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4188 4189 /** 4190 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4191 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4192 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4193 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4194 */ 4195 enum iwm_tx_pm_timeouts { 4196 IWM_PM_FRAME_NONE = 0, 4197 IWM_PM_FRAME_MGMT = 2, 4198 IWM_PM_FRAME_ASSOC = 3, 4199 }; 4200 4201 /* 4202 * TX command security control 4203 */ 4204 #define IWM_TX_CMD_SEC_WEP 0x01 4205 #define IWM_TX_CMD_SEC_CCM 0x02 4206 #define IWM_TX_CMD_SEC_TKIP 0x03 4207 #define IWM_TX_CMD_SEC_EXT 0x04 4208 #define IWM_TX_CMD_SEC_MSK 0x07 4209 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4210 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4211 #define IWM_TX_CMD_SEC_KEY128 0x08 4212 4213 /* TODO: how does these values are OK with only 16 bit variable??? */ 4214 /* 4215 * TX command next frame info 4216 * 4217 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4218 * bit 3 - immediate ACK required 4219 * bit 4 - rate is taken from STA table 4220 * bit 5 - frame belongs to BA stream 4221 * bit 6 - immediate BA response expected 4222 * bit 7 - unused 4223 * bits 8:15 - Station ID 4224 * bits 16:31 - rate 4225 */ 4226 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4227 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4228 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4229 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4230 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4231 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4232 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4233 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4234 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4235 4236 /* 4237 * TX command Frame life time in us - to be written in pm_frame_timeout 4238 */ 4239 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4240 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4241 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4242 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4243 4244 /* 4245 * TID for non QoS frames - to be written in tid_tspec 4246 */ 4247 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4248 4249 /* 4250 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4251 */ 4252 #define IWM_DEFAULT_TX_RETRY 15 4253 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4254 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4255 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4256 #define IWM_LOW_RETRY_LIMIT 7 4257 4258 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4259 /** 4260 * struct iwm_tx_cmd - TX command struct to FW 4261 * ( IWM_TX_CMD = 0x1c ) 4262 * @len: in bytes of the payload, see below for details 4263 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4264 * Used for fragmentation and bursting, but not in 11n aggregation. 4265 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4266 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4267 * cleared. Combination of IWM_RATE_MCS_* 4268 * @sta_id: index of destination station in FW station table 4269 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4270 * @initial_rate_index: index into the rate table for initial TX attempt. 4271 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4272 * @key: security key 4273 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4274 * @life_time: frame life time (usecs??) 4275 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4276 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4277 * @dram_msb_ptr: upper bits of the scratch physical address 4278 * @rts_retry_limit: max attempts for RTS 4279 * @data_retry_limit: max attempts to send the data packet 4280 * @tid_spec: TID/tspec 4281 * @pm_frame_timeout: PM TX frame timeout 4282 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4283 * specified by HCCA protocol 4284 * 4285 * The byte count (both len and next_frame_len) includes MAC header 4286 * (24/26/30/32 bytes) 4287 * + 2 bytes pad if 26/30 header size 4288 * + 8 byte IV for CCM or TKIP (not used for WEP) 4289 * + Data payload 4290 * + 8-byte MIC (not used for CCM/WEP) 4291 * It does not include post-MAC padding, i.e., 4292 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4293 * Range of len: 14-2342 bytes. 4294 * 4295 * After the struct fields the MAC header is placed, plus any padding, 4296 * and then the actial payload. 4297 */ 4298 struct iwm_tx_cmd { 4299 uint16_t len; 4300 uint16_t next_frame_len; 4301 uint32_t tx_flags; 4302 struct { 4303 uint8_t try_cnt; 4304 uint8_t btkill_cnt; 4305 uint16_t reserved; 4306 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4307 uint32_t rate_n_flags; 4308 uint8_t sta_id; 4309 uint8_t sec_ctl; 4310 uint8_t initial_rate_index; 4311 uint8_t reserved2; 4312 uint8_t key[16]; 4313 uint16_t next_frame_flags; 4314 uint16_t reserved3; 4315 uint32_t life_time; 4316 uint32_t dram_lsb_ptr; 4317 uint8_t dram_msb_ptr; 4318 uint8_t rts_retry_limit; 4319 uint8_t data_retry_limit; 4320 uint8_t tid_tspec; 4321 uint16_t pm_frame_timeout; 4322 uint16_t driver_txop; 4323 uint8_t payload[0]; 4324 struct ieee80211_frame hdr[0]; 4325 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4326 4327 /* 4328 * TX response related data 4329 */ 4330 4331 /* 4332 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4333 * @IWM_TX_STATUS_SUCCESS: 4334 * @IWM_TX_STATUS_DIRECT_DONE: 4335 * @IWM_TX_STATUS_POSTPONE_DELAY: 4336 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4337 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4338 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4339 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4340 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4341 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4342 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4343 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4344 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4345 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4346 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4347 * @IWM_TX_STATUS_FAIL_DEST_PS: 4348 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4349 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4350 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4351 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4352 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4353 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4354 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4355 * @IWM_TX_STATUS_FAIL_FW_DROP: 4356 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4357 * STA table 4358 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4359 * @IWM_TX_MODE_MSK: 4360 * @IWM_TX_MODE_NO_BURST: 4361 * @IWM_TX_MODE_IN_BURST_SEQ: 4362 * @IWM_TX_MODE_FIRST_IN_BURST: 4363 * @IWM_TX_QUEUE_NUM_MSK: 4364 * 4365 * Valid only if frame_count =1 4366 * TODO: complete documentation 4367 */ 4368 enum iwm_tx_status { 4369 IWM_TX_STATUS_MSK = 0x000000ff, 4370 IWM_TX_STATUS_SUCCESS = 0x01, 4371 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4372 /* postpone TX */ 4373 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4374 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4375 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4376 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4377 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4378 /* abort TX */ 4379 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4380 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4381 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4382 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4383 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4384 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4385 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4386 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4387 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4388 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4389 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4390 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4391 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4392 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4393 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4394 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4395 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4396 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4397 IWM_TX_MODE_MSK = 0x00000f00, 4398 IWM_TX_MODE_NO_BURST = 0x00000000, 4399 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4400 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4401 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4402 IWM_TX_NARROW_BW_MSK = 0x00060000, 4403 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4404 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4405 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4406 }; 4407 4408 /* 4409 * enum iwm_tx_agg_status - TX aggregation status 4410 * @IWM_AGG_TX_STATE_STATUS_MSK: 4411 * @IWM_AGG_TX_STATE_TRANSMITTED: 4412 * @IWM_AGG_TX_STATE_UNDERRUN: 4413 * @IWM_AGG_TX_STATE_BT_PRIO: 4414 * @IWM_AGG_TX_STATE_FEW_BYTES: 4415 * @IWM_AGG_TX_STATE_ABORT: 4416 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4417 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4418 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4419 * @IWM_AGG_TX_STATE_SCD_QUERY: 4420 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4421 * @IWM_AGG_TX_STATE_RESPONSE: 4422 * @IWM_AGG_TX_STATE_DUMP_TX: 4423 * @IWM_AGG_TX_STATE_DELAY_TX: 4424 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4425 * occur if tx failed for this frame when it was a member of a previous 4426 * aggregation block). If rate scaling is used, retry count indicates the 4427 * rate table entry used for all frames in the new agg. 4428 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4429 * this frame 4430 * 4431 * TODO: complete documentation 4432 */ 4433 enum iwm_tx_agg_status { 4434 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4435 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4436 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4437 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4438 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4439 IWM_AGG_TX_STATE_ABORT = 0x008, 4440 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4441 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4442 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4443 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4444 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4445 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4446 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4447 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4448 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4449 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4450 }; 4451 4452 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4453 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4454 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4455 4456 /* 4457 * The mask below describes a status where we are absolutely sure that the MPDU 4458 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4459 * written the bytes to the TXE, but we know nothing about what the DSP did. 4460 */ 4461 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4462 IWM_AGG_TX_STATE_ABORT | \ 4463 IWM_AGG_TX_STATE_SCD_QUERY) 4464 4465 /* 4466 * IWM_REPLY_TX = 0x1c (response) 4467 * 4468 * This response may be in one of two slightly different formats, indicated 4469 * by the frame_count field: 4470 * 4471 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4472 * frame. Multiple attempts, at various bit rates, may have been made for 4473 * this frame. 4474 * 4475 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4476 * frames that used block-acknowledge. All frames were transmitted at 4477 * same rate. Rate scaling may have been used if first frame in this new 4478 * agg block failed in previous agg block(s). 4479 * 4480 * Note that, for aggregation, ACK (block-ack) status is not delivered 4481 * here; block-ack has not been received by the time the device records 4482 * this status. 4483 * This status relates to reasons the tx might have been blocked or aborted 4484 * within the device, rather than whether it was received successfully by 4485 * the destination station. 4486 */ 4487 4488 /** 4489 * struct iwm_agg_tx_status - per packet TX aggregation status 4490 * @status: enum iwm_tx_agg_status 4491 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4492 */ 4493 struct iwm_agg_tx_status { 4494 uint16_t status; 4495 uint16_t sequence; 4496 } __packed; 4497 4498 /* 4499 * definitions for initial rate index field 4500 * bits [3:0] initial rate index 4501 * bits [6:4] rate table color, used for the initial rate 4502 * bit-7 invalid rate indication 4503 */ 4504 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4505 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4506 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4507 4508 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4509 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4510 4511 /** 4512 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4513 * ( IWM_REPLY_TX = 0x1c ) 4514 * @frame_count: 1 no aggregation, >1 aggregation 4515 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4516 * @failure_rts: num of failures due to unsuccessful RTS 4517 * @failure_frame: num failures due to no ACK (unused for agg) 4518 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4519 * Tx of all the batch. IWM_RATE_MCS_* 4520 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4521 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4522 * in usec. 4523 * @pa_status: tx power info 4524 * @pa_integ_res_a: tx power info 4525 * @pa_integ_res_b: tx power info 4526 * @pa_integ_res_c: tx power info 4527 * @measurement_req_id: tx power info 4528 * @tfd_info: TFD information set by the FH 4529 * @seq_ctl: sequence control from the Tx cmd 4530 * @byte_cnt: byte count from the Tx cmd 4531 * @tlc_info: TLC rate info 4532 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4533 * @frame_ctrl: frame control 4534 * @status: for non-agg: frame status IWM_TX_STATUS_* 4535 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4536 * follow this one, up to frame_count. 4537 * 4538 * After the array of statuses comes the SSN of the SCD. Look at 4539 * %iwm_mvm_get_scd_ssn for more details. 4540 */ 4541 struct iwm_mvm_tx_resp { 4542 uint8_t frame_count; 4543 uint8_t bt_kill_count; 4544 uint8_t failure_rts; 4545 uint8_t failure_frame; 4546 uint32_t initial_rate; 4547 uint16_t wireless_media_time; 4548 4549 uint8_t pa_status; 4550 uint8_t pa_integ_res_a[3]; 4551 uint8_t pa_integ_res_b[3]; 4552 uint8_t pa_integ_res_c[3]; 4553 uint16_t measurement_req_id; 4554 uint16_t reserved; 4555 4556 uint32_t tfd_info; 4557 uint16_t seq_ctl; 4558 uint16_t byte_cnt; 4559 uint8_t tlc_info; 4560 uint8_t ra_tid; 4561 uint16_t frame_ctrl; 4562 4563 struct iwm_agg_tx_status status; 4564 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4565 4566 /** 4567 * struct iwm_mvm_ba_notif - notifies about reception of BA 4568 * ( IWM_BA_NOTIF = 0xc5 ) 4569 * @sta_addr_lo32: lower 32 bits of the MAC address 4570 * @sta_addr_hi16: upper 16 bits of the MAC address 4571 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4572 * @tid: tid of the session 4573 * @seq_ctl: 4574 * @bitmap: the bitmap of the BA notification as seen in the air 4575 * @scd_flow: the tx queue this BA relates to 4576 * @scd_ssn: the index of the last contiguously sent packet 4577 * @txed: number of Txed frames in this batch 4578 * @txed_2_done: number of Acked frames in this batch 4579 */ 4580 struct iwm_mvm_ba_notif { 4581 uint32_t sta_addr_lo32; 4582 uint16_t sta_addr_hi16; 4583 uint16_t reserved; 4584 4585 uint8_t sta_id; 4586 uint8_t tid; 4587 uint16_t seq_ctl; 4588 uint64_t bitmap; 4589 uint16_t scd_flow; 4590 uint16_t scd_ssn; 4591 uint8_t txed; 4592 uint8_t txed_2_done; 4593 uint16_t reserved1; 4594 } __packed; 4595 4596 /* 4597 * struct iwm_mac_beacon_cmd - beacon template command 4598 * @tx: the tx commands associated with the beacon frame 4599 * @template_id: currently equal to the mac context id of the coresponding 4600 * mac. 4601 * @tim_idx: the offset of the tim IE in the beacon 4602 * @tim_size: the length of the tim IE 4603 * @frame: the template of the beacon frame 4604 */ 4605 struct iwm_mac_beacon_cmd { 4606 struct iwm_tx_cmd tx; 4607 uint32_t template_id; 4608 uint32_t tim_idx; 4609 uint32_t tim_size; 4610 struct ieee80211_frame frame[0]; 4611 } __packed; 4612 4613 struct iwm_beacon_notif { 4614 struct iwm_mvm_tx_resp beacon_notify_hdr; 4615 uint64_t tsf; 4616 uint32_t ibss_mgr_status; 4617 } __packed; 4618 4619 /** 4620 * enum iwm_dump_control - dump (flush) control flags 4621 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4622 * and the TFD queues are empty. 4623 */ 4624 enum iwm_dump_control { 4625 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4626 }; 4627 4628 /** 4629 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4630 * @queues_ctl: bitmap of queues to flush 4631 * @flush_ctl: control flags 4632 * @reserved: reserved 4633 */ 4634 struct iwm_tx_path_flush_cmd { 4635 uint32_t queues_ctl; 4636 uint16_t flush_ctl; 4637 uint16_t reserved; 4638 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4639 4640 /** 4641 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4642 * @tx_resp: the Tx response from the fw (agg or non-agg) 4643 * 4644 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4645 * it can't know that everything will go well until the end of the AMPDU, it 4646 * can't know in advance the number of MPDUs that will be sent in the current 4647 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4648 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4649 * of the batch. This is why the SSN of the SCD is written at the end of the 4650 * whole struct at a variable offset. This function knows how to cope with the 4651 * variable offset and returns the SSN of the SCD. 4652 */ 4653 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4654 { 4655 return le32_to_cpup((uint32_t *)&tx_resp->status + 4656 tx_resp->frame_count) & 0xfff; 4657 } 4658 4659 /** 4660 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4661 * @token: 4662 * @sta_id: station id 4663 * @tid: 4664 * @scd_queue: scheduler queue to confiug 4665 * @enable: 1 queue enable, 0 queue disable 4666 * @aggregate: 1 aggregated queue, 0 otherwise 4667 * @tx_fifo: %enum iwm_mvm_tx_fifo 4668 * @window: BA window size 4669 * @ssn: SSN for the BA agreement 4670 */ 4671 struct iwm_scd_txq_cfg_cmd { 4672 uint8_t token; 4673 uint8_t sta_id; 4674 uint8_t tid; 4675 uint8_t scd_queue; 4676 uint8_t enable; 4677 uint8_t aggregate; 4678 uint8_t tx_fifo; 4679 uint8_t window; 4680 uint16_t ssn; 4681 uint16_t reserved; 4682 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4683 4684 /** 4685 * struct iwm_scd_txq_cfg_rsp 4686 * @token: taken from the command 4687 * @sta_id: station id from the command 4688 * @tid: tid from the command 4689 * @scd_queue: scd_queue from the command 4690 */ 4691 struct iwm_scd_txq_cfg_rsp { 4692 uint8_t token; 4693 uint8_t sta_id; 4694 uint8_t tid; 4695 uint8_t scd_queue; 4696 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4697 4698 4699 /* Scan Commands, Responses, Notifications */ 4700 4701 /* Max number of IEs for direct SSID scans in a command */ 4702 #define IWM_PROBE_OPTION_MAX 20 4703 4704 /** 4705 * struct iwm_ssid_ie - directed scan network information element 4706 * 4707 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4708 * selected by "type" bit field in struct iwm_scan_channel; 4709 * each channel may select different ssids from among the 20 entries. 4710 * SSID IEs get transmitted in reverse order of entry. 4711 */ 4712 struct iwm_ssid_ie { 4713 uint8_t id; 4714 uint8_t len; 4715 uint8_t ssid[IEEE80211_NWID_LEN]; 4716 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4717 4718 /* scan offload */ 4719 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4720 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4721 #define IWM_SCAN_MAX_PROFILES 11 4722 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4723 4724 /* Default watchdog (in MS) for scheduled scan iteration */ 4725 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4726 4727 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4728 #define IWM_CAN_ABORT_STATUS 1 4729 4730 #define IWM_FULL_SCAN_MULTIPLIER 5 4731 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4732 #define IWM_MAX_SCHED_SCAN_PLANS 2 4733 4734 /** 4735 * iwm_scan_schedule_lmac - schedule of scan offload 4736 * @delay: delay between iterations, in seconds. 4737 * @iterations: num of scan iterations 4738 * @full_scan_mul: number of partial scans before each full scan 4739 */ 4740 struct iwm_scan_schedule_lmac { 4741 uint16_t delay; 4742 uint8_t iterations; 4743 uint8_t full_scan_mul; 4744 } __packed; /* SCAN_SCHEDULE_API_S */ 4745 4746 /** 4747 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4748 * @tx_flags: combination of TX_CMD_FLG_* 4749 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4750 * cleared. Combination of RATE_MCS_* 4751 * @sta_id: index of destination station in FW station table 4752 * @reserved: for alignment and future use 4753 */ 4754 struct iwm_scan_req_tx_cmd { 4755 uint32_t tx_flags; 4756 uint32_t rate_n_flags; 4757 uint8_t sta_id; 4758 uint8_t reserved[3]; 4759 } __packed; 4760 4761 enum iwm_scan_channel_flags_lmac { 4762 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4763 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4764 }; 4765 4766 /** 4767 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4768 * @flags: bits 1-20: directed scan to i'th ssid 4769 * other bits &enum iwm_scan_channel_flags_lmac 4770 * @channel_number: channel number 1-13 etc 4771 * @iter_count: scan iteration on this channel 4772 * @iter_interval: interval in seconds between iterations on one channel 4773 */ 4774 struct iwm_scan_channel_cfg_lmac { 4775 uint32_t flags; 4776 uint16_t channel_num; 4777 uint16_t iter_count; 4778 uint32_t iter_interval; 4779 } __packed; 4780 4781 /* 4782 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4783 * @offset: offset in the data block 4784 * @len: length of the segment 4785 */ 4786 struct iwm_scan_probe_segment { 4787 uint16_t offset; 4788 uint16_t len; 4789 } __packed; 4790 4791 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4792 * @mac_header: first (and common) part of the probe 4793 * @band_data: band specific data 4794 * @common_data: last (and common) part of the probe 4795 * @buf: raw data block 4796 */ 4797 struct iwm_scan_probe_req { 4798 struct iwm_scan_probe_segment mac_header; 4799 struct iwm_scan_probe_segment band_data[2]; 4800 struct iwm_scan_probe_segment common_data; 4801 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4802 } __packed; 4803 4804 enum iwm_scan_channel_flags { 4805 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4806 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4807 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4808 }; 4809 4810 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4811 * @flags: enum iwm_scan_channel_flags 4812 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4813 * involved. 4814 * 1 - EBS is disabled. 4815 * 2 - every second scan will be full scan(and so on). 4816 */ 4817 struct iwm_scan_channel_opt { 4818 uint16_t flags; 4819 uint16_t non_ebs_ratio; 4820 } __packed; 4821 4822 /** 4823 * iwm_mvm_lmac_scan_flags 4824 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4825 * without filtering. 4826 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4827 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4828 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4829 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4830 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4831 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4832 * and DS parameter set IEs into probe requests. 4833 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4834 * 1, 6 and 11. 4835 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4836 */ 4837 enum iwm_mvm_lmac_scan_flags { 4838 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4839 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4840 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4841 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4842 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4843 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4844 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4845 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4846 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4847 }; 4848 4849 enum iwm_scan_priority { 4850 IWM_SCAN_PRIORITY_LOW, 4851 IWM_SCAN_PRIORITY_MEDIUM, 4852 IWM_SCAN_PRIORITY_HIGH, 4853 }; 4854 4855 /** 4856 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4857 * @reserved1: for alignment and future use 4858 * @channel_num: num of channels to scan 4859 * @active-dwell: dwell time for active channels 4860 * @passive-dwell: dwell time for passive channels 4861 * @fragmented-dwell: dwell time for fragmented passive scan 4862 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4863 * @reserved2: for alignment and future use 4864 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4865 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4866 * @max_out_time: max time (in TU) to be out of associated channel 4867 * @suspend_time: pause scan this long (TUs) when returning to service channel 4868 * @flags: RXON flags 4869 * @filter_flags: RXON filter 4870 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4871 * @direct_scan: list of SSIDs for directed active scan 4872 * @scan_prio: enum iwm_scan_priority 4873 * @iter_num: number of scan iterations 4874 * @delay: delay in seconds before first iteration 4875 * @schedule: two scheduling plans. The first one is finite, the second one can 4876 * be infinite. 4877 * @channel_opt: channel optimization options, for full and partial scan 4878 * @data: channel configuration and probe request packet. 4879 */ 4880 struct iwm_scan_req_lmac { 4881 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4882 uint32_t reserved1; 4883 uint8_t n_channels; 4884 uint8_t active_dwell; 4885 uint8_t passive_dwell; 4886 uint8_t fragmented_dwell; 4887 uint8_t extended_dwell; 4888 uint8_t reserved2; 4889 uint16_t rx_chain_select; 4890 uint32_t scan_flags; 4891 uint32_t max_out_time; 4892 uint32_t suspend_time; 4893 /* RX_ON_FLAGS_API_S_VER_1 */ 4894 uint32_t flags; 4895 uint32_t filter_flags; 4896 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4897 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4898 uint32_t scan_prio; 4899 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4900 uint32_t iter_num; 4901 uint32_t delay; 4902 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4903 struct iwm_scan_channel_opt channel_opt[2]; 4904 uint8_t data[]; 4905 } __packed; 4906 4907 /** 4908 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4909 * @last_schedule_line: last schedule line executed (fast or regular) 4910 * @last_schedule_iteration: last scan iteration executed before scan abort 4911 * @status: enum iwm_scan_offload_complete_status 4912 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4913 * @time_after_last_iter; time in seconds elapsed after last iteration 4914 */ 4915 struct iwm_periodic_scan_complete { 4916 uint8_t last_schedule_line; 4917 uint8_t last_schedule_iteration; 4918 uint8_t status; 4919 uint8_t ebs_status; 4920 uint32_t time_after_last_iter; 4921 uint32_t reserved; 4922 } __packed; 4923 4924 /* How many statistics are gathered for each channel */ 4925 #define IWM_SCAN_RESULTS_STATISTICS 1 4926 4927 /** 4928 * enum iwm_scan_complete_status - status codes for scan complete notifications 4929 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully 4930 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user 4931 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed 4932 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready 4933 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed 4934 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed 4935 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command 4936 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort 4937 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax 4938 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful 4939 * (not an error!) 4940 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver 4941 * asked for 4942 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events 4943 */ 4944 enum iwm_scan_complete_status { 4945 IWM_SCAN_COMP_STATUS_OK = 0x1, 4946 IWM_SCAN_COMP_STATUS_ABORT = 0x2, 4947 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3, 4948 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4, 4949 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5, 4950 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6, 4951 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7, 4952 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8, 4953 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9, 4954 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA, 4955 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B, 4956 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C, 4957 }; 4958 4959 /** 4960 * struct iwm_scan_results_notif - scan results for one channel 4961 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 ) 4962 * @channel: which channel the results are from 4963 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4964 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4965 * @num_probe_not_sent: # of request that weren't sent due to not enough time 4966 * @duration: duration spent in channel, in usecs 4967 * @statistics: statistics gathered for this channel 4968 */ 4969 struct iwm_scan_results_notif { 4970 uint8_t channel; 4971 uint8_t band; 4972 uint8_t probe_status; 4973 uint8_t num_probe_not_sent; 4974 uint32_t duration; 4975 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS]; 4976 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */ 4977 4978 enum iwm_scan_framework_client { 4979 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 4980 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 4981 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 4982 }; 4983 4984 /** 4985 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 4986 * @ssid: MAC address to filter out 4987 * @reported_rssi: AP rssi reported to the host 4988 * @client_bitmap: clients ignore this entry - enum scan_framework_client 4989 */ 4990 struct iwm_scan_offload_blacklist { 4991 uint8_t ssid[IEEE80211_ADDR_LEN]; 4992 uint8_t reported_rssi; 4993 uint8_t client_bitmap; 4994 } __packed; 4995 4996 enum iwm_scan_offload_network_type { 4997 IWM_NETWORK_TYPE_BSS = 1, 4998 IWM_NETWORK_TYPE_IBSS = 2, 4999 IWM_NETWORK_TYPE_ANY = 3, 5000 }; 5001 5002 enum iwm_scan_offload_band_selection { 5003 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5004 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5005 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5006 }; 5007 5008 /** 5009 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5010 * @ssid_index: index to ssid list in fixed part 5011 * @unicast_cipher: encryption olgorithm to match - bitmap 5012 * @aut_alg: authentication olgorithm to match - bitmap 5013 * @network_type: enum iwm_scan_offload_network_type 5014 * @band_selection: enum iwm_scan_offload_band_selection 5015 * @client_bitmap: clients waiting for match - enum scan_framework_client 5016 */ 5017 struct iwm_scan_offload_profile { 5018 uint8_t ssid_index; 5019 uint8_t unicast_cipher; 5020 uint8_t auth_alg; 5021 uint8_t network_type; 5022 uint8_t band_selection; 5023 uint8_t client_bitmap; 5024 uint8_t reserved[2]; 5025 } __packed; 5026 5027 /** 5028 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5029 * @blaclist: AP list to filter off from scan results 5030 * @profiles: profiles to search for match 5031 * @blacklist_len: length of blacklist 5032 * @num_profiles: num of profiles in the list 5033 * @match_notify: clients waiting for match found notification 5034 * @pass_match: clients waiting for the results 5035 * @active_clients: active clients bitmap - enum scan_framework_client 5036 * @any_beacon_notify: clients waiting for match notification without match 5037 */ 5038 struct iwm_scan_offload_profile_cfg { 5039 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5040 uint8_t blacklist_len; 5041 uint8_t num_profiles; 5042 uint8_t match_notify; 5043 uint8_t pass_match; 5044 uint8_t active_clients; 5045 uint8_t any_beacon_notify; 5046 uint8_t reserved[2]; 5047 } __packed; 5048 5049 enum iwm_scan_offload_complete_status { 5050 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5051 IWM_SCAN_OFFLOAD_ABORTED = 2, 5052 }; 5053 5054 /** 5055 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5056 * SCAN_COMPLETE_NTF_API_S_VER_3 5057 * @scanned_channels: number of channels scanned (and number of valid results) 5058 * @status: one of SCAN_COMP_STATUS_* 5059 * @bt_status: BT on/off status 5060 * @last_channel: last channel that was scanned 5061 * @tsf_low: TSF timer (lower half) in usecs 5062 * @tsf_high: TSF timer (higher half) in usecs 5063 * @results: an array of scan results, only "scanned_channels" of them are valid 5064 */ 5065 struct iwm_lmac_scan_complete_notif { 5066 uint8_t scanned_channels; 5067 uint8_t status; 5068 uint8_t bt_status; 5069 uint8_t last_channel; 5070 uint32_t tsf_low; 5071 uint32_t tsf_high; 5072 struct iwm_scan_results_notif results[]; 5073 } __packed; 5074 5075 5076 /* UMAC Scan API */ 5077 5078 /* The maximum of either of these cannot exceed 8, because we use an 5079 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5080 */ 5081 #define IWM_MVM_MAX_UMAC_SCANS 8 5082 #define IWM_MVM_MAX_LMAC_SCANS 1 5083 5084 enum iwm_scan_config_flags { 5085 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5086 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5087 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5088 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5089 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5090 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5091 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5092 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5093 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5094 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5095 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5096 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5097 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5098 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5099 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5100 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5101 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5102 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5103 5104 /* Bits 26-31 are for num of channels in channel_array */ 5105 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5106 }; 5107 5108 enum iwm_scan_config_rates { 5109 /* OFDM basic rates */ 5110 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5111 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5112 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5113 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5114 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5115 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5116 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5117 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5118 /* CCK basic rates */ 5119 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5120 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5121 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5122 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5123 5124 /* Bits 16-27 are for supported rates */ 5125 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5126 }; 5127 5128 enum iwm_channel_flags { 5129 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5130 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5131 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5132 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5133 }; 5134 5135 /** 5136 * struct iwm_scan_config 5137 * @flags: enum scan_config_flags 5138 * @tx_chains: valid_tx antenna - ANT_* definitions 5139 * @rx_chains: valid_rx antenna - ANT_* definitions 5140 * @legacy_rates: default legacy rates - enum scan_config_rates 5141 * @out_of_channel_time: default max out of serving channel time 5142 * @suspend_time: default max suspend time 5143 * @dwell_active: default dwell time for active scan 5144 * @dwell_passive: default dwell time for passive scan 5145 * @dwell_fragmented: default dwell time for fragmented scan 5146 * @dwell_extended: default dwell time for channels 1, 6 and 11 5147 * @mac_addr: default mac address to be used in probes 5148 * @bcast_sta_id: the index of the station in the fw 5149 * @channel_flags: default channel flags - enum iwm_channel_flags 5150 * scan_config_channel_flag 5151 * @channel_array: default supported channels 5152 */ 5153 struct iwm_scan_config { 5154 uint32_t flags; 5155 uint32_t tx_chains; 5156 uint32_t rx_chains; 5157 uint32_t legacy_rates; 5158 uint32_t out_of_channel_time; 5159 uint32_t suspend_time; 5160 uint8_t dwell_active; 5161 uint8_t dwell_passive; 5162 uint8_t dwell_fragmented; 5163 uint8_t dwell_extended; 5164 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5165 uint8_t bcast_sta_id; 5166 uint8_t channel_flags; 5167 uint8_t channel_array[]; 5168 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5169 5170 /** 5171 * iwm_umac_scan_flags 5172 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5173 * can be preempted by other scan requests with higher priority. 5174 * The low priority scan will be resumed when the higher proirity scan is 5175 * completed. 5176 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5177 * when scan starts. 5178 */ 5179 enum iwm_umac_scan_flags { 5180 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5181 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5182 }; 5183 5184 enum iwm_umac_scan_uid_offsets { 5185 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5186 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5187 }; 5188 5189 enum iwm_umac_scan_general_flags { 5190 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5191 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5192 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5193 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5194 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5195 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5196 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5197 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5198 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5199 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5200 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5201 }; 5202 5203 /** 5204 * struct iwm_scan_channel_cfg_umac 5205 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5206 * @channel_num: channel number 1-13 etc. 5207 * @iter_count: repetition count for the channel. 5208 * @iter_interval: interval between two scan iterations on one channel. 5209 */ 5210 struct iwm_scan_channel_cfg_umac { 5211 uint32_t flags; 5212 uint8_t channel_num; 5213 uint8_t iter_count; 5214 uint16_t iter_interval; 5215 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5216 5217 /** 5218 * struct iwm_scan_umac_schedule 5219 * @interval: interval in seconds between scan iterations 5220 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5221 * @reserved: for alignment and future use 5222 */ 5223 struct iwm_scan_umac_schedule { 5224 uint16_t interval; 5225 uint8_t iter_count; 5226 uint8_t reserved; 5227 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5228 5229 /** 5230 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5231 * parameters following channels configuration array. 5232 * @schedule: two scheduling plans. 5233 * @delay: delay in TUs before starting the first scan iteration 5234 * @reserved: for future use and alignment 5235 * @preq: probe request with IEs blocks 5236 * @direct_scan: list of SSIDs for directed active scan 5237 */ 5238 struct iwm_scan_req_umac_tail { 5239 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5240 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5241 uint16_t delay; 5242 uint16_t reserved; 5243 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5244 struct iwm_scan_probe_req preq; 5245 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5246 } __packed; 5247 5248 /** 5249 * struct iwm_scan_req_umac 5250 * @flags: &enum iwm_umac_scan_flags 5251 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5252 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5253 * @general_flags: &enum iwm_umac_scan_general_flags 5254 * @extended_dwell: dwell time for channels 1, 6 and 11 5255 * @active_dwell: dwell time for active scan 5256 * @passive_dwell: dwell time for passive scan 5257 * @fragmented_dwell: dwell time for fragmented passive scan 5258 * @max_out_time: max out of serving channel time 5259 * @suspend_time: max suspend time 5260 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5261 * @channel_flags: &enum iwm_scan_channel_flags 5262 * @n_channels: num of channels in scan request 5263 * @reserved: for future use and alignment 5264 * @data: &struct iwm_scan_channel_cfg_umac and 5265 * &struct iwm_scan_req_umac_tail 5266 */ 5267 struct iwm_scan_req_umac { 5268 uint32_t flags; 5269 uint32_t uid; 5270 uint32_t ooc_priority; 5271 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5272 uint32_t general_flags; 5273 uint8_t extended_dwell; 5274 uint8_t active_dwell; 5275 uint8_t passive_dwell; 5276 uint8_t fragmented_dwell; 5277 uint32_t max_out_time; 5278 uint32_t suspend_time; 5279 uint32_t scan_priority; 5280 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5281 uint8_t channel_flags; 5282 uint8_t n_channels; 5283 uint16_t reserved; 5284 uint8_t data[]; 5285 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5286 5287 /** 5288 * struct iwm_umac_scan_abort 5289 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5290 * @flags: reserved 5291 */ 5292 struct iwm_umac_scan_abort { 5293 uint32_t uid; 5294 uint32_t flags; 5295 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5296 5297 /** 5298 * struct iwm_umac_scan_complete 5299 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5300 * @last_schedule: last scheduling line 5301 * @last_iter: last scan iteration number 5302 * @scan status: &enum iwm_scan_offload_complete_status 5303 * @ebs_status: &enum iwm_scan_ebs_status 5304 * @time_from_last_iter: time elapsed from last iteration 5305 * @reserved: for future use 5306 */ 5307 struct iwm_umac_scan_complete { 5308 uint32_t uid; 5309 uint8_t last_schedule; 5310 uint8_t last_iter; 5311 uint8_t status; 5312 uint8_t ebs_status; 5313 uint32_t time_from_last_iter; 5314 uint32_t reserved; 5315 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5316 5317 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5318 /** 5319 * struct iwm_scan_offload_profile_match - match information 5320 * @bssid: matched bssid 5321 * @channel: channel where the match occurred 5322 * @energy: 5323 * @matching_feature: 5324 * @matching_channels: bitmap of channels that matched, referencing 5325 * the channels passed in tue scan offload request 5326 */ 5327 struct iwm_scan_offload_profile_match { 5328 uint8_t bssid[IEEE80211_ADDR_LEN]; 5329 uint16_t reserved; 5330 uint8_t channel; 5331 uint8_t energy; 5332 uint8_t matching_feature; 5333 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5334 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5335 5336 /** 5337 * struct iwm_scan_offload_profiles_query - match results query response 5338 * @matched_profiles: bitmap of matched profiles, referencing the 5339 * matches passed in the scan offload request 5340 * @last_scan_age: age of the last offloaded scan 5341 * @n_scans_done: number of offloaded scans done 5342 * @gp2_d0u: GP2 when D0U occurred 5343 * @gp2_invoked: GP2 when scan offload was invoked 5344 * @resume_while_scanning: not used 5345 * @self_recovery: obsolete 5346 * @reserved: reserved 5347 * @matches: array of match information, one for each match 5348 */ 5349 struct iwm_scan_offload_profiles_query { 5350 uint32_t matched_profiles; 5351 uint32_t last_scan_age; 5352 uint32_t n_scans_done; 5353 uint32_t gp2_d0u; 5354 uint32_t gp2_invoked; 5355 uint8_t resume_while_scanning; 5356 uint8_t self_recovery; 5357 uint16_t reserved; 5358 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5359 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5360 5361 /** 5362 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5363 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5364 * @scanned_channels: number of channels scanned and number of valid elements in 5365 * results array 5366 * @status: one of SCAN_COMP_STATUS_* 5367 * @bt_status: BT on/off status 5368 * @last_channel: last channel that was scanned 5369 * @tsf_low: TSF timer (lower half) in usecs 5370 * @tsf_high: TSF timer (higher half) in usecs 5371 * @results: array of scan results, only "scanned_channels" of them are valid 5372 */ 5373 struct iwm_umac_scan_iter_complete_notif { 5374 uint32_t uid; 5375 uint8_t scanned_channels; 5376 uint8_t status; 5377 uint8_t bt_status; 5378 uint8_t last_channel; 5379 uint32_t tsf_low; 5380 uint32_t tsf_high; 5381 struct iwm_scan_results_notif results[]; 5382 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5383 5384 /* Please keep this enum *SORTED* by hex value. 5385 * Needed for binary search, otherwise a warning will be triggered. 5386 */ 5387 enum iwm_scan_subcmd_ids { 5388 IWM_GSCAN_START_CMD = 0x0, 5389 IWM_GSCAN_STOP_CMD = 0x1, 5390 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5391 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5392 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5393 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5394 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5395 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5396 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5397 }; 5398 5399 /* STA API */ 5400 5401 /** 5402 * enum iwm_sta_flags - flags for the ADD_STA host command 5403 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5404 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5405 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5406 * @IWM_STA_FLG_PS: set if STA is in Power Save 5407 * @IWM_STA_FLG_INVALID: set if STA is invalid 5408 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5409 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5410 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5411 * @IWM_STA_FLG_PAN: STA is for PAN interface 5412 * @IWM_STA_FLG_CLASS_AUTH: 5413 * @IWM_STA_FLG_CLASS_ASSOC: 5414 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5415 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5416 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5417 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5418 * initialised by driver and can be updated by fw upon reception of 5419 * action frames that can change the channel width. When cleared the fw 5420 * will send all the frames in 20MHz even when FAT channel is requested. 5421 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5422 * driver and can be updated by fw upon reception of action frames. 5423 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5424 */ 5425 enum iwm_sta_flags { 5426 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5427 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5428 5429 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5430 5431 IWM_STA_FLG_PS = (1 << 8), 5432 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5433 IWM_STA_FLG_PAN = (1 << 13), 5434 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5435 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5436 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5437 5438 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5439 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5440 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5441 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5442 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5443 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5444 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5445 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5446 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5447 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5448 5449 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5450 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5451 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5452 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5453 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5454 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5455 5456 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5457 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5458 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5459 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5460 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5461 5462 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5463 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5464 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5465 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5466 }; 5467 5468 /** 5469 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5470 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5471 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5472 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5473 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5474 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5475 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5476 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5477 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5478 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5479 * station info array (1 - n 1X mode) 5480 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5481 * @IWM_STA_KEY_NOT_VALID: key is invalid 5482 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5483 * @IWM_STA_KEY_MULTICAST: set for multical key 5484 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5485 */ 5486 enum iwm_sta_key_flag { 5487 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5488 IWM_STA_KEY_FLG_WEP = (1 << 0), 5489 IWM_STA_KEY_FLG_CCM = (2 << 0), 5490 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5491 IWM_STA_KEY_FLG_EXT = (4 << 0), 5492 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5493 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5494 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5495 5496 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5497 IWM_STA_KEY_FLG_KEYID_POS = 8, 5498 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5499 IWM_STA_KEY_NOT_VALID = (1 << 11), 5500 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5501 IWM_STA_KEY_MULTICAST = (1 << 14), 5502 IWM_STA_KEY_MFP = (1 << 15), 5503 }; 5504 5505 /** 5506 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5507 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5508 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5509 * @IWM_STA_MODIFY_TX_RATE: unused 5510 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5511 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5512 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5513 * @IWM_STA_MODIFY_PROT_TH: 5514 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5515 */ 5516 enum iwm_sta_modify_flag { 5517 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5518 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5519 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5520 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5521 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5522 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5523 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5524 IWM_STA_MODIFY_QUEUES = (1 << 7), 5525 }; 5526 5527 #define IWM_STA_MODE_MODIFY 1 5528 5529 /** 5530 * enum iwm_sta_sleep_flag - type of sleep of the station 5531 * @IWM_STA_SLEEP_STATE_AWAKE: 5532 * @IWM_STA_SLEEP_STATE_PS_POLL: 5533 * @IWM_STA_SLEEP_STATE_UAPSD: 5534 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5535 * (last) released frame 5536 */ 5537 enum iwm_sta_sleep_flag { 5538 IWM_STA_SLEEP_STATE_AWAKE = 0, 5539 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5540 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5541 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5542 }; 5543 5544 /* STA ID and color bits definitions */ 5545 #define IWM_STA_ID_SEED (0x0f) 5546 #define IWM_STA_ID_POS (0) 5547 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5548 5549 #define IWM_STA_COLOR_SEED (0x7) 5550 #define IWM_STA_COLOR_POS (4) 5551 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5552 5553 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5554 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5555 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5556 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5557 5558 #define IWM_STA_KEY_MAX_NUM (16) 5559 #define IWM_STA_KEY_IDX_INVALID (0xff) 5560 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5561 #define IWM_MAX_GLOBAL_KEYS (4) 5562 #define IWM_STA_KEY_LEN_WEP40 (5) 5563 #define IWM_STA_KEY_LEN_WEP104 (13) 5564 5565 /** 5566 * struct iwm_mvm_keyinfo - key information 5567 * @key_flags: type %iwm_sta_key_flag 5568 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5569 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5570 * @key_offset: key offset in the fw's key table 5571 * @key: 16-byte unicast decryption key 5572 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5573 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5574 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5575 */ 5576 struct iwm_mvm_keyinfo { 5577 uint16_t key_flags; 5578 uint8_t tkip_rx_tsc_byte2; 5579 uint8_t reserved1; 5580 uint16_t tkip_rx_ttak[5]; 5581 uint8_t key_offset; 5582 uint8_t reserved2; 5583 uint8_t key[16]; 5584 uint64_t tx_secur_seq_cnt; 5585 uint64_t hw_tkip_mic_rx_key; 5586 uint64_t hw_tkip_mic_tx_key; 5587 } __packed; 5588 5589 #define IWM_ADD_STA_STATUS_MASK 0xFF 5590 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5591 #define IWM_ADD_STA_BAID_MASK 0x7F00 5592 #define IWM_ADD_STA_BAID_SHIFT 8 5593 5594 /** 5595 * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table. 5596 * ( REPLY_ADD_STA = 0x18 ) 5597 * @add_modify: 1: modify existing, 0: add new station 5598 * @awake_acs: 5599 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5600 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5601 * @mac_id_n_color: the Mac context this station belongs to 5602 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5603 * @sta_id: index of station in uCode's station table 5604 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5605 * alone. 1 - modify, 0 - don't change. 5606 * @station_flags: look at %iwm_sta_flags 5607 * @station_flags_msk: what of %station_flags have changed 5608 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5609 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5610 * add_immediate_ba_ssn. 5611 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5612 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5613 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5614 * add_immediate_ba_tid. 5615 * @sleep_tx_count: number of packets to transmit to station even though it is 5616 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5617 * keeps track of STA sleep state. 5618 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5619 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5620 * mac-addr. 5621 * @beamform_flags: beam forming controls 5622 * @tfd_queue_msk: tfd queues used by this station 5623 * 5624 * The device contains an internal table of per-station information, with info 5625 * on security keys, aggregation parameters, and Tx rates for initial Tx 5626 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5627 * 5628 * ADD_STA sets up the table entry for one station, either creating a new 5629 * entry, or modifying a pre-existing one. 5630 */ 5631 struct iwm_mvm_add_sta_cmd_v7 { 5632 uint8_t add_modify; 5633 uint8_t awake_acs; 5634 uint16_t tid_disable_tx; 5635 uint32_t mac_id_n_color; 5636 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5637 uint16_t reserved2; 5638 uint8_t sta_id; 5639 uint8_t modify_mask; 5640 uint16_t reserved3; 5641 uint32_t station_flags; 5642 uint32_t station_flags_msk; 5643 uint8_t add_immediate_ba_tid; 5644 uint8_t remove_immediate_ba_tid; 5645 uint16_t add_immediate_ba_ssn; 5646 uint16_t sleep_tx_count; 5647 uint16_t sleep_state_flags; 5648 uint16_t assoc_id; 5649 uint16_t beamform_flags; 5650 uint32_t tfd_queue_msk; 5651 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5652 5653 /** 5654 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5655 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5656 * @sta_id: index of station in uCode's station table 5657 * @key_offset: key offset in key storage 5658 * @key_flags: type %iwm_sta_key_flag 5659 * @key: key material data 5660 * @key2: key material data 5661 * @rx_secur_seq_cnt: RX security sequence counter for the key 5662 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5663 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5664 */ 5665 struct iwm_mvm_add_sta_key_cmd { 5666 uint8_t sta_id; 5667 uint8_t key_offset; 5668 uint16_t key_flags; 5669 uint8_t key[16]; 5670 uint8_t key2[16]; 5671 uint8_t rx_secur_seq_cnt[16]; 5672 uint8_t tkip_rx_tsc_byte2; 5673 uint8_t reserved; 5674 uint16_t tkip_rx_ttak[5]; 5675 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5676 5677 /** 5678 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5679 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5680 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5681 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5682 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5683 * that doesn't exist. 5684 */ 5685 enum iwm_mvm_add_sta_rsp_status { 5686 IWM_ADD_STA_SUCCESS = 0x1, 5687 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5688 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5689 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5690 }; 5691 5692 /** 5693 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5694 * ( IWM_REMOVE_STA = 0x19 ) 5695 * @sta_id: the station id of the station to be removed 5696 */ 5697 struct iwm_mvm_rm_sta_cmd { 5698 uint8_t sta_id; 5699 uint8_t reserved[3]; 5700 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5701 5702 /** 5703 * struct iwm_mvm_mgmt_mcast_key_cmd 5704 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5705 * @ctrl_flags: %iwm_sta_key_flag 5706 * @IGTK: 5707 * @K1: IGTK master key 5708 * @K2: IGTK sub key 5709 * @sta_id: station ID that support IGTK 5710 * @key_id: 5711 * @receive_seq_cnt: initial RSC/PN needed for replay check 5712 */ 5713 struct iwm_mvm_mgmt_mcast_key_cmd { 5714 uint32_t ctrl_flags; 5715 uint8_t IGTK[16]; 5716 uint8_t K1[16]; 5717 uint8_t K2[16]; 5718 uint32_t key_id; 5719 uint32_t sta_id; 5720 uint64_t receive_seq_cnt; 5721 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5722 5723 struct iwm_mvm_wep_key { 5724 uint8_t key_index; 5725 uint8_t key_offset; 5726 uint16_t reserved1; 5727 uint8_t key_size; 5728 uint8_t reserved2[3]; 5729 uint8_t key[16]; 5730 } __packed; 5731 5732 struct iwm_mvm_wep_key_cmd { 5733 uint32_t mac_id_n_color; 5734 uint8_t num_keys; 5735 uint8_t decryption_type; 5736 uint8_t flags; 5737 uint8_t reserved; 5738 struct iwm_mvm_wep_key wep_key[0]; 5739 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5740 5741 /* 5742 * BT coex 5743 */ 5744 5745 enum iwm_bt_coex_mode { 5746 IWM_BT_COEX_DISABLE = 0x0, 5747 IWM_BT_COEX_NW = 0x1, 5748 IWM_BT_COEX_BT = 0x2, 5749 IWM_BT_COEX_WIFI = 0x3, 5750 }; /* BT_COEX_MODES_E */ 5751 5752 enum iwm_bt_coex_enabled_modules { 5753 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5754 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5755 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5756 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5757 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5758 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5759 5760 /** 5761 * struct iwm_bt_coex_cmd - bt coex configuration command 5762 * @mode: enum %iwm_bt_coex_mode 5763 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5764 * 5765 * The structure is used for the BT_COEX command. 5766 */ 5767 struct iwm_bt_coex_cmd { 5768 uint32_t mode; 5769 uint32_t enabled_modules; 5770 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5771 5772 5773 /* 5774 * Location Aware Regulatory (LAR) API - MCC updates 5775 */ 5776 5777 /** 5778 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5779 * regulatory profile according to the given MCC (Mobile Country Code). 5780 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5781 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5782 * MCC in the cmd response will be the relevant MCC in the NVM. 5783 * @mcc: given mobile country code 5784 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5785 * @reserved: reserved for alignment 5786 */ 5787 struct iwm_mcc_update_cmd_v1 { 5788 uint16_t mcc; 5789 uint8_t source_id; 5790 uint8_t reserved; 5791 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5792 5793 /** 5794 * struct iwm_mcc_update_cmd - Request the device to update geographic 5795 * regulatory profile according to the given MCC (Mobile Country Code). 5796 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5797 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5798 * MCC in the cmd response will be the relevant MCC in the NVM. 5799 * @mcc: given mobile country code 5800 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5801 * @reserved: reserved for alignment 5802 * @key: integrity key for MCC API OEM testing 5803 * @reserved2: reserved 5804 */ 5805 struct iwm_mcc_update_cmd { 5806 uint16_t mcc; 5807 uint8_t source_id; 5808 uint8_t reserved; 5809 uint32_t key; 5810 uint32_t reserved2[5]; 5811 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5812 5813 /** 5814 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5815 * Contains the new channel control profile map, if changed, and the new MCC 5816 * (mobile country code). 5817 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5818 * @status: see &enum iwm_mcc_update_status 5819 * @mcc: the new applied MCC 5820 * @cap: capabilities for all channels which matches the MCC 5821 * @source_id: the MCC source, see iwm_mcc_source 5822 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5823 * channels, depending on platform) 5824 * @channels: channel control data map, DWORD for each channel. Only the first 5825 * 16bits are used. 5826 */ 5827 struct iwm_mcc_update_resp_v1 { 5828 uint32_t status; 5829 uint16_t mcc; 5830 uint8_t cap; 5831 uint8_t source_id; 5832 uint32_t n_channels; 5833 uint32_t channels[0]; 5834 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5835 5836 /** 5837 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5838 * Contains the new channel control profile map, if changed, and the new MCC 5839 * (mobile country code). 5840 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5841 * @status: see &enum iwm_mcc_update_status 5842 * @mcc: the new applied MCC 5843 * @cap: capabilities for all channels which matches the MCC 5844 * @source_id: the MCC source, see iwm_mcc_source 5845 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5846 * @reserved: reserved. 5847 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5848 * channels, depending on platform) 5849 * @channels: channel control data map, DWORD for each channel. Only the first 5850 * 16bits are used. 5851 */ 5852 struct iwm_mcc_update_resp { 5853 uint32_t status; 5854 uint16_t mcc; 5855 uint8_t cap; 5856 uint8_t source_id; 5857 uint16_t time; 5858 uint16_t reserved; 5859 uint32_t n_channels; 5860 uint32_t channels[0]; 5861 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5862 5863 /** 5864 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5865 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5866 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5867 * the cellular and connectivity cores that gets updates of the mcc, and 5868 * notifies the ucode directly of any mcc change. 5869 * The ucode requests the driver to request the device to update geographic 5870 * regulatory profile according to the given MCC (Mobile Country Code). 5871 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5872 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5873 * MCC in the cmd response will be the relevant MCC in the NVM. 5874 * @mcc: given mobile country code 5875 * @source_id: identity of the change originator, see iwm_mcc_source 5876 * @reserved1: reserved for alignment 5877 */ 5878 struct iwm_mcc_chub_notif { 5879 uint16_t mcc; 5880 uint8_t source_id; 5881 uint8_t reserved1; 5882 } __packed; /* LAR_MCC_NOTIFY_S */ 5883 5884 enum iwm_mcc_update_status { 5885 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5886 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5887 IWM_MCC_RESP_INVALID, 5888 IWM_MCC_RESP_NVM_DISABLED, 5889 IWM_MCC_RESP_ILLEGAL, 5890 IWM_MCC_RESP_LOW_PRIORITY, 5891 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5892 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5893 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5894 }; 5895 5896 enum iwm_mcc_source { 5897 IWM_MCC_SOURCE_OLD_FW = 0, 5898 IWM_MCC_SOURCE_ME = 1, 5899 IWM_MCC_SOURCE_BIOS = 2, 5900 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5901 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5902 IWM_MCC_SOURCE_WIFI = 5, 5903 IWM_MCC_SOURCE_RESERVED = 6, 5904 IWM_MCC_SOURCE_DEFAULT = 7, 5905 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5906 IWM_MCC_SOURCE_MCC_API = 9, 5907 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5908 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5909 }; 5910 5911 /** 5912 * struct iwm_dts_measurement_notif_v1 - measurements notification 5913 * 5914 * @temp: the measured temperature 5915 * @voltage: the measured voltage 5916 */ 5917 struct iwm_dts_measurement_notif_v1 { 5918 int32_t temp; 5919 int32_t voltage; 5920 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5921 5922 /** 5923 * struct iwm_dts_measurement_notif_v2 - measurements notification 5924 * 5925 * @temp: the measured temperature 5926 * @voltage: the measured voltage 5927 * @threshold_idx: the trip index that was crossed 5928 */ 5929 struct iwm_dts_measurement_notif_v2 { 5930 int32_t temp; 5931 int32_t voltage; 5932 int32_t threshold_idx; 5933 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5934 5935 /* 5936 * Some cherry-picked definitions 5937 */ 5938 5939 #define IWM_FRAME_LIMIT 64 5940 5941 /* 5942 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 5943 * As the firmware is slowly running out of command IDs and grouping of 5944 * commands is desirable anyway, the firmware is extending the command 5945 * header from 4 bytes to 8 bytes to introduce a group (in place of the 5946 * former flags field, since that's always 0 on commands and thus can 5947 * be easily used to distinguish between the two). 5948 * 5949 * These functions retrieve specific information from the id field in 5950 * the iwm_host_cmd struct which contains the command id, the group id, 5951 * and the version of the command. 5952 */ 5953 static inline uint8_t 5954 iwm_cmd_opcode(uint32_t cmdid) 5955 { 5956 return cmdid & 0xff; 5957 } 5958 5959 static inline uint8_t 5960 iwm_cmd_groupid(uint32_t cmdid) 5961 { 5962 return ((cmdid & 0Xff00) >> 8); 5963 } 5964 5965 static inline uint8_t 5966 iwm_cmd_version(uint32_t cmdid) 5967 { 5968 return ((cmdid & 0xff0000) >> 16); 5969 } 5970 5971 static inline uint32_t 5972 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 5973 { 5974 return opcode + (groupid << 8) + (version << 16); 5975 } 5976 5977 /* make uint16_t wide id out of uint8_t group and opcode */ 5978 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 5979 5980 /* due to the conversion, this group is special */ 5981 #define IWM_ALWAYS_LONG_GROUP 1 5982 5983 struct iwm_cmd_header { 5984 uint8_t code; 5985 uint8_t flags; 5986 uint8_t idx; 5987 uint8_t qid; 5988 } __packed; 5989 5990 struct iwm_cmd_header_wide { 5991 uint8_t opcode; 5992 uint8_t group_id; 5993 uint8_t idx; 5994 uint8_t qid; 5995 uint16_t length; 5996 uint8_t reserved; 5997 uint8_t version; 5998 } __packed; 5999 6000 enum iwm_power_scheme { 6001 IWM_POWER_SCHEME_CAM = 1, 6002 IWM_POWER_SCHEME_BPS, 6003 IWM_POWER_SCHEME_LP 6004 }; 6005 6006 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6007 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6008 #define IWM_CMD_FAILED_MSK 0x40 6009 6010 /** 6011 * struct iwm_device_cmd 6012 * 6013 * For allocation of the command and tx queues, this establishes the overall 6014 * size of the largest command we send to uCode, except for commands that 6015 * aren't fully copied and use other TFD space. 6016 */ 6017 struct iwm_device_cmd { 6018 union { 6019 struct { 6020 struct iwm_cmd_header hdr; 6021 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6022 }; 6023 struct { 6024 struct iwm_cmd_header_wide hdr_wide; 6025 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6026 sizeof(struct iwm_cmd_header_wide) + 6027 sizeof(struct iwm_cmd_header)]; 6028 }; 6029 }; 6030 } __packed; 6031 6032 struct iwm_rx_packet { 6033 /* 6034 * The first 4 bytes of the RX frame header contain both the RX frame 6035 * size and some flags. 6036 * Bit fields: 6037 * 31: flag flush RB request 6038 * 30: flag ignore TC (terminal counter) request 6039 * 29: flag fast IRQ request 6040 * 28-14: Reserved 6041 * 13-00: RX frame size 6042 */ 6043 uint32_t len_n_flags; 6044 struct iwm_cmd_header hdr; 6045 uint8_t data[]; 6046 } __packed; 6047 6048 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6049 6050 static inline uint32_t 6051 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6052 { 6053 6054 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6055 } 6056 6057 static inline uint32_t 6058 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6059 { 6060 6061 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6062 } 6063 6064 6065 #define IWM_MIN_DBM -100 6066 #define IWM_MAX_DBM -33 /* realistic guess */ 6067 6068 #define IWM_READ(sc, reg) \ 6069 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6070 6071 #define IWM_WRITE(sc, reg, val) \ 6072 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6073 6074 #define IWM_WRITE_1(sc, reg, val) \ 6075 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6076 6077 #define IWM_SETBITS(sc, reg, mask) \ 6078 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6079 6080 #define IWM_CLRBITS(sc, reg, mask) \ 6081 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6082 6083 #define IWM_BARRIER_WRITE(sc) \ 6084 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6085 BUS_SPACE_BARRIER_WRITE) 6086 6087 #define IWM_BARRIER_READ_WRITE(sc) \ 6088 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6089 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6090 6091 #endif /* __IF_IWM_REG_H__ */ 6092