1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2 /* $FreeBSD$ */ 3 4 /****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * CSR (control and status registers) 74 * 75 * CSR registers are mapped directly into PCI bus space, and are accessible 76 * whenever platform supplies power to device, even when device is in 77 * low power states due to driver-invoked device resets 78 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 79 * 80 * Use iwl_write32() and iwl_read32() family to access these registers; 81 * these provide simple PCI bus access, without waking up the MAC. 82 * Do not use iwl_write_direct32() family for these registers; 83 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 84 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 85 * the CSR registers. 86 * 87 * NOTE: Device does need to be awake in order to read this memory 88 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 89 */ 90 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 91 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 92 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 93 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 94 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 95 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 96 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 97 #define IWM_CSR_GP_CNTRL (0x024) 98 99 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 100 #define IWM_CSR_INT_PERIODIC_REG (0x005) 101 102 /* 103 * Hardware revision info 104 * Bit fields: 105 * 31-16: Reserved 106 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 108 * 1-0: "Dash" (-) value, as in A-1, etc. 109 */ 110 #define IWM_CSR_HW_REV (0x028) 111 112 /* 113 * EEPROM and OTP (one-time-programmable) memory reads 114 * 115 * NOTE: Device must be awake, initialized via apm_ops.init(), 116 * in order to read. 117 */ 118 #define IWM_CSR_EEPROM_REG (0x02c) 119 #define IWM_CSR_EEPROM_GP (0x030) 120 #define IWM_CSR_OTP_GP_REG (0x034) 121 122 #define IWM_CSR_GIO_REG (0x03C) 123 #define IWM_CSR_GP_UCODE_REG (0x048) 124 #define IWM_CSR_GP_DRIVER_REG (0x050) 125 126 /* 127 * UCODE-DRIVER GP (general purpose) mailbox registers. 128 * SET/CLR registers set/clear bit(s) if "1" is written. 129 */ 130 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 131 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 132 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 133 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 134 135 #define IWM_CSR_MBOX_SET_REG (0x088) 136 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 137 138 #define IWM_CSR_LED_REG (0x094) 139 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 140 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 141 142 143 /* GIO Chicken Bits (PCI Express bus link power management) */ 144 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 145 146 /* Analog phase-lock-loop configuration */ 147 #define IWM_CSR_ANA_PLL_CFG (0x20c) 148 149 /* 150 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 151 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 152 * See also IWM_CSR_HW_REV register. 153 * Bit fields: 154 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 155 * 1-0: "Dash" (-) value, as in C-1, etc. 156 */ 157 #define IWM_CSR_HW_REV_WA_REG (0x22C) 158 159 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 160 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 161 162 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 163 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 164 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 166 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 167 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 171 172 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 173 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 178 179 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 180 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 183 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 184 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 186 187 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 188 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 189 190 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 191 * acknowledged (reset) by host writing "1" to flagged bits. */ 192 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 193 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 194 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 195 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 196 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 197 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 198 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 199 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 200 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 201 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 202 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 203 204 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 205 IWM_CSR_INT_BIT_HW_ERR | \ 206 IWM_CSR_INT_BIT_FH_TX | \ 207 IWM_CSR_INT_BIT_SW_ERR | \ 208 IWM_CSR_INT_BIT_RF_KILL | \ 209 IWM_CSR_INT_BIT_SW_RX | \ 210 IWM_CSR_INT_BIT_WAKEUP | \ 211 IWM_CSR_INT_BIT_ALIVE | \ 212 IWM_CSR_INT_BIT_RX_PERIODIC) 213 214 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 215 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 216 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 217 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 218 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 219 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 220 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 221 222 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 223 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 224 IWM_CSR_FH_INT_BIT_RX_CHNL0) 225 226 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 227 IWM_CSR_FH_INT_BIT_TX_CHNL0) 228 229 /* GPIO */ 230 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 231 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 232 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 233 234 /* RESET */ 235 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 236 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 237 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 238 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 239 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 240 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 241 242 /* 243 * GP (general purpose) CONTROL REGISTER 244 * Bit fields: 245 * 27: HW_RF_KILL_SW 246 * Indicates state of (platform's) hardware RF-Kill switch 247 * 26-24: POWER_SAVE_TYPE 248 * Indicates current power-saving mode: 249 * 000 -- No power saving 250 * 001 -- MAC power-down 251 * 010 -- PHY (radio) power-down 252 * 011 -- Error 253 * 9-6: SYS_CONFIG 254 * Indicates current system configuration, reflecting pins on chip 255 * as forced high/low by device circuit board. 256 * 4: GOING_TO_SLEEP 257 * Indicates MAC is entering a power-saving sleep power-down. 258 * Not a good time to access device-internal resources. 259 * 3: MAC_ACCESS_REQ 260 * Host sets this to request and maintain MAC wakeup, to allow host 261 * access to device-internal resources. Host must wait for 262 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 263 * device registers. 264 * 2: INIT_DONE 265 * Host sets this to put device into fully operational D0 power mode. 266 * Host resets this after SW_RESET to put device into low power mode. 267 * 0: MAC_CLOCK_READY 268 * Indicates MAC (ucode processor, etc.) is powered up and can run. 269 * Internal resources are accessible. 270 * NOTE: This does not indicate that the processor is actually running. 271 * NOTE: This does not indicate that device has completed 272 * init or post-power-down restore of internal SRAM memory. 273 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 274 * SRAM is restored and uCode is in normal operation mode. 275 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 276 * do not need to save/restore it. 277 * NOTE: After device reset, this bit remains "0" until host sets 278 * INIT_DONE 279 */ 280 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 281 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 283 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 284 285 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 286 287 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 288 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 289 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 290 291 292 /* HW REV */ 293 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 294 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 295 296 /** 297 * hw_rev values 298 */ 299 enum { 300 IWM_SILICON_A_STEP = 0, 301 IWM_SILICON_B_STEP, 302 IWM_SILICON_C_STEP, 303 }; 304 305 306 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 307 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 308 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 309 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 310 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 311 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 312 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 313 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 314 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 315 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 316 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 317 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 318 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 319 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 320 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 321 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 322 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 323 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 324 325 /* EEPROM REG */ 326 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 327 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 328 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 329 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 330 331 /* EEPROM GP */ 332 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 333 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 334 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 335 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 336 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 337 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 338 339 /* One-time-programmable memory general purpose reg */ 340 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 341 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 342 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 343 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 344 345 /* GP REG */ 346 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 347 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 348 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 349 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 350 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 351 352 353 /* CSR GIO */ 354 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 355 356 /* 357 * UCODE-DRIVER GP (general purpose) mailbox register 1 358 * Host driver and uCode write and/or read this register to communicate with 359 * each other. 360 * Bit fields: 361 * 4: UCODE_DISABLE 362 * Host sets this to request permanent halt of uCode, same as 363 * sending CARD_STATE command with "halt" bit set. 364 * 3: CT_KILL_EXIT 365 * Host sets this to request exit from CT_KILL state, i.e. host thinks 366 * device temperature is low enough to continue normal operation. 367 * 2: CMD_BLOCKED 368 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 369 * to release uCode to clear all Tx and command queues, enter 370 * unassociated mode, and power down. 371 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 372 * 1: SW_BIT_RFKILL 373 * Host sets this when issuing CARD_STATE command to request 374 * device sleep. 375 * 0: MAC_SLEEP 376 * uCode sets this when preparing a power-saving power-down. 377 * uCode resets this when power-up is complete and SRAM is sane. 378 * NOTE: device saves internal SRAM data to host when powering down, 379 * and must restore this data after powering back up. 380 * MAC_SLEEP is the best indication that restore is complete. 381 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 382 * do not need to save/restore it. 383 */ 384 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 385 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 386 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 387 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 388 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 389 390 /* GP Driver */ 391 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 392 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 393 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 394 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 395 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 396 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 397 398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 399 400 /* GIO Chicken Bits (PCI Express bus link power management) */ 401 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 402 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 403 404 /* LED */ 405 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 406 #define IWM_CSR_LED_REG_TURN_ON (0x60) 407 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 408 409 /* ANA_PLL */ 410 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 411 412 /* HPET MEM debug */ 413 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 414 415 /* DRAM INT TABLE */ 416 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 417 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 418 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 419 420 /* SECURE boot registers */ 421 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 422 enum iwm_secure_boot_config_reg { 423 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 424 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 425 }; 426 427 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 428 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 429 enum iwm_secure_boot_status_reg { 430 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 431 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 432 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 433 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 435 }; 436 437 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 438 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 439 440 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 441 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 442 443 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 444 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 445 446 #define IWM_CSR_SECURE_TIME_OUT (100) 447 448 /* extended range in FW SRAM */ 449 #define IWM_FW_MEM_EXTENDED_START 0x40000 450 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 451 452 /* FW chicken bits */ 453 #define IWM_LMPM_CHICK 0xa01ff8 454 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 455 456 #define IWM_FH_TCSR_0_REG0 (0x1D00) 457 458 /* 459 * HBUS (Host-side Bus) 460 * 461 * HBUS registers are mapped directly into PCI bus space, but are used 462 * to indirectly access device's internal memory or registers that 463 * may be powered-down. 464 * 465 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 466 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 467 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 468 * internal resources. 469 * 470 * Do not use iwl_write32()/iwl_read32() family to access these registers; 471 * these provide only simple PCI bus access, without waking up the MAC. 472 */ 473 #define IWM_HBUS_BASE (0x400) 474 475 /* 476 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 477 * structures, error log, event log, verifying uCode load). 478 * First write to address register, then read from or write to data register 479 * to complete the job. Once the address register is set up, accesses to 480 * data registers auto-increment the address by one dword. 481 * Bit usage for address registers (read or write): 482 * 0-31: memory address within device 483 */ 484 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 485 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 486 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 487 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 488 489 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 490 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 491 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 492 493 /* 494 * Registers for accessing device's internal peripheral registers 495 * (e.g. SCD, BSM, etc.). First write to address register, 496 * then read from or write to data register to complete the job. 497 * Bit usage for address registers (read or write): 498 * 0-15: register address (offset) within device 499 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 500 */ 501 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 502 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 503 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 504 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 505 506 /* enable the ID buf for read */ 507 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 508 #define IWM_WFMP_MAC_ADDR_0 0xa03080 509 #define IWM_WFMP_MAC_ADDR_1 0xa03084 510 #define IWM_LMPM_PMG_EN 0xa01cec 511 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 512 #define IWM_RFIC_REG_RD 0xad0470 513 #define IWM_WFPM_CTRL_REG 0xa03030 514 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 515 #define IWM_ENABLE_WFPM 0x80000000 516 517 #define IWM_AUX_MISC_REG 0xa200b0 518 #define IWM_HW_STEP_LOCATION_BITS 24 519 520 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 521 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 522 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 523 #define IWM_RSA_ENABLE 0xa24b08 524 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 525 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 526 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 527 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 528 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 529 #define IWM_SB_CPU_1_STATUS 0xa01e30 530 #define IWM_SB_CPU_2_STATUS 0Xa01e34 531 532 /* Used to enable DBGM */ 533 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 534 535 /* 536 * Per-Tx-queue write pointer (index, really!) 537 * Indicates index to next TFD that driver will fill (1 past latest filled). 538 * Bit usage: 539 * 0-7: queue write index 540 * 11-8: queue selector 541 */ 542 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 543 544 /********************************************************** 545 * CSR values 546 **********************************************************/ 547 /* 548 * host interrupt timeout value 549 * used with setting interrupt coalescing timer 550 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 551 * 552 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 553 */ 554 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 555 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 556 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 557 #define IWM_HOST_INT_OPER_MODE (1 << 31) 558 559 /***************************************************************************** 560 * 7000/3000 series SHR DTS addresses * 561 *****************************************************************************/ 562 563 /* Diode Results Register Structure: */ 564 enum iwm_dtd_diode_reg { 565 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 566 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 567 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 568 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 569 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 570 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 571 /* Those are the masks INSIDE the flags bit-field: */ 572 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 573 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 574 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 575 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 576 }; 577 578 /** 579 * enum iwm_ucode_tlv_flag - ucode API flags 580 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 581 * was a separate TLV but moved here to save space. 582 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 583 * treats good CRC threshold as a boolean 584 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 585 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 586 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 587 * offload profile config command. 588 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 589 * (rather than two) IPv6 addresses 590 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 591 * from the probe request template. 592 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 593 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 594 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 595 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 596 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 597 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 598 */ 599 enum iwm_ucode_tlv_flag { 600 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 601 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 602 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 603 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 604 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 605 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 606 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 607 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 608 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 609 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 610 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 611 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 612 }; 613 614 #define IWM_UCODE_TLV_FLAG_BITS \ 615 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 616 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 617 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 618 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 619 620 /** 621 * enum iwm_ucode_tlv_api - ucode api 622 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 623 * longer than the passive one, which is essential for fragmented scan. 624 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 625 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 626 * 627 * @IWM_NUM_UCODE_TLV_API: number of bits used 628 */ 629 enum iwm_ucode_tlv_api { 630 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8, 631 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9, 632 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18, 633 634 IWM_NUM_UCODE_TLV_API = 32 635 }; 636 637 #define IWM_UCODE_TLV_API_BITS \ 638 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 639 640 /** 641 * enum iwm_ucode_tlv_capa - ucode capabilities 642 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 643 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 644 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 645 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 646 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 647 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 648 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 649 * tx power value into TPC Report action frame and Link Measurement Report 650 * action frame 651 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 652 * channel in DS parameter set element in probe requests. 653 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 654 * probe requests. 655 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 656 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 657 * which also implies support for the scheduler configuration command 658 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 659 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 660 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 661 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 662 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 663 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 664 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 665 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 666 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 667 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 668 * sources for the MCC. This TLV bit is a future replacement to 669 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 670 * is supported. 671 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 672 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 673 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 674 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 675 * 0=no support) 676 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 677 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 678 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 679 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 680 * antenna the beacon should be transmitted 681 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 682 * from AP and will send it upon d0i3 exit. 683 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 684 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 685 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 686 * thresholds reporting 687 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 688 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 689 * regular image. 690 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 691 * memory addresses from the firmware. 692 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 693 * @IWM_UCODE_TLV_CAPA_TX_POWER_ACK: reduced TX power API has larger 694 * command size (command version 4) that supports toggling ACK TX 695 * power reduction. 696 * 697 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 698 */ 699 enum iwm_ucode_tlv_capa { 700 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 701 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 702 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 703 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 704 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 705 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 706 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 707 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 708 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 709 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 710 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 711 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 712 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 713 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 714 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 715 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 716 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 717 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 718 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 719 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 720 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 721 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 722 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 723 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 724 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 725 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 726 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 727 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 728 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 729 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 730 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 731 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 732 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 733 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 734 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 735 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 736 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 737 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 738 IWM_UCODE_TLV_CAPA_TX_POWER_ACK = 84, 739 740 IWM_NUM_UCODE_TLV_CAPA = 128 741 }; 742 743 /* The default calibrate table size if not specified by firmware file */ 744 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 745 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 746 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 747 748 /* The default max probe length if not specified by the firmware file */ 749 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 750 751 /* 752 * enumeration of ucode section. 753 * This enumeration is used directly for older firmware (before 16.0). 754 * For new firmware, there can be up to 4 sections (see below) but the 755 * first one packaged into the firmware file is the DATA section and 756 * some debugging code accesses that. 757 */ 758 enum iwm_ucode_sec { 759 IWM_UCODE_SECTION_DATA, 760 IWM_UCODE_SECTION_INST, 761 }; 762 /* 763 * For 16.0 uCode and above, there is no differentiation between sections, 764 * just an offset to the HW address. 765 */ 766 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 767 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 768 769 /* uCode version contains 4 values: Major/Minor/API/Serial */ 770 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 771 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 772 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 773 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 774 775 /* 776 * Calibration control struct. 777 * Sent as part of the phy configuration command. 778 * @flow_trigger: bitmap for which calibrations to perform according to 779 * flow triggers. 780 * @event_trigger: bitmap for which calibrations to perform according to 781 * event triggers. 782 */ 783 struct iwm_tlv_calib_ctrl { 784 uint32_t flow_trigger; 785 uint32_t event_trigger; 786 } __packed; 787 788 enum iwm_fw_phy_cfg { 789 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 790 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 791 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 792 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 793 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 794 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 795 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 796 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 797 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 798 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 799 }; 800 801 #define IWM_UCODE_MAX_CS 1 802 803 /** 804 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 805 * @cipher: a cipher suite selector 806 * @flags: cipher scheme flags (currently reserved for a future use) 807 * @hdr_len: a size of MPDU security header 808 * @pn_len: a size of PN 809 * @pn_off: an offset of pn from the beginning of the security header 810 * @key_idx_off: an offset of key index byte in the security header 811 * @key_idx_mask: a bit mask of key_idx bits 812 * @key_idx_shift: bit shift needed to get key_idx 813 * @mic_len: mic length in bytes 814 * @hw_cipher: a HW cipher index used in host commands 815 */ 816 struct iwm_fw_cipher_scheme { 817 uint32_t cipher; 818 uint8_t flags; 819 uint8_t hdr_len; 820 uint8_t pn_len; 821 uint8_t pn_off; 822 uint8_t key_idx_off; 823 uint8_t key_idx_mask; 824 uint8_t key_idx_shift; 825 uint8_t mic_len; 826 uint8_t hw_cipher; 827 } __packed; 828 829 /** 830 * struct iwm_fw_cscheme_list - a cipher scheme list 831 * @size: a number of entries 832 * @cs: cipher scheme entries 833 */ 834 struct iwm_fw_cscheme_list { 835 uint8_t size; 836 struct iwm_fw_cipher_scheme cs[]; 837 } __packed; 838 839 /* v1/v2 uCode file layout */ 840 struct iwm_ucode_header { 841 uint32_t ver; /* major/minor/API/serial */ 842 union { 843 struct { 844 uint32_t inst_size; /* bytes of runtime code */ 845 uint32_t data_size; /* bytes of runtime data */ 846 uint32_t init_size; /* bytes of init code */ 847 uint32_t init_data_size; /* bytes of init data */ 848 uint32_t boot_size; /* bytes of bootstrap code */ 849 uint8_t data[0]; /* in same order as sizes */ 850 } v1; 851 struct { 852 uint32_t build; /* build number */ 853 uint32_t inst_size; /* bytes of runtime code */ 854 uint32_t data_size; /* bytes of runtime data */ 855 uint32_t init_size; /* bytes of init code */ 856 uint32_t init_data_size; /* bytes of init data */ 857 uint32_t boot_size; /* bytes of bootstrap code */ 858 uint8_t data[0]; /* in same order as sizes */ 859 } v2; 860 } u; 861 }; 862 863 /* 864 * new TLV uCode file layout 865 * 866 * The new TLV file format contains TLVs, that each specify 867 * some piece of data. 868 */ 869 870 enum iwm_ucode_tlv_type { 871 IWM_UCODE_TLV_INVALID = 0, /* unused */ 872 IWM_UCODE_TLV_INST = 1, 873 IWM_UCODE_TLV_DATA = 2, 874 IWM_UCODE_TLV_INIT = 3, 875 IWM_UCODE_TLV_INIT_DATA = 4, 876 IWM_UCODE_TLV_BOOT = 5, 877 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 878 IWM_UCODE_TLV_PAN = 7, 879 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 880 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 881 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 882 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 883 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 884 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 885 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 886 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 887 IWM_UCODE_TLV_WOWLAN_INST = 16, 888 IWM_UCODE_TLV_WOWLAN_DATA = 17, 889 IWM_UCODE_TLV_FLAGS = 18, 890 IWM_UCODE_TLV_SEC_RT = 19, 891 IWM_UCODE_TLV_SEC_INIT = 20, 892 IWM_UCODE_TLV_SEC_WOWLAN = 21, 893 IWM_UCODE_TLV_DEF_CALIB = 22, 894 IWM_UCODE_TLV_PHY_SKU = 23, 895 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 896 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 897 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 898 IWM_UCODE_TLV_NUM_OF_CPU = 27, 899 IWM_UCODE_TLV_CSCHEME = 28, 900 901 /* 902 * Following two are not in our base tag, but allow 903 * handling ucode version 9. 904 */ 905 IWM_UCODE_TLV_API_CHANGES_SET = 29, 906 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 907 908 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 909 IWM_UCODE_TLV_PAGING = 32, 910 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 911 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 912 IWM_UCODE_TLV_FW_VERSION = 36, 913 IWM_UCODE_TLV_FW_DBG_DEST = 38, 914 IWM_UCODE_TLV_FW_DBG_CONF = 39, 915 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 916 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 917 IWM_UCODE_TLV_FW_MEM_SEG = 51, 918 }; 919 920 struct iwm_ucode_tlv { 921 uint32_t type; /* see above */ 922 uint32_t length; /* not including type/length fields */ 923 uint8_t data[0]; 924 }; 925 926 struct iwm_ucode_api { 927 uint32_t api_index; 928 uint32_t api_flags; 929 } __packed; 930 931 struct iwm_ucode_capa { 932 uint32_t api_index; 933 uint32_t api_capa; 934 } __packed; 935 936 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 937 938 struct iwm_tlv_ucode_header { 939 /* 940 * The TLV style ucode header is distinguished from 941 * the v1/v2 style header by first four bytes being 942 * zero, as such is an invalid combination of 943 * major/minor/API/serial versions. 944 */ 945 uint32_t zero; 946 uint32_t magic; 947 uint8_t human_readable[64]; 948 uint32_t ver; /* major/minor/API/serial */ 949 uint32_t build; 950 uint64_t ignore; 951 /* 952 * The data contained herein has a TLV layout, 953 * see above for the TLV header and types. 954 * Note that each TLV is padded to a length 955 * that is a multiple of 4 for alignment. 956 */ 957 uint8_t data[0]; 958 }; 959 960 /* 961 * Registers in this file are internal, not PCI bus memory mapped. 962 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 963 */ 964 #define IWM_PRPH_BASE (0x00000) 965 #define IWM_PRPH_END (0xFFFFF) 966 967 /* APMG (power management) constants */ 968 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 969 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 970 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 971 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 972 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 973 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 974 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 975 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 976 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 977 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 978 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 979 980 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 981 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 982 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 983 984 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 985 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 986 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 987 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 988 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 989 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 990 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 991 992 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 993 994 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 995 996 /* Device system time */ 997 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 998 999 /* Device NMI register */ 1000 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1001 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1002 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1003 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1004 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1005 1006 /* 1007 * Device reset for family 8000 1008 * write to bit 24 in order to reset the CPU 1009 */ 1010 #define IWM_RELEASE_CPU_RESET 0x300c 1011 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1012 1013 1014 /***************************************************************************** 1015 * 7000/3000 series SHR DTS addresses * 1016 *****************************************************************************/ 1017 1018 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1019 #define IWM_DTSC_CFG_MODE (0x00a10604) 1020 #define IWM_DTSC_VREF_AVG (0x00a10648) 1021 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1022 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1023 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1024 1025 1026 /** 1027 * Tx Scheduler 1028 * 1029 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1030 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1031 * host DRAM. It steers each frame's Tx command (which contains the frame 1032 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1033 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1034 * but one DMA channel may take input from several queues. 1035 * 1036 * Tx DMA FIFOs have dedicated purposes. 1037 * 1038 * For 5000 series and up, they are used differently 1039 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1040 * 1041 * 0 -- EDCA BK (background) frames, lowest priority 1042 * 1 -- EDCA BE (best effort) frames, normal priority 1043 * 2 -- EDCA VI (video) frames, higher priority 1044 * 3 -- EDCA VO (voice) and management frames, highest priority 1045 * 4 -- unused 1046 * 5 -- unused 1047 * 6 -- unused 1048 * 7 -- Commands 1049 * 1050 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1051 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1052 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1053 * 1054 * The driver sets up each queue to work in one of two modes: 1055 * 1056 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1057 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1058 * contains TFDs for a unique combination of Recipient Address (RA) 1059 * and Traffic Identifier (TID), that is, traffic of a given 1060 * Quality-Of-Service (QOS) priority, destined for a single station. 1061 * 1062 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1063 * each frame within the BA window, including whether it's been transmitted, 1064 * and whether it's been acknowledged by the receiving station. The device 1065 * automatically processes block-acks received from the receiving STA, 1066 * and reschedules un-acked frames to be retransmitted (successful 1067 * Tx completion may end up being out-of-order). 1068 * 1069 * The driver must maintain the queue's Byte Count table in host DRAM 1070 * for this mode. 1071 * This mode does not support fragmentation. 1072 * 1073 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1074 * The device may automatically retry Tx, but will retry only one frame 1075 * at a time, until receiving ACK from receiving station, or reaching 1076 * retry limit and giving up. 1077 * 1078 * The command queue (#4/#9) must use this mode! 1079 * This mode does not require use of the Byte Count table in host DRAM. 1080 * 1081 * Driver controls scheduler operation via 3 means: 1082 * 1) Scheduler registers 1083 * 2) Shared scheduler data base in internal SRAM 1084 * 3) Shared data in host DRAM 1085 * 1086 * Initialization: 1087 * 1088 * When loading, driver should allocate memory for: 1089 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1090 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1091 * (1024 bytes for each queue). 1092 * 1093 * After receiving "Alive" response from uCode, driver must initialize 1094 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1095 * the driver can't issue commands!): 1096 */ 1097 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1098 1099 /** 1100 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1101 * can keep track of at one time when creating block-ack chains of frames. 1102 * Note that "64" matches the number of ack bits in a block-ack packet. 1103 */ 1104 #define IWM_SCD_WIN_SIZE 64 1105 #define IWM_SCD_FRAME_LIMIT 64 1106 1107 #define IWM_SCD_TXFIFO_POS_TID (0) 1108 #define IWM_SCD_TXFIFO_POS_RA (4) 1109 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1110 1111 /* agn SCD */ 1112 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1113 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1114 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1115 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1116 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1117 1118 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1119 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1120 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1121 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1122 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1123 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1124 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1125 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1126 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1127 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1128 1129 /* Context Data */ 1130 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1131 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1132 1133 /* Tx status */ 1134 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1135 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1136 1137 /* Translation Data */ 1138 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1139 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1140 1141 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1142 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1143 1144 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1145 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1146 1147 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1148 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1149 1150 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1151 1152 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1153 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1154 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1155 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1156 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1157 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1158 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1159 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1160 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1161 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1162 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1163 1164 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1165 { 1166 if (chnl < 20) 1167 return IWM_SCD_BASE + 0x18 + chnl * 4; 1168 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1169 } 1170 1171 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1172 { 1173 if (chnl < 20) 1174 return IWM_SCD_BASE + 0x68 + chnl * 4; 1175 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1176 } 1177 1178 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1179 { 1180 if (chnl < 20) 1181 return IWM_SCD_BASE + 0x10c + chnl * 4; 1182 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1183 } 1184 1185 /*********************** END TX SCHEDULER *************************************/ 1186 1187 /* Oscillator clock */ 1188 #define IWM_OSC_CLK (0xa04068) 1189 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1190 1191 /****************************/ 1192 /* Flow Handler Definitions */ 1193 /****************************/ 1194 1195 /** 1196 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1197 * Addresses are offsets from device's PCI hardware base address. 1198 */ 1199 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1200 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1201 1202 /** 1203 * Keep-Warm (KW) buffer base address. 1204 * 1205 * Driver must allocate a 4KByte buffer that is for keeping the 1206 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1207 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1208 * from going into a power-savings mode that would cause higher DRAM latency, 1209 * and possible data over/under-runs, before all Tx/Rx is complete. 1210 * 1211 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1212 * of the buffer, which must be 4K aligned. Once this is set up, the device 1213 * automatically invokes keep-warm accesses when normal accesses might not 1214 * be sufficient to maintain fast DRAM response. 1215 * 1216 * Bit fields: 1217 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1218 */ 1219 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1220 1221 1222 /** 1223 * TFD Circular Buffers Base (CBBC) addresses 1224 * 1225 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1226 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1227 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1228 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1229 * aligned (address bits 0-7 must be 0). 1230 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1231 * for them are in different places. 1232 * 1233 * Bit fields in each pointer register: 1234 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1235 */ 1236 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1237 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1238 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1239 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1240 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1241 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1242 1243 /* Find TFD CB base pointer for given queue */ 1244 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1245 { 1246 if (chnl < 16) 1247 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1248 if (chnl < 20) 1249 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1250 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1251 } 1252 1253 1254 /** 1255 * Rx SRAM Control and Status Registers (RSCSR) 1256 * 1257 * These registers provide handshake between driver and device for the Rx queue 1258 * (this queue handles *all* command responses, notifications, Rx data, etc. 1259 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1260 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1261 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1262 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1263 * mapping between RBDs and RBs. 1264 * 1265 * Driver must allocate host DRAM memory for the following, and set the 1266 * physical address of each into device registers: 1267 * 1268 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1269 * entries (although any power of 2, up to 4096, is selectable by driver). 1270 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1271 * (typically 4K, although 8K or 16K are also selectable by driver). 1272 * Driver sets up RB size and number of RBDs in the CB via Rx config 1273 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1274 * 1275 * Bit fields within one RBD: 1276 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1277 * 1278 * Driver sets physical address [35:8] of base of RBD circular buffer 1279 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1280 * 1281 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1282 * (RBs) have been filled, via a "write pointer", actually the index of 1283 * the RB's corresponding RBD within the circular buffer. Driver sets 1284 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1285 * 1286 * Bit fields in lower dword of Rx status buffer (upper dword not used 1287 * by driver: 1288 * 31-12: Not used by driver 1289 * 11- 0: Index of last filled Rx buffer descriptor 1290 * (device writes, driver reads this value) 1291 * 1292 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1293 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1294 * and update the device's "write" index register, 1295 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1296 * 1297 * This "write" index corresponds to the *next* RBD that the driver will make 1298 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1299 * the circular buffer. This value should initially be 0 (before preparing any 1300 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1301 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1302 * "read" index has advanced past 1! See below). 1303 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1304 * 1305 * As the device fills RBs (referenced from contiguous RBDs within the circular 1306 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1307 * to tell the driver the index of the latest filled RBD. The driver must 1308 * read this "read" index from DRAM after receiving an Rx interrupt from device 1309 * 1310 * The driver must also internally keep track of a third index, which is the 1311 * next RBD to process. When receiving an Rx interrupt, driver should process 1312 * all filled but unprocessed RBs up to, but not including, the RB 1313 * corresponding to the "read" index. For example, if "read" index becomes "1", 1314 * driver may process the RB pointed to by RBD 0. Depending on volume of 1315 * traffic, there may be many RBs to process. 1316 * 1317 * If read index == write index, device thinks there is no room to put new data. 1318 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1319 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1320 * and "read" indexes; that is, make sure that there are no more than 254 1321 * buffers waiting to be filled. 1322 */ 1323 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1324 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1325 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1326 1327 /** 1328 * Physical base address of 8-byte Rx Status buffer. 1329 * Bit fields: 1330 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1331 */ 1332 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1333 1334 /** 1335 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1336 * Bit fields: 1337 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1338 */ 1339 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1340 1341 /** 1342 * Rx write pointer (index, really!). 1343 * Bit fields: 1344 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1345 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1346 */ 1347 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1348 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1349 1350 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1351 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1352 1353 /** 1354 * Rx Config/Status Registers (RCSR) 1355 * Rx Config Reg for channel 0 (only channel used) 1356 * 1357 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1358 * normal operation (see bit fields). 1359 * 1360 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1361 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1362 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1363 * 1364 * Bit fields: 1365 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1366 * '10' operate normally 1367 * 29-24: reserved 1368 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1369 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1370 * 19-18: reserved 1371 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1372 * '10' 12K, '11' 16K. 1373 * 15-14: reserved 1374 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1375 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1376 * typical value 0x10 (about 1/2 msec) 1377 * 3- 0: reserved 1378 */ 1379 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1380 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1381 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1382 1383 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1384 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1385 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1386 1387 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1388 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1389 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1390 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1391 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1392 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1393 1394 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1395 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1396 #define IWM_RX_RB_TIMEOUT (0x11) 1397 1398 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1399 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1400 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1401 1402 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1403 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1404 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1405 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1406 1407 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1408 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1409 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1410 1411 /** 1412 * Rx Shared Status Registers (RSSR) 1413 * 1414 * After stopping Rx DMA channel (writing 0 to 1415 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1416 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1417 * 1418 * Bit fields: 1419 * 24: 1 = Channel 0 is idle 1420 * 1421 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1422 * contain default values that should not be altered by the driver. 1423 */ 1424 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1425 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1426 1427 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1428 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1429 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1430 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1431 1432 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1433 1434 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1435 1436 /* TFDB Area - TFDs buffer table */ 1437 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1438 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1439 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1440 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1441 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1442 1443 /** 1444 * Transmit DMA Channel Control/Status Registers (TCSR) 1445 * 1446 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1447 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1448 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1449 * 1450 * To use a Tx DMA channel, driver must initialize its 1451 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1452 * 1453 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1454 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1455 * 1456 * All other bits should be 0. 1457 * 1458 * Bit fields: 1459 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1460 * '10' operate normally 1461 * 29- 4: Reserved, set to "0" 1462 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1463 * 2- 0: Reserved, set to "0" 1464 */ 1465 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1466 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1467 1468 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1469 #define IWM_FH_TCSR_CHNL_NUM (8) 1470 1471 /* TCSR: tx_config register values */ 1472 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1473 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1474 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1475 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1476 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1477 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1478 1479 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1480 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1481 1482 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1483 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1484 1485 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1486 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1487 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1488 1489 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1490 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1491 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1492 1493 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1494 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1495 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1496 1497 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1498 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1499 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1500 1501 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1502 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1503 1504 /** 1505 * Tx Shared Status Registers (TSSR) 1506 * 1507 * After stopping Tx DMA channel (writing 0 to 1508 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1509 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1510 * (channel's buffers empty | no pending requests). 1511 * 1512 * Bit fields: 1513 * 31-24: 1 = Channel buffers empty (channel 7:0) 1514 * 23-16: 1 = No pending requests (channel 7:0) 1515 */ 1516 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1517 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1518 1519 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1520 1521 /** 1522 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1523 * 31: Indicates an address error when accessed to internal memory 1524 * uCode/driver must write "1" in order to clear this flag 1525 * 30: Indicates that Host did not send the expected number of dwords to FH 1526 * uCode/driver must write "1" in order to clear this flag 1527 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1528 * command was received from the scheduler while the TRB was already full 1529 * with previous command 1530 * uCode/driver must write "1" in order to clear this flag 1531 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1532 * bit is set, it indicates that the FH has received a full indication 1533 * from the RTC TxFIFO and the current value of the TxCredit counter was 1534 * not equal to zero. This mean that the credit mechanism was not 1535 * synchronized to the TxFIFO status 1536 * uCode/driver must write "1" in order to clear this flag 1537 */ 1538 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1539 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1540 1541 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1542 1543 /* Tx service channels */ 1544 #define IWM_FH_SRVC_CHNL (9) 1545 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1546 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1547 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1548 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1549 1550 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1551 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1552 (_chan) * 4) 1553 1554 /* Instruct FH to increment the retry count of a packet when 1555 * it is brought from the memory to TX-FIFO 1556 */ 1557 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1558 1559 #define IWM_RX_QUEUE_SIZE 256 1560 #define IWM_RX_QUEUE_MASK 255 1561 #define IWM_RX_QUEUE_SIZE_LOG 8 1562 1563 /* 1564 * RX related structures and functions 1565 */ 1566 #define IWM_RX_FREE_BUFFERS 64 1567 #define IWM_RX_LOW_WATERMARK 8 1568 1569 /** 1570 * struct iwm_rb_status - reseve buffer status 1571 * host memory mapped FH registers 1572 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1573 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1574 * @finished_rb_num [0:11] - Indicates the index of the current RB 1575 * in which the last frame was written to 1576 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1577 * which was transferred 1578 */ 1579 struct iwm_rb_status { 1580 uint16_t closed_rb_num; 1581 uint16_t closed_fr_num; 1582 uint16_t finished_rb_num; 1583 uint16_t finished_fr_nam; 1584 uint32_t unused; 1585 } __packed; 1586 1587 1588 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1589 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1590 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1591 IWM_TFD_QUEUE_SIZE_BC_DUP) 1592 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1593 #define IWM_NUM_OF_TBS 20 1594 1595 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1596 { 1597 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1598 } 1599 /** 1600 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1601 * 1602 * This structure contains dma address and length of transmission address 1603 * 1604 * @lo: low [31:0] portion of the dma address of TX buffer 1605 * every even is unaligned on 16 bit boundary 1606 * @hi_n_len 0-3 [35:32] portion of dma 1607 * 4-15 length of the tx buffer 1608 */ 1609 struct iwm_tfd_tb { 1610 uint32_t lo; 1611 uint16_t hi_n_len; 1612 } __packed; 1613 1614 /** 1615 * struct iwm_tfd 1616 * 1617 * Transmit Frame Descriptor (TFD) 1618 * 1619 * @ __reserved1[3] reserved 1620 * @ num_tbs 0-4 number of active tbs 1621 * 5 reserved 1622 * 6-7 padding (not used) 1623 * @ tbs[20] transmit frame buffer descriptors 1624 * @ __pad padding 1625 * 1626 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1627 * Both driver and device share these circular buffers, each of which must be 1628 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1629 * 1630 * Driver must indicate the physical address of the base of each 1631 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1632 * 1633 * Each TFD contains pointer/size information for up to 20 data buffers 1634 * in host DRAM. These buffers collectively contain the (one) frame described 1635 * by the TFD. Each buffer must be a single contiguous block of memory within 1636 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1637 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1638 * Tx frame, up to 8 KBytes in size. 1639 * 1640 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1641 */ 1642 struct iwm_tfd { 1643 uint8_t __reserved1[3]; 1644 uint8_t num_tbs; 1645 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1646 uint32_t __pad; 1647 } __packed; 1648 1649 /* Keep Warm Size */ 1650 #define IWM_KW_SIZE 0x1000 /* 4k */ 1651 1652 /* Fixed (non-configurable) rx data from phy */ 1653 1654 /** 1655 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1656 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1657 * @tfd_offset 0-12 - tx command byte count 1658 * 12-16 - station index 1659 */ 1660 struct iwm_agn_scd_bc_tbl { 1661 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1662 } __packed; 1663 1664 /* Maximum number of Tx queues. */ 1665 #define IWM_MVM_MAX_QUEUES 31 1666 1667 /* Tx queue numbers */ 1668 enum { 1669 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1670 IWM_MVM_CMD_QUEUE = 9, 1671 IWM_MVM_AUX_QUEUE = 15, 1672 }; 1673 1674 enum iwm_mvm_tx_fifo { 1675 IWM_MVM_TX_FIFO_BK = 0, 1676 IWM_MVM_TX_FIFO_BE, 1677 IWM_MVM_TX_FIFO_VI, 1678 IWM_MVM_TX_FIFO_VO, 1679 IWM_MVM_TX_FIFO_MCAST = 5, 1680 IWM_MVM_TX_FIFO_CMD = 7, 1681 }; 1682 1683 #define IWM_MVM_STATION_COUNT 16 1684 1685 /* commands */ 1686 enum { 1687 IWM_MVM_ALIVE = 0x1, 1688 IWM_REPLY_ERROR = 0x2, 1689 1690 IWM_INIT_COMPLETE_NOTIF = 0x4, 1691 1692 /* PHY context commands */ 1693 IWM_PHY_CONTEXT_CMD = 0x8, 1694 IWM_DBG_CFG = 0x9, 1695 1696 /* UMAC scan commands */ 1697 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1698 IWM_SCAN_CFG_CMD = 0xc, 1699 IWM_SCAN_REQ_UMAC = 0xd, 1700 IWM_SCAN_ABORT_UMAC = 0xe, 1701 IWM_SCAN_COMPLETE_UMAC = 0xf, 1702 1703 /* station table */ 1704 IWM_ADD_STA_KEY = 0x17, 1705 IWM_ADD_STA = 0x18, 1706 IWM_REMOVE_STA = 0x19, 1707 1708 /* TX */ 1709 IWM_TX_CMD = 0x1c, 1710 IWM_TXPATH_FLUSH = 0x1e, 1711 IWM_MGMT_MCAST_KEY = 0x1f, 1712 1713 /* scheduler config */ 1714 IWM_SCD_QUEUE_CFG = 0x1d, 1715 1716 /* global key */ 1717 IWM_WEP_KEY = 0x20, 1718 1719 /* MAC and Binding commands */ 1720 IWM_MAC_CONTEXT_CMD = 0x28, 1721 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1722 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1723 IWM_BINDING_CONTEXT_CMD = 0x2b, 1724 IWM_TIME_QUOTA_CMD = 0x2c, 1725 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1726 1727 IWM_LQ_CMD = 0x4e, 1728 1729 /* paging block to FW cpu2 */ 1730 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1731 1732 /* Scan offload */ 1733 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1734 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1735 IWM_HOT_SPOT_CMD = 0x53, 1736 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1737 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1738 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1739 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1740 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1741 1742 /* Phy */ 1743 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1744 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1745 IWM_PHY_DB_CMD = 0x6c, 1746 1747 /* Power - legacy power table command */ 1748 IWM_POWER_TABLE_CMD = 0x77, 1749 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1750 IWM_LTR_CONFIG = 0xee, 1751 1752 /* Thermal Throttling*/ 1753 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1754 1755 /* NVM */ 1756 IWM_NVM_ACCESS_CMD = 0x88, 1757 1758 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1759 1760 IWM_BEACON_NOTIFICATION = 0x90, 1761 IWM_BEACON_TEMPLATE_CMD = 0x91, 1762 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1763 IWM_BT_CONFIG = 0x9b, 1764 IWM_STATISTICS_NOTIFICATION = 0x9d, 1765 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1766 1767 /* RF-KILL commands and notifications */ 1768 IWM_CARD_STATE_CMD = 0xa0, 1769 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1770 1771 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1772 1773 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1774 1775 /* Power - new power table command */ 1776 IWM_MAC_PM_POWER_TABLE = 0xa9, 1777 1778 IWM_REPLY_RX_PHY_CMD = 0xc0, 1779 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1780 IWM_BA_NOTIF = 0xc5, 1781 1782 /* Location Aware Regulatory */ 1783 IWM_MCC_UPDATE_CMD = 0xc8, 1784 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1785 1786 /* BT Coex */ 1787 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1788 IWM_BT_COEX_PROT_ENV = 0xcd, 1789 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1790 IWM_BT_COEX_CI = 0x5d, 1791 1792 IWM_REPLY_SF_CFG_CMD = 0xd1, 1793 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1794 1795 /* DTS measurements */ 1796 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1797 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1798 1799 IWM_REPLY_DEBUG_CMD = 0xf0, 1800 IWM_DEBUG_LOG_MSG = 0xf7, 1801 1802 IWM_MCAST_FILTER_CMD = 0xd0, 1803 1804 /* D3 commands/notifications */ 1805 IWM_D3_CONFIG_CMD = 0xd3, 1806 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1807 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1808 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1809 1810 /* for WoWLAN in particular */ 1811 IWM_WOWLAN_PATTERNS = 0xe0, 1812 IWM_WOWLAN_CONFIGURATION = 0xe1, 1813 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1814 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1815 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1816 IWM_WOWLAN_GET_STATUSES = 0xe5, 1817 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1818 1819 /* and for NetDetect */ 1820 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1821 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1822 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1823 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1824 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1825 }; 1826 1827 enum iwm_phy_ops_subcmd_ids { 1828 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1829 IWM_CTDP_CONFIG_CMD = 0x03, 1830 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1831 IWM_CT_KILL_NOTIFICATION = 0xFE, 1832 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1833 }; 1834 1835 /* command groups */ 1836 enum { 1837 IWM_LEGACY_GROUP = 0x0, 1838 IWM_LONG_GROUP = 0x1, 1839 IWM_SYSTEM_GROUP = 0x2, 1840 IWM_MAC_CONF_GROUP = 0x3, 1841 IWM_PHY_OPS_GROUP = 0x4, 1842 IWM_DATA_PATH_GROUP = 0x5, 1843 IWM_PROT_OFFLOAD_GROUP = 0xb, 1844 }; 1845 1846 /** 1847 * struct iwm_cmd_response - generic response struct for most commands 1848 * @status: status of the command asked, changes for each one 1849 */ 1850 struct iwm_cmd_response { 1851 uint32_t status; 1852 }; 1853 1854 /* 1855 * struct iwm_tx_ant_cfg_cmd 1856 * @valid: valid antenna configuration 1857 */ 1858 struct iwm_tx_ant_cfg_cmd { 1859 uint32_t valid; 1860 } __packed; 1861 1862 /** 1863 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1864 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1865 * @flags: (reserved for future implementation) 1866 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1867 * @pwr_restriction: TX power restriction in dBms. 1868 */ 1869 struct iwm_reduce_tx_power_cmd { 1870 uint8_t flags; 1871 uint8_t mac_context_id; 1872 uint16_t pwr_restriction; 1873 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1874 1875 enum iwm_dev_tx_power_cmd_mode { 1876 IWM_TX_POWER_MODE_SET_MAC = 0, 1877 IWM_TX_POWER_MODE_SET_DEVICE = 1, 1878 IWM_TX_POWER_MODE_SET_CHAINS = 2, 1879 IWM_TX_POWER_MODE_SET_ACK = 3, 1880 }; /* TX_POWER_REDUCED_FLAGS_TYPE_API_E_VER_4 */ 1881 1882 #define IWM_NUM_CHAIN_LIMITS 2 1883 #define IWM_NUM_SUB_BANDS 5 1884 1885 /** 1886 * struct iwm_dev_tx_power_cmd - TX power reduction command 1887 * @set_mode: see &enum iwl_dev_tx_power_cmd_mode 1888 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1889 * @pwr_restriction: TX power restriction in 1/8 dBms. 1890 * @dev_24: device TX power restriction in 1/8 dBms 1891 * @dev_52_low: device TX power restriction upper band - low 1892 * @dev_52_high: device TX power restriction upper band - high 1893 * @per_chain_restriction: per chain restrictions 1894 */ 1895 struct iwm_dev_tx_power_cmd_v3 { 1896 uint32_t set_mode; 1897 uint32_t mac_context_id; 1898 uint16_t pwr_restriction; 1899 uint16_t dev_24; 1900 uint16_t dev_52_low; 1901 uint16_t dev_52_high; 1902 uint16_t per_chain_restriction[IWM_NUM_CHAIN_LIMITS][IWM_NUM_SUB_BANDS]; 1903 } __packed; /* TX_REDUCED_POWER_API_S_VER_3 */ 1904 1905 #define IWM_DEV_MAX_TX_POWER 0x7FFF 1906 1907 /** 1908 * struct iwm_dev_tx_power_cmd - TX power reduction command 1909 * @v3: version 3 of the command, embedded here for easier software handling 1910 * @enable_ack_reduction: enable or disable close range ack TX power 1911 * reduction. 1912 */ 1913 struct iwm_dev_tx_power_cmd { 1914 /* v4 is just an extension of v3 - keep this here */ 1915 struct iwm_dev_tx_power_cmd_v3 v3; 1916 uint8_t enable_ack_reduction; 1917 uint8_t reserved[3]; 1918 } __packed; /* TX_REDUCED_POWER_API_S_VER_4 */ 1919 1920 /* 1921 * Calibration control struct. 1922 * Sent as part of the phy configuration command. 1923 * @flow_trigger: bitmap for which calibrations to perform according to 1924 * flow triggers. 1925 * @event_trigger: bitmap for which calibrations to perform according to 1926 * event triggers. 1927 */ 1928 struct iwm_calib_ctrl { 1929 uint32_t flow_trigger; 1930 uint32_t event_trigger; 1931 } __packed; 1932 1933 /* This enum defines the bitmap of various calibrations to enable in both 1934 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1935 */ 1936 enum iwm_calib_cfg { 1937 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1938 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1939 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1940 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1941 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1942 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1943 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1944 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1945 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1946 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1947 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1948 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1949 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1950 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1951 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1952 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1953 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1954 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1955 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1956 }; 1957 1958 /* 1959 * Phy configuration command. 1960 */ 1961 struct iwm_phy_cfg_cmd { 1962 uint32_t phy_cfg; 1963 struct iwm_calib_ctrl calib_control; 1964 } __packed; 1965 1966 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1967 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1968 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1969 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1970 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1971 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1972 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1973 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1974 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 1975 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 1976 1977 1978 /* Target of the IWM_NVM_ACCESS_CMD */ 1979 enum { 1980 IWM_NVM_ACCESS_TARGET_CACHE = 0, 1981 IWM_NVM_ACCESS_TARGET_OTP = 1, 1982 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 1983 }; 1984 1985 /* Section types for IWM_NVM_ACCESS_CMD */ 1986 enum { 1987 IWM_NVM_SECTION_TYPE_SW = 1, 1988 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 1989 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 1990 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 1991 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 1992 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 1993 IWM_NVM_MAX_NUM_SECTIONS = 13, 1994 }; 1995 1996 /** 1997 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 1998 * @op_code: 0 - read, 1 - write 1999 * @target: IWM_NVM_ACCESS_TARGET_* 2000 * @type: IWM_NVM_SECTION_TYPE_* 2001 * @offset: offset in bytes into the section 2002 * @length: in bytes, to read/write 2003 * @data: if write operation, the data to write. On read its empty 2004 */ 2005 struct iwm_nvm_access_cmd { 2006 uint8_t op_code; 2007 uint8_t target; 2008 uint16_t type; 2009 uint16_t offset; 2010 uint16_t length; 2011 uint8_t data[]; 2012 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2013 2014 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2015 2016 /* 2017 * struct iwm_fw_paging_cmd - paging layout 2018 * 2019 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2020 * 2021 * Send to FW the paging layout in the driver. 2022 * 2023 * @flags: various flags for the command 2024 * @block_size: the block size in powers of 2 2025 * @block_num: number of blocks specified in the command. 2026 * @device_phy_addr: virtual addresses from device side 2027 */ 2028 struct iwm_fw_paging_cmd { 2029 uint32_t flags; 2030 uint32_t block_size; 2031 uint32_t block_num; 2032 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2033 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2034 2035 /* 2036 * Fw items ID's 2037 * 2038 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2039 * download 2040 */ 2041 enum iwm_fw_item_id { 2042 IWM_FW_ITEM_ID_PAGING = 3, 2043 }; 2044 2045 /* 2046 * struct iwm_fw_get_item_cmd - get an item from the fw 2047 */ 2048 struct iwm_fw_get_item_cmd { 2049 uint32_t item_id; 2050 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2051 2052 /** 2053 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2054 * @offset: offset in bytes into the section 2055 * @length: in bytes, either how much was written or read 2056 * @type: IWM_NVM_SECTION_TYPE_* 2057 * @status: 0 for success, fail otherwise 2058 * @data: if read operation, the data returned. Empty on write. 2059 */ 2060 struct iwm_nvm_access_resp { 2061 uint16_t offset; 2062 uint16_t length; 2063 uint16_t type; 2064 uint16_t status; 2065 uint8_t data[]; 2066 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2067 2068 /* IWM_MVM_ALIVE 0x1 */ 2069 2070 /* alive response is_valid values */ 2071 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2072 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2073 2074 /* alive response ver_type values */ 2075 enum { 2076 IWM_FW_TYPE_HW = 0, 2077 IWM_FW_TYPE_PROT = 1, 2078 IWM_FW_TYPE_AP = 2, 2079 IWM_FW_TYPE_WOWLAN = 3, 2080 IWM_FW_TYPE_TIMING = 4, 2081 IWM_FW_TYPE_WIPAN = 5 2082 }; 2083 2084 /* alive response ver_subtype values */ 2085 enum { 2086 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2087 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2088 IWM_FW_SUBTYPE_REDUCED = 2, 2089 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2090 IWM_FW_SUBTYPE_WOWLAN = 4, 2091 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2092 IWM_FW_SUBTYPE_WIPAN = 6, 2093 IWM_FW_SUBTYPE_INITIALIZE = 9 2094 }; 2095 2096 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2097 #define IWM_ALIVE_STATUS_OK 0xCAFE 2098 2099 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2100 2101 struct iwm_lmac_alive { 2102 uint32_t ucode_major; 2103 uint32_t ucode_minor; 2104 uint8_t ver_subtype; 2105 uint8_t ver_type; 2106 uint8_t mac; 2107 uint8_t opt; 2108 uint32_t timestamp; 2109 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2110 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2111 uint32_t cpu_register_ptr; 2112 uint32_t dbgm_config_ptr; 2113 uint32_t alive_counter_ptr; 2114 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2115 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2116 uint32_t st_fwrd_size; 2117 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */ 2118 2119 struct iwm_umac_alive { 2120 uint32_t umac_major; /* UMAC version: major */ 2121 uint32_t umac_minor; /* UMAC version: minor */ 2122 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2123 uint32_t dbg_print_buff_addr; 2124 } __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */ 2125 2126 struct iwm_mvm_alive_resp_v3 { 2127 uint16_t status; 2128 uint16_t flags; 2129 struct iwm_lmac_alive lmac_data; 2130 struct iwm_umac_alive umac_data; 2131 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2132 2133 struct iwm_mvm_alive_resp { 2134 uint16_t status; 2135 uint16_t flags; 2136 struct iwm_lmac_alive lmac_data[2]; 2137 struct iwm_umac_alive umac_data; 2138 } __packed; /* ALIVE_RES_API_S_VER_4 */ 2139 2140 /* Error response/notification */ 2141 enum { 2142 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2143 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2144 IWM_FW_ERR_SERVICE = 0x2, 2145 IWM_FW_ERR_ARC_MEMORY = 0x3, 2146 IWM_FW_ERR_ARC_CODE = 0x4, 2147 IWM_FW_ERR_WATCH_DOG = 0x5, 2148 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2149 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2150 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2151 IWM_FW_ERR_UNEXPECTED = 0xFE, 2152 IWM_FW_ERR_FATAL = 0xFF 2153 }; 2154 2155 /** 2156 * struct iwm_error_resp - FW error indication 2157 * ( IWM_REPLY_ERROR = 0x2 ) 2158 * @error_type: one of IWM_FW_ERR_* 2159 * @cmd_id: the command ID for which the error occurred 2160 * @bad_cmd_seq_num: sequence number of the erroneous command 2161 * @error_service: which service created the error, applicable only if 2162 * error_type = 2, otherwise 0 2163 * @timestamp: TSF in usecs. 2164 */ 2165 struct iwm_error_resp { 2166 uint32_t error_type; 2167 uint8_t cmd_id; 2168 uint8_t reserved1; 2169 uint16_t bad_cmd_seq_num; 2170 uint32_t error_service; 2171 uint64_t timestamp; 2172 } __packed; 2173 2174 2175 /* Common PHY, MAC and Bindings definitions */ 2176 2177 #define IWM_MAX_MACS_IN_BINDING (3) 2178 #define IWM_MAX_BINDINGS (4) 2179 #define IWM_AUX_BINDING_INDEX (3) 2180 #define IWM_MAX_PHYS (4) 2181 2182 /* Used to extract ID and color from the context dword */ 2183 #define IWM_FW_CTXT_ID_POS (0) 2184 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2185 #define IWM_FW_CTXT_COLOR_POS (8) 2186 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2187 #define IWM_FW_CTXT_INVALID (0xffffffff) 2188 2189 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2190 (_color << IWM_FW_CTXT_COLOR_POS)) 2191 2192 /* Possible actions on PHYs, MACs and Bindings */ 2193 enum { 2194 IWM_FW_CTXT_ACTION_STUB = 0, 2195 IWM_FW_CTXT_ACTION_ADD, 2196 IWM_FW_CTXT_ACTION_MODIFY, 2197 IWM_FW_CTXT_ACTION_REMOVE, 2198 IWM_FW_CTXT_ACTION_NUM 2199 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2200 2201 /* Time Events */ 2202 2203 /* Time Event types, according to MAC type */ 2204 enum iwm_time_event_type { 2205 /* BSS Station Events */ 2206 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2207 IWM_TE_BSS_STA_ASSOC, 2208 IWM_TE_BSS_EAP_DHCP_PROT, 2209 IWM_TE_BSS_QUIET_PERIOD, 2210 2211 /* P2P Device Events */ 2212 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2213 IWM_TE_P2P_DEVICE_LISTEN, 2214 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2215 IWM_TE_P2P_DEVICE_FULL_SCAN, 2216 2217 /* P2P Client Events */ 2218 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2219 IWM_TE_P2P_CLIENT_ASSOC, 2220 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2221 2222 /* P2P GO Events */ 2223 IWM_TE_P2P_GO_ASSOC_PROT, 2224 IWM_TE_P2P_GO_REPETITIVE_NOA, 2225 IWM_TE_P2P_GO_CT_WINDOW, 2226 2227 /* WiDi Sync Events */ 2228 IWM_TE_WIDI_TX_SYNC, 2229 2230 IWM_TE_MAX 2231 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2232 2233 2234 2235 /* Time event - defines for command API v1 */ 2236 2237 /* 2238 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2239 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2240 * the first fragment is scheduled. 2241 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2242 * the first 2 fragments are scheduled. 2243 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2244 * number of fragments are valid. 2245 * 2246 * Other than the constant defined above, specifying a fragmentation value 'x' 2247 * means that the event can be fragmented but only the first 'x' will be 2248 * scheduled. 2249 */ 2250 enum { 2251 IWM_TE_V1_FRAG_NONE = 0, 2252 IWM_TE_V1_FRAG_SINGLE = 1, 2253 IWM_TE_V1_FRAG_DUAL = 2, 2254 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2255 }; 2256 2257 /* If a Time Event can be fragmented, this is the max number of fragments */ 2258 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2259 /* Repeat the time event endlessly (until removed) */ 2260 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2261 /* If a Time Event has bounded repetitions, this is the maximal value */ 2262 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2263 2264 /* Time Event dependencies: none, on another TE, or in a specific time */ 2265 enum { 2266 IWM_TE_V1_INDEPENDENT = 0, 2267 IWM_TE_V1_DEP_OTHER = (1 << 0), 2268 IWM_TE_V1_DEP_TSF = (1 << 1), 2269 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2270 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2271 2272 /* 2273 * @IWM_TE_V1_NOTIF_NONE: no notifications 2274 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2275 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2276 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2277 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2278 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2279 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2280 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2281 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2282 * 2283 * Supported Time event notifications configuration. 2284 * A notification (both event and fragment) includes a status indicating weather 2285 * the FW was able to schedule the event or not. For fragment start/end 2286 * notification the status is always success. There is no start/end fragment 2287 * notification for monolithic events. 2288 */ 2289 enum { 2290 IWM_TE_V1_NOTIF_NONE = 0, 2291 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2292 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2293 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2294 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2295 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2296 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2297 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2298 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2299 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2300 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2301 2302 /* Time event - defines for command API */ 2303 2304 /* 2305 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2306 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2307 * the first fragment is scheduled. 2308 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2309 * the first 2 fragments are scheduled. 2310 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2311 * number of fragments are valid. 2312 * 2313 * Other than the constant defined above, specifying a fragmentation value 'x' 2314 * means that the event can be fragmented but only the first 'x' will be 2315 * scheduled. 2316 */ 2317 enum { 2318 IWM_TE_V2_FRAG_NONE = 0, 2319 IWM_TE_V2_FRAG_SINGLE = 1, 2320 IWM_TE_V2_FRAG_DUAL = 2, 2321 IWM_TE_V2_FRAG_MAX = 0xfe, 2322 IWM_TE_V2_FRAG_ENDLESS = 0xff 2323 }; 2324 2325 /* Repeat the time event endlessly (until removed) */ 2326 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2327 /* If a Time Event has bounded repetitions, this is the maximal value */ 2328 #define IWM_TE_V2_REPEAT_MAX 0xfe 2329 2330 #define IWM_TE_V2_PLACEMENT_POS 12 2331 #define IWM_TE_V2_ABSENCE_POS 15 2332 2333 /* Time event policy values 2334 * A notification (both event and fragment) includes a status indicating weather 2335 * the FW was able to schedule the event or not. For fragment start/end 2336 * notification the status is always success. There is no start/end fragment 2337 * notification for monolithic events. 2338 * 2339 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2340 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2341 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2342 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2343 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2344 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2345 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2346 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2347 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2348 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2349 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2350 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2351 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2352 */ 2353 enum { 2354 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2355 2356 /* notifications (event start/stop, fragment start/stop) */ 2357 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2358 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2359 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2360 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2361 2362 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2363 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2364 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2365 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2366 2367 IWM_TE_V2_NOTIF_MSK = 0xff, 2368 2369 /* placement characteristics */ 2370 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2371 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2372 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2373 2374 /* are we present or absent during the Time Event. */ 2375 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2376 }; 2377 2378 /** 2379 * struct iwm_time_event_cmd_api - configuring Time Events 2380 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2381 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2382 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2383 * @id_and_color: ID and color of the relevant MAC 2384 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2385 * @id: this field has two meanings, depending on the action: 2386 * If the action is ADD, then it means the type of event to add. 2387 * For all other actions it is the unique event ID assigned when the 2388 * event was added by the FW. 2389 * @apply_time: When to start the Time Event (in GP2) 2390 * @max_delay: maximum delay to event's start (apply time), in TU 2391 * @depends_on: the unique ID of the event we depend on (if any) 2392 * @interval: interval between repetitions, in TU 2393 * @duration: duration of event in TU 2394 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2395 * @max_frags: maximal number of fragments the Time Event can be divided to 2396 * @policy: defines whether uCode shall notify the host or other uCode modules 2397 * on event and/or fragment start and/or end 2398 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2399 * IWM_TE_EVENT_SOCIOPATHIC 2400 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2401 */ 2402 struct iwm_time_event_cmd { 2403 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2404 uint32_t id_and_color; 2405 uint32_t action; 2406 uint32_t id; 2407 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2408 uint32_t apply_time; 2409 uint32_t max_delay; 2410 uint32_t depends_on; 2411 uint32_t interval; 2412 uint32_t duration; 2413 uint8_t repeat; 2414 uint8_t max_frags; 2415 uint16_t policy; 2416 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2417 2418 /** 2419 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2420 * @status: bit 0 indicates success, all others specify errors 2421 * @id: the Time Event type 2422 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2423 * @id_and_color: ID and color of the relevant MAC 2424 */ 2425 struct iwm_time_event_resp { 2426 uint32_t status; 2427 uint32_t id; 2428 uint32_t unique_id; 2429 uint32_t id_and_color; 2430 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2431 2432 /** 2433 * struct iwm_time_event_notif - notifications of time event start/stop 2434 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2435 * @timestamp: action timestamp in GP2 2436 * @session_id: session's unique id 2437 * @unique_id: unique id of the Time Event itself 2438 * @id_and_color: ID and color of the relevant MAC 2439 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2440 * @status: true if scheduled, false otherwise (not executed) 2441 */ 2442 struct iwm_time_event_notif { 2443 uint32_t timestamp; 2444 uint32_t session_id; 2445 uint32_t unique_id; 2446 uint32_t id_and_color; 2447 uint32_t action; 2448 uint32_t status; 2449 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2450 2451 2452 /* Bindings and Time Quota */ 2453 2454 /** 2455 * struct iwm_binding_cmd - configuring bindings 2456 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2457 * @id_and_color: ID and color of the relevant Binding 2458 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2459 * @macs: array of MAC id and colors which belong to the binding 2460 * @phy: PHY id and color which belongs to the binding 2461 */ 2462 struct iwm_binding_cmd { 2463 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2464 uint32_t id_and_color; 2465 uint32_t action; 2466 /* IWM_BINDING_DATA_API_S_VER_1 */ 2467 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2468 uint32_t phy; 2469 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2470 2471 /* The maximal number of fragments in the FW's schedule session */ 2472 #define IWM_MVM_MAX_QUOTA 128 2473 2474 /** 2475 * struct iwm_time_quota_data - configuration of time quota per binding 2476 * @id_and_color: ID and color of the relevant Binding 2477 * @quota: absolute time quota in TU. The scheduler will try to divide the 2478 * remainig quota (after Time Events) according to this quota. 2479 * @max_duration: max uninterrupted context duration in TU 2480 */ 2481 struct iwm_time_quota_data { 2482 uint32_t id_and_color; 2483 uint32_t quota; 2484 uint32_t max_duration; 2485 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2486 2487 /** 2488 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2489 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2490 * @quotas: allocations per binding 2491 */ 2492 struct iwm_time_quota_cmd { 2493 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2494 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2495 2496 2497 /* PHY context */ 2498 2499 /* Supported bands */ 2500 #define IWM_PHY_BAND_5 (0) 2501 #define IWM_PHY_BAND_24 (1) 2502 2503 /* Supported channel width, vary if there is VHT support */ 2504 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2505 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2506 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2507 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2508 2509 /* 2510 * Control channel position: 2511 * For legacy set bit means upper channel, otherwise lower. 2512 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2513 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2514 * center_freq 2515 * | 2516 * 40Mhz |_______|_______| 2517 * 80Mhz |_______|_______|_______|_______| 2518 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2519 * code 011 010 001 000 | 100 101 110 111 2520 */ 2521 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2522 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2523 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2524 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2525 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2526 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2527 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2528 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2529 2530 /* 2531 * @band: IWM_PHY_BAND_* 2532 * @channel: channel number 2533 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2534 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2535 */ 2536 struct iwm_fw_channel_info { 2537 uint8_t band; 2538 uint8_t channel; 2539 uint8_t width; 2540 uint8_t ctrl_pos; 2541 } __packed; 2542 2543 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2544 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2545 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2546 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2547 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2548 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2549 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2550 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2551 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2552 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2553 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2554 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2555 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2556 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2557 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2558 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2559 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2560 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2561 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2562 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2563 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2564 2565 /* TODO: fix the value, make it depend on firmware at runtime? */ 2566 #define IWM_NUM_PHY_CTX 3 2567 2568 /* TODO: complete missing documentation */ 2569 /** 2570 * struct iwm_phy_context_cmd - config of the PHY context 2571 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2572 * @id_and_color: ID and color of the relevant Binding 2573 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2574 * @apply_time: 0 means immediate apply and context switch. 2575 * other value means apply new params after X usecs 2576 * @tx_param_color: ??? 2577 * @channel_info: 2578 * @txchain_info: ??? 2579 * @rxchain_info: ??? 2580 * @acquisition_data: ??? 2581 * @dsp_cfg_flags: set to 0 2582 */ 2583 struct iwm_phy_context_cmd { 2584 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2585 uint32_t id_and_color; 2586 uint32_t action; 2587 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2588 uint32_t apply_time; 2589 uint32_t tx_param_color; 2590 struct iwm_fw_channel_info ci; 2591 uint32_t txchain_info; 2592 uint32_t rxchain_info; 2593 uint32_t acquisition_data; 2594 uint32_t dsp_cfg_flags; 2595 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2596 2597 #define IWM_RX_INFO_PHY_CNT 8 2598 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2599 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2600 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2601 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2602 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2603 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2604 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2605 2606 #define IWM_RX_INFO_AGC_IDX 1 2607 #define IWM_RX_INFO_RSSI_AB_IDX 2 2608 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2609 #define IWM_OFDM_AGC_A_POS 0 2610 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2611 #define IWM_OFDM_AGC_B_POS 7 2612 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2613 #define IWM_OFDM_AGC_CODE_POS 20 2614 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2615 #define IWM_OFDM_RSSI_A_POS 0 2616 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2617 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2618 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2619 #define IWM_OFDM_RSSI_B_POS 16 2620 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2621 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2622 2623 /** 2624 * struct iwm_rx_phy_info - phy info 2625 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2626 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2627 * @cfg_phy_cnt: configurable DSP phy data byte count 2628 * @stat_id: configurable DSP phy data set ID 2629 * @reserved1: 2630 * @system_timestamp: GP2 at on air rise 2631 * @timestamp: TSF at on air rise 2632 * @beacon_time_stamp: beacon at on-air rise 2633 * @phy_flags: general phy flags: band, modulation, ... 2634 * @channel: channel number 2635 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2636 * @rate_n_flags: IWM_RATE_MCS_* 2637 * @byte_count: frame's byte-count 2638 * @frame_time: frame's time on the air, based on byte count and frame rate 2639 * calculation 2640 * @mac_active_msk: what MACs were active when the frame was received 2641 * 2642 * Before each Rx, the device sends this data. It contains PHY information 2643 * about the reception of the packet. 2644 */ 2645 struct iwm_rx_phy_info { 2646 uint8_t non_cfg_phy_cnt; 2647 uint8_t cfg_phy_cnt; 2648 uint8_t stat_id; 2649 uint8_t reserved1; 2650 uint32_t system_timestamp; 2651 uint64_t timestamp; 2652 uint32_t beacon_time_stamp; 2653 uint16_t phy_flags; 2654 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2655 uint16_t channel; 2656 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2657 uint8_t rate; 2658 uint8_t rflags; 2659 uint16_t xrflags; 2660 uint32_t byte_count; 2661 uint16_t mac_active_msk; 2662 uint16_t frame_time; 2663 } __packed; 2664 2665 struct iwm_rx_mpdu_res_start { 2666 uint16_t byte_count; 2667 uint16_t reserved; 2668 } __packed; 2669 2670 /** 2671 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2672 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2673 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2674 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2675 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2676 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2677 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2678 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2679 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2680 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2681 */ 2682 enum iwm_rx_phy_flags { 2683 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2684 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2685 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2686 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2687 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2688 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2689 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2690 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2691 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2692 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2693 }; 2694 2695 /** 2696 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2697 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2698 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2699 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2700 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2701 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2702 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2703 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2704 * in the driver. 2705 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2706 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2707 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2708 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2709 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2710 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2711 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2712 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2713 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2714 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2715 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2716 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2717 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2718 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2719 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2720 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2721 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2722 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2723 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2724 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2725 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2726 */ 2727 enum iwm_mvm_rx_status { 2728 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2729 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2730 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2731 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2732 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2733 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2734 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2735 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2736 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2737 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2738 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2739 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2740 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2741 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2742 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2743 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2744 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2745 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2746 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2747 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2748 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2749 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2750 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2751 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2752 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2753 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2754 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2755 }; 2756 2757 /** 2758 * struct iwm_radio_version_notif - information on the radio version 2759 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2760 * @radio_flavor: 2761 * @radio_step: 2762 * @radio_dash: 2763 */ 2764 struct iwm_radio_version_notif { 2765 uint32_t radio_flavor; 2766 uint32_t radio_step; 2767 uint32_t radio_dash; 2768 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2769 2770 enum iwm_card_state_flags { 2771 IWM_CARD_ENABLED = 0x00, 2772 IWM_HW_CARD_DISABLED = 0x01, 2773 IWM_SW_CARD_DISABLED = 0x02, 2774 IWM_CT_KILL_CARD_DISABLED = 0x04, 2775 IWM_HALT_CARD_DISABLED = 0x08, 2776 IWM_CARD_DISABLED_MSK = 0x0f, 2777 IWM_CARD_IS_RX_ON = 0x10, 2778 }; 2779 2780 /** 2781 * struct iwm_radio_version_notif - information on the radio version 2782 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2783 * @flags: %iwm_card_state_flags 2784 */ 2785 struct iwm_card_state_notif { 2786 uint32_t flags; 2787 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2788 2789 /** 2790 * struct iwm_missed_beacons_notif - information on missed beacons 2791 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2792 * @mac_id: interface ID 2793 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2794 * beacons since last RX. 2795 * @consec_missed_beacons: number of consecutive missed beacons 2796 * @num_expected_beacons: 2797 * @num_recvd_beacons: 2798 */ 2799 struct iwm_missed_beacons_notif { 2800 uint32_t mac_id; 2801 uint32_t consec_missed_beacons_since_last_rx; 2802 uint32_t consec_missed_beacons; 2803 uint32_t num_expected_beacons; 2804 uint32_t num_recvd_beacons; 2805 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2806 2807 /** 2808 * struct iwm_mfuart_load_notif - mfuart image version & status 2809 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2810 * @installed_ver: installed image version 2811 * @external_ver: external image version 2812 * @status: MFUART loading status 2813 * @duration: MFUART loading time 2814 */ 2815 struct iwm_mfuart_load_notif { 2816 uint32_t installed_ver; 2817 uint32_t external_ver; 2818 uint32_t status; 2819 uint32_t duration; 2820 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2821 2822 /** 2823 * struct iwm_set_calib_default_cmd - set default value for calibration. 2824 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2825 * @calib_index: the calibration to set value for 2826 * @length: of data 2827 * @data: the value to set for the calibration result 2828 */ 2829 struct iwm_set_calib_default_cmd { 2830 uint16_t calib_index; 2831 uint16_t length; 2832 uint8_t data[0]; 2833 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2834 2835 #define IWM_MAX_PORT_ID_NUM 2 2836 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2837 2838 /** 2839 * struct iwm_mcast_filter_cmd - configure multicast filter. 2840 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2841 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2842 * to identify network interface adopted in host-device IF. 2843 * It is used by FW as index in array of addresses. This array has 2844 * IWM_MAX_PORT_ID_NUM members. 2845 * @count: Number of MAC addresses in the array 2846 * @pass_all: Set 1 to pass all multicast packets. 2847 * @bssid: current association BSSID. 2848 * @addr_list: Place holder for array of MAC addresses. 2849 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2850 */ 2851 struct iwm_mcast_filter_cmd { 2852 uint8_t filter_own; 2853 uint8_t port_id; 2854 uint8_t count; 2855 uint8_t pass_all; 2856 uint8_t bssid[6]; 2857 uint8_t reserved[2]; 2858 uint8_t addr_list[0]; 2859 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2860 2861 /* 2862 * The first MAC indices (starting from 0) 2863 * are available to the driver, AUX follows 2864 */ 2865 #define IWM_MAC_INDEX_AUX 4 2866 #define IWM_MAC_INDEX_MIN_DRIVER 0 2867 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 2868 #define IWM_NUM_MAC_INDEX (IWM_MAC_INDEX_AUX + 1) 2869 2870 /*********************************** 2871 * Statistics API 2872 ***********************************/ 2873 struct iwm_mvm_statistics_dbg { 2874 uint32_t burst_check; 2875 uint32_t burst_count; 2876 uint32_t wait_for_silence_timeout_cnt; 2877 uint32_t reserved[3]; 2878 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2879 2880 struct iwm_mvm_statistics_div { 2881 uint32_t tx_on_a; 2882 uint32_t tx_on_b; 2883 uint32_t exec_time; 2884 uint32_t probe_time; 2885 uint32_t rssi_ant; 2886 uint32_t reserved2; 2887 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2888 2889 struct iwm_mvm_statistics_rx_non_phy { 2890 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2891 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2892 uint32_t non_bssid_frames; /* number of frames with BSSID that 2893 * doesn't belong to the STA BSSID */ 2894 uint32_t filtered_frames; /* count frames that were dumped in the 2895 * filtering process */ 2896 uint32_t non_channel_beacons; /* beacons with our bss id but not on 2897 * our serving channel */ 2898 uint32_t channel_beacons; /* beacons with our bss id and in our 2899 * serving channel */ 2900 uint32_t num_missed_bcon; /* number of missed beacons */ 2901 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2902 * ADC was in saturation */ 2903 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2904 * for INA */ 2905 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2906 uint32_t interference_data_flag; /* flag for interference data 2907 * availability. 1 when data is 2908 * available. */ 2909 uint32_t channel_load; /* counts RX Enable time in uSec */ 2910 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2911 * and CCK) counter */ 2912 uint32_t beacon_rssi_a; 2913 uint32_t beacon_rssi_b; 2914 uint32_t beacon_rssi_c; 2915 uint32_t beacon_energy_a; 2916 uint32_t beacon_energy_b; 2917 uint32_t beacon_energy_c; 2918 uint32_t num_bt_kills; 2919 uint32_t mac_id; 2920 uint32_t directed_data_mpdu; 2921 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 2922 2923 struct iwm_mvm_statistics_rx_phy { 2924 uint32_t ina_cnt; 2925 uint32_t fina_cnt; 2926 uint32_t plcp_err; 2927 uint32_t crc32_err; 2928 uint32_t overrun_err; 2929 uint32_t early_overrun_err; 2930 uint32_t crc32_good; 2931 uint32_t false_alarm_cnt; 2932 uint32_t fina_sync_err_cnt; 2933 uint32_t sfd_timeout; 2934 uint32_t fina_timeout; 2935 uint32_t unresponded_rts; 2936 uint32_t rxe_frame_limit_overrun; 2937 uint32_t sent_ack_cnt; 2938 uint32_t sent_cts_cnt; 2939 uint32_t sent_ba_rsp_cnt; 2940 uint32_t dsp_self_kill; 2941 uint32_t mh_format_err; 2942 uint32_t re_acq_main_rssi_sum; 2943 uint32_t reserved; 2944 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 2945 2946 struct iwm_mvm_statistics_rx_ht_phy { 2947 uint32_t plcp_err; 2948 uint32_t overrun_err; 2949 uint32_t early_overrun_err; 2950 uint32_t crc32_good; 2951 uint32_t crc32_err; 2952 uint32_t mh_format_err; 2953 uint32_t agg_crc32_good; 2954 uint32_t agg_mpdu_cnt; 2955 uint32_t agg_cnt; 2956 uint32_t unsupport_mcs; 2957 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 2958 2959 struct iwm_mvm_statistics_tx_non_phy { 2960 uint32_t preamble_cnt; 2961 uint32_t rx_detected_cnt; 2962 uint32_t bt_prio_defer_cnt; 2963 uint32_t bt_prio_kill_cnt; 2964 uint32_t few_bytes_cnt; 2965 uint32_t cts_timeout; 2966 uint32_t ack_timeout; 2967 uint32_t expected_ack_cnt; 2968 uint32_t actual_ack_cnt; 2969 uint32_t dump_msdu_cnt; 2970 uint32_t burst_abort_next_frame_mismatch_cnt; 2971 uint32_t burst_abort_missing_next_frame_cnt; 2972 uint32_t cts_timeout_collision; 2973 uint32_t ack_or_ba_timeout_collision; 2974 } __packed; /* IWM_STATISTICS_TX_NON_PHY_API_S_VER_3 */ 2975 2976 #define IWM_MAX_CHAINS 3 2977 2978 struct iwm_mvm_statistics_tx_non_phy_agg { 2979 uint32_t ba_timeout; 2980 uint32_t ba_reschedule_frames; 2981 uint32_t scd_query_agg_frame_cnt; 2982 uint32_t scd_query_no_agg; 2983 uint32_t scd_query_agg; 2984 uint32_t scd_query_mismatch; 2985 uint32_t frame_not_ready; 2986 uint32_t underrun; 2987 uint32_t bt_prio_kill; 2988 uint32_t rx_ba_rsp_cnt; 2989 int8_t txpower[IWM_MAX_CHAINS]; 2990 int8_t reserved; 2991 uint32_t reserved2; 2992 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 2993 2994 struct iwm_mvm_statistics_tx_channel_width { 2995 uint32_t ext_cca_narrow_ch20[1]; 2996 uint32_t ext_cca_narrow_ch40[2]; 2997 uint32_t ext_cca_narrow_ch80[3]; 2998 uint32_t ext_cca_narrow_ch160[4]; 2999 uint32_t last_tx_ch_width_indx; 3000 uint32_t rx_detected_per_ch_width[4]; 3001 uint32_t success_per_ch_width[4]; 3002 uint32_t fail_per_ch_width[4]; 3003 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3004 3005 struct iwm_mvm_statistics_tx { 3006 struct iwm_mvm_statistics_tx_non_phy general; 3007 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3008 struct iwm_mvm_statistics_tx_channel_width channel_width; 3009 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3010 3011 3012 struct iwm_mvm_statistics_bt_activity { 3013 uint32_t hi_priority_tx_req_cnt; 3014 uint32_t hi_priority_tx_denied_cnt; 3015 uint32_t lo_priority_tx_req_cnt; 3016 uint32_t lo_priority_tx_denied_cnt; 3017 uint32_t hi_priority_rx_req_cnt; 3018 uint32_t hi_priority_rx_denied_cnt; 3019 uint32_t lo_priority_rx_req_cnt; 3020 uint32_t lo_priority_rx_denied_cnt; 3021 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3022 3023 struct iwm_mvm_statistics_general_v8 { 3024 uint32_t radio_temperature; 3025 uint32_t radio_voltage; 3026 struct iwm_mvm_statistics_dbg dbg; 3027 uint32_t sleep_time; 3028 uint32_t slots_out; 3029 uint32_t slots_idle; 3030 uint32_t ttl_timestamp; 3031 struct iwm_mvm_statistics_div slow_div; 3032 uint32_t rx_enable_counter; 3033 /* 3034 * num_of_sos_states: 3035 * count the number of times we have to re-tune 3036 * in order to get out of bad PHY status 3037 */ 3038 uint32_t num_of_sos_states; 3039 uint32_t beacon_filtered; 3040 uint32_t missed_beacons; 3041 uint8_t beacon_filter_average_energy; 3042 uint8_t beacon_filter_reason; 3043 uint8_t beacon_filter_current_energy; 3044 uint8_t beacon_filter_reserved; 3045 uint32_t beacon_filter_delta_time; 3046 struct iwm_mvm_statistics_bt_activity bt_activity; 3047 uint64_t rx_time; 3048 uint64_t on_time_rf; 3049 uint64_t on_time_scan; 3050 uint64_t tx_time; 3051 uint32_t beacon_counter[IWM_NUM_MAC_INDEX]; 3052 uint8_t beacon_average_energy[IWM_NUM_MAC_INDEX]; 3053 uint8_t reserved[4 - (IWM_NUM_MAC_INDEX % 4)]; 3054 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_8 */ 3055 3056 struct iwm_mvm_statistics_rx { 3057 struct iwm_mvm_statistics_rx_phy ofdm; 3058 struct iwm_mvm_statistics_rx_phy cck; 3059 struct iwm_mvm_statistics_rx_non_phy general; 3060 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3061 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3062 3063 /* 3064 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3065 * 3066 * By default, uCode issues this notification after receiving a beacon 3067 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3068 * IWM_STATISTICS_CMD (0x9c), below. 3069 */ 3070 3071 struct iwm_notif_statistics_v10 { 3072 uint32_t flag; 3073 struct iwm_mvm_statistics_rx rx; 3074 struct iwm_mvm_statistics_tx tx; 3075 struct iwm_mvm_statistics_general_v8 general; 3076 } __packed; /* IWM_STATISTICS_NTFY_API_S_VER_10 */ 3077 3078 #define IWM_STATISTICS_FLG_CLEAR 0x1 3079 #define IWM_STATISTICS_FLG_DISABLE_NOTIF 0x2 3080 3081 struct iwm_statistics_cmd { 3082 uint32_t flags; 3083 } __packed; /* IWM_STATISTICS_CMD_API_S_VER_1 */ 3084 3085 /*********************************** 3086 * Smart Fifo API 3087 ***********************************/ 3088 /* Smart Fifo state */ 3089 enum iwm_sf_state { 3090 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3091 IWM_SF_FULL_ON, 3092 IWM_SF_UNINIT, 3093 IWM_SF_INIT_OFF, 3094 IWM_SF_HW_NUM_STATES 3095 }; 3096 3097 /* Smart Fifo possible scenario */ 3098 enum iwm_sf_scenario { 3099 IWM_SF_SCENARIO_SINGLE_UNICAST, 3100 IWM_SF_SCENARIO_AGG_UNICAST, 3101 IWM_SF_SCENARIO_MULTICAST, 3102 IWM_SF_SCENARIO_BA_RESP, 3103 IWM_SF_SCENARIO_TX_RESP, 3104 IWM_SF_NUM_SCENARIO 3105 }; 3106 3107 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3108 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3109 3110 /* smart FIFO default values */ 3111 #define IWM_SF_W_MARK_SISO 4096 3112 #define IWM_SF_W_MARK_MIMO2 8192 3113 #define IWM_SF_W_MARK_MIMO3 6144 3114 #define IWM_SF_W_MARK_LEGACY 4096 3115 #define IWM_SF_W_MARK_SCAN 4096 3116 3117 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3118 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3119 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3120 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3121 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3122 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3123 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3124 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3125 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3126 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3127 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3128 3129 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3130 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3131 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3132 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3133 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3134 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3135 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3136 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3137 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3138 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3139 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3140 3141 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3142 3143 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3144 3145 /** 3146 * Smart Fifo configuration command. 3147 * @state: smart fifo state, types listed in enum %iwm_sf_state. 3148 * @watermark: Minimum allowed available free space in RXF for transient state. 3149 * @long_delay_timeouts: aging and idle timer values for each scenario 3150 * in long delay state. 3151 * @full_on_timeouts: timer values for each scenario in full on state. 3152 */ 3153 struct iwm_sf_cfg_cmd { 3154 uint32_t state; 3155 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3156 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3157 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3158 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3159 3160 enum iwm_ac { 3161 IWM_AC_BK, 3162 IWM_AC_BE, 3163 IWM_AC_VI, 3164 IWM_AC_VO, 3165 IWM_AC_NUM, 3166 }; 3167 3168 /** 3169 * enum iwm_mac_protection_flags - MAC context flags 3170 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3171 * this will require CCK RTS/CTS2self. 3172 * RTS/CTS will protect full burst time. 3173 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3174 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3175 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3176 */ 3177 enum iwm_mac_protection_flags { 3178 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3179 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3180 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3181 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3182 }; 3183 3184 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3185 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3186 3187 /** 3188 * enum iwm_mac_types - Supported MAC types 3189 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3190 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3191 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3192 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3193 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3194 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3195 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3196 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3197 * @IWM_FW_MAC_TYPE_GO: P2P GO 3198 * @IWM_FW_MAC_TYPE_TEST: ? 3199 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3200 */ 3201 enum iwm_mac_types { 3202 IWM_FW_MAC_TYPE_FIRST = 1, 3203 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3204 IWM_FW_MAC_TYPE_LISTENER, 3205 IWM_FW_MAC_TYPE_PIBSS, 3206 IWM_FW_MAC_TYPE_IBSS, 3207 IWM_FW_MAC_TYPE_BSS_STA, 3208 IWM_FW_MAC_TYPE_P2P_DEVICE, 3209 IWM_FW_MAC_TYPE_P2P_STA, 3210 IWM_FW_MAC_TYPE_GO, 3211 IWM_FW_MAC_TYPE_TEST, 3212 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3213 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3214 3215 /** 3216 * enum iwm_tsf_id - TSF hw timer ID 3217 * @IWM_TSF_ID_A: use TSF A 3218 * @IWM_TSF_ID_B: use TSF B 3219 * @IWM_TSF_ID_C: use TSF C 3220 * @IWM_TSF_ID_D: use TSF D 3221 * @IWM_NUM_TSF_IDS: number of TSF timers available 3222 */ 3223 enum iwm_tsf_id { 3224 IWM_TSF_ID_A = 0, 3225 IWM_TSF_ID_B = 1, 3226 IWM_TSF_ID_C = 2, 3227 IWM_TSF_ID_D = 3, 3228 IWM_NUM_TSF_IDS = 4, 3229 }; /* IWM_TSF_ID_API_E_VER_1 */ 3230 3231 /** 3232 * struct iwm_mac_data_ap - configuration data for AP MAC context 3233 * @beacon_time: beacon transmit time in system time 3234 * @beacon_tsf: beacon transmit time in TSF 3235 * @bi: beacon interval in TU 3236 * @bi_reciprocal: 2^32 / bi 3237 * @dtim_interval: dtim transmit time in TU 3238 * @dtim_reciprocal: 2^32 / dtim_interval 3239 * @mcast_qid: queue ID for multicast traffic 3240 * @beacon_template: beacon template ID 3241 */ 3242 struct iwm_mac_data_ap { 3243 uint32_t beacon_time; 3244 uint64_t beacon_tsf; 3245 uint32_t bi; 3246 uint32_t bi_reciprocal; 3247 uint32_t dtim_interval; 3248 uint32_t dtim_reciprocal; 3249 uint32_t mcast_qid; 3250 uint32_t beacon_template; 3251 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3252 3253 /** 3254 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3255 * @beacon_time: beacon transmit time in system time 3256 * @beacon_tsf: beacon transmit time in TSF 3257 * @bi: beacon interval in TU 3258 * @bi_reciprocal: 2^32 / bi 3259 * @beacon_template: beacon template ID 3260 */ 3261 struct iwm_mac_data_ibss { 3262 uint32_t beacon_time; 3263 uint64_t beacon_tsf; 3264 uint32_t bi; 3265 uint32_t bi_reciprocal; 3266 uint32_t beacon_template; 3267 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3268 3269 /** 3270 * struct iwm_mac_data_sta - configuration data for station MAC context 3271 * @is_assoc: 1 for associated state, 0 otherwise 3272 * @dtim_time: DTIM arrival time in system time 3273 * @dtim_tsf: DTIM arrival time in TSF 3274 * @bi: beacon interval in TU, applicable only when associated 3275 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3276 * @dtim_interval: DTIM interval in TU, applicable only when associated 3277 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3278 * @listen_interval: in beacon intervals, applicable only when associated 3279 * @assoc_id: unique ID assigned by the AP during association 3280 */ 3281 struct iwm_mac_data_sta { 3282 uint32_t is_assoc; 3283 uint32_t dtim_time; 3284 uint64_t dtim_tsf; 3285 uint32_t bi; 3286 uint32_t bi_reciprocal; 3287 uint32_t dtim_interval; 3288 uint32_t dtim_reciprocal; 3289 uint32_t listen_interval; 3290 uint32_t assoc_id; 3291 uint32_t assoc_beacon_arrive_time; 3292 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3293 3294 /** 3295 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3296 * @ap: iwm_mac_data_ap struct with most config data 3297 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3298 * 0 indicates that there is no CT window. 3299 * @opp_ps_enabled: indicate that opportunistic PS allowed 3300 */ 3301 struct iwm_mac_data_go { 3302 struct iwm_mac_data_ap ap; 3303 uint32_t ctwin; 3304 uint32_t opp_ps_enabled; 3305 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3306 3307 /** 3308 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3309 * @sta: iwm_mac_data_sta struct with most config data 3310 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3311 * 0 indicates that there is no CT window. 3312 */ 3313 struct iwm_mac_data_p2p_sta { 3314 struct iwm_mac_data_sta sta; 3315 uint32_t ctwin; 3316 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3317 3318 /** 3319 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3320 * @stats_interval: interval in TU between statistics notifications to host. 3321 */ 3322 struct iwm_mac_data_pibss { 3323 uint32_t stats_interval; 3324 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3325 3326 /* 3327 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3328 * context. 3329 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3330 * other channels as well. This should be to true only in case that the 3331 * device is discoverable and there is an active GO. Note that setting this 3332 * field when not needed, will increase the number of interrupts and have 3333 * effect on the platform power, as this setting opens the Rx filters on 3334 * all macs. 3335 */ 3336 struct iwm_mac_data_p2p_dev { 3337 uint32_t is_disc_extended; 3338 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3339 3340 /** 3341 * enum iwm_mac_filter_flags - MAC context filter flags 3342 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3343 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3344 * control frames to the host 3345 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3346 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3347 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3348 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3349 * (in station mode when associated) 3350 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3351 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3352 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3353 */ 3354 enum iwm_mac_filter_flags { 3355 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3356 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3357 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3358 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3359 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3360 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3361 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3362 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3363 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3364 }; 3365 3366 /** 3367 * enum iwm_mac_qos_flags - QoS flags 3368 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3369 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3370 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3371 * 3372 */ 3373 enum iwm_mac_qos_flags { 3374 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3375 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3376 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3377 }; 3378 3379 /** 3380 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3381 * @cw_min: Contention window, start value in numbers of slots. 3382 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3383 * @cw_max: Contention window, max value in numbers of slots. 3384 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3385 * @aifsn: Number of slots in Arbitration Interframe Space (before 3386 * performing random backoff timing prior to Tx). Device default 1. 3387 * @fifos_mask: FIFOs used by this MAC for this AC 3388 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3389 * 3390 * One instance of this config struct for each of 4 EDCA access categories 3391 * in struct iwm_qosparam_cmd. 3392 * 3393 * Device will automatically increase contention window by (2*CW) + 1 for each 3394 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3395 * value, to cap the CW value. 3396 */ 3397 struct iwm_ac_qos { 3398 uint16_t cw_min; 3399 uint16_t cw_max; 3400 uint8_t aifsn; 3401 uint8_t fifos_mask; 3402 uint16_t edca_txop; 3403 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3404 3405 /** 3406 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3407 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3408 * @id_and_color: ID and color of the MAC 3409 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3410 * @mac_type: one of IWM_FW_MAC_TYPE_* 3411 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3412 * @node_addr: MAC address 3413 * @bssid_addr: BSSID 3414 * @cck_rates: basic rates available for CCK 3415 * @ofdm_rates: basic rates available for OFDM 3416 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3417 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3418 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3419 * @filter_flags: combination of IWM_MAC_FILTER_* 3420 * @qos_flags: from IWM_MAC_QOS_FLG_* 3421 * @ac: one iwm_mac_qos configuration for each AC 3422 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3423 */ 3424 struct iwm_mac_ctx_cmd { 3425 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3426 uint32_t id_and_color; 3427 uint32_t action; 3428 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3429 uint32_t mac_type; 3430 uint32_t tsf_id; 3431 uint8_t node_addr[6]; 3432 uint16_t reserved_for_node_addr; 3433 uint8_t bssid_addr[6]; 3434 uint16_t reserved_for_bssid_addr; 3435 uint32_t cck_rates; 3436 uint32_t ofdm_rates; 3437 uint32_t protection_flags; 3438 uint32_t cck_short_preamble; 3439 uint32_t short_slot; 3440 uint32_t filter_flags; 3441 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3442 uint32_t qos_flags; 3443 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3444 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3445 union { 3446 struct iwm_mac_data_ap ap; 3447 struct iwm_mac_data_go go; 3448 struct iwm_mac_data_sta sta; 3449 struct iwm_mac_data_p2p_sta p2p_sta; 3450 struct iwm_mac_data_p2p_dev p2p_dev; 3451 struct iwm_mac_data_pibss pibss; 3452 struct iwm_mac_data_ibss ibss; 3453 }; 3454 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3455 3456 static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3457 { 3458 if (!v) 3459 return 0; 3460 return 0xFFFFFFFF / v; 3461 } 3462 3463 #define IWM_NONQOS_SEQ_GET 0x1 3464 #define IWM_NONQOS_SEQ_SET 0x2 3465 struct iwm_nonqos_seq_query_cmd { 3466 uint32_t get_set_flag; 3467 uint32_t mac_id_n_color; 3468 uint16_t value; 3469 uint16_t reserved; 3470 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3471 3472 /* Power Management Commands, Responses, Notifications */ 3473 3474 /** 3475 * enum iwm_ltr_config_flags - masks for LTR config command flags 3476 * @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 3477 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 3478 * memory access 3479 * @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 3480 * reg change 3481 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 3482 * D0 to D3 3483 * @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 3484 * @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 3485 * @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 3486 */ 3487 enum iwm_ltr_config_flags { 3488 IWM_LTR_CFG_FLAG_FEATURE_ENABLE = (1 << 0), 3489 IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS = (1 << 1), 3490 IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH = (1 << 2), 3491 IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 = (1 << 3), 3492 IWM_LTR_CFG_FLAG_SW_SET_SHORT = (1 << 4), 3493 IWM_LTR_CFG_FLAG_SW_SET_LONG = (1 << 5), 3494 IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD = (1 << 6), 3495 }; 3496 3497 /** 3498 * struct iwm_ltr_config_cmd_v1 - configures the LTR 3499 * @flags: See %enum iwm_ltr_config_flags 3500 */ 3501 struct iwm_ltr_config_cmd_v1 { 3502 uint32_t flags; 3503 uint32_t static_long; 3504 uint32_t static_short; 3505 } __packed; /* LTR_CAPABLE_API_S_VER_1 */ 3506 3507 #define IWM_LTR_VALID_STATES_NUM 4 3508 3509 /** 3510 * struct iwm_ltr_config_cmd - configures the LTR 3511 * @flags: See %enum iwm_ltr_config_flags 3512 * @static_long: 3513 * @static_short: 3514 * @ltr_cfg_values: 3515 * @ltr_short_idle_timeout: 3516 */ 3517 struct iwm_ltr_config_cmd { 3518 uint32_t flags; 3519 uint32_t static_long; 3520 uint32_t static_short; 3521 uint32_t ltr_cfg_values[IWM_LTR_VALID_STATES_NUM]; 3522 uint32_t ltr_short_idle_timeout; 3523 } __packed; /* LTR_CAPABLE_API_S_VER_2 */ 3524 3525 /* Radio LP RX Energy Threshold measured in dBm */ 3526 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3527 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3528 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3529 3530 /** 3531 * enum iwm_scan_flags - masks for power table command flags 3532 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3533 * receiver and transmitter. '0' - does not allow. 3534 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3535 * '1' Driver enables PM (use rest of parameters) 3536 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3537 * '1' PM could sleep over DTIM till listen Interval. 3538 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3539 * access categories are both delivery and trigger enabled. 3540 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3541 * PBW Snoozing enabled 3542 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3543 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3544 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3545 * detection enablement 3546 */ 3547 enum iwm_power_flags { 3548 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3549 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3550 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3551 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3552 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3553 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3554 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3555 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3556 }; 3557 3558 #define IWM_POWER_VEC_SIZE 5 3559 3560 /** 3561 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3562 * is used also with a new power API for device wide power settings. 3563 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3564 * 3565 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3566 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3567 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3568 * set regardless of power scheme or current power state. 3569 * FW use this value also when PM is disabled. 3570 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3571 * PSM transition - legacy PM 3572 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3573 * PSM transition - legacy PM 3574 * @sleep_interval: not in use 3575 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3576 * is set. For example, if it is required to skip over 3577 * one DTIM, this value need to be set to 2 (DTIM periods). 3578 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3579 * Default: 80dbm 3580 */ 3581 struct iwm_powertable_cmd { 3582 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3583 uint16_t flags; 3584 uint8_t keep_alive_seconds; 3585 uint8_t debug_flags; 3586 uint32_t rx_data_timeout; 3587 uint32_t tx_data_timeout; 3588 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3589 uint32_t skip_dtim_periods; 3590 uint32_t lprx_rssi_threshold; 3591 } __packed; 3592 3593 /** 3594 * enum iwm_device_power_flags - masks for device power command flags 3595 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3596 * receiver and transmitter. '0' - does not allow. 3597 */ 3598 enum iwm_device_power_flags { 3599 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3600 }; 3601 3602 /** 3603 * struct iwm_device_power_cmd - device wide power command. 3604 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3605 * 3606 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3607 */ 3608 struct iwm_device_power_cmd { 3609 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3610 uint16_t flags; 3611 uint16_t reserved; 3612 } __packed; 3613 3614 /** 3615 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3616 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3617 * @id_and_color: MAC contex identifier 3618 * @flags: Power table command flags from POWER_FLAGS_* 3619 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3620 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3621 * set regardless of power scheme or current power state. 3622 * FW use this value also when PM is disabled. 3623 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3624 * PSM transition - legacy PM 3625 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3626 * PSM transition - legacy PM 3627 * @sleep_interval: not in use 3628 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3629 * is set. For example, if it is required to skip over 3630 * one DTIM, this value need to be set to 2 (DTIM periods). 3631 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3632 * PSM transition - uAPSD 3633 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3634 * PSM transition - uAPSD 3635 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3636 * Default: 80dbm 3637 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3638 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3639 * from the AP [msec] 3640 * @snooze_window: A window of time in which PBW snoozing insures that all 3641 * packets received. It is also the minimum time from last 3642 * received unicast RX packet, before client stops snoozing 3643 * for data. [msec] 3644 * @snooze_step: TBD 3645 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3646 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3647 * each corresponding AC. 3648 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3649 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3650 * values. 3651 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3652 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3653 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3654 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3655 * @limited_ps_threshold: 3656 */ 3657 struct iwm_mac_power_cmd { 3658 /* CONTEXT_DESC_API_T_VER_1 */ 3659 uint32_t id_and_color; 3660 3661 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3662 uint16_t flags; 3663 uint16_t keep_alive_seconds; 3664 uint32_t rx_data_timeout; 3665 uint32_t tx_data_timeout; 3666 uint32_t rx_data_timeout_uapsd; 3667 uint32_t tx_data_timeout_uapsd; 3668 uint8_t lprx_rssi_threshold; 3669 uint8_t skip_dtim_periods; 3670 uint16_t snooze_interval; 3671 uint16_t snooze_window; 3672 uint8_t snooze_step; 3673 uint8_t qndp_tid; 3674 uint8_t uapsd_ac_flags; 3675 uint8_t uapsd_max_sp; 3676 uint8_t heavy_tx_thld_packets; 3677 uint8_t heavy_rx_thld_packets; 3678 uint8_t heavy_tx_thld_percentage; 3679 uint8_t heavy_rx_thld_percentage; 3680 uint8_t limited_ps_threshold; 3681 uint8_t reserved; 3682 } __packed; 3683 3684 /* 3685 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3686 * associated AP is identified as improperly implementing uAPSD protocol. 3687 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3688 * @sta_id: index of station in uCode's station table - associated AP ID in 3689 * this context. 3690 */ 3691 struct iwm_uapsd_misbehaving_ap_notif { 3692 uint32_t sta_id; 3693 uint8_t mac_id; 3694 uint8_t reserved[3]; 3695 } __packed; 3696 3697 /** 3698 * struct iwm_beacon_filter_cmd 3699 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3700 * @id_and_color: MAC contex identifier 3701 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3702 * to driver if delta in Energy values calculated for this and last 3703 * passed beacon is greater than this threshold. Zero value means that 3704 * the Energy change is ignored for beacon filtering, and beacon will 3705 * not be forced to be sent to driver regardless of this delta. Typical 3706 * energy delta 5dB. 3707 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3708 * Send beacon to driver if delta in Energy values calculated for this 3709 * and last passed beacon is greater than this threshold. Zero value 3710 * means that the Energy change is ignored for beacon filtering while in 3711 * Roaming state, typical energy delta 1dB. 3712 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3713 * calculated for current beacon is less than the threshold, use 3714 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3715 * Threshold. Typical energy threshold is -72dBm. 3716 * @bf_temp_threshold: This threshold determines the type of temperature 3717 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3718 * If the current temperature is above this threshold - Fast filter 3719 * will be used, If the current temperature is below this threshold - 3720 * Slow filter will be used. 3721 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3722 * calculated for this and the last passed beacon is greater than this 3723 * threshold. Zero value means that the temperature change is ignored for 3724 * beacon filtering; beacons will not be forced to be sent to driver 3725 * regardless of whether its temperature has been changed. 3726 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3727 * calculated for this and the last passed beacon is greater than this 3728 * threshold. Zero value means that the temperature change is ignored for 3729 * beacon filtering; beacons will not be forced to be sent to driver 3730 * regardless of whether its temperature has been changed. 3731 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3732 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3733 * for a specific period of time. Units: Beacons. 3734 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3735 * for a longer period of time then this escape-timeout. Units: Beacons. 3736 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3737 */ 3738 struct iwm_beacon_filter_cmd { 3739 uint32_t bf_energy_delta; 3740 uint32_t bf_roaming_energy_delta; 3741 uint32_t bf_roaming_state; 3742 uint32_t bf_temp_threshold; 3743 uint32_t bf_temp_fast_filter; 3744 uint32_t bf_temp_slow_filter; 3745 uint32_t bf_enable_beacon_filter; 3746 uint32_t bf_debug_flag; 3747 uint32_t bf_escape_timer; 3748 uint32_t ba_escape_timer; 3749 uint32_t ba_enable_beacon_abort; 3750 } __packed; 3751 3752 /* Beacon filtering and beacon abort */ 3753 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3754 #define IWM_BF_ENERGY_DELTA_MAX 255 3755 #define IWM_BF_ENERGY_DELTA_MIN 0 3756 3757 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3758 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3759 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3760 3761 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3762 #define IWM_BF_ROAMING_STATE_MAX 255 3763 #define IWM_BF_ROAMING_STATE_MIN 0 3764 3765 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3766 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3767 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3768 3769 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3770 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3771 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3772 3773 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3774 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3775 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3776 3777 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3778 3779 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3780 3781 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3782 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3783 #define IWM_BF_ESCAPE_TIMER_MIN 0 3784 3785 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3786 #define IWM_BA_ESCAPE_TIMER_D3 9 3787 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3788 #define IWM_BA_ESCAPE_TIMER_MIN 0 3789 3790 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3791 3792 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3793 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3794 .bf_roaming_energy_delta = \ 3795 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3796 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3797 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3798 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3799 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3800 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3801 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3802 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3803 3804 /* 3805 * These serve as indexes into 3806 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3807 * TODO: avoid overlap between legacy and HT rates 3808 */ 3809 enum { 3810 IWM_RATE_1M_INDEX = 0, 3811 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3812 IWM_RATE_2M_INDEX, 3813 IWM_RATE_5M_INDEX, 3814 IWM_RATE_11M_INDEX, 3815 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3816 IWM_RATE_6M_INDEX, 3817 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3818 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3819 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3820 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3821 IWM_RATE_9M_INDEX, 3822 IWM_RATE_12M_INDEX, 3823 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3824 IWM_RATE_18M_INDEX, 3825 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3826 IWM_RATE_24M_INDEX, 3827 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3828 IWM_RATE_36M_INDEX, 3829 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3830 IWM_RATE_48M_INDEX, 3831 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3832 IWM_RATE_54M_INDEX, 3833 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3834 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3835 IWM_RATE_60M_INDEX, 3836 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3837 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3838 IWM_RATE_MCS_8_INDEX, 3839 IWM_RATE_MCS_9_INDEX, 3840 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3841 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3842 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3843 }; 3844 3845 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3846 3847 /* fw API values for legacy bit rates, both OFDM and CCK */ 3848 enum { 3849 IWM_RATE_6M_PLCP = 13, 3850 IWM_RATE_9M_PLCP = 15, 3851 IWM_RATE_12M_PLCP = 5, 3852 IWM_RATE_18M_PLCP = 7, 3853 IWM_RATE_24M_PLCP = 9, 3854 IWM_RATE_36M_PLCP = 11, 3855 IWM_RATE_48M_PLCP = 1, 3856 IWM_RATE_54M_PLCP = 3, 3857 IWM_RATE_1M_PLCP = 10, 3858 IWM_RATE_2M_PLCP = 20, 3859 IWM_RATE_5M_PLCP = 55, 3860 IWM_RATE_11M_PLCP = 110, 3861 IWM_RATE_INVM_PLCP = -1, 3862 }; 3863 3864 /* 3865 * rate_n_flags bit fields 3866 * 3867 * The 32-bit value has different layouts in the low 8 bites depending on the 3868 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3869 * for CCK and OFDM). 3870 * 3871 * High-throughput (HT) rate format 3872 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3873 * Very High-throughput (VHT) rate format 3874 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3875 * Legacy OFDM rate format for bits 7:0 3876 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3877 * Legacy CCK rate format for bits 7:0: 3878 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3879 */ 3880 3881 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3882 #define IWM_RATE_MCS_HT_POS 8 3883 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3884 3885 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3886 #define IWM_RATE_MCS_CCK_POS 9 3887 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3888 3889 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3890 #define IWM_RATE_MCS_VHT_POS 26 3891 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3892 3893 3894 /* 3895 * High-throughput (HT) rate format for bits 7:0 3896 * 3897 * 2-0: MCS rate base 3898 * 0) 6 Mbps 3899 * 1) 12 Mbps 3900 * 2) 18 Mbps 3901 * 3) 24 Mbps 3902 * 4) 36 Mbps 3903 * 5) 48 Mbps 3904 * 6) 54 Mbps 3905 * 7) 60 Mbps 3906 * 4-3: 0) Single stream (SISO) 3907 * 1) Dual stream (MIMO) 3908 * 2) Triple stream (MIMO) 3909 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3910 * (bits 7-6 are zero) 3911 * 3912 * Together the low 5 bits work out to the MCS index because we don't 3913 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3914 * streams and 16-23 have three streams. We could also support MCS 32 3915 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3916 */ 3917 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3918 #define IWM_RATE_HT_MCS_NSS_POS 3 3919 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3920 3921 /* Bit 10: (1) Use Green Field preamble */ 3922 #define IWM_RATE_HT_MCS_GF_POS 10 3923 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3924 3925 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3926 3927 /* 3928 * Very High-throughput (VHT) rate format for bits 7:0 3929 * 3930 * 3-0: VHT MCS (0-9) 3931 * 5-4: number of streams - 1: 3932 * 0) Single stream (SISO) 3933 * 1) Dual stream (MIMO) 3934 * 2) Triple stream (MIMO) 3935 */ 3936 3937 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3938 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3939 #define IWM_RATE_VHT_MCS_NSS_POS 4 3940 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3941 3942 /* 3943 * Legacy OFDM rate format for bits 7:0 3944 * 3945 * 3-0: 0xD) 6 Mbps 3946 * 0xF) 9 Mbps 3947 * 0x5) 12 Mbps 3948 * 0x7) 18 Mbps 3949 * 0x9) 24 Mbps 3950 * 0xB) 36 Mbps 3951 * 0x1) 48 Mbps 3952 * 0x3) 54 Mbps 3953 * (bits 7-4 are 0) 3954 * 3955 * Legacy CCK rate format for bits 7:0: 3956 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3957 * 3958 * 6-0: 10) 1 Mbps 3959 * 20) 2 Mbps 3960 * 55) 5.5 Mbps 3961 * 110) 11 Mbps 3962 * (bit 7 is 0) 3963 */ 3964 #define IWM_RATE_LEGACY_RATE_MSK 0xff 3965 3966 3967 /* 3968 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 3969 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 3970 */ 3971 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 3972 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3973 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3974 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3975 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3976 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 3977 3978 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 3979 #define IWM_RATE_MCS_SGI_POS 13 3980 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 3981 3982 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 3983 #define IWM_RATE_MCS_ANT_POS 14 3984 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 3985 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 3986 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 3987 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 3988 IWM_RATE_MCS_ANT_B_MSK) 3989 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 3990 IWM_RATE_MCS_ANT_C_MSK) 3991 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 3992 #define IWM_RATE_MCS_ANT_NUM 3 3993 3994 /* Bit 17-18: (0) SS, (1) SS*2 */ 3995 #define IWM_RATE_MCS_STBC_POS 17 3996 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 3997 3998 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 3999 #define IWM_RATE_MCS_BF_POS 19 4000 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4001 4002 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4003 #define IWM_RATE_MCS_ZLF_POS 20 4004 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4005 4006 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4007 #define IWM_RATE_MCS_DUP_POS 24 4008 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4009 4010 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4011 #define IWM_RATE_MCS_LDPC_POS 27 4012 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4013 4014 4015 /* Link Quality definitions */ 4016 4017 /* # entries in rate scale table to support Tx retries */ 4018 #define IWM_LQ_MAX_RETRY_NUM 16 4019 4020 /* Link quality command flags bit fields */ 4021 4022 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4023 #define IWM_LQ_FLAG_USE_RTS_POS 0 4024 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4025 4026 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4027 #define IWM_LQ_FLAG_COLOR_POS 1 4028 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4029 4030 /* Bit 4-5: Tx RTS BW Signalling 4031 * (0) No RTS BW signalling 4032 * (1) Static BW signalling 4033 * (2) Dynamic BW signalling 4034 */ 4035 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4036 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4037 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4038 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4039 4040 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4041 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4042 */ 4043 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4044 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4045 4046 /* Single Stream Tx Parameters (lq_cmd->ss_params) 4047 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 4048 * used for single stream Tx. 4049 */ 4050 4051 /* Bit 0-1: Max STBC streams allowed. Can be 0-3. 4052 * (0) - No STBC allowed 4053 * (1) - 2x1 STBC allowed (HT/VHT) 4054 * (2) - 4x2 STBC allowed (HT/VHT) 4055 * (3) - 3x2 STBC allowed (HT only) 4056 * All our chips are at most 2 antennas so only (1) is valid for now. 4057 */ 4058 #define IWM_LQ_SS_STBC_ALLOWED_POS 0 4059 #define IWM_LQ_SS_STBC_ALLOWED_MSK (3 << IWM_LQ_SS_STBC_ALLOWED_MSK) 4060 4061 /* 2x1 STBC is allowed */ 4062 #define IWM_LQ_SS_STBC_1SS_ALLOWED (1 << IWM_LQ_SS_STBC_ALLOWED_POS) 4063 4064 /* Bit 2: Beamformer (VHT only) is allowed */ 4065 #define IWM_LQ_SS_BFER_ALLOWED_POS 2 4066 #define IWM_LQ_SS_BFER_ALLOWED (1 << IWM_LQ_SS_BFER_ALLOWED_POS) 4067 4068 /* Bit 3: Force BFER or STBC for testing 4069 * If this is set: 4070 * If BFER is allowed then force the ucode to choose BFER else 4071 * If STBC is allowed then force the ucode to choose STBC over SISO 4072 */ 4073 #define IWM_LQ_SS_FORCE_POS 3 4074 #define IWM_LQ_SS_FORCE (1 << IWM_LQ_SS_FORCE_POS) 4075 4076 /* Bit 31: ss_params field is valid. Used for FW backward compatibility 4077 * with other drivers which don't support the ss_params API yet 4078 */ 4079 #define IWM_LQ_SS_PARAMS_VALID_POS 31 4080 #define IWM_LQ_SS_PARAMS_VALID (1 << IWM_LQ_SS_PARAMS_VALID_POS) 4081 4082 /** 4083 * struct iwm_lq_cmd - link quality command 4084 * @sta_id: station to update 4085 * @control: not used 4086 * @flags: combination of IWM_LQ_FLAG_* 4087 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4088 * and SISO rates 4089 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4090 * Should be ANT_[ABC] 4091 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4092 * @initial_rate_index: first index from rs_table per AC category 4093 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4094 * value of 100 is one usec. Range is 100 to 8000 4095 * @agg_disable_start_th: try-count threshold for starting aggregation. 4096 * If a frame has higher try-count, it should not be selected for 4097 * starting an aggregation sequence. 4098 * @agg_frame_cnt_limit: max frame count in an aggregation. 4099 * 0: no limit 4100 * 1: no aggregation (one frame per aggregation) 4101 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4102 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4103 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4104 * @ss_params: single stream features. declare whether STBC or BFER are allowed. 4105 */ 4106 struct iwm_lq_cmd { 4107 uint8_t sta_id; 4108 uint8_t reduced_tpc; 4109 uint16_t control; 4110 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4111 uint8_t flags; 4112 uint8_t mimo_delim; 4113 uint8_t single_stream_ant_msk; 4114 uint8_t dual_stream_ant_msk; 4115 uint8_t initial_rate_index[IWM_AC_NUM]; 4116 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4117 uint16_t agg_time_limit; 4118 uint8_t agg_disable_start_th; 4119 uint8_t agg_frame_cnt_limit; 4120 uint32_t reserved2; 4121 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4122 uint32_t ss_params; 4123 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4124 4125 /** 4126 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4127 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4128 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4129 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4130 * Otherwise, use rate_n_flags from the TX command 4131 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4132 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4133 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4134 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4135 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4136 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4137 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4138 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4139 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4140 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4141 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4142 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4143 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4144 * Should be set for beacons and probe responses 4145 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4146 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4147 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4148 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4149 * Should be set for 26/30 length MAC headers 4150 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4151 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4152 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4153 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4154 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4155 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4156 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4157 */ 4158 enum iwm_tx_flags { 4159 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4160 IWM_TX_CMD_FLG_ACK = (1 << 3), 4161 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4162 IWM_TX_CMD_FLG_BA = (1 << 5), 4163 IWM_TX_CMD_FLG_BAR = (1 << 6), 4164 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4165 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4166 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4167 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4168 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4169 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4170 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4171 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4172 IWM_TX_CMD_FLG_TSF = (1 << 16), 4173 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4174 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4175 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4176 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4177 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4178 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4179 IWM_TX_CMD_FLG_DUR = (1 << 25), 4180 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4181 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4182 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4183 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4184 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4185 4186 /** 4187 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4188 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4189 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4190 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4191 */ 4192 enum iwm_tx_pm_timeouts { 4193 IWM_PM_FRAME_NONE = 0, 4194 IWM_PM_FRAME_MGMT = 2, 4195 IWM_PM_FRAME_ASSOC = 3, 4196 }; 4197 4198 /* 4199 * TX command security control 4200 */ 4201 #define IWM_TX_CMD_SEC_WEP 0x01 4202 #define IWM_TX_CMD_SEC_CCM 0x02 4203 #define IWM_TX_CMD_SEC_TKIP 0x03 4204 #define IWM_TX_CMD_SEC_EXT 0x04 4205 #define IWM_TX_CMD_SEC_MSK 0x07 4206 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4207 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4208 #define IWM_TX_CMD_SEC_KEY128 0x08 4209 4210 /* 4211 * TX command Frame life time in us - to be written in pm_frame_timeout 4212 */ 4213 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4214 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4215 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4216 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4217 4218 /* 4219 * TID for non QoS frames - to be written in tid_tspec 4220 */ 4221 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4222 4223 /* 4224 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4225 */ 4226 #define IWM_DEFAULT_TX_RETRY 15 4227 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4228 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4229 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4230 #define IWM_LOW_RETRY_LIMIT 7 4231 4232 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4233 /** 4234 * struct iwm_tx_cmd - TX command struct to FW 4235 * ( IWM_TX_CMD = 0x1c ) 4236 * @len: in bytes of the payload, see below for details 4237 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4238 * Used for fragmentation and bursting, but not in 11n aggregation. 4239 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4240 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4241 * cleared. Combination of IWM_RATE_MCS_* 4242 * @sta_id: index of destination station in FW station table 4243 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4244 * @initial_rate_index: index into the rate table for initial TX attempt. 4245 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4246 * @key: security key 4247 * @reserved3: reserved 4248 * @life_time: frame life time (usecs??) 4249 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4250 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4251 * @dram_msb_ptr: upper bits of the scratch physical address 4252 * @rts_retry_limit: max attempts for RTS 4253 * @data_retry_limit: max attempts to send the data packet 4254 * @tid_spec: TID/tspec 4255 * @pm_frame_timeout: PM TX frame timeout 4256 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4257 * specified by HCCA protocol 4258 * 4259 * The byte count (both len and next_frame_len) includes MAC header 4260 * (24/26/30/32 bytes) 4261 * + 2 bytes pad if 26/30 header size 4262 * + 8 byte IV for CCM or TKIP (not used for WEP) 4263 * + Data payload 4264 * + 8-byte MIC (not used for CCM/WEP) 4265 * It does not include post-MAC padding, i.e., 4266 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4267 * Range of len: 14-2342 bytes. 4268 * 4269 * After the struct fields the MAC header is placed, plus any padding, 4270 * and then the actial payload. 4271 */ 4272 struct iwm_tx_cmd { 4273 uint16_t len; 4274 uint16_t next_frame_len; 4275 uint32_t tx_flags; 4276 struct { 4277 uint8_t try_cnt; 4278 uint8_t btkill_cnt; 4279 uint16_t reserved; 4280 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4281 uint32_t rate_n_flags; 4282 uint8_t sta_id; 4283 uint8_t sec_ctl; 4284 uint8_t initial_rate_index; 4285 uint8_t reserved2; 4286 uint8_t key[16]; 4287 uint16_t next_frame_flags; 4288 uint16_t reserved3; 4289 uint32_t life_time; 4290 uint32_t dram_lsb_ptr; 4291 uint8_t dram_msb_ptr; 4292 uint8_t rts_retry_limit; 4293 uint8_t data_retry_limit; 4294 uint8_t tid_tspec; 4295 uint16_t pm_frame_timeout; 4296 uint16_t driver_txop; 4297 uint8_t payload[0]; 4298 struct ieee80211_frame hdr[0]; 4299 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4300 4301 /* 4302 * TX response related data 4303 */ 4304 4305 /* 4306 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4307 * @IWM_TX_STATUS_SUCCESS: 4308 * @IWM_TX_STATUS_DIRECT_DONE: 4309 * @IWM_TX_STATUS_POSTPONE_DELAY: 4310 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4311 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4312 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4313 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4314 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4315 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4316 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4317 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4318 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4319 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4320 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4321 * @IWM_TX_STATUS_FAIL_DEST_PS: 4322 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4323 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4324 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4325 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4326 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4327 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4328 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4329 * @IWM_TX_STATUS_FAIL_FW_DROP: 4330 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4331 * STA table 4332 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4333 * @IWM_TX_MODE_MSK: 4334 * @IWM_TX_MODE_NO_BURST: 4335 * @IWM_TX_MODE_IN_BURST_SEQ: 4336 * @IWM_TX_MODE_FIRST_IN_BURST: 4337 * @IWM_TX_QUEUE_NUM_MSK: 4338 * 4339 * Valid only if frame_count =1 4340 * TODO: complete documentation 4341 */ 4342 enum iwm_tx_status { 4343 IWM_TX_STATUS_MSK = 0x000000ff, 4344 IWM_TX_STATUS_SUCCESS = 0x01, 4345 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4346 /* postpone TX */ 4347 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4348 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4349 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4350 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4351 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4352 /* abort TX */ 4353 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4354 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4355 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4356 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4357 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4358 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4359 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4360 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4361 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4362 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4363 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4364 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4365 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4366 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4367 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4368 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4369 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4370 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4371 IWM_TX_MODE_MSK = 0x00000f00, 4372 IWM_TX_MODE_NO_BURST = 0x00000000, 4373 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4374 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4375 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4376 IWM_TX_NARROW_BW_MSK = 0x00060000, 4377 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4378 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4379 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4380 }; 4381 4382 /* 4383 * enum iwm_tx_agg_status - TX aggregation status 4384 * @IWM_AGG_TX_STATE_STATUS_MSK: 4385 * @IWM_AGG_TX_STATE_TRANSMITTED: 4386 * @IWM_AGG_TX_STATE_UNDERRUN: 4387 * @IWM_AGG_TX_STATE_BT_PRIO: 4388 * @IWM_AGG_TX_STATE_FEW_BYTES: 4389 * @IWM_AGG_TX_STATE_ABORT: 4390 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4391 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4392 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4393 * @IWM_AGG_TX_STATE_SCD_QUERY: 4394 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4395 * @IWM_AGG_TX_STATE_RESPONSE: 4396 * @IWM_AGG_TX_STATE_DUMP_TX: 4397 * @IWM_AGG_TX_STATE_DELAY_TX: 4398 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4399 * occur if tx failed for this frame when it was a member of a previous 4400 * aggregation block). If rate scaling is used, retry count indicates the 4401 * rate table entry used for all frames in the new agg. 4402 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4403 * this frame 4404 * 4405 * TODO: complete documentation 4406 */ 4407 enum iwm_tx_agg_status { 4408 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4409 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4410 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4411 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4412 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4413 IWM_AGG_TX_STATE_ABORT = 0x008, 4414 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4415 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4416 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4417 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4418 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4419 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4420 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4421 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4422 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4423 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4424 }; 4425 4426 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4427 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4428 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4429 4430 /* 4431 * The mask below describes a status where we are absolutely sure that the MPDU 4432 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4433 * written the bytes to the TXE, but we know nothing about what the DSP did. 4434 */ 4435 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4436 IWM_AGG_TX_STATE_ABORT | \ 4437 IWM_AGG_TX_STATE_SCD_QUERY) 4438 4439 /* 4440 * IWM_REPLY_TX = 0x1c (response) 4441 * 4442 * This response may be in one of two slightly different formats, indicated 4443 * by the frame_count field: 4444 * 4445 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4446 * frame. Multiple attempts, at various bit rates, may have been made for 4447 * this frame. 4448 * 4449 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4450 * frames that used block-acknowledge. All frames were transmitted at 4451 * same rate. Rate scaling may have been used if first frame in this new 4452 * agg block failed in previous agg block(s). 4453 * 4454 * Note that, for aggregation, ACK (block-ack) status is not delivered 4455 * here; block-ack has not been received by the time the device records 4456 * this status. 4457 * This status relates to reasons the tx might have been blocked or aborted 4458 * within the device, rather than whether it was received successfully by 4459 * the destination station. 4460 */ 4461 4462 /** 4463 * struct iwm_agg_tx_status - per packet TX aggregation status 4464 * @status: enum iwm_tx_agg_status 4465 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4466 */ 4467 struct iwm_agg_tx_status { 4468 uint16_t status; 4469 uint16_t sequence; 4470 } __packed; 4471 4472 /* 4473 * definitions for initial rate index field 4474 * bits [3:0] initial rate index 4475 * bits [6:4] rate table color, used for the initial rate 4476 * bit-7 invalid rate indication 4477 */ 4478 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4479 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4480 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4481 4482 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4483 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4484 4485 /** 4486 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4487 * ( IWM_REPLY_TX = 0x1c ) 4488 * @frame_count: 1 no aggregation, >1 aggregation 4489 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4490 * @failure_rts: num of failures due to unsuccessful RTS 4491 * @failure_frame: num failures due to no ACK (unused for agg) 4492 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4493 * Tx of all the batch. IWM_RATE_MCS_* 4494 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4495 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4496 * in usec. 4497 * @pa_status: tx power info 4498 * @pa_integ_res_a: tx power info 4499 * @pa_integ_res_b: tx power info 4500 * @pa_integ_res_c: tx power info 4501 * @measurement_req_id: tx power info 4502 * @tfd_info: TFD information set by the FH 4503 * @seq_ctl: sequence control from the Tx cmd 4504 * @byte_cnt: byte count from the Tx cmd 4505 * @tlc_info: TLC rate info 4506 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4507 * @frame_ctrl: frame control 4508 * @status: for non-agg: frame status IWM_TX_STATUS_* 4509 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4510 * follow this one, up to frame_count. 4511 * 4512 * After the array of statuses comes the SSN of the SCD. Look at 4513 * %iwm_mvm_get_scd_ssn for more details. 4514 */ 4515 struct iwm_mvm_tx_resp { 4516 uint8_t frame_count; 4517 uint8_t bt_kill_count; 4518 uint8_t failure_rts; 4519 uint8_t failure_frame; 4520 uint32_t initial_rate; 4521 uint16_t wireless_media_time; 4522 4523 uint8_t pa_status; 4524 uint8_t pa_integ_res_a[3]; 4525 uint8_t pa_integ_res_b[3]; 4526 uint8_t pa_integ_res_c[3]; 4527 uint16_t measurement_req_id; 4528 uint8_t reduced_tpc; 4529 uint8_t reserved; 4530 4531 uint32_t tfd_info; 4532 uint16_t seq_ctl; 4533 uint16_t byte_cnt; 4534 uint8_t tlc_info; 4535 uint8_t ra_tid; 4536 uint16_t frame_ctrl; 4537 4538 struct iwm_agg_tx_status status; 4539 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4540 4541 /** 4542 * struct iwm_mvm_ba_notif - notifies about reception of BA 4543 * ( IWM_BA_NOTIF = 0xc5 ) 4544 * @sta_addr_lo32: lower 32 bits of the MAC address 4545 * @sta_addr_hi16: upper 16 bits of the MAC address 4546 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4547 * @tid: tid of the session 4548 * @seq_ctl: 4549 * @bitmap: the bitmap of the BA notification as seen in the air 4550 * @scd_flow: the tx queue this BA relates to 4551 * @scd_ssn: the index of the last contiguously sent packet 4552 * @txed: number of Txed frames in this batch 4553 * @txed_2_done: number of Acked frames in this batch 4554 */ 4555 struct iwm_mvm_ba_notif { 4556 uint32_t sta_addr_lo32; 4557 uint16_t sta_addr_hi16; 4558 uint16_t reserved; 4559 4560 uint8_t sta_id; 4561 uint8_t tid; 4562 uint16_t seq_ctl; 4563 uint64_t bitmap; 4564 uint16_t scd_flow; 4565 uint16_t scd_ssn; 4566 uint8_t txed; 4567 uint8_t txed_2_done; 4568 uint16_t reserved1; 4569 } __packed; 4570 4571 /* 4572 * struct iwm_mac_beacon_cmd - beacon template command 4573 * @tx: the tx commands associated with the beacon frame 4574 * @template_id: currently equal to the mac context id of the coresponding 4575 * mac. 4576 * @tim_idx: the offset of the tim IE in the beacon 4577 * @tim_size: the length of the tim IE 4578 * @frame: the template of the beacon frame 4579 */ 4580 struct iwm_mac_beacon_cmd { 4581 struct iwm_tx_cmd tx; 4582 uint32_t template_id; 4583 uint32_t tim_idx; 4584 uint32_t tim_size; 4585 struct ieee80211_frame frame[0]; 4586 } __packed; 4587 4588 struct iwm_beacon_notif { 4589 struct iwm_mvm_tx_resp beacon_notify_hdr; 4590 uint64_t tsf; 4591 uint32_t ibss_mgr_status; 4592 } __packed; 4593 4594 /** 4595 * enum iwm_dump_control - dump (flush) control flags 4596 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4597 * and the TFD queues are empty. 4598 */ 4599 enum iwm_dump_control { 4600 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4601 }; 4602 4603 /** 4604 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4605 * @queues_ctl: bitmap of queues to flush 4606 * @flush_ctl: control flags 4607 * @reserved: reserved 4608 */ 4609 struct iwm_tx_path_flush_cmd { 4610 uint32_t queues_ctl; 4611 uint16_t flush_ctl; 4612 uint16_t reserved; 4613 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4614 4615 /** 4616 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4617 * @tx_resp: the Tx response from the fw (agg or non-agg) 4618 * 4619 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4620 * it can't know that everything will go well until the end of the AMPDU, it 4621 * can't know in advance the number of MPDUs that will be sent in the current 4622 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4623 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4624 * of the batch. This is why the SSN of the SCD is written at the end of the 4625 * whole struct at a variable offset. This function knows how to cope with the 4626 * variable offset and returns the SSN of the SCD. 4627 */ 4628 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4629 { 4630 return le32_to_cpup((uint32_t *)&tx_resp->status + 4631 tx_resp->frame_count) & 0xfff; 4632 } 4633 4634 /** 4635 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4636 * @token: 4637 * @sta_id: station id 4638 * @tid: 4639 * @scd_queue: scheduler queue to confiug 4640 * @enable: 1 queue enable, 0 queue disable 4641 * @aggregate: 1 aggregated queue, 0 otherwise 4642 * @tx_fifo: %enum iwm_mvm_tx_fifo 4643 * @window: BA window size 4644 * @ssn: SSN for the BA agreement 4645 */ 4646 struct iwm_scd_txq_cfg_cmd { 4647 uint8_t token; 4648 uint8_t sta_id; 4649 uint8_t tid; 4650 uint8_t scd_queue; 4651 uint8_t enable; 4652 uint8_t aggregate; 4653 uint8_t tx_fifo; 4654 uint8_t window; 4655 uint16_t ssn; 4656 uint16_t reserved; 4657 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4658 4659 /** 4660 * struct iwm_scd_txq_cfg_rsp 4661 * @token: taken from the command 4662 * @sta_id: station id from the command 4663 * @tid: tid from the command 4664 * @scd_queue: scd_queue from the command 4665 */ 4666 struct iwm_scd_txq_cfg_rsp { 4667 uint8_t token; 4668 uint8_t sta_id; 4669 uint8_t tid; 4670 uint8_t scd_queue; 4671 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4672 4673 4674 /* Scan Commands, Responses, Notifications */ 4675 4676 /* Max number of IEs for direct SSID scans in a command */ 4677 #define IWM_PROBE_OPTION_MAX 20 4678 4679 /** 4680 * struct iwm_ssid_ie - directed scan network information element 4681 * 4682 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4683 * selected by "type" bit field in struct iwm_scan_channel; 4684 * each channel may select different ssids from among the 20 entries. 4685 * SSID IEs get transmitted in reverse order of entry. 4686 */ 4687 struct iwm_ssid_ie { 4688 uint8_t id; 4689 uint8_t len; 4690 uint8_t ssid[IEEE80211_NWID_LEN]; 4691 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4692 4693 /* scan offload */ 4694 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4695 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4696 #define IWM_SCAN_MAX_PROFILES 11 4697 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4698 4699 /* Default watchdog (in MS) for scheduled scan iteration */ 4700 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4701 4702 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4703 #define IWM_CAN_ABORT_STATUS 1 4704 4705 #define IWM_FULL_SCAN_MULTIPLIER 5 4706 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4707 #define IWM_MAX_SCHED_SCAN_PLANS 2 4708 4709 /** 4710 * iwm_scan_schedule_lmac - schedule of scan offload 4711 * @delay: delay between iterations, in seconds. 4712 * @iterations: num of scan iterations 4713 * @full_scan_mul: number of partial scans before each full scan 4714 */ 4715 struct iwm_scan_schedule_lmac { 4716 uint16_t delay; 4717 uint8_t iterations; 4718 uint8_t full_scan_mul; 4719 } __packed; /* SCAN_SCHEDULE_API_S */ 4720 4721 /** 4722 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4723 * @tx_flags: combination of TX_CMD_FLG_* 4724 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4725 * cleared. Combination of RATE_MCS_* 4726 * @sta_id: index of destination station in FW station table 4727 * @reserved: for alignment and future use 4728 */ 4729 struct iwm_scan_req_tx_cmd { 4730 uint32_t tx_flags; 4731 uint32_t rate_n_flags; 4732 uint8_t sta_id; 4733 uint8_t reserved[3]; 4734 } __packed; 4735 4736 enum iwm_scan_channel_flags_lmac { 4737 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4738 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4739 }; 4740 4741 /** 4742 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4743 * @flags: bits 1-20: directed scan to i'th ssid 4744 * other bits &enum iwm_scan_channel_flags_lmac 4745 * @channel_number: channel number 1-13 etc 4746 * @iter_count: scan iteration on this channel 4747 * @iter_interval: interval in seconds between iterations on one channel 4748 */ 4749 struct iwm_scan_channel_cfg_lmac { 4750 uint32_t flags; 4751 uint16_t channel_num; 4752 uint16_t iter_count; 4753 uint32_t iter_interval; 4754 } __packed; 4755 4756 /* 4757 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4758 * @offset: offset in the data block 4759 * @len: length of the segment 4760 */ 4761 struct iwm_scan_probe_segment { 4762 uint16_t offset; 4763 uint16_t len; 4764 } __packed; 4765 4766 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4767 * @mac_header: first (and common) part of the probe 4768 * @band_data: band specific data 4769 * @common_data: last (and common) part of the probe 4770 * @buf: raw data block 4771 */ 4772 struct iwm_scan_probe_req { 4773 struct iwm_scan_probe_segment mac_header; 4774 struct iwm_scan_probe_segment band_data[2]; 4775 struct iwm_scan_probe_segment common_data; 4776 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4777 } __packed; 4778 4779 enum iwm_scan_channel_flags { 4780 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4781 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4782 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4783 }; 4784 4785 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4786 * @flags: enum iwm_scan_channel_flags 4787 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4788 * involved. 4789 * 1 - EBS is disabled. 4790 * 2 - every second scan will be full scan(and so on). 4791 */ 4792 struct iwm_scan_channel_opt { 4793 uint16_t flags; 4794 uint16_t non_ebs_ratio; 4795 } __packed; 4796 4797 /** 4798 * iwm_mvm_lmac_scan_flags 4799 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4800 * without filtering. 4801 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4802 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4803 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4804 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4805 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4806 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4807 * and DS parameter set IEs into probe requests. 4808 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4809 * 1, 6 and 11. 4810 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4811 */ 4812 enum iwm_mvm_lmac_scan_flags { 4813 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4814 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4815 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4816 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4817 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4818 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4819 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4820 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4821 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4822 }; 4823 4824 enum iwm_scan_priority { 4825 IWM_SCAN_PRIORITY_LOW, 4826 IWM_SCAN_PRIORITY_MEDIUM, 4827 IWM_SCAN_PRIORITY_HIGH, 4828 }; 4829 4830 /** 4831 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4832 * @reserved1: for alignment and future use 4833 * @channel_num: num of channels to scan 4834 * @active-dwell: dwell time for active channels 4835 * @passive-dwell: dwell time for passive channels 4836 * @fragmented-dwell: dwell time for fragmented passive scan 4837 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4838 * @reserved2: for alignment and future use 4839 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4840 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4841 * @max_out_time: max time (in TU) to be out of associated channel 4842 * @suspend_time: pause scan this long (TUs) when returning to service channel 4843 * @flags: RXON flags 4844 * @filter_flags: RXON filter 4845 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4846 * @direct_scan: list of SSIDs for directed active scan 4847 * @scan_prio: enum iwm_scan_priority 4848 * @iter_num: number of scan iterations 4849 * @delay: delay in seconds before first iteration 4850 * @schedule: two scheduling plans. The first one is finite, the second one can 4851 * be infinite. 4852 * @channel_opt: channel optimization options, for full and partial scan 4853 * @data: channel configuration and probe request packet. 4854 */ 4855 struct iwm_scan_req_lmac { 4856 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4857 uint32_t reserved1; 4858 uint8_t n_channels; 4859 uint8_t active_dwell; 4860 uint8_t passive_dwell; 4861 uint8_t fragmented_dwell; 4862 uint8_t extended_dwell; 4863 uint8_t reserved2; 4864 uint16_t rx_chain_select; 4865 uint32_t scan_flags; 4866 uint32_t max_out_time; 4867 uint32_t suspend_time; 4868 /* RX_ON_FLAGS_API_S_VER_1 */ 4869 uint32_t flags; 4870 uint32_t filter_flags; 4871 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4872 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4873 uint32_t scan_prio; 4874 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4875 uint32_t iter_num; 4876 uint32_t delay; 4877 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4878 struct iwm_scan_channel_opt channel_opt[2]; 4879 uint8_t data[]; 4880 } __packed; 4881 4882 /** 4883 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4884 * @last_schedule_line: last schedule line executed (fast or regular) 4885 * @last_schedule_iteration: last scan iteration executed before scan abort 4886 * @status: enum iwm_scan_offload_complete_status 4887 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4888 * @time_after_last_iter; time in seconds elapsed after last iteration 4889 */ 4890 struct iwm_periodic_scan_complete { 4891 uint8_t last_schedule_line; 4892 uint8_t last_schedule_iteration; 4893 uint8_t status; 4894 uint8_t ebs_status; 4895 uint32_t time_after_last_iter; 4896 uint32_t reserved; 4897 } __packed; 4898 4899 /** 4900 * struct iwm_scan_results_notif - scan results for one channel - 4901 * SCAN_RESULT_NTF_API_S_VER_3 4902 * @channel: which channel the results are from 4903 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4904 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4905 * @num_probe_not_sent: # of request that weren't sent due to not enough time 4906 * @duration: duration spent in channel, in usecs 4907 */ 4908 struct iwm_scan_results_notif { 4909 uint8_t channel; 4910 uint8_t band; 4911 uint8_t probe_status; 4912 uint8_t num_probe_not_sent; 4913 uint32_t duration; 4914 } __packed; 4915 4916 enum iwm_scan_framework_client { 4917 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 4918 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 4919 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 4920 }; 4921 4922 /** 4923 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 4924 * @ssid: MAC address to filter out 4925 * @reported_rssi: AP rssi reported to the host 4926 * @client_bitmap: clients ignore this entry - enum scan_framework_client 4927 */ 4928 struct iwm_scan_offload_blacklist { 4929 uint8_t ssid[IEEE80211_ADDR_LEN]; 4930 uint8_t reported_rssi; 4931 uint8_t client_bitmap; 4932 } __packed; 4933 4934 enum iwm_scan_offload_network_type { 4935 IWM_NETWORK_TYPE_BSS = 1, 4936 IWM_NETWORK_TYPE_IBSS = 2, 4937 IWM_NETWORK_TYPE_ANY = 3, 4938 }; 4939 4940 enum iwm_scan_offload_band_selection { 4941 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 4942 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 4943 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 4944 }; 4945 4946 /** 4947 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 4948 * @ssid_index: index to ssid list in fixed part 4949 * @unicast_cipher: encryption olgorithm to match - bitmap 4950 * @aut_alg: authentication olgorithm to match - bitmap 4951 * @network_type: enum iwm_scan_offload_network_type 4952 * @band_selection: enum iwm_scan_offload_band_selection 4953 * @client_bitmap: clients waiting for match - enum scan_framework_client 4954 */ 4955 struct iwm_scan_offload_profile { 4956 uint8_t ssid_index; 4957 uint8_t unicast_cipher; 4958 uint8_t auth_alg; 4959 uint8_t network_type; 4960 uint8_t band_selection; 4961 uint8_t client_bitmap; 4962 uint8_t reserved[2]; 4963 } __packed; 4964 4965 /** 4966 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 4967 * @blaclist: AP list to filter off from scan results 4968 * @profiles: profiles to search for match 4969 * @blacklist_len: length of blacklist 4970 * @num_profiles: num of profiles in the list 4971 * @match_notify: clients waiting for match found notification 4972 * @pass_match: clients waiting for the results 4973 * @active_clients: active clients bitmap - enum scan_framework_client 4974 * @any_beacon_notify: clients waiting for match notification without match 4975 */ 4976 struct iwm_scan_offload_profile_cfg { 4977 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 4978 uint8_t blacklist_len; 4979 uint8_t num_profiles; 4980 uint8_t match_notify; 4981 uint8_t pass_match; 4982 uint8_t active_clients; 4983 uint8_t any_beacon_notify; 4984 uint8_t reserved[2]; 4985 } __packed; 4986 4987 enum iwm_scan_offload_complete_status { 4988 IWM_SCAN_OFFLOAD_COMPLETED = 1, 4989 IWM_SCAN_OFFLOAD_ABORTED = 2, 4990 }; 4991 4992 enum iwm_scan_ebs_status { 4993 IWM_SCAN_EBS_SUCCESS, 4994 IWM_SCAN_EBS_FAILED, 4995 IWM_SCAN_EBS_CHAN_NOT_FOUND, 4996 IWM_SCAN_EBS_INACTIVE, 4997 }; 4998 4999 /** 5000 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5001 * SCAN_COMPLETE_NTF_API_S_VER_3 5002 * @scanned_channels: number of channels scanned (and number of valid results) 5003 * @status: one of SCAN_COMP_STATUS_* 5004 * @bt_status: BT on/off status 5005 * @last_channel: last channel that was scanned 5006 * @tsf_low: TSF timer (lower half) in usecs 5007 * @tsf_high: TSF timer (higher half) in usecs 5008 * @results: an array of scan results, only "scanned_channels" of them are valid 5009 */ 5010 struct iwm_lmac_scan_complete_notif { 5011 uint8_t scanned_channels; 5012 uint8_t status; 5013 uint8_t bt_status; 5014 uint8_t last_channel; 5015 uint32_t tsf_low; 5016 uint32_t tsf_high; 5017 struct iwm_scan_results_notif results[]; 5018 } __packed; 5019 5020 5021 /* UMAC Scan API */ 5022 5023 /* The maximum of either of these cannot exceed 8, because we use an 5024 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5025 */ 5026 #define IWM_MVM_MAX_UMAC_SCANS 8 5027 #define IWM_MVM_MAX_LMAC_SCANS 1 5028 5029 enum iwm_scan_config_flags { 5030 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5031 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5032 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5033 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5034 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5035 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5036 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5037 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5038 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5039 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5040 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5041 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5042 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5043 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5044 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5045 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5046 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5047 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5048 5049 /* Bits 26-31 are for num of channels in channel_array */ 5050 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5051 }; 5052 5053 enum iwm_scan_config_rates { 5054 /* OFDM basic rates */ 5055 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5056 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5057 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5058 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5059 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5060 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5061 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5062 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5063 /* CCK basic rates */ 5064 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5065 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5066 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5067 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5068 5069 /* Bits 16-27 are for supported rates */ 5070 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5071 }; 5072 5073 enum iwm_channel_flags { 5074 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5075 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5076 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5077 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5078 }; 5079 5080 /** 5081 * struct iwm_scan_config 5082 * @flags: enum scan_config_flags 5083 * @tx_chains: valid_tx antenna - ANT_* definitions 5084 * @rx_chains: valid_rx antenna - ANT_* definitions 5085 * @legacy_rates: default legacy rates - enum scan_config_rates 5086 * @out_of_channel_time: default max out of serving channel time 5087 * @suspend_time: default max suspend time 5088 * @dwell_active: default dwell time for active scan 5089 * @dwell_passive: default dwell time for passive scan 5090 * @dwell_fragmented: default dwell time for fragmented scan 5091 * @dwell_extended: default dwell time for channels 1, 6 and 11 5092 * @mac_addr: default mac address to be used in probes 5093 * @bcast_sta_id: the index of the station in the fw 5094 * @channel_flags: default channel flags - enum iwm_channel_flags 5095 * scan_config_channel_flag 5096 * @channel_array: default supported channels 5097 */ 5098 struct iwm_scan_config { 5099 uint32_t flags; 5100 uint32_t tx_chains; 5101 uint32_t rx_chains; 5102 uint32_t legacy_rates; 5103 uint32_t out_of_channel_time; 5104 uint32_t suspend_time; 5105 uint8_t dwell_active; 5106 uint8_t dwell_passive; 5107 uint8_t dwell_fragmented; 5108 uint8_t dwell_extended; 5109 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5110 uint8_t bcast_sta_id; 5111 uint8_t channel_flags; 5112 uint8_t channel_array[]; 5113 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5114 5115 /** 5116 * iwm_umac_scan_flags 5117 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5118 * can be preempted by other scan requests with higher priority. 5119 * The low priority scan will be resumed when the higher proirity scan is 5120 * completed. 5121 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5122 * when scan starts. 5123 */ 5124 enum iwm_umac_scan_flags { 5125 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5126 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5127 }; 5128 5129 enum iwm_umac_scan_uid_offsets { 5130 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5131 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5132 }; 5133 5134 enum iwm_umac_scan_general_flags { 5135 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5136 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5137 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5138 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5139 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5140 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5141 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5142 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5143 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5144 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5145 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5146 }; 5147 5148 /** 5149 * struct iwm_scan_channel_cfg_umac 5150 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5151 * @channel_num: channel number 1-13 etc. 5152 * @iter_count: repetition count for the channel. 5153 * @iter_interval: interval between two scan iterations on one channel. 5154 */ 5155 struct iwm_scan_channel_cfg_umac { 5156 uint32_t flags; 5157 uint8_t channel_num; 5158 uint8_t iter_count; 5159 uint16_t iter_interval; 5160 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5161 5162 /** 5163 * struct iwm_scan_umac_schedule 5164 * @interval: interval in seconds between scan iterations 5165 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5166 * @reserved: for alignment and future use 5167 */ 5168 struct iwm_scan_umac_schedule { 5169 uint16_t interval; 5170 uint8_t iter_count; 5171 uint8_t reserved; 5172 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5173 5174 /** 5175 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5176 * parameters following channels configuration array. 5177 * @schedule: two scheduling plans. 5178 * @delay: delay in TUs before starting the first scan iteration 5179 * @reserved: for future use and alignment 5180 * @preq: probe request with IEs blocks 5181 * @direct_scan: list of SSIDs for directed active scan 5182 */ 5183 struct iwm_scan_req_umac_tail { 5184 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5185 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5186 uint16_t delay; 5187 uint16_t reserved; 5188 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5189 struct iwm_scan_probe_req preq; 5190 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5191 } __packed; 5192 5193 /** 5194 * struct iwm_scan_req_umac 5195 * @flags: &enum iwm_umac_scan_flags 5196 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5197 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5198 * @general_flags: &enum iwm_umac_scan_general_flags 5199 * @extended_dwell: dwell time for channels 1, 6 and 11 5200 * @active_dwell: dwell time for active scan 5201 * @passive_dwell: dwell time for passive scan 5202 * @fragmented_dwell: dwell time for fragmented passive scan 5203 * @max_out_time: max out of serving channel time 5204 * @suspend_time: max suspend time 5205 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5206 * @channel_flags: &enum iwm_scan_channel_flags 5207 * @n_channels: num of channels in scan request 5208 * @reserved: for future use and alignment 5209 * @data: &struct iwm_scan_channel_cfg_umac and 5210 * &struct iwm_scan_req_umac_tail 5211 */ 5212 struct iwm_scan_req_umac { 5213 uint32_t flags; 5214 uint32_t uid; 5215 uint32_t ooc_priority; 5216 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5217 uint32_t general_flags; 5218 uint8_t extended_dwell; 5219 uint8_t active_dwell; 5220 uint8_t passive_dwell; 5221 uint8_t fragmented_dwell; 5222 uint32_t max_out_time; 5223 uint32_t suspend_time; 5224 uint32_t scan_priority; 5225 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5226 uint8_t channel_flags; 5227 uint8_t n_channels; 5228 uint16_t reserved; 5229 uint8_t data[]; 5230 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5231 5232 /** 5233 * struct iwm_umac_scan_abort 5234 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5235 * @flags: reserved 5236 */ 5237 struct iwm_umac_scan_abort { 5238 uint32_t uid; 5239 uint32_t flags; 5240 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5241 5242 /** 5243 * struct iwm_umac_scan_complete 5244 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5245 * @last_schedule: last scheduling line 5246 * @last_iter: last scan iteration number 5247 * @scan status: &enum iwm_scan_offload_complete_status 5248 * @ebs_status: &enum iwm_scan_ebs_status 5249 * @time_from_last_iter: time elapsed from last iteration 5250 * @reserved: for future use 5251 */ 5252 struct iwm_umac_scan_complete { 5253 uint32_t uid; 5254 uint8_t last_schedule; 5255 uint8_t last_iter; 5256 uint8_t status; 5257 uint8_t ebs_status; 5258 uint32_t time_from_last_iter; 5259 uint32_t reserved; 5260 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5261 5262 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5263 /** 5264 * struct iwm_scan_offload_profile_match - match information 5265 * @bssid: matched bssid 5266 * @channel: channel where the match occurred 5267 * @energy: 5268 * @matching_feature: 5269 * @matching_channels: bitmap of channels that matched, referencing 5270 * the channels passed in tue scan offload request 5271 */ 5272 struct iwm_scan_offload_profile_match { 5273 uint8_t bssid[IEEE80211_ADDR_LEN]; 5274 uint16_t reserved; 5275 uint8_t channel; 5276 uint8_t energy; 5277 uint8_t matching_feature; 5278 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5279 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5280 5281 /** 5282 * struct iwm_scan_offload_profiles_query - match results query response 5283 * @matched_profiles: bitmap of matched profiles, referencing the 5284 * matches passed in the scan offload request 5285 * @last_scan_age: age of the last offloaded scan 5286 * @n_scans_done: number of offloaded scans done 5287 * @gp2_d0u: GP2 when D0U occurred 5288 * @gp2_invoked: GP2 when scan offload was invoked 5289 * @resume_while_scanning: not used 5290 * @self_recovery: obsolete 5291 * @reserved: reserved 5292 * @matches: array of match information, one for each match 5293 */ 5294 struct iwm_scan_offload_profiles_query { 5295 uint32_t matched_profiles; 5296 uint32_t last_scan_age; 5297 uint32_t n_scans_done; 5298 uint32_t gp2_d0u; 5299 uint32_t gp2_invoked; 5300 uint8_t resume_while_scanning; 5301 uint8_t self_recovery; 5302 uint16_t reserved; 5303 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5304 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5305 5306 /** 5307 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5308 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5309 * @scanned_channels: number of channels scanned and number of valid elements in 5310 * results array 5311 * @status: one of SCAN_COMP_STATUS_* 5312 * @bt_status: BT on/off status 5313 * @last_channel: last channel that was scanned 5314 * @tsf_low: TSF timer (lower half) in usecs 5315 * @tsf_high: TSF timer (higher half) in usecs 5316 * @results: array of scan results, only "scanned_channels" of them are valid 5317 */ 5318 struct iwm_umac_scan_iter_complete_notif { 5319 uint32_t uid; 5320 uint8_t scanned_channels; 5321 uint8_t status; 5322 uint8_t bt_status; 5323 uint8_t last_channel; 5324 uint32_t tsf_low; 5325 uint32_t tsf_high; 5326 struct iwm_scan_results_notif results[]; 5327 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5328 5329 /* Please keep this enum *SORTED* by hex value. 5330 * Needed for binary search, otherwise a warning will be triggered. 5331 */ 5332 enum iwm_scan_subcmd_ids { 5333 IWM_GSCAN_START_CMD = 0x0, 5334 IWM_GSCAN_STOP_CMD = 0x1, 5335 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5336 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5337 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5338 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5339 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5340 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5341 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5342 }; 5343 5344 /* STA API */ 5345 5346 /** 5347 * enum iwm_sta_flags - flags for the ADD_STA host command 5348 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5349 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5350 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5351 * @IWM_STA_FLG_PS: set if STA is in Power Save 5352 * @IWM_STA_FLG_INVALID: set if STA is invalid 5353 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5354 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5355 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5356 * @IWM_STA_FLG_PAN: STA is for PAN interface 5357 * @IWM_STA_FLG_CLASS_AUTH: 5358 * @IWM_STA_FLG_CLASS_ASSOC: 5359 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5360 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5361 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5362 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5363 * initialised by driver and can be updated by fw upon reception of 5364 * action frames that can change the channel width. When cleared the fw 5365 * will send all the frames in 20MHz even when FAT channel is requested. 5366 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5367 * driver and can be updated by fw upon reception of action frames. 5368 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5369 */ 5370 enum iwm_sta_flags { 5371 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5372 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5373 5374 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5375 5376 IWM_STA_FLG_PS = (1 << 8), 5377 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5378 IWM_STA_FLG_PAN = (1 << 13), 5379 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5380 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5381 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5382 5383 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5384 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5385 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5386 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5387 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5388 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5389 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5390 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5391 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5392 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5393 5394 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5395 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5396 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5397 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5398 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5399 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5400 5401 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5402 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5403 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5404 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5405 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5406 5407 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5408 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5409 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5410 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5411 }; 5412 5413 /** 5414 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5415 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5416 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5417 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5418 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5419 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5420 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5421 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5422 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5423 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5424 * station info array (1 - n 1X mode) 5425 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5426 * @IWM_STA_KEY_NOT_VALID: key is invalid 5427 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5428 * @IWM_STA_KEY_MULTICAST: set for multical key 5429 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5430 */ 5431 enum iwm_sta_key_flag { 5432 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5433 IWM_STA_KEY_FLG_WEP = (1 << 0), 5434 IWM_STA_KEY_FLG_CCM = (2 << 0), 5435 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5436 IWM_STA_KEY_FLG_EXT = (4 << 0), 5437 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5438 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5439 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5440 5441 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5442 IWM_STA_KEY_FLG_KEYID_POS = 8, 5443 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5444 IWM_STA_KEY_NOT_VALID = (1 << 11), 5445 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5446 IWM_STA_KEY_MULTICAST = (1 << 14), 5447 IWM_STA_KEY_MFP = (1 << 15), 5448 }; 5449 5450 /** 5451 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5452 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5453 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5454 * @IWM_STA_MODIFY_TX_RATE: unused 5455 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5456 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5457 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5458 * @IWM_STA_MODIFY_PROT_TH: 5459 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5460 */ 5461 enum iwm_sta_modify_flag { 5462 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5463 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5464 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5465 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5466 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5467 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5468 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5469 IWM_STA_MODIFY_QUEUES = (1 << 7), 5470 }; 5471 5472 #define IWM_STA_MODE_MODIFY 1 5473 5474 /** 5475 * enum iwm_sta_sleep_flag - type of sleep of the station 5476 * @IWM_STA_SLEEP_STATE_AWAKE: 5477 * @IWM_STA_SLEEP_STATE_PS_POLL: 5478 * @IWM_STA_SLEEP_STATE_UAPSD: 5479 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5480 * (last) released frame 5481 */ 5482 enum iwm_sta_sleep_flag { 5483 IWM_STA_SLEEP_STATE_AWAKE = 0, 5484 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5485 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5486 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5487 }; 5488 5489 /* STA ID and color bits definitions */ 5490 #define IWM_STA_ID_SEED (0x0f) 5491 #define IWM_STA_ID_POS (0) 5492 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5493 5494 #define IWM_STA_COLOR_SEED (0x7) 5495 #define IWM_STA_COLOR_POS (4) 5496 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5497 5498 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5499 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5500 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5501 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5502 5503 #define IWM_STA_KEY_MAX_NUM (16) 5504 #define IWM_STA_KEY_IDX_INVALID (0xff) 5505 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5506 #define IWM_MAX_GLOBAL_KEYS (4) 5507 #define IWM_STA_KEY_LEN_WEP40 (5) 5508 #define IWM_STA_KEY_LEN_WEP104 (13) 5509 5510 /** 5511 * struct iwm_mvm_keyinfo - key information 5512 * @key_flags: type %iwm_sta_key_flag 5513 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5514 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5515 * @key_offset: key offset in the fw's key table 5516 * @key: 16-byte unicast decryption key 5517 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5518 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5519 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5520 */ 5521 struct iwm_mvm_keyinfo { 5522 uint16_t key_flags; 5523 uint8_t tkip_rx_tsc_byte2; 5524 uint8_t reserved1; 5525 uint16_t tkip_rx_ttak[5]; 5526 uint8_t key_offset; 5527 uint8_t reserved2; 5528 uint8_t key[16]; 5529 uint64_t tx_secur_seq_cnt; 5530 uint64_t hw_tkip_mic_rx_key; 5531 uint64_t hw_tkip_mic_tx_key; 5532 } __packed; 5533 5534 #define IWM_ADD_STA_STATUS_MASK 0xFF 5535 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5536 #define IWM_ADD_STA_BAID_MASK 0x7F00 5537 #define IWM_ADD_STA_BAID_SHIFT 8 5538 5539 /** 5540 * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table. 5541 * ( REPLY_ADD_STA = 0x18 ) 5542 * @add_modify: 1: modify existing, 0: add new station 5543 * @awake_acs: 5544 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5545 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5546 * @mac_id_n_color: the Mac context this station belongs to 5547 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5548 * @sta_id: index of station in uCode's station table 5549 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5550 * alone. 1 - modify, 0 - don't change. 5551 * @station_flags: look at %iwm_sta_flags 5552 * @station_flags_msk: what of %station_flags have changed 5553 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5554 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5555 * add_immediate_ba_ssn. 5556 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5557 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5558 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5559 * add_immediate_ba_tid. 5560 * @sleep_tx_count: number of packets to transmit to station even though it is 5561 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5562 * keeps track of STA sleep state. 5563 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5564 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5565 * mac-addr. 5566 * @beamform_flags: beam forming controls 5567 * @tfd_queue_msk: tfd queues used by this station 5568 * 5569 * The device contains an internal table of per-station information, with info 5570 * on security keys, aggregation parameters, and Tx rates for initial Tx 5571 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5572 * 5573 * ADD_STA sets up the table entry for one station, either creating a new 5574 * entry, or modifying a pre-existing one. 5575 */ 5576 struct iwm_mvm_add_sta_cmd { 5577 uint8_t add_modify; 5578 uint8_t awake_acs; 5579 uint16_t tid_disable_tx; 5580 uint32_t mac_id_n_color; 5581 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5582 uint16_t reserved2; 5583 uint8_t sta_id; 5584 uint8_t modify_mask; 5585 uint16_t reserved3; 5586 uint32_t station_flags; 5587 uint32_t station_flags_msk; 5588 uint8_t add_immediate_ba_tid; 5589 uint8_t remove_immediate_ba_tid; 5590 uint16_t add_immediate_ba_ssn; 5591 uint16_t sleep_tx_count; 5592 uint16_t sleep_state_flags; 5593 uint16_t assoc_id; 5594 uint16_t beamform_flags; 5595 uint32_t tfd_queue_msk; 5596 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5597 5598 /** 5599 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5600 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5601 * @sta_id: index of station in uCode's station table 5602 * @key_offset: key offset in key storage 5603 * @key_flags: type %iwm_sta_key_flag 5604 * @key: key material data 5605 * @key2: key material data 5606 * @rx_secur_seq_cnt: RX security sequence counter for the key 5607 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5608 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5609 */ 5610 struct iwm_mvm_add_sta_key_cmd { 5611 uint8_t sta_id; 5612 uint8_t key_offset; 5613 uint16_t key_flags; 5614 uint8_t key[16]; 5615 uint8_t key2[16]; 5616 uint8_t rx_secur_seq_cnt[16]; 5617 uint8_t tkip_rx_tsc_byte2; 5618 uint8_t reserved; 5619 uint16_t tkip_rx_ttak[5]; 5620 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5621 5622 /** 5623 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5624 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5625 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5626 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5627 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5628 * that doesn't exist. 5629 */ 5630 enum iwm_mvm_add_sta_rsp_status { 5631 IWM_ADD_STA_SUCCESS = 0x1, 5632 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5633 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5634 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5635 }; 5636 5637 /** 5638 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5639 * ( IWM_REMOVE_STA = 0x19 ) 5640 * @sta_id: the station id of the station to be removed 5641 */ 5642 struct iwm_mvm_rm_sta_cmd { 5643 uint8_t sta_id; 5644 uint8_t reserved[3]; 5645 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5646 5647 /** 5648 * struct iwm_mvm_mgmt_mcast_key_cmd 5649 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5650 * @ctrl_flags: %iwm_sta_key_flag 5651 * @IGTK: 5652 * @K1: IGTK master key 5653 * @K2: IGTK sub key 5654 * @sta_id: station ID that support IGTK 5655 * @key_id: 5656 * @receive_seq_cnt: initial RSC/PN needed for replay check 5657 */ 5658 struct iwm_mvm_mgmt_mcast_key_cmd { 5659 uint32_t ctrl_flags; 5660 uint8_t IGTK[16]; 5661 uint8_t K1[16]; 5662 uint8_t K2[16]; 5663 uint32_t key_id; 5664 uint32_t sta_id; 5665 uint64_t receive_seq_cnt; 5666 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5667 5668 struct iwm_mvm_wep_key { 5669 uint8_t key_index; 5670 uint8_t key_offset; 5671 uint16_t reserved1; 5672 uint8_t key_size; 5673 uint8_t reserved2[3]; 5674 uint8_t key[16]; 5675 } __packed; 5676 5677 struct iwm_mvm_wep_key_cmd { 5678 uint32_t mac_id_n_color; 5679 uint8_t num_keys; 5680 uint8_t decryption_type; 5681 uint8_t flags; 5682 uint8_t reserved; 5683 struct iwm_mvm_wep_key wep_key[0]; 5684 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5685 5686 /* 5687 * BT coex 5688 */ 5689 5690 enum iwm_bt_coex_mode { 5691 IWM_BT_COEX_DISABLE = 0x0, 5692 IWM_BT_COEX_NW = 0x1, 5693 IWM_BT_COEX_BT = 0x2, 5694 IWM_BT_COEX_WIFI = 0x3, 5695 }; /* BT_COEX_MODES_E */ 5696 5697 enum iwm_bt_coex_enabled_modules { 5698 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5699 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5700 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5701 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5702 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5703 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5704 5705 /** 5706 * struct iwm_bt_coex_cmd - bt coex configuration command 5707 * @mode: enum %iwm_bt_coex_mode 5708 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5709 * 5710 * The structure is used for the BT_COEX command. 5711 */ 5712 struct iwm_bt_coex_cmd { 5713 uint32_t mode; 5714 uint32_t enabled_modules; 5715 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5716 5717 5718 /* 5719 * Location Aware Regulatory (LAR) API - MCC updates 5720 */ 5721 5722 /** 5723 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5724 * regulatory profile according to the given MCC (Mobile Country Code). 5725 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5726 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5727 * MCC in the cmd response will be the relevant MCC in the NVM. 5728 * @mcc: given mobile country code 5729 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5730 * @reserved: reserved for alignment 5731 */ 5732 struct iwm_mcc_update_cmd_v1 { 5733 uint16_t mcc; 5734 uint8_t source_id; 5735 uint8_t reserved; 5736 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5737 5738 /** 5739 * struct iwm_mcc_update_cmd - Request the device to update geographic 5740 * regulatory profile according to the given MCC (Mobile Country Code). 5741 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5742 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5743 * MCC in the cmd response will be the relevant MCC in the NVM. 5744 * @mcc: given mobile country code 5745 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5746 * @reserved: reserved for alignment 5747 * @key: integrity key for MCC API OEM testing 5748 * @reserved2: reserved 5749 */ 5750 struct iwm_mcc_update_cmd { 5751 uint16_t mcc; 5752 uint8_t source_id; 5753 uint8_t reserved; 5754 uint32_t key; 5755 uint32_t reserved2[5]; 5756 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5757 5758 /** 5759 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5760 * Contains the new channel control profile map, if changed, and the new MCC 5761 * (mobile country code). 5762 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5763 * @status: see &enum iwm_mcc_update_status 5764 * @mcc: the new applied MCC 5765 * @cap: capabilities for all channels which matches the MCC 5766 * @source_id: the MCC source, see iwm_mcc_source 5767 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5768 * channels, depending on platform) 5769 * @channels: channel control data map, DWORD for each channel. Only the first 5770 * 16bits are used. 5771 */ 5772 struct iwm_mcc_update_resp_v1 { 5773 uint32_t status; 5774 uint16_t mcc; 5775 uint8_t cap; 5776 uint8_t source_id; 5777 uint32_t n_channels; 5778 uint32_t channels[0]; 5779 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5780 5781 /** 5782 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5783 * Contains the new channel control profile map, if changed, and the new MCC 5784 * (mobile country code). 5785 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5786 * @status: see &enum iwm_mcc_update_status 5787 * @mcc: the new applied MCC 5788 * @cap: capabilities for all channels which matches the MCC 5789 * @source_id: the MCC source, see iwm_mcc_source 5790 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5791 * @reserved: reserved. 5792 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5793 * channels, depending on platform) 5794 * @channels: channel control data map, DWORD for each channel. Only the first 5795 * 16bits are used. 5796 */ 5797 struct iwm_mcc_update_resp { 5798 uint32_t status; 5799 uint16_t mcc; 5800 uint8_t cap; 5801 uint8_t source_id; 5802 uint16_t time; 5803 uint16_t reserved; 5804 uint32_t n_channels; 5805 uint32_t channels[0]; 5806 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5807 5808 /** 5809 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5810 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5811 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5812 * the cellular and connectivity cores that gets updates of the mcc, and 5813 * notifies the ucode directly of any mcc change. 5814 * The ucode requests the driver to request the device to update geographic 5815 * regulatory profile according to the given MCC (Mobile Country Code). 5816 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5817 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5818 * MCC in the cmd response will be the relevant MCC in the NVM. 5819 * @mcc: given mobile country code 5820 * @source_id: identity of the change originator, see iwm_mcc_source 5821 * @reserved1: reserved for alignment 5822 */ 5823 struct iwm_mcc_chub_notif { 5824 uint16_t mcc; 5825 uint8_t source_id; 5826 uint8_t reserved1; 5827 } __packed; /* LAR_MCC_NOTIFY_S */ 5828 5829 enum iwm_mcc_update_status { 5830 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5831 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5832 IWM_MCC_RESP_INVALID, 5833 IWM_MCC_RESP_NVM_DISABLED, 5834 IWM_MCC_RESP_ILLEGAL, 5835 IWM_MCC_RESP_LOW_PRIORITY, 5836 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5837 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5838 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5839 }; 5840 5841 enum iwm_mcc_source { 5842 IWM_MCC_SOURCE_OLD_FW = 0, 5843 IWM_MCC_SOURCE_ME = 1, 5844 IWM_MCC_SOURCE_BIOS = 2, 5845 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5846 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5847 IWM_MCC_SOURCE_WIFI = 5, 5848 IWM_MCC_SOURCE_RESERVED = 6, 5849 IWM_MCC_SOURCE_DEFAULT = 7, 5850 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5851 IWM_MCC_SOURCE_MCC_API = 9, 5852 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5853 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5854 }; 5855 5856 /** 5857 * struct iwm_dts_measurement_notif_v1 - measurements notification 5858 * 5859 * @temp: the measured temperature 5860 * @voltage: the measured voltage 5861 */ 5862 struct iwm_dts_measurement_notif_v1 { 5863 int32_t temp; 5864 int32_t voltage; 5865 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5866 5867 /** 5868 * struct iwm_dts_measurement_notif_v2 - measurements notification 5869 * 5870 * @temp: the measured temperature 5871 * @voltage: the measured voltage 5872 * @threshold_idx: the trip index that was crossed 5873 */ 5874 struct iwm_dts_measurement_notif_v2 { 5875 int32_t temp; 5876 int32_t voltage; 5877 int32_t threshold_idx; 5878 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5879 5880 /* 5881 * Some cherry-picked definitions 5882 */ 5883 5884 #define IWM_FRAME_LIMIT 64 5885 5886 /* 5887 * These functions retrieve specific information from the id field in 5888 * the iwm_host_cmd struct which contains the command id, the group id, 5889 * and the version of the command and vice versa. 5890 */ 5891 static inline uint8_t 5892 iwm_cmd_opcode(uint32_t cmdid) 5893 { 5894 return cmdid & 0xff; 5895 } 5896 5897 static inline uint8_t 5898 iwm_cmd_groupid(uint32_t cmdid) 5899 { 5900 return ((cmdid & 0xff00) >> 8); 5901 } 5902 5903 static inline uint8_t 5904 iwm_cmd_version(uint32_t cmdid) 5905 { 5906 return ((cmdid & 0xff0000) >> 16); 5907 } 5908 5909 static inline uint32_t 5910 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 5911 { 5912 return opcode + (groupid << 8) + (version << 16); 5913 } 5914 5915 /* make uint16_t wide id out of uint8_t group and opcode */ 5916 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 5917 5918 /* due to the conversion, this group is special */ 5919 #define IWM_ALWAYS_LONG_GROUP 1 5920 5921 struct iwm_cmd_header { 5922 uint8_t code; 5923 uint8_t flags; 5924 uint8_t idx; 5925 uint8_t qid; 5926 } __packed; 5927 5928 struct iwm_cmd_header_wide { 5929 uint8_t opcode; 5930 uint8_t group_id; 5931 uint8_t idx; 5932 uint8_t qid; 5933 uint16_t length; 5934 uint8_t reserved; 5935 uint8_t version; 5936 } __packed; 5937 5938 /** 5939 * enum iwm_power_scheme 5940 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 5941 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 5942 * @IWM_POWER_LEVEL_LP - Low Power 5943 */ 5944 enum iwm_power_scheme { 5945 IWM_POWER_SCHEME_CAM = 1, 5946 IWM_POWER_SCHEME_BPS, 5947 IWM_POWER_SCHEME_LP 5948 }; 5949 5950 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 5951 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 5952 #define IWM_CMD_FAILED_MSK 0x40 5953 5954 /** 5955 * struct iwm_device_cmd 5956 * 5957 * For allocation of the command and tx queues, this establishes the overall 5958 * size of the largest command we send to uCode, except for commands that 5959 * aren't fully copied and use other TFD space. 5960 */ 5961 struct iwm_device_cmd { 5962 union { 5963 struct { 5964 struct iwm_cmd_header hdr; 5965 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 5966 }; 5967 struct { 5968 struct iwm_cmd_header_wide hdr_wide; 5969 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 5970 sizeof(struct iwm_cmd_header_wide) + 5971 sizeof(struct iwm_cmd_header)]; 5972 }; 5973 }; 5974 } __packed; 5975 5976 struct iwm_rx_packet { 5977 /* 5978 * The first 4 bytes of the RX frame header contain both the RX frame 5979 * size and some flags. 5980 * Bit fields: 5981 * 31: flag flush RB request 5982 * 30: flag ignore TC (terminal counter) request 5983 * 29: flag fast IRQ request 5984 * 28-14: Reserved 5985 * 13-00: RX frame size 5986 */ 5987 uint32_t len_n_flags; 5988 struct iwm_cmd_header hdr; 5989 uint8_t data[]; 5990 } __packed; 5991 5992 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 5993 #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 5994 #define IWM_FH_RSCSR_FRAME_ALIGN 0x40 5995 5996 static inline uint32_t 5997 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 5998 { 5999 6000 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6001 } 6002 6003 static inline uint32_t 6004 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6005 { 6006 6007 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6008 } 6009 6010 6011 #define IWM_MIN_DBM -100 6012 #define IWM_MAX_DBM -33 /* realistic guess */ 6013 6014 #define IWM_READ(sc, reg) \ 6015 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6016 6017 #define IWM_WRITE(sc, reg, val) \ 6018 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6019 6020 #define IWM_WRITE_1(sc, reg, val) \ 6021 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6022 6023 #define IWM_SETBITS(sc, reg, mask) \ 6024 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6025 6026 #define IWM_CLRBITS(sc, reg, mask) \ 6027 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6028 6029 #define IWM_BARRIER_WRITE(sc) \ 6030 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6031 BUS_SPACE_BARRIER_WRITE) 6032 6033 #define IWM_BARRIER_READ_WRITE(sc) \ 6034 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6035 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6036 6037 #endif /* __IF_IWM_REG_H__ */ 6038