1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */ 2 /* $FreeBSD$ */ 3 4 /****************************************************************************** 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <ilw@linux.intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef __IF_IWM_REG_H__ 67 #define __IF_IWM_REG_H__ 68 69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_))) 70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_))) 71 72 /* 73 * CSR (control and status registers) 74 * 75 * CSR registers are mapped directly into PCI bus space, and are accessible 76 * whenever platform supplies power to device, even when device is in 77 * low power states due to driver-invoked device resets 78 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 79 * 80 * Use iwl_write32() and iwl_read32() family to access these registers; 81 * these provide simple PCI bus access, without waking up the MAC. 82 * Do not use iwl_write_direct32() family for these registers; 83 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 84 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 85 * the CSR registers. 86 * 87 * NOTE: Device does need to be awake in order to read this memory 88 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers 89 */ 90 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 91 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 92 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */ 93 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */ 94 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 95 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */ 96 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 97 #define IWM_CSR_GP_CNTRL (0x024) 98 99 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 100 #define IWM_CSR_INT_PERIODIC_REG (0x005) 101 102 /* 103 * Hardware revision info 104 * Bit fields: 105 * 31-16: Reserved 106 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions 107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 108 * 1-0: "Dash" (-) value, as in A-1, etc. 109 */ 110 #define IWM_CSR_HW_REV (0x028) 111 112 /* 113 * EEPROM and OTP (one-time-programmable) memory reads 114 * 115 * NOTE: Device must be awake, initialized via apm_ops.init(), 116 * in order to read. 117 */ 118 #define IWM_CSR_EEPROM_REG (0x02c) 119 #define IWM_CSR_EEPROM_GP (0x030) 120 #define IWM_CSR_OTP_GP_REG (0x034) 121 122 #define IWM_CSR_GIO_REG (0x03C) 123 #define IWM_CSR_GP_UCODE_REG (0x048) 124 #define IWM_CSR_GP_DRIVER_REG (0x050) 125 126 /* 127 * UCODE-DRIVER GP (general purpose) mailbox registers. 128 * SET/CLR registers set/clear bit(s) if "1" is written. 129 */ 130 #define IWM_CSR_UCODE_DRV_GP1 (0x054) 131 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058) 132 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c) 133 #define IWM_CSR_UCODE_DRV_GP2 (0x060) 134 135 #define IWM_CSR_MBOX_SET_REG (0x088) 136 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20 137 138 #define IWM_CSR_LED_REG (0x094) 139 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0) 140 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 141 142 143 /* GIO Chicken Bits (PCI Express bus link power management) */ 144 #define IWM_CSR_GIO_CHICKEN_BITS (0x100) 145 146 /* Analog phase-lock-loop configuration */ 147 #define IWM_CSR_ANA_PLL_CFG (0x20c) 148 149 /* 150 * CSR Hardware Revision Workaround Register. Indicates hardware rev; 151 * "step" determines CCK backoff for txpower calculation. Used for 4965 only. 152 * See also IWM_CSR_HW_REV register. 153 * Bit fields: 154 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step 155 * 1-0: "Dash" (-) value, as in C-1, etc. 156 */ 157 #define IWM_CSR_HW_REV_WA_REG (0x22C) 158 159 #define IWM_CSR_DBG_HPET_MEM_REG (0x240) 160 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 161 162 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */ 163 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 164 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 166 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 167 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 171 172 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 173 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 178 179 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 180 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 183 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 184 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 185 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 186 187 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 188 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 189 190 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 191 * acknowledged (reset) by host writing "1" to flagged bits. */ 192 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 193 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 194 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 195 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 196 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 197 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 198 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 199 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 200 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 201 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 202 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 203 204 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \ 205 IWM_CSR_INT_BIT_HW_ERR | \ 206 IWM_CSR_INT_BIT_FH_TX | \ 207 IWM_CSR_INT_BIT_SW_ERR | \ 208 IWM_CSR_INT_BIT_RF_KILL | \ 209 IWM_CSR_INT_BIT_SW_RX | \ 210 IWM_CSR_INT_BIT_WAKEUP | \ 211 IWM_CSR_INT_BIT_ALIVE | \ 212 IWM_CSR_INT_BIT_RX_PERIODIC) 213 214 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 215 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ 216 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 217 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 218 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 219 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 220 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 221 222 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \ 223 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \ 224 IWM_CSR_FH_INT_BIT_RX_CHNL0) 225 226 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \ 227 IWM_CSR_FH_INT_BIT_TX_CHNL0) 228 229 /* GPIO */ 230 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) 231 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) 232 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) 233 234 /* RESET */ 235 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 236 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 237 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 238 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 239 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 240 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 241 242 /* 243 * GP (general purpose) CONTROL REGISTER 244 * Bit fields: 245 * 27: HW_RF_KILL_SW 246 * Indicates state of (platform's) hardware RF-Kill switch 247 * 26-24: POWER_SAVE_TYPE 248 * Indicates current power-saving mode: 249 * 000 -- No power saving 250 * 001 -- MAC power-down 251 * 010 -- PHY (radio) power-down 252 * 011 -- Error 253 * 9-6: SYS_CONFIG 254 * Indicates current system configuration, reflecting pins on chip 255 * as forced high/low by device circuit board. 256 * 4: GOING_TO_SLEEP 257 * Indicates MAC is entering a power-saving sleep power-down. 258 * Not a good time to access device-internal resources. 259 * 3: MAC_ACCESS_REQ 260 * Host sets this to request and maintain MAC wakeup, to allow host 261 * access to device-internal resources. Host must wait for 262 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 263 * device registers. 264 * 2: INIT_DONE 265 * Host sets this to put device into fully operational D0 power mode. 266 * Host resets this after SW_RESET to put device into low power mode. 267 * 0: MAC_CLOCK_READY 268 * Indicates MAC (ucode processor, etc.) is powered up and can run. 269 * Internal resources are accessible. 270 * NOTE: This does not indicate that the processor is actually running. 271 * NOTE: This does not indicate that device has completed 272 * init or post-power-down restore of internal SRAM memory. 273 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 274 * SRAM is restored and uCode is in normal operation mode. 275 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 276 * do not need to save/restore it. 277 * NOTE: After device reset, this bit remains "0" until host sets 278 * INIT_DONE 279 */ 280 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 281 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 283 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 284 285 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 286 287 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 288 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) 289 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 290 291 292 /* HW REV */ 293 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 294 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 295 296 /** 297 * hw_rev values 298 */ 299 enum { 300 IWM_SILICON_A_STEP = 0, 301 IWM_SILICON_B_STEP, 302 IWM_SILICON_C_STEP, 303 }; 304 305 306 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0) 307 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020) 308 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030) 309 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050) 310 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040) 311 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060) 312 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070) 313 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080) 314 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084) 315 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0) 316 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05 317 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05 318 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0) 319 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100) 320 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110) 321 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120) 322 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210) 323 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0) 324 325 /* EEPROM REG */ 326 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) 327 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002) 328 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) 329 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) 330 331 /* EEPROM GP */ 332 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ 333 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) 334 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) 335 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) 336 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) 337 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) 338 339 /* One-time-programmable memory general purpose reg */ 340 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ 341 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ 342 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ 343 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ 344 345 /* GP REG */ 346 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ 347 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000) 348 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000) 349 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000) 350 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) 351 352 353 /* CSR GIO */ 354 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002) 355 356 /* 357 * UCODE-DRIVER GP (general purpose) mailbox register 1 358 * Host driver and uCode write and/or read this register to communicate with 359 * each other. 360 * Bit fields: 361 * 4: UCODE_DISABLE 362 * Host sets this to request permanent halt of uCode, same as 363 * sending CARD_STATE command with "halt" bit set. 364 * 3: CT_KILL_EXIT 365 * Host sets this to request exit from CT_KILL state, i.e. host thinks 366 * device temperature is low enough to continue normal operation. 367 * 2: CMD_BLOCKED 368 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 369 * to release uCode to clear all Tx and command queues, enter 370 * unassociated mode, and power down. 371 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 372 * 1: SW_BIT_RFKILL 373 * Host sets this when issuing CARD_STATE command to request 374 * device sleep. 375 * 0: MAC_SLEEP 376 * uCode sets this when preparing a power-saving power-down. 377 * uCode resets this when power-up is complete and SRAM is sane. 378 * NOTE: device saves internal SRAM data to host when powering down, 379 * and must restore this data after powering back up. 380 * MAC_SLEEP is the best indication that restore is complete. 381 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 382 * do not need to save/restore it. 383 */ 384 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 385 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 386 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 387 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 388 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 389 390 /* GP Driver */ 391 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 392 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) 393 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) 394 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) 395 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) 396 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) 397 398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) 399 400 /* GIO Chicken Bits (PCI Express bus link power management) */ 401 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 402 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 403 404 /* LED */ 405 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) 406 #define IWM_CSR_LED_REG_TURN_ON (0x60) 407 #define IWM_CSR_LED_REG_TURN_OFF (0x20) 408 409 /* ANA_PLL */ 410 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300) 411 412 /* HPET MEM debug */ 413 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 414 415 /* DRAM INT TABLE */ 416 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31) 417 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 418 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 419 420 /* SECURE boot registers */ 421 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100) 422 enum iwm_secure_boot_config_reg { 423 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001, 424 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002, 425 }; 426 427 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100) 428 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100) 429 enum iwm_secure_boot_status_reg { 430 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003, 431 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002, 432 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004, 433 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008, 434 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010, 435 }; 436 437 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0 438 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000 439 440 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78 441 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c 442 443 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000 444 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400 445 446 #define IWM_CSR_SECURE_TIME_OUT (100) 447 448 /* extended range in FW SRAM */ 449 #define IWM_FW_MEM_EXTENDED_START 0x40000 450 #define IWM_FW_MEM_EXTENDED_END 0x57FFF 451 452 /* FW chicken bits */ 453 #define IWM_LMPM_CHICK 0xa01ff8 454 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01 455 456 #define IWM_FH_TCSR_0_REG0 (0x1D00) 457 458 /* 459 * HBUS (Host-side Bus) 460 * 461 * HBUS registers are mapped directly into PCI bus space, but are used 462 * to indirectly access device's internal memory or registers that 463 * may be powered-down. 464 * 465 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 466 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 467 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 468 * internal resources. 469 * 470 * Do not use iwl_write32()/iwl_read32() family to access these registers; 471 * these provide only simple PCI bus access, without waking up the MAC. 472 */ 473 #define IWM_HBUS_BASE (0x400) 474 475 /* 476 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 477 * structures, error log, event log, verifying uCode load). 478 * First write to address register, then read from or write to data register 479 * to complete the job. Once the address register is set up, accesses to 480 * data registers auto-increment the address by one dword. 481 * Bit usage for address registers (read or write): 482 * 0-31: memory address within device 483 */ 484 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c) 485 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010) 486 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018) 487 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c) 488 489 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ 490 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030) 491 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) 492 493 /* 494 * Registers for accessing device's internal peripheral registers 495 * (e.g. SCD, BSM, etc.). First write to address register, 496 * then read from or write to data register to complete the job. 497 * Bit usage for address registers (read or write): 498 * 0-15: register address (offset) within device 499 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 500 */ 501 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044) 502 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048) 503 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c) 504 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050) 505 506 /* enable the ID buf for read */ 507 #define IWM_WFPM_PS_CTL_CLR 0xa0300c 508 #define IWM_WFMP_MAC_ADDR_0 0xa03080 509 #define IWM_WFMP_MAC_ADDR_1 0xa03084 510 #define IWM_LMPM_PMG_EN 0xa01cec 511 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 512 #define IWM_RFIC_REG_RD 0xad0470 513 #define IWM_WFPM_CTRL_REG 0xa03030 514 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 515 #define IWM_ENABLE_WFPM 0x80000000 516 517 #define IWM_AUX_MISC_REG 0xa200b0 518 #define IWM_HW_STEP_LOCATION_BITS 24 519 520 #define IWM_AUX_MISC_MASTER1_EN 0xa20818 521 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 522 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 523 #define IWM_RSA_ENABLE 0xa24b08 524 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0 525 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78 526 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000 527 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000 528 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088 529 #define IWM_SB_CPU_1_STATUS 0xa01e30 530 #define IWM_SB_CPU_2_STATUS 0Xa01e34 531 532 /* Used to enable DBGM */ 533 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c) 534 535 /* 536 * Per-Tx-queue write pointer (index, really!) 537 * Indicates index to next TFD that driver will fill (1 past latest filled). 538 * Bit usage: 539 * 0-7: queue write index 540 * 11-8: queue selector 541 */ 542 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060) 543 544 /********************************************************** 545 * CSR values 546 **********************************************************/ 547 /* 548 * host interrupt timeout value 549 * used with setting interrupt coalescing timer 550 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 551 * 552 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 553 */ 554 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF) 555 #define IWM_HOST_INT_TIMEOUT_DEF (0x40) 556 #define IWM_HOST_INT_TIMEOUT_MIN (0x0) 557 #define IWM_HOST_INT_OPER_MODE (1 << 31) 558 559 /***************************************************************************** 560 * 7000/3000 series SHR DTS addresses * 561 *****************************************************************************/ 562 563 /* Diode Results Register Structure: */ 564 enum iwm_dtd_diode_reg { 565 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ 566 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ 567 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ 568 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ 569 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ 570 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ 571 /* Those are the masks INSIDE the flags bit-field: */ 572 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, 573 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ 574 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, 575 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ 576 }; 577 578 /** 579 * enum iwm_ucode_tlv_flag - ucode API flags 580 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 581 * was a separate TLV but moved here to save space. 582 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 583 * treats good CRC threshold as a boolean 584 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 585 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 586 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 587 * offload profile config command. 588 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 589 * (rather than two) IPv6 addresses 590 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 591 * from the probe request template. 592 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 593 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 594 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 595 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 596 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 597 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 598 */ 599 enum iwm_ucode_tlv_flag { 600 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0), 601 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1), 602 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2), 603 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7), 604 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10), 605 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12), 606 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15), 607 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16), 608 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24), 609 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25), 610 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26), 611 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29), 612 }; 613 614 #define IWM_UCODE_TLV_FLAG_BITS \ 615 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \ 616 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \ 617 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \ 618 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 619 620 /** 621 * enum iwm_ucode_tlv_api - ucode api 622 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 623 * longer than the passive one, which is essential for fragmented scan. 624 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 625 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 626 * 627 * @IWM_NUM_UCODE_TLV_API: number of bits used 628 */ 629 enum iwm_ucode_tlv_api { 630 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8, 631 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9, 632 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18, 633 634 IWM_NUM_UCODE_TLV_API = 32 635 }; 636 637 #define IWM_UCODE_TLV_API_BITS \ 638 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN" 639 640 /** 641 * enum iwm_ucode_tlv_capa - ucode capabilities 642 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 643 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 644 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 645 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 646 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 647 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 648 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 649 * tx power value into TPC Report action frame and Link Measurement Report 650 * action frame 651 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 652 * channel in DS parameter set element in probe requests. 653 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 654 * probe requests. 655 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 656 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 657 * which also implies support for the scheduler configuration command 658 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 659 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 660 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 661 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 662 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 663 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 664 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 665 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 666 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 667 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 668 * sources for the MCC. This TLV bit is a future replacement to 669 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 670 * is supported. 671 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 672 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 673 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 674 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 675 * 0=no support) 676 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 677 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 678 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 679 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 680 * antenna the beacon should be transmitted 681 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 682 * from AP and will send it upon d0i3 exit. 683 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 684 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 685 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 686 * thresholds reporting 687 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 688 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 689 * regular image. 690 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 691 * memory addresses from the firmware. 692 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 693 * @IWM_UCODE_TLV_CAPA_TX_POWER_ACK: reduced TX power API has larger 694 * command size (command version 4) that supports toggling ACK TX 695 * power reduction. 696 * 697 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used 698 */ 699 enum iwm_ucode_tlv_capa { 700 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0, 701 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1, 702 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2, 703 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3, 704 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5, 705 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6, 706 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8, 707 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9, 708 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10, 709 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11, 710 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12, 711 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13, 712 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17, 713 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18, 714 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19, 715 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20, 716 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21, 717 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22, 718 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26, 719 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28, 720 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29, 721 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30, 722 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31, 723 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34, 724 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35, 725 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64, 726 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65, 727 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67, 728 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68, 729 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71, 730 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72, 731 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73, 732 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74, 733 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75, 734 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76, 735 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77, 736 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80, 737 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81, 738 IWM_UCODE_TLV_CAPA_TX_POWER_ACK = 84, 739 740 IWM_NUM_UCODE_TLV_CAPA = 128 741 }; 742 743 /* The default calibrate table size if not specified by firmware file */ 744 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 745 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19 746 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253 747 748 /* The default max probe length if not specified by the firmware file */ 749 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200 750 751 /* 752 * enumeration of ucode section. 753 * This enumeration is used directly for older firmware (before 16.0). 754 * For new firmware, there can be up to 4 sections (see below) but the 755 * first one packaged into the firmware file is the DATA section and 756 * some debugging code accesses that. 757 */ 758 enum iwm_ucode_sec { 759 IWM_UCODE_SECTION_DATA, 760 IWM_UCODE_SECTION_INST, 761 }; 762 /* 763 * For 16.0 uCode and above, there is no differentiation between sections, 764 * just an offset to the HW address. 765 */ 766 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 767 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB 768 769 /* uCode version contains 4 values: Major/Minor/API/Serial */ 770 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 771 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 772 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 773 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 774 775 /* 776 * Calibration control struct. 777 * Sent as part of the phy configuration command. 778 * @flow_trigger: bitmap for which calibrations to perform according to 779 * flow triggers. 780 * @event_trigger: bitmap for which calibrations to perform according to 781 * event triggers. 782 */ 783 struct iwm_tlv_calib_ctrl { 784 uint32_t flow_trigger; 785 uint32_t event_trigger; 786 } __packed; 787 788 enum iwm_fw_phy_cfg { 789 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0, 790 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS, 791 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2, 792 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS, 793 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4, 794 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS, 795 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16, 796 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS, 797 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20, 798 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS, 799 }; 800 801 #define IWM_UCODE_MAX_CS 1 802 803 /** 804 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW. 805 * @cipher: a cipher suite selector 806 * @flags: cipher scheme flags (currently reserved for a future use) 807 * @hdr_len: a size of MPDU security header 808 * @pn_len: a size of PN 809 * @pn_off: an offset of pn from the beginning of the security header 810 * @key_idx_off: an offset of key index byte in the security header 811 * @key_idx_mask: a bit mask of key_idx bits 812 * @key_idx_shift: bit shift needed to get key_idx 813 * @mic_len: mic length in bytes 814 * @hw_cipher: a HW cipher index used in host commands 815 */ 816 struct iwm_fw_cipher_scheme { 817 uint32_t cipher; 818 uint8_t flags; 819 uint8_t hdr_len; 820 uint8_t pn_len; 821 uint8_t pn_off; 822 uint8_t key_idx_off; 823 uint8_t key_idx_mask; 824 uint8_t key_idx_shift; 825 uint8_t mic_len; 826 uint8_t hw_cipher; 827 } __packed; 828 829 /** 830 * struct iwm_fw_cscheme_list - a cipher scheme list 831 * @size: a number of entries 832 * @cs: cipher scheme entries 833 */ 834 struct iwm_fw_cscheme_list { 835 uint8_t size; 836 struct iwm_fw_cipher_scheme cs[]; 837 } __packed; 838 839 /* v1/v2 uCode file layout */ 840 struct iwm_ucode_header { 841 uint32_t ver; /* major/minor/API/serial */ 842 union { 843 struct { 844 uint32_t inst_size; /* bytes of runtime code */ 845 uint32_t data_size; /* bytes of runtime data */ 846 uint32_t init_size; /* bytes of init code */ 847 uint32_t init_data_size; /* bytes of init data */ 848 uint32_t boot_size; /* bytes of bootstrap code */ 849 uint8_t data[0]; /* in same order as sizes */ 850 } v1; 851 struct { 852 uint32_t build; /* build number */ 853 uint32_t inst_size; /* bytes of runtime code */ 854 uint32_t data_size; /* bytes of runtime data */ 855 uint32_t init_size; /* bytes of init code */ 856 uint32_t init_data_size; /* bytes of init data */ 857 uint32_t boot_size; /* bytes of bootstrap code */ 858 uint8_t data[0]; /* in same order as sizes */ 859 } v2; 860 } u; 861 }; 862 863 /* 864 * new TLV uCode file layout 865 * 866 * The new TLV file format contains TLVs, that each specify 867 * some piece of data. 868 */ 869 870 enum iwm_ucode_tlv_type { 871 IWM_UCODE_TLV_INVALID = 0, /* unused */ 872 IWM_UCODE_TLV_INST = 1, 873 IWM_UCODE_TLV_DATA = 2, 874 IWM_UCODE_TLV_INIT = 3, 875 IWM_UCODE_TLV_INIT_DATA = 4, 876 IWM_UCODE_TLV_BOOT = 5, 877 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */ 878 IWM_UCODE_TLV_PAN = 7, 879 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8, 880 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9, 881 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10, 882 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11, 883 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12, 884 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13, 885 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14, 886 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 887 IWM_UCODE_TLV_WOWLAN_INST = 16, 888 IWM_UCODE_TLV_WOWLAN_DATA = 17, 889 IWM_UCODE_TLV_FLAGS = 18, 890 IWM_UCODE_TLV_SEC_RT = 19, 891 IWM_UCODE_TLV_SEC_INIT = 20, 892 IWM_UCODE_TLV_SEC_WOWLAN = 21, 893 IWM_UCODE_TLV_DEF_CALIB = 22, 894 IWM_UCODE_TLV_PHY_SKU = 23, 895 IWM_UCODE_TLV_SECURE_SEC_RT = 24, 896 IWM_UCODE_TLV_SECURE_SEC_INIT = 25, 897 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26, 898 IWM_UCODE_TLV_NUM_OF_CPU = 27, 899 IWM_UCODE_TLV_CSCHEME = 28, 900 901 /* 902 * Following two are not in our base tag, but allow 903 * handling ucode version 9. 904 */ 905 IWM_UCODE_TLV_API_CHANGES_SET = 29, 906 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30, 907 908 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31, 909 IWM_UCODE_TLV_PAGING = 32, 910 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34, 911 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35, 912 IWM_UCODE_TLV_FW_VERSION = 36, 913 IWM_UCODE_TLV_FW_DBG_DEST = 38, 914 IWM_UCODE_TLV_FW_DBG_CONF = 39, 915 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40, 916 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50, 917 IWM_UCODE_TLV_FW_MEM_SEG = 51, 918 }; 919 920 struct iwm_ucode_tlv { 921 uint32_t type; /* see above */ 922 uint32_t length; /* not including type/length fields */ 923 uint8_t data[0]; 924 }; 925 926 struct iwm_ucode_api { 927 uint32_t api_index; 928 uint32_t api_flags; 929 } __packed; 930 931 struct iwm_ucode_capa { 932 uint32_t api_index; 933 uint32_t api_capa; 934 } __packed; 935 936 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749 937 938 struct iwm_tlv_ucode_header { 939 /* 940 * The TLV style ucode header is distinguished from 941 * the v1/v2 style header by first four bytes being 942 * zero, as such is an invalid combination of 943 * major/minor/API/serial versions. 944 */ 945 uint32_t zero; 946 uint32_t magic; 947 uint8_t human_readable[64]; 948 uint32_t ver; /* major/minor/API/serial */ 949 uint32_t build; 950 uint64_t ignore; 951 /* 952 * The data contained herein has a TLV layout, 953 * see above for the TLV header and types. 954 * Note that each TLV is padded to a length 955 * that is a multiple of 4 for alignment. 956 */ 957 uint8_t data[0]; 958 }; 959 960 /* 961 * Registers in this file are internal, not PCI bus memory mapped. 962 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers. 963 */ 964 #define IWM_PRPH_BASE (0x00000) 965 #define IWM_PRPH_END (0xFFFFF) 966 967 /* APMG (power management) constants */ 968 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000) 969 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000) 970 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004) 971 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008) 972 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c) 973 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010) 974 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014) 975 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c) 976 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020) 977 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058) 978 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C) 979 980 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 981 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 982 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 983 984 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 985 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 986 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 987 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 988 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 989 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 990 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 991 992 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 993 994 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000) 995 996 /* Device system time */ 997 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C 998 999 /* Device NMI register */ 1000 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30 1001 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01 1002 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80 1003 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24 1004 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000 1005 1006 /* 1007 * Device reset for family 8000 1008 * write to bit 24 in order to reset the CPU 1009 */ 1010 #define IWM_RELEASE_CPU_RESET 0x300c 1011 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000 1012 1013 1014 /***************************************************************************** 1015 * 7000/3000 series SHR DTS addresses * 1016 *****************************************************************************/ 1017 1018 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024) 1019 #define IWM_DTSC_CFG_MODE (0x00a10604) 1020 #define IWM_DTSC_VREF_AVG (0x00a10648) 1021 #define IWM_DTSC_VREF5_AVG (0x00a1064c) 1022 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2) 1023 #define IWM_DTSC_PTAT_AVG (0x00a10650) 1024 1025 1026 /** 1027 * Tx Scheduler 1028 * 1029 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 1030 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 1031 * host DRAM. It steers each frame's Tx command (which contains the frame 1032 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 1033 * device. A queue maps to only one (selectable by driver) Tx DMA channel, 1034 * but one DMA channel may take input from several queues. 1035 * 1036 * Tx DMA FIFOs have dedicated purposes. 1037 * 1038 * For 5000 series and up, they are used differently 1039 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 1040 * 1041 * 0 -- EDCA BK (background) frames, lowest priority 1042 * 1 -- EDCA BE (best effort) frames, normal priority 1043 * 2 -- EDCA VI (video) frames, higher priority 1044 * 3 -- EDCA VO (voice) and management frames, highest priority 1045 * 4 -- unused 1046 * 5 -- unused 1047 * 6 -- unused 1048 * 7 -- Commands 1049 * 1050 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 1051 * In addition, driver can map the remaining queues to Tx DMA/FIFO 1052 * channels 0-3 to support 11n aggregation via EDCA DMA channels. 1053 * 1054 * The driver sets up each queue to work in one of two modes: 1055 * 1056 * 1) Scheduler-Ack, in which the scheduler automatically supports a 1057 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 1058 * contains TFDs for a unique combination of Recipient Address (RA) 1059 * and Traffic Identifier (TID), that is, traffic of a given 1060 * Quality-Of-Service (QOS) priority, destined for a single station. 1061 * 1062 * In scheduler-ack mode, the scheduler keeps track of the Tx status of 1063 * each frame within the BA window, including whether it's been transmitted, 1064 * and whether it's been acknowledged by the receiving station. The device 1065 * automatically processes block-acks received from the receiving STA, 1066 * and reschedules un-acked frames to be retransmitted (successful 1067 * Tx completion may end up being out-of-order). 1068 * 1069 * The driver must maintain the queue's Byte Count table in host DRAM 1070 * for this mode. 1071 * This mode does not support fragmentation. 1072 * 1073 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 1074 * The device may automatically retry Tx, but will retry only one frame 1075 * at a time, until receiving ACK from receiving station, or reaching 1076 * retry limit and giving up. 1077 * 1078 * The command queue (#4/#9) must use this mode! 1079 * This mode does not require use of the Byte Count table in host DRAM. 1080 * 1081 * Driver controls scheduler operation via 3 means: 1082 * 1) Scheduler registers 1083 * 2) Shared scheduler data base in internal SRAM 1084 * 3) Shared data in host DRAM 1085 * 1086 * Initialization: 1087 * 1088 * When loading, driver should allocate memory for: 1089 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 1090 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 1091 * (1024 bytes for each queue). 1092 * 1093 * After receiving "Alive" response from uCode, driver must initialize 1094 * the scheduler (especially for queue #4/#9, the command queue, otherwise 1095 * the driver can't issue commands!): 1096 */ 1097 #define IWM_SCD_MEM_LOWER_BOUND (0x0000) 1098 1099 /** 1100 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1101 * can keep track of at one time when creating block-ack chains of frames. 1102 * Note that "64" matches the number of ack bits in a block-ack packet. 1103 */ 1104 #define IWM_SCD_WIN_SIZE 64 1105 #define IWM_SCD_FRAME_LIMIT 64 1106 1107 #define IWM_SCD_TXFIFO_POS_TID (0) 1108 #define IWM_SCD_TXFIFO_POS_RA (4) 1109 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 1110 1111 /* agn SCD */ 1112 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0) 1113 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 1114 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4) 1115 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 1116 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000) 1117 1118 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 1119 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 1120 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 1121 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 1122 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 1123 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 1124 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1125 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1126 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0) 1127 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18) 1128 1129 /* Context Data */ 1130 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600) 1131 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1132 1133 /* Tx status */ 1134 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0) 1135 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1136 1137 /* Translation Data */ 1138 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0) 1139 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808) 1140 1141 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\ 1142 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 1143 1144 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\ 1145 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 1146 1147 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 1148 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 1149 1150 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) 1151 1152 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0) 1153 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8) 1154 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c) 1155 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10) 1156 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14) 1157 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8) 1158 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244) 1159 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248) 1160 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108) 1161 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8) 1162 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254) 1163 1164 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl) 1165 { 1166 if (chnl < 20) 1167 return IWM_SCD_BASE + 0x18 + chnl * 4; 1168 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; 1169 } 1170 1171 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl) 1172 { 1173 if (chnl < 20) 1174 return IWM_SCD_BASE + 0x68 + chnl * 4; 1175 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; 1176 } 1177 1178 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl) 1179 { 1180 if (chnl < 20) 1181 return IWM_SCD_BASE + 0x10c + chnl * 4; 1182 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; 1183 } 1184 1185 /*********************** END TX SCHEDULER *************************************/ 1186 1187 /* Oscillator clock */ 1188 #define IWM_OSC_CLK (0xa04068) 1189 #define IWM_OSC_CLK_FORCE_CONTROL (0x8) 1190 1191 /****************************/ 1192 /* Flow Handler Definitions */ 1193 /****************************/ 1194 1195 /** 1196 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 1197 * Addresses are offsets from device's PCI hardware base address. 1198 */ 1199 #define IWM_FH_MEM_LOWER_BOUND (0x1000) 1200 #define IWM_FH_MEM_UPPER_BOUND (0x2000) 1201 1202 /** 1203 * Keep-Warm (KW) buffer base address. 1204 * 1205 * Driver must allocate a 4KByte buffer that is for keeping the 1206 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 1207 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 1208 * from going into a power-savings mode that would cause higher DRAM latency, 1209 * and possible data over/under-runs, before all Tx/Rx is complete. 1210 * 1211 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 1212 * of the buffer, which must be 4K aligned. Once this is set up, the device 1213 * automatically invokes keep-warm accesses when normal accesses might not 1214 * be sufficient to maintain fast DRAM response. 1215 * 1216 * Bit fields: 1217 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 1218 */ 1219 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C) 1220 1221 1222 /** 1223 * TFD Circular Buffers Base (CBBC) addresses 1224 * 1225 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 1226 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 1227 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 1228 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 1229 * aligned (address bits 0-7 must be 0). 1230 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 1231 * for them are in different places. 1232 * 1233 * Bit fields in each pointer register: 1234 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 1235 */ 1236 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1237 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10) 1238 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0) 1239 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1240 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20) 1241 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80) 1242 1243 /* Find TFD CB base pointer for given queue */ 1244 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl) 1245 { 1246 if (chnl < 16) 1247 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 1248 if (chnl < 20) 1249 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 1250 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 1251 } 1252 1253 1254 /** 1255 * Rx SRAM Control and Status Registers (RSCSR) 1256 * 1257 * These registers provide handshake between driver and device for the Rx queue 1258 * (this queue handles *all* command responses, notifications, Rx data, etc. 1259 * sent from uCode to host driver). Unlike Tx, there is only one Rx 1260 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 1261 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 1262 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 1263 * mapping between RBDs and RBs. 1264 * 1265 * Driver must allocate host DRAM memory for the following, and set the 1266 * physical address of each into device registers: 1267 * 1268 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 1269 * entries (although any power of 2, up to 4096, is selectable by driver). 1270 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 1271 * (typically 4K, although 8K or 16K are also selectable by driver). 1272 * Driver sets up RB size and number of RBDs in the CB via Rx config 1273 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG. 1274 * 1275 * Bit fields within one RBD: 1276 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 1277 * 1278 * Driver sets physical address [35:8] of base of RBD circular buffer 1279 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 1280 * 1281 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 1282 * (RBs) have been filled, via a "write pointer", actually the index of 1283 * the RB's corresponding RBD within the circular buffer. Driver sets 1284 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 1285 * 1286 * Bit fields in lower dword of Rx status buffer (upper dword not used 1287 * by driver: 1288 * 31-12: Not used by driver 1289 * 11- 0: Index of last filled Rx buffer descriptor 1290 * (device writes, driver reads this value) 1291 * 1292 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 1293 * enter pointers to these RBs into contiguous RBD circular buffer entries, 1294 * and update the device's "write" index register, 1295 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 1296 * 1297 * This "write" index corresponds to the *next* RBD that the driver will make 1298 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 1299 * the circular buffer. This value should initially be 0 (before preparing any 1300 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 1301 * wrap back to 0 at the end of the circular buffer (but don't wrap before 1302 * "read" index has advanced past 1! See below). 1303 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 1304 * 1305 * As the device fills RBs (referenced from contiguous RBDs within the circular 1306 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 1307 * to tell the driver the index of the latest filled RBD. The driver must 1308 * read this "read" index from DRAM after receiving an Rx interrupt from device 1309 * 1310 * The driver must also internally keep track of a third index, which is the 1311 * next RBD to process. When receiving an Rx interrupt, driver should process 1312 * all filled but unprocessed RBs up to, but not including, the RB 1313 * corresponding to the "read" index. For example, if "read" index becomes "1", 1314 * driver may process the RB pointed to by RBD 0. Depending on volume of 1315 * traffic, there may be many RBs to process. 1316 * 1317 * If read index == write index, device thinks there is no room to put new data. 1318 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 1319 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 1320 * and "read" indexes; that is, make sure that there are no more than 254 1321 * buffers waiting to be filled. 1322 */ 1323 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0) 1324 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1325 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND) 1326 1327 /** 1328 * Physical base address of 8-byte Rx Status buffer. 1329 * Bit fields: 1330 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 1331 */ 1332 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0) 1333 1334 /** 1335 * Physical base address of Rx Buffer Descriptor Circular Buffer. 1336 * Bit fields: 1337 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 1338 */ 1339 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004) 1340 1341 /** 1342 * Rx write pointer (index, really!). 1343 * Bit fields: 1344 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 1345 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 1346 */ 1347 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008) 1348 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 1349 1350 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c) 1351 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 1352 1353 /** 1354 * Rx Config/Status Registers (RCSR) 1355 * Rx Config Reg for channel 0 (only channel used) 1356 * 1357 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 1358 * normal operation (see bit fields). 1359 * 1360 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 1361 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for 1362 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 1363 * 1364 * Bit fields: 1365 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1366 * '10' operate normally 1367 * 29-24: reserved 1368 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 1369 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 1370 * 19-18: reserved 1371 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 1372 * '10' 12K, '11' 16K. 1373 * 15-14: reserved 1374 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 1375 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 1376 * typical value 0x10 (about 1/2 msec) 1377 * 3- 0: reserved 1378 */ 1379 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00) 1380 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0) 1381 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND) 1382 1383 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0) 1384 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8) 1385 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10) 1386 1387 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 1388 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 1389 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 1390 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 1391 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 1392 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 1393 1394 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 1395 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 1396 #define IWM_RX_RB_TIMEOUT (0x11) 1397 1398 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1399 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1400 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1401 1402 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1403 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 1404 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 1405 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 1406 1407 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 1408 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1409 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1410 1411 /** 1412 * Rx Shared Status Registers (RSSR) 1413 * 1414 * After stopping Rx DMA channel (writing 0 to 1415 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 1416 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 1417 * 1418 * Bit fields: 1419 * 24: 1 = Channel 0 is idle 1420 * 1421 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 1422 * contain default values that should not be altered by the driver. 1423 */ 1424 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40) 1425 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1426 1427 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND) 1428 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004) 1429 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 1430 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008) 1431 1432 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 1433 1434 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 1435 1436 /* TFDB Area - TFDs buffer table */ 1437 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 1438 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900) 1439 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958) 1440 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 1441 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 1442 1443 /** 1444 * Transmit DMA Channel Control/Status Registers (TCSR) 1445 * 1446 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 1447 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 1448 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 1449 * 1450 * To use a Tx DMA channel, driver must initialize its 1451 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 1452 * 1453 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 1454 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 1455 * 1456 * All other bits should be 0. 1457 * 1458 * Bit fields: 1459 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 1460 * '10' operate normally 1461 * 29- 4: Reserved, set to "0" 1462 * 3: Enable internal DMA requests (1, normal operation), disable (0) 1463 * 2- 0: Reserved, set to "0" 1464 */ 1465 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00) 1466 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60) 1467 1468 /* Find Control/Status reg for given Tx DMA/FIFO channel */ 1469 #define IWM_FH_TCSR_CHNL_NUM (8) 1470 1471 /* TCSR: tx_config register values */ 1472 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 1473 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 1474 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 1475 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 1476 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 1477 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 1478 1479 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 1480 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 1481 1482 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 1483 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 1484 1485 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 1486 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 1487 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 1488 1489 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 1490 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 1491 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 1492 1493 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 1494 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 1495 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 1496 1497 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 1498 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 1499 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 1500 1501 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 1502 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 1503 1504 /** 1505 * Tx Shared Status Registers (TSSR) 1506 * 1507 * After stopping Tx DMA channel (writing 0 to 1508 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 1509 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 1510 * (channel's buffers empty | no pending requests). 1511 * 1512 * Bit fields: 1513 * 31-24: 1 = Channel buffers empty (channel 7:0) 1514 * 23-16: 1 = No pending requests (channel 7:0) 1515 */ 1516 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0) 1517 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0) 1518 1519 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010) 1520 1521 /** 1522 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 1523 * 31: Indicates an address error when accessed to internal memory 1524 * uCode/driver must write "1" in order to clear this flag 1525 * 30: Indicates that Host did not send the expected number of dwords to FH 1526 * uCode/driver must write "1" in order to clear this flag 1527 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 1528 * command was received from the scheduler while the TRB was already full 1529 * with previous command 1530 * uCode/driver must write "1" in order to clear this flag 1531 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 1532 * bit is set, it indicates that the FH has received a full indication 1533 * from the RTC TxFIFO and the current value of the TxCredit counter was 1534 * not equal to zero. This mean that the credit mechanism was not 1535 * synchronized to the TxFIFO status 1536 * uCode/driver must write "1" in order to clear this flag 1537 */ 1538 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018) 1539 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008) 1540 1541 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 1542 1543 /* Tx service channels */ 1544 #define IWM_FH_SRVC_CHNL (9) 1545 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8) 1546 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0) 1547 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 1548 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 1549 1550 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98) 1551 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \ 1552 (_chan) * 4) 1553 1554 /* Instruct FH to increment the retry count of a packet when 1555 * it is brought from the memory to TX-FIFO 1556 */ 1557 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 1558 1559 #define IWM_RX_QUEUE_SIZE 256 1560 #define IWM_RX_QUEUE_MASK 255 1561 #define IWM_RX_QUEUE_SIZE_LOG 8 1562 1563 /* 1564 * RX related structures and functions 1565 */ 1566 #define IWM_RX_FREE_BUFFERS 64 1567 #define IWM_RX_LOW_WATERMARK 8 1568 1569 /** 1570 * struct iwm_rb_status - reseve buffer status 1571 * host memory mapped FH registers 1572 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1573 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1574 * @finished_rb_num [0:11] - Indicates the index of the current RB 1575 * in which the last frame was written to 1576 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1577 * which was transferred 1578 */ 1579 struct iwm_rb_status { 1580 uint16_t closed_rb_num; 1581 uint16_t closed_fr_num; 1582 uint16_t finished_rb_num; 1583 uint16_t finished_fr_nam; 1584 uint32_t unused; 1585 } __packed; 1586 1587 1588 #define IWM_TFD_QUEUE_SIZE_MAX (256) 1589 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64) 1590 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \ 1591 IWM_TFD_QUEUE_SIZE_BC_DUP) 1592 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36) 1593 #define IWM_NUM_OF_TBS 20 1594 1595 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr) 1596 { 1597 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF; 1598 } 1599 /** 1600 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor 1601 * 1602 * This structure contains dma address and length of transmission address 1603 * 1604 * @lo: low [31:0] portion of the dma address of TX buffer 1605 * every even is unaligned on 16 bit boundary 1606 * @hi_n_len 0-3 [35:32] portion of dma 1607 * 4-15 length of the tx buffer 1608 */ 1609 struct iwm_tfd_tb { 1610 uint32_t lo; 1611 uint16_t hi_n_len; 1612 } __packed; 1613 1614 /** 1615 * struct iwm_tfd 1616 * 1617 * Transmit Frame Descriptor (TFD) 1618 * 1619 * @ __reserved1[3] reserved 1620 * @ num_tbs 0-4 number of active tbs 1621 * 5 reserved 1622 * 6-7 padding (not used) 1623 * @ tbs[20] transmit frame buffer descriptors 1624 * @ __pad padding 1625 * 1626 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1627 * Both driver and device share these circular buffers, each of which must be 1628 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 1629 * 1630 * Driver must indicate the physical address of the base of each 1631 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers. 1632 * 1633 * Each TFD contains pointer/size information for up to 20 data buffers 1634 * in host DRAM. These buffers collectively contain the (one) frame described 1635 * by the TFD. Each buffer must be a single contiguous block of memory within 1636 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1637 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1638 * Tx frame, up to 8 KBytes in size. 1639 * 1640 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1641 */ 1642 struct iwm_tfd { 1643 uint8_t __reserved1[3]; 1644 uint8_t num_tbs; 1645 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS]; 1646 uint32_t __pad; 1647 } __packed; 1648 1649 /* Keep Warm Size */ 1650 #define IWM_KW_SIZE 0x1000 /* 4k */ 1651 1652 /* Fixed (non-configurable) rx data from phy */ 1653 1654 /** 1655 * struct iwm_agn_schedq_bc_tbl scheduler byte count table 1656 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR 1657 * @tfd_offset 0-12 - tx command byte count 1658 * 12-16 - station index 1659 */ 1660 struct iwm_agn_scd_bc_tbl { 1661 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE]; 1662 } __packed; 1663 1664 /* Maximum number of Tx queues. */ 1665 #define IWM_MVM_MAX_QUEUES 31 1666 1667 /* Tx queue numbers */ 1668 enum { 1669 IWM_MVM_OFFCHANNEL_QUEUE = 8, 1670 IWM_MVM_CMD_QUEUE = 9, 1671 IWM_MVM_AUX_QUEUE = 15, 1672 }; 1673 1674 enum iwm_mvm_tx_fifo { 1675 IWM_MVM_TX_FIFO_BK = 0, 1676 IWM_MVM_TX_FIFO_BE, 1677 IWM_MVM_TX_FIFO_VI, 1678 IWM_MVM_TX_FIFO_VO, 1679 IWM_MVM_TX_FIFO_MCAST = 5, 1680 IWM_MVM_TX_FIFO_CMD = 7, 1681 }; 1682 1683 #define IWM_MVM_STATION_COUNT 16 1684 1685 /* commands */ 1686 enum { 1687 IWM_MVM_ALIVE = 0x1, 1688 IWM_REPLY_ERROR = 0x2, 1689 1690 IWM_INIT_COMPLETE_NOTIF = 0x4, 1691 1692 /* PHY context commands */ 1693 IWM_PHY_CONTEXT_CMD = 0x8, 1694 IWM_DBG_CFG = 0x9, 1695 1696 /* UMAC scan commands */ 1697 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5, 1698 IWM_SCAN_CFG_CMD = 0xc, 1699 IWM_SCAN_REQ_UMAC = 0xd, 1700 IWM_SCAN_ABORT_UMAC = 0xe, 1701 IWM_SCAN_COMPLETE_UMAC = 0xf, 1702 1703 /* station table */ 1704 IWM_ADD_STA_KEY = 0x17, 1705 IWM_ADD_STA = 0x18, 1706 IWM_REMOVE_STA = 0x19, 1707 1708 /* TX */ 1709 IWM_TX_CMD = 0x1c, 1710 IWM_TXPATH_FLUSH = 0x1e, 1711 IWM_MGMT_MCAST_KEY = 0x1f, 1712 1713 /* scheduler config */ 1714 IWM_SCD_QUEUE_CFG = 0x1d, 1715 1716 /* global key */ 1717 IWM_WEP_KEY = 0x20, 1718 1719 /* MAC and Binding commands */ 1720 IWM_MAC_CONTEXT_CMD = 0x28, 1721 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */ 1722 IWM_TIME_EVENT_NOTIFICATION = 0x2a, 1723 IWM_BINDING_CONTEXT_CMD = 0x2b, 1724 IWM_TIME_QUOTA_CMD = 0x2c, 1725 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d, 1726 1727 IWM_LQ_CMD = 0x4e, 1728 1729 /* paging block to FW cpu2 */ 1730 IWM_FW_PAGING_BLOCK_CMD = 0x4f, 1731 1732 /* Scan offload */ 1733 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51, 1734 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52, 1735 IWM_HOT_SPOT_CMD = 0x53, 1736 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d, 1737 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e, 1738 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f, 1739 IWM_MATCH_FOUND_NOTIFICATION = 0xd9, 1740 IWM_SCAN_ITERATION_COMPLETE = 0xe7, 1741 1742 /* Phy */ 1743 IWM_PHY_CONFIGURATION_CMD = 0x6a, 1744 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b, 1745 IWM_PHY_DB_CMD = 0x6c, 1746 1747 /* Power - legacy power table command */ 1748 IWM_POWER_TABLE_CMD = 0x77, 1749 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78, 1750 IWM_LTR_CONFIG = 0xee, 1751 1752 /* Thermal Throttling*/ 1753 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e, 1754 1755 /* NVM */ 1756 IWM_NVM_ACCESS_CMD = 0x88, 1757 1758 IWM_SET_CALIB_DEFAULT_CMD = 0x8e, 1759 1760 IWM_BEACON_NOTIFICATION = 0x90, 1761 IWM_BEACON_TEMPLATE_CMD = 0x91, 1762 IWM_TX_ANT_CONFIGURATION_CMD = 0x98, 1763 IWM_BT_CONFIG = 0x9b, 1764 IWM_STATISTICS_NOTIFICATION = 0x9d, 1765 IWM_REDUCE_TX_POWER_CMD = 0x9f, 1766 1767 /* RF-KILL commands and notifications */ 1768 IWM_CARD_STATE_CMD = 0xa0, 1769 IWM_CARD_STATE_NOTIFICATION = 0xa1, 1770 1771 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2, 1772 1773 IWM_MFUART_LOAD_NOTIFICATION = 0xb1, 1774 1775 /* Power - new power table command */ 1776 IWM_MAC_PM_POWER_TABLE = 0xa9, 1777 1778 IWM_REPLY_RX_PHY_CMD = 0xc0, 1779 IWM_REPLY_RX_MPDU_CMD = 0xc1, 1780 IWM_BA_NOTIF = 0xc5, 1781 1782 /* Location Aware Regulatory */ 1783 IWM_MCC_UPDATE_CMD = 0xc8, 1784 IWM_MCC_CHUB_UPDATE_CMD = 0xc9, 1785 1786 /* BT Coex */ 1787 IWM_BT_COEX_PRIO_TABLE = 0xcc, 1788 IWM_BT_COEX_PROT_ENV = 0xcd, 1789 IWM_BT_PROFILE_NOTIFICATION = 0xce, 1790 IWM_BT_COEX_CI = 0x5d, 1791 1792 IWM_REPLY_SF_CFG_CMD = 0xd1, 1793 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2, 1794 1795 /* DTS measurements */ 1796 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc, 1797 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd, 1798 1799 IWM_REPLY_DEBUG_CMD = 0xf0, 1800 IWM_DEBUG_LOG_MSG = 0xf7, 1801 1802 IWM_MCAST_FILTER_CMD = 0xd0, 1803 1804 /* D3 commands/notifications */ 1805 IWM_D3_CONFIG_CMD = 0xd3, 1806 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4, 1807 IWM_OFFLOADS_QUERY_CMD = 0xd5, 1808 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6, 1809 1810 /* for WoWLAN in particular */ 1811 IWM_WOWLAN_PATTERNS = 0xe0, 1812 IWM_WOWLAN_CONFIGURATION = 0xe1, 1813 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2, 1814 IWM_WOWLAN_TKIP_PARAM = 0xe3, 1815 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4, 1816 IWM_WOWLAN_GET_STATUSES = 0xe5, 1817 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6, 1818 1819 /* and for NetDetect */ 1820 IWM_NET_DETECT_CONFIG_CMD = 0x54, 1821 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56, 1822 IWM_NET_DETECT_PROFILES_CMD = 0x57, 1823 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58, 1824 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59, 1825 1826 IWM_REPLY_MAX = 0xff, 1827 }; 1828 1829 enum iwm_phy_ops_subcmd_ids { 1830 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0, 1831 IWM_CTDP_CONFIG_CMD = 0x03, 1832 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04, 1833 IWM_CT_KILL_NOTIFICATION = 0xFE, 1834 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF, 1835 }; 1836 1837 /* command groups */ 1838 enum { 1839 IWM_LEGACY_GROUP = 0x0, 1840 IWM_LONG_GROUP = 0x1, 1841 IWM_SYSTEM_GROUP = 0x2, 1842 IWM_MAC_CONF_GROUP = 0x3, 1843 IWM_PHY_OPS_GROUP = 0x4, 1844 IWM_DATA_PATH_GROUP = 0x5, 1845 IWM_PROT_OFFLOAD_GROUP = 0xb, 1846 }; 1847 1848 /** 1849 * struct iwm_cmd_response - generic response struct for most commands 1850 * @status: status of the command asked, changes for each one 1851 */ 1852 struct iwm_cmd_response { 1853 uint32_t status; 1854 }; 1855 1856 /* 1857 * struct iwm_tx_ant_cfg_cmd 1858 * @valid: valid antenna configuration 1859 */ 1860 struct iwm_tx_ant_cfg_cmd { 1861 uint32_t valid; 1862 } __packed; 1863 1864 /** 1865 * struct iwm_reduce_tx_power_cmd - TX power reduction command 1866 * IWM_REDUCE_TX_POWER_CMD = 0x9f 1867 * @flags: (reserved for future implementation) 1868 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1869 * @pwr_restriction: TX power restriction in dBms. 1870 */ 1871 struct iwm_reduce_tx_power_cmd { 1872 uint8_t flags; 1873 uint8_t mac_context_id; 1874 uint16_t pwr_restriction; 1875 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */ 1876 1877 enum iwm_dev_tx_power_cmd_mode { 1878 IWM_TX_POWER_MODE_SET_MAC = 0, 1879 IWM_TX_POWER_MODE_SET_DEVICE = 1, 1880 IWM_TX_POWER_MODE_SET_CHAINS = 2, 1881 IWM_TX_POWER_MODE_SET_ACK = 3, 1882 }; /* TX_POWER_REDUCED_FLAGS_TYPE_API_E_VER_4 */ 1883 1884 #define IWM_NUM_CHAIN_LIMITS 2 1885 #define IWM_NUM_SUB_BANDS 5 1886 1887 /** 1888 * struct iwm_dev_tx_power_cmd - TX power reduction command 1889 * @set_mode: see &enum iwl_dev_tx_power_cmd_mode 1890 * @mac_context_id: id of the mac ctx for which we are reducing TX power. 1891 * @pwr_restriction: TX power restriction in 1/8 dBms. 1892 * @dev_24: device TX power restriction in 1/8 dBms 1893 * @dev_52_low: device TX power restriction upper band - low 1894 * @dev_52_high: device TX power restriction upper band - high 1895 * @per_chain_restriction: per chain restrictions 1896 */ 1897 struct iwm_dev_tx_power_cmd_v3 { 1898 uint32_t set_mode; 1899 uint32_t mac_context_id; 1900 uint16_t pwr_restriction; 1901 uint16_t dev_24; 1902 uint16_t dev_52_low; 1903 uint16_t dev_52_high; 1904 uint16_t per_chain_restriction[IWM_NUM_CHAIN_LIMITS][IWM_NUM_SUB_BANDS]; 1905 } __packed; /* TX_REDUCED_POWER_API_S_VER_3 */ 1906 1907 #define IWM_DEV_MAX_TX_POWER 0x7FFF 1908 1909 /** 1910 * struct iwm_dev_tx_power_cmd - TX power reduction command 1911 * @v3: version 3 of the command, embedded here for easier software handling 1912 * @enable_ack_reduction: enable or disable close range ack TX power 1913 * reduction. 1914 */ 1915 struct iwm_dev_tx_power_cmd { 1916 /* v4 is just an extension of v3 - keep this here */ 1917 struct iwm_dev_tx_power_cmd_v3 v3; 1918 uint8_t enable_ack_reduction; 1919 uint8_t reserved[3]; 1920 } __packed; /* TX_REDUCED_POWER_API_S_VER_4 */ 1921 1922 /* 1923 * Calibration control struct. 1924 * Sent as part of the phy configuration command. 1925 * @flow_trigger: bitmap for which calibrations to perform according to 1926 * flow triggers. 1927 * @event_trigger: bitmap for which calibrations to perform according to 1928 * event triggers. 1929 */ 1930 struct iwm_calib_ctrl { 1931 uint32_t flow_trigger; 1932 uint32_t event_trigger; 1933 } __packed; 1934 1935 /* This enum defines the bitmap of various calibrations to enable in both 1936 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD. 1937 */ 1938 enum iwm_calib_cfg { 1939 IWM_CALIB_CFG_XTAL_IDX = (1 << 0), 1940 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1), 1941 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2), 1942 IWM_CALIB_CFG_PAPD_IDX = (1 << 3), 1943 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4), 1944 IWM_CALIB_CFG_DC_IDX = (1 << 5), 1945 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6), 1946 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7), 1947 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8), 1948 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9), 1949 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10), 1950 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11), 1951 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12), 1952 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13), 1953 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14), 1954 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15), 1955 IWM_CALIB_CFG_DAC_IDX = (1 << 16), 1956 IWM_CALIB_CFG_ABS_IDX = (1 << 17), 1957 IWM_CALIB_CFG_AGC_IDX = (1 << 18), 1958 }; 1959 1960 /* 1961 * Phy configuration command. 1962 */ 1963 struct iwm_phy_cfg_cmd { 1964 uint32_t phy_cfg; 1965 struct iwm_calib_ctrl calib_control; 1966 } __packed; 1967 1968 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1969 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1970 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1971 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1972 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8) 1973 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9) 1974 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10) 1975 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12) 1976 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13) 1977 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14) 1978 1979 1980 /* Target of the IWM_NVM_ACCESS_CMD */ 1981 enum { 1982 IWM_NVM_ACCESS_TARGET_CACHE = 0, 1983 IWM_NVM_ACCESS_TARGET_OTP = 1, 1984 IWM_NVM_ACCESS_TARGET_EEPROM = 2, 1985 }; 1986 1987 /* Section types for IWM_NVM_ACCESS_CMD */ 1988 enum { 1989 IWM_NVM_SECTION_TYPE_SW = 1, 1990 IWM_NVM_SECTION_TYPE_REGULATORY = 3, 1991 IWM_NVM_SECTION_TYPE_CALIBRATION = 4, 1992 IWM_NVM_SECTION_TYPE_PRODUCTION = 5, 1993 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11, 1994 IWM_NVM_SECTION_TYPE_PHY_SKU = 12, 1995 IWM_NVM_MAX_NUM_SECTIONS = 13, 1996 }; 1997 1998 /** 1999 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section 2000 * @op_code: 0 - read, 1 - write 2001 * @target: IWM_NVM_ACCESS_TARGET_* 2002 * @type: IWM_NVM_SECTION_TYPE_* 2003 * @offset: offset in bytes into the section 2004 * @length: in bytes, to read/write 2005 * @data: if write operation, the data to write. On read its empty 2006 */ 2007 struct iwm_nvm_access_cmd { 2008 uint8_t op_code; 2009 uint8_t target; 2010 uint16_t type; 2011 uint16_t offset; 2012 uint16_t length; 2013 uint8_t data[]; 2014 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */ 2015 2016 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */ 2017 2018 /* 2019 * struct iwm_fw_paging_cmd - paging layout 2020 * 2021 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f) 2022 * 2023 * Send to FW the paging layout in the driver. 2024 * 2025 * @flags: various flags for the command 2026 * @block_size: the block size in powers of 2 2027 * @block_num: number of blocks specified in the command. 2028 * @device_phy_addr: virtual addresses from device side 2029 */ 2030 struct iwm_fw_paging_cmd { 2031 uint32_t flags; 2032 uint32_t block_size; 2033 uint32_t block_num; 2034 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS]; 2035 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */ 2036 2037 /* 2038 * Fw items ID's 2039 * 2040 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload 2041 * download 2042 */ 2043 enum iwm_fw_item_id { 2044 IWM_FW_ITEM_ID_PAGING = 3, 2045 }; 2046 2047 /* 2048 * struct iwm_fw_get_item_cmd - get an item from the fw 2049 */ 2050 struct iwm_fw_get_item_cmd { 2051 uint32_t item_id; 2052 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */ 2053 2054 /** 2055 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD 2056 * @offset: offset in bytes into the section 2057 * @length: in bytes, either how much was written or read 2058 * @type: IWM_NVM_SECTION_TYPE_* 2059 * @status: 0 for success, fail otherwise 2060 * @data: if read operation, the data returned. Empty on write. 2061 */ 2062 struct iwm_nvm_access_resp { 2063 uint16_t offset; 2064 uint16_t length; 2065 uint16_t type; 2066 uint16_t status; 2067 uint8_t data[]; 2068 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */ 2069 2070 /* IWM_MVM_ALIVE 0x1 */ 2071 2072 /* alive response is_valid values */ 2073 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0) 2074 #define IWM_ALIVE_RESP_RFKILL (1 << 1) 2075 2076 /* alive response ver_type values */ 2077 enum { 2078 IWM_FW_TYPE_HW = 0, 2079 IWM_FW_TYPE_PROT = 1, 2080 IWM_FW_TYPE_AP = 2, 2081 IWM_FW_TYPE_WOWLAN = 3, 2082 IWM_FW_TYPE_TIMING = 4, 2083 IWM_FW_TYPE_WIPAN = 5 2084 }; 2085 2086 /* alive response ver_subtype values */ 2087 enum { 2088 IWM_FW_SUBTYPE_FULL_FEATURE = 0, 2089 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */ 2090 IWM_FW_SUBTYPE_REDUCED = 2, 2091 IWM_FW_SUBTYPE_ALIVE_ONLY = 3, 2092 IWM_FW_SUBTYPE_WOWLAN = 4, 2093 IWM_FW_SUBTYPE_AP_SUBTYPE = 5, 2094 IWM_FW_SUBTYPE_WIPAN = 6, 2095 IWM_FW_SUBTYPE_INITIALIZE = 9 2096 }; 2097 2098 #define IWM_ALIVE_STATUS_ERR 0xDEAD 2099 #define IWM_ALIVE_STATUS_OK 0xCAFE 2100 2101 #define IWM_ALIVE_FLG_RFKILL (1 << 0) 2102 2103 struct iwm_mvm_alive_resp_ver1 { 2104 uint16_t status; 2105 uint16_t flags; 2106 uint8_t ucode_minor; 2107 uint8_t ucode_major; 2108 uint16_t id; 2109 uint8_t api_minor; 2110 uint8_t api_major; 2111 uint8_t ver_subtype; 2112 uint8_t ver_type; 2113 uint8_t mac; 2114 uint8_t opt; 2115 uint16_t reserved2; 2116 uint32_t timestamp; 2117 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2118 uint32_t log_event_table_ptr; /* SRAM address for event log */ 2119 uint32_t cpu_register_ptr; 2120 uint32_t dbgm_config_ptr; 2121 uint32_t alive_counter_ptr; 2122 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2123 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */ 2124 2125 struct iwm_mvm_alive_resp_ver2 { 2126 uint16_t status; 2127 uint16_t flags; 2128 uint8_t ucode_minor; 2129 uint8_t ucode_major; 2130 uint16_t id; 2131 uint8_t api_minor; 2132 uint8_t api_major; 2133 uint8_t ver_subtype; 2134 uint8_t ver_type; 2135 uint8_t mac; 2136 uint8_t opt; 2137 uint16_t reserved2; 2138 uint32_t timestamp; 2139 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2140 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2141 uint32_t cpu_register_ptr; 2142 uint32_t dbgm_config_ptr; 2143 uint32_t alive_counter_ptr; 2144 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2145 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2146 uint32_t st_fwrd_size; 2147 uint8_t umac_minor; /* UMAC version: minor */ 2148 uint8_t umac_major; /* UMAC version: major */ 2149 uint16_t umac_id; /* UMAC version: id */ 2150 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2151 uint32_t dbg_print_buff_addr; 2152 } __packed; /* ALIVE_RES_API_S_VER_2 */ 2153 2154 struct iwm_mvm_alive_resp { 2155 uint16_t status; 2156 uint16_t flags; 2157 uint32_t ucode_minor; 2158 uint32_t ucode_major; 2159 uint8_t ver_subtype; 2160 uint8_t ver_type; 2161 uint8_t mac; 2162 uint8_t opt; 2163 uint32_t timestamp; 2164 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2165 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2166 uint32_t cpu_register_ptr; 2167 uint32_t dbgm_config_ptr; 2168 uint32_t alive_counter_ptr; 2169 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2170 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2171 uint32_t st_fwrd_size; 2172 uint32_t umac_minor; /* UMAC version: minor */ 2173 uint32_t umac_major; /* UMAC version: major */ 2174 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2175 uint32_t dbg_print_buff_addr; 2176 } __packed; /* ALIVE_RES_API_S_VER_3 */ 2177 2178 /* Error response/notification */ 2179 enum { 2180 IWM_FW_ERR_UNKNOWN_CMD = 0x0, 2181 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1, 2182 IWM_FW_ERR_SERVICE = 0x2, 2183 IWM_FW_ERR_ARC_MEMORY = 0x3, 2184 IWM_FW_ERR_ARC_CODE = 0x4, 2185 IWM_FW_ERR_WATCH_DOG = 0x5, 2186 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10, 2187 IWM_FW_ERR_WEP_KEY_SIZE = 0x11, 2188 IWM_FW_ERR_OBSOLETE_FUNC = 0x12, 2189 IWM_FW_ERR_UNEXPECTED = 0xFE, 2190 IWM_FW_ERR_FATAL = 0xFF 2191 }; 2192 2193 /** 2194 * struct iwm_error_resp - FW error indication 2195 * ( IWM_REPLY_ERROR = 0x2 ) 2196 * @error_type: one of IWM_FW_ERR_* 2197 * @cmd_id: the command ID for which the error occurred 2198 * @bad_cmd_seq_num: sequence number of the erroneous command 2199 * @error_service: which service created the error, applicable only if 2200 * error_type = 2, otherwise 0 2201 * @timestamp: TSF in usecs. 2202 */ 2203 struct iwm_error_resp { 2204 uint32_t error_type; 2205 uint8_t cmd_id; 2206 uint8_t reserved1; 2207 uint16_t bad_cmd_seq_num; 2208 uint32_t error_service; 2209 uint64_t timestamp; 2210 } __packed; 2211 2212 2213 /* Common PHY, MAC and Bindings definitions */ 2214 2215 #define IWM_MAX_MACS_IN_BINDING (3) 2216 #define IWM_MAX_BINDINGS (4) 2217 #define IWM_AUX_BINDING_INDEX (3) 2218 #define IWM_MAX_PHYS (4) 2219 2220 /* Used to extract ID and color from the context dword */ 2221 #define IWM_FW_CTXT_ID_POS (0) 2222 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS) 2223 #define IWM_FW_CTXT_COLOR_POS (8) 2224 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS) 2225 #define IWM_FW_CTXT_INVALID (0xffffffff) 2226 2227 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\ 2228 (_color << IWM_FW_CTXT_COLOR_POS)) 2229 2230 /* Possible actions on PHYs, MACs and Bindings */ 2231 enum { 2232 IWM_FW_CTXT_ACTION_STUB = 0, 2233 IWM_FW_CTXT_ACTION_ADD, 2234 IWM_FW_CTXT_ACTION_MODIFY, 2235 IWM_FW_CTXT_ACTION_REMOVE, 2236 IWM_FW_CTXT_ACTION_NUM 2237 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2238 2239 /* Time Events */ 2240 2241 /* Time Event types, according to MAC type */ 2242 enum iwm_time_event_type { 2243 /* BSS Station Events */ 2244 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC, 2245 IWM_TE_BSS_STA_ASSOC, 2246 IWM_TE_BSS_EAP_DHCP_PROT, 2247 IWM_TE_BSS_QUIET_PERIOD, 2248 2249 /* P2P Device Events */ 2250 IWM_TE_P2P_DEVICE_DISCOVERABLE, 2251 IWM_TE_P2P_DEVICE_LISTEN, 2252 IWM_TE_P2P_DEVICE_ACTION_SCAN, 2253 IWM_TE_P2P_DEVICE_FULL_SCAN, 2254 2255 /* P2P Client Events */ 2256 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC, 2257 IWM_TE_P2P_CLIENT_ASSOC, 2258 IWM_TE_P2P_CLIENT_QUIET_PERIOD, 2259 2260 /* P2P GO Events */ 2261 IWM_TE_P2P_GO_ASSOC_PROT, 2262 IWM_TE_P2P_GO_REPETITIVE_NOA, 2263 IWM_TE_P2P_GO_CT_WINDOW, 2264 2265 /* WiDi Sync Events */ 2266 IWM_TE_WIDI_TX_SYNC, 2267 2268 IWM_TE_MAX 2269 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */ 2270 2271 2272 2273 /* Time event - defines for command API v1 */ 2274 2275 /* 2276 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed. 2277 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2278 * the first fragment is scheduled. 2279 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only 2280 * the first 2 fragments are scheduled. 2281 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2282 * number of fragments are valid. 2283 * 2284 * Other than the constant defined above, specifying a fragmentation value 'x' 2285 * means that the event can be fragmented but only the first 'x' will be 2286 * scheduled. 2287 */ 2288 enum { 2289 IWM_TE_V1_FRAG_NONE = 0, 2290 IWM_TE_V1_FRAG_SINGLE = 1, 2291 IWM_TE_V1_FRAG_DUAL = 2, 2292 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff 2293 }; 2294 2295 /* If a Time Event can be fragmented, this is the max number of fragments */ 2296 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff 2297 /* Repeat the time event endlessly (until removed) */ 2298 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff 2299 /* If a Time Event has bounded repetitions, this is the maximal value */ 2300 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff 2301 2302 /* Time Event dependencies: none, on another TE, or in a specific time */ 2303 enum { 2304 IWM_TE_V1_INDEPENDENT = 0, 2305 IWM_TE_V1_DEP_OTHER = (1 << 0), 2306 IWM_TE_V1_DEP_TSF = (1 << 1), 2307 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2), 2308 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */ 2309 2310 /* 2311 * @IWM_TE_V1_NOTIF_NONE: no notifications 2312 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start 2313 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end 2314 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use 2315 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use. 2316 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2317 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2318 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use. 2319 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use. 2320 * 2321 * Supported Time event notifications configuration. 2322 * A notification (both event and fragment) includes a status indicating weather 2323 * the FW was able to schedule the event or not. For fragment start/end 2324 * notification the status is always success. There is no start/end fragment 2325 * notification for monolithic events. 2326 */ 2327 enum { 2328 IWM_TE_V1_NOTIF_NONE = 0, 2329 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0), 2330 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1), 2331 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2332 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2333 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4), 2334 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5), 2335 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2336 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2337 IWM_T2_V2_START_IMMEDIATELY = (1 << 11), 2338 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */ 2339 2340 /* Time event - defines for command API */ 2341 2342 /* 2343 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2344 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2345 * the first fragment is scheduled. 2346 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2347 * the first 2 fragments are scheduled. 2348 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2349 * number of fragments are valid. 2350 * 2351 * Other than the constant defined above, specifying a fragmentation value 'x' 2352 * means that the event can be fragmented but only the first 'x' will be 2353 * scheduled. 2354 */ 2355 enum { 2356 IWM_TE_V2_FRAG_NONE = 0, 2357 IWM_TE_V2_FRAG_SINGLE = 1, 2358 IWM_TE_V2_FRAG_DUAL = 2, 2359 IWM_TE_V2_FRAG_MAX = 0xfe, 2360 IWM_TE_V2_FRAG_ENDLESS = 0xff 2361 }; 2362 2363 /* Repeat the time event endlessly (until removed) */ 2364 #define IWM_TE_V2_REPEAT_ENDLESS 0xff 2365 /* If a Time Event has bounded repetitions, this is the maximal value */ 2366 #define IWM_TE_V2_REPEAT_MAX 0xfe 2367 2368 #define IWM_TE_V2_PLACEMENT_POS 12 2369 #define IWM_TE_V2_ABSENCE_POS 15 2370 2371 /* Time event policy values 2372 * A notification (both event and fragment) includes a status indicating weather 2373 * the FW was able to schedule the event or not. For fragment start/end 2374 * notification the status is always success. There is no start/end fragment 2375 * notification for monolithic events. 2376 * 2377 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2378 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2379 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2380 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2381 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2382 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2383 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2384 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2385 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2386 * @IWM_TE_V2_DEP_OTHER: depends on another time event 2387 * @IWM_TE_V2_DEP_TSF: depends on a specific time 2388 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2389 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event. 2390 */ 2391 enum { 2392 IWM_TE_V2_DEFAULT_POLICY = 0x0, 2393 2394 /* notifications (event start/stop, fragment start/stop) */ 2395 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0), 2396 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1), 2397 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2), 2398 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3), 2399 2400 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4), 2401 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5), 2402 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6), 2403 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7), 2404 2405 IWM_TE_V2_NOTIF_MSK = 0xff, 2406 2407 /* placement characteristics */ 2408 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS), 2409 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)), 2410 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)), 2411 2412 /* are we present or absent during the Time Event. */ 2413 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS), 2414 }; 2415 2416 /** 2417 * struct iwm_time_event_cmd_api - configuring Time Events 2418 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2419 * with version 1. determined by IWM_UCODE_TLV_FLAGS) 2420 * ( IWM_TIME_EVENT_CMD = 0x29 ) 2421 * @id_and_color: ID and color of the relevant MAC 2422 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2423 * @id: this field has two meanings, depending on the action: 2424 * If the action is ADD, then it means the type of event to add. 2425 * For all other actions it is the unique event ID assigned when the 2426 * event was added by the FW. 2427 * @apply_time: When to start the Time Event (in GP2) 2428 * @max_delay: maximum delay to event's start (apply time), in TU 2429 * @depends_on: the unique ID of the event we depend on (if any) 2430 * @interval: interval between repetitions, in TU 2431 * @duration: duration of event in TU 2432 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS 2433 * @max_frags: maximal number of fragments the Time Event can be divided to 2434 * @policy: defines whether uCode shall notify the host or other uCode modules 2435 * on event and/or fragment start and/or end 2436 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF 2437 * IWM_TE_EVENT_SOCIOPATHIC 2438 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_* 2439 */ 2440 struct iwm_time_event_cmd { 2441 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2442 uint32_t id_and_color; 2443 uint32_t action; 2444 uint32_t id; 2445 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2446 uint32_t apply_time; 2447 uint32_t max_delay; 2448 uint32_t depends_on; 2449 uint32_t interval; 2450 uint32_t duration; 2451 uint8_t repeat; 2452 uint8_t max_frags; 2453 uint16_t policy; 2454 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2455 2456 /** 2457 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd 2458 * @status: bit 0 indicates success, all others specify errors 2459 * @id: the Time Event type 2460 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2461 * @id_and_color: ID and color of the relevant MAC 2462 */ 2463 struct iwm_time_event_resp { 2464 uint32_t status; 2465 uint32_t id; 2466 uint32_t unique_id; 2467 uint32_t id_and_color; 2468 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2469 2470 /** 2471 * struct iwm_time_event_notif - notifications of time event start/stop 2472 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a ) 2473 * @timestamp: action timestamp in GP2 2474 * @session_id: session's unique id 2475 * @unique_id: unique id of the Time Event itself 2476 * @id_and_color: ID and color of the relevant MAC 2477 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END 2478 * @status: true if scheduled, false otherwise (not executed) 2479 */ 2480 struct iwm_time_event_notif { 2481 uint32_t timestamp; 2482 uint32_t session_id; 2483 uint32_t unique_id; 2484 uint32_t id_and_color; 2485 uint32_t action; 2486 uint32_t status; 2487 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2488 2489 2490 /* Bindings and Time Quota */ 2491 2492 /** 2493 * struct iwm_binding_cmd - configuring bindings 2494 * ( IWM_BINDING_CONTEXT_CMD = 0x2b ) 2495 * @id_and_color: ID and color of the relevant Binding 2496 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2497 * @macs: array of MAC id and colors which belong to the binding 2498 * @phy: PHY id and color which belongs to the binding 2499 */ 2500 struct iwm_binding_cmd { 2501 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2502 uint32_t id_and_color; 2503 uint32_t action; 2504 /* IWM_BINDING_DATA_API_S_VER_1 */ 2505 uint32_t macs[IWM_MAX_MACS_IN_BINDING]; 2506 uint32_t phy; 2507 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */ 2508 2509 /* The maximal number of fragments in the FW's schedule session */ 2510 #define IWM_MVM_MAX_QUOTA 128 2511 2512 /** 2513 * struct iwm_time_quota_data - configuration of time quota per binding 2514 * @id_and_color: ID and color of the relevant Binding 2515 * @quota: absolute time quota in TU. The scheduler will try to divide the 2516 * remainig quota (after Time Events) according to this quota. 2517 * @max_duration: max uninterrupted context duration in TU 2518 */ 2519 struct iwm_time_quota_data { 2520 uint32_t id_and_color; 2521 uint32_t quota; 2522 uint32_t max_duration; 2523 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */ 2524 2525 /** 2526 * struct iwm_time_quota_cmd - configuration of time quota between bindings 2527 * ( IWM_TIME_QUOTA_CMD = 0x2c ) 2528 * @quotas: allocations per binding 2529 */ 2530 struct iwm_time_quota_cmd { 2531 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS]; 2532 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2533 2534 2535 /* PHY context */ 2536 2537 /* Supported bands */ 2538 #define IWM_PHY_BAND_5 (0) 2539 #define IWM_PHY_BAND_24 (1) 2540 2541 /* Supported channel width, vary if there is VHT support */ 2542 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0) 2543 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1) 2544 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2) 2545 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3) 2546 2547 /* 2548 * Control channel position: 2549 * For legacy set bit means upper channel, otherwise lower. 2550 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2551 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2552 * center_freq 2553 * | 2554 * 40Mhz |_______|_______| 2555 * 80Mhz |_______|_______|_______|_______| 2556 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2557 * code 011 010 001 000 | 100 101 110 111 2558 */ 2559 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2560 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2561 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2562 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2563 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2564 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2565 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2566 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2567 2568 /* 2569 * @band: IWM_PHY_BAND_* 2570 * @channel: channel number 2571 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2572 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2573 */ 2574 struct iwm_fw_channel_info { 2575 uint8_t band; 2576 uint8_t channel; 2577 uint8_t width; 2578 uint8_t ctrl_pos; 2579 } __packed; 2580 2581 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2582 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2583 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2584 #define IWM_PHY_RX_CHAIN_VALID_POS (1) 2585 #define IWM_PHY_RX_CHAIN_VALID_MSK \ 2586 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS) 2587 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2588 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2589 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS) 2590 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2591 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2592 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2593 #define IWM_PHY_RX_CHAIN_CNT_POS (10) 2594 #define IWM_PHY_RX_CHAIN_CNT_MSK \ 2595 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS) 2596 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2597 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2598 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS) 2599 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2600 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2601 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS) 2602 2603 /* TODO: fix the value, make it depend on firmware at runtime? */ 2604 #define IWM_NUM_PHY_CTX 3 2605 2606 /* TODO: complete missing documentation */ 2607 /** 2608 * struct iwm_phy_context_cmd - config of the PHY context 2609 * ( IWM_PHY_CONTEXT_CMD = 0x8 ) 2610 * @id_and_color: ID and color of the relevant Binding 2611 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 2612 * @apply_time: 0 means immediate apply and context switch. 2613 * other value means apply new params after X usecs 2614 * @tx_param_color: ??? 2615 * @channel_info: 2616 * @txchain_info: ??? 2617 * @rxchain_info: ??? 2618 * @acquisition_data: ??? 2619 * @dsp_cfg_flags: set to 0 2620 */ 2621 struct iwm_phy_context_cmd { 2622 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2623 uint32_t id_and_color; 2624 uint32_t action; 2625 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */ 2626 uint32_t apply_time; 2627 uint32_t tx_param_color; 2628 struct iwm_fw_channel_info ci; 2629 uint32_t txchain_info; 2630 uint32_t rxchain_info; 2631 uint32_t acquisition_data; 2632 uint32_t dsp_cfg_flags; 2633 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */ 2634 2635 #define IWM_RX_INFO_PHY_CNT 8 2636 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1 2637 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2638 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2639 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2640 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0 2641 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8 2642 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16 2643 2644 #define IWM_RX_INFO_AGC_IDX 1 2645 #define IWM_RX_INFO_RSSI_AB_IDX 2 2646 #define IWM_OFDM_AGC_A_MSK 0x0000007f 2647 #define IWM_OFDM_AGC_A_POS 0 2648 #define IWM_OFDM_AGC_B_MSK 0x00003f80 2649 #define IWM_OFDM_AGC_B_POS 7 2650 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000 2651 #define IWM_OFDM_AGC_CODE_POS 20 2652 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff 2653 #define IWM_OFDM_RSSI_A_POS 0 2654 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2655 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8 2656 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000 2657 #define IWM_OFDM_RSSI_B_POS 16 2658 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2659 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24 2660 2661 /** 2662 * struct iwm_rx_phy_info - phy info 2663 * (IWM_REPLY_RX_PHY_CMD = 0xc0) 2664 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2665 * @cfg_phy_cnt: configurable DSP phy data byte count 2666 * @stat_id: configurable DSP phy data set ID 2667 * @reserved1: 2668 * @system_timestamp: GP2 at on air rise 2669 * @timestamp: TSF at on air rise 2670 * @beacon_time_stamp: beacon at on-air rise 2671 * @phy_flags: general phy flags: band, modulation, ... 2672 * @channel: channel number 2673 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2674 * @rate_n_flags: IWM_RATE_MCS_* 2675 * @byte_count: frame's byte-count 2676 * @frame_time: frame's time on the air, based on byte count and frame rate 2677 * calculation 2678 * @mac_active_msk: what MACs were active when the frame was received 2679 * 2680 * Before each Rx, the device sends this data. It contains PHY information 2681 * about the reception of the packet. 2682 */ 2683 struct iwm_rx_phy_info { 2684 uint8_t non_cfg_phy_cnt; 2685 uint8_t cfg_phy_cnt; 2686 uint8_t stat_id; 2687 uint8_t reserved1; 2688 uint32_t system_timestamp; 2689 uint64_t timestamp; 2690 uint32_t beacon_time_stamp; 2691 uint16_t phy_flags; 2692 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2693 uint16_t channel; 2694 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT]; 2695 uint8_t rate; 2696 uint8_t rflags; 2697 uint16_t xrflags; 2698 uint32_t byte_count; 2699 uint16_t mac_active_msk; 2700 uint16_t frame_time; 2701 } __packed; 2702 2703 struct iwm_rx_mpdu_res_start { 2704 uint16_t byte_count; 2705 uint16_t reserved; 2706 } __packed; 2707 2708 /** 2709 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags 2710 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2711 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK: 2712 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2713 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: 2714 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2715 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2716 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2717 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2718 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2719 */ 2720 enum iwm_rx_phy_flags { 2721 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0), 2722 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1), 2723 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2), 2724 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3), 2725 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 2726 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 2727 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7), 2728 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8), 2729 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9), 2730 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10), 2731 }; 2732 2733 /** 2734 * enum iwm_mvm_rx_status - written by fw for each Rx packet 2735 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 2736 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 2737 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 2738 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID: 2739 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 2740 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 2741 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 2742 * in the driver. 2743 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 2744 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 2745 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 2746 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 2747 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 2748 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 2749 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 2750 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 2751 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 2752 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 2753 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 2754 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 2755 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 2756 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 2757 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 2758 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 2759 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 2760 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: 2761 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL: 2762 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: 2763 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK: 2764 */ 2765 enum iwm_mvm_rx_status { 2766 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0), 2767 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1), 2768 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2), 2769 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3), 2770 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4), 2771 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5), 2772 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6), 2773 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7), 2774 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7), 2775 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 2776 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 2777 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 2778 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 2779 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 2780 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8), 2781 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 2782 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 2783 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11), 2784 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12), 2785 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13), 2786 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14), 2787 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15), 2788 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000), 2789 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000), 2790 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29), 2791 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000), 2792 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000), 2793 }; 2794 2795 /** 2796 * struct iwm_radio_version_notif - information on the radio version 2797 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 ) 2798 * @radio_flavor: 2799 * @radio_step: 2800 * @radio_dash: 2801 */ 2802 struct iwm_radio_version_notif { 2803 uint32_t radio_flavor; 2804 uint32_t radio_step; 2805 uint32_t radio_dash; 2806 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 2807 2808 enum iwm_card_state_flags { 2809 IWM_CARD_ENABLED = 0x00, 2810 IWM_HW_CARD_DISABLED = 0x01, 2811 IWM_SW_CARD_DISABLED = 0x02, 2812 IWM_CT_KILL_CARD_DISABLED = 0x04, 2813 IWM_HALT_CARD_DISABLED = 0x08, 2814 IWM_CARD_DISABLED_MSK = 0x0f, 2815 IWM_CARD_IS_RX_ON = 0x10, 2816 }; 2817 2818 /** 2819 * struct iwm_radio_version_notif - information on the radio version 2820 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 ) 2821 * @flags: %iwm_card_state_flags 2822 */ 2823 struct iwm_card_state_notif { 2824 uint32_t flags; 2825 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 2826 2827 /** 2828 * struct iwm_missed_beacons_notif - information on missed beacons 2829 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 2830 * @mac_id: interface ID 2831 * @consec_missed_beacons_since_last_rx: number of consecutive missed 2832 * beacons since last RX. 2833 * @consec_missed_beacons: number of consecutive missed beacons 2834 * @num_expected_beacons: 2835 * @num_recvd_beacons: 2836 */ 2837 struct iwm_missed_beacons_notif { 2838 uint32_t mac_id; 2839 uint32_t consec_missed_beacons_since_last_rx; 2840 uint32_t consec_missed_beacons; 2841 uint32_t num_expected_beacons; 2842 uint32_t num_recvd_beacons; 2843 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */ 2844 2845 /** 2846 * struct iwm_mfuart_load_notif - mfuart image version & status 2847 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 ) 2848 * @installed_ver: installed image version 2849 * @external_ver: external image version 2850 * @status: MFUART loading status 2851 * @duration: MFUART loading time 2852 */ 2853 struct iwm_mfuart_load_notif { 2854 uint32_t installed_ver; 2855 uint32_t external_ver; 2856 uint32_t status; 2857 uint32_t duration; 2858 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 2859 2860 /** 2861 * struct iwm_set_calib_default_cmd - set default value for calibration. 2862 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e ) 2863 * @calib_index: the calibration to set value for 2864 * @length: of data 2865 * @data: the value to set for the calibration result 2866 */ 2867 struct iwm_set_calib_default_cmd { 2868 uint16_t calib_index; 2869 uint16_t length; 2870 uint8_t data[0]; 2871 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */ 2872 2873 #define IWM_MAX_PORT_ID_NUM 2 2874 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256 2875 2876 /** 2877 * struct iwm_mcast_filter_cmd - configure multicast filter. 2878 * @filter_own: Set 1 to filter out multicast packets sent by station itself 2879 * @port_id: Multicast MAC addresses array specifier. This is a strange way 2880 * to identify network interface adopted in host-device IF. 2881 * It is used by FW as index in array of addresses. This array has 2882 * IWM_MAX_PORT_ID_NUM members. 2883 * @count: Number of MAC addresses in the array 2884 * @pass_all: Set 1 to pass all multicast packets. 2885 * @bssid: current association BSSID. 2886 * @addr_list: Place holder for array of MAC addresses. 2887 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 2888 */ 2889 struct iwm_mcast_filter_cmd { 2890 uint8_t filter_own; 2891 uint8_t port_id; 2892 uint8_t count; 2893 uint8_t pass_all; 2894 uint8_t bssid[6]; 2895 uint8_t reserved[2]; 2896 uint8_t addr_list[0]; 2897 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */ 2898 2899 /* 2900 * The first MAC indices (starting from 0) 2901 * are available to the driver, AUX follows 2902 */ 2903 #define IWM_MAC_INDEX_AUX 4 2904 #define IWM_MAC_INDEX_MIN_DRIVER 0 2905 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX 2906 #define IWM_NUM_MAC_INDEX (IWM_MAC_INDEX_AUX + 1) 2907 2908 /*********************************** 2909 * Statistics API 2910 ***********************************/ 2911 struct iwm_mvm_statistics_dbg { 2912 uint32_t burst_check; 2913 uint32_t burst_count; 2914 uint32_t wait_for_silence_timeout_cnt; 2915 uint32_t reserved[3]; 2916 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */ 2917 2918 struct iwm_mvm_statistics_div { 2919 uint32_t tx_on_a; 2920 uint32_t tx_on_b; 2921 uint32_t exec_time; 2922 uint32_t probe_time; 2923 uint32_t rssi_ant; 2924 uint32_t reserved2; 2925 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */ 2926 2927 struct iwm_mvm_statistics_rx_non_phy { 2928 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 2929 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 2930 uint32_t non_bssid_frames; /* number of frames with BSSID that 2931 * doesn't belong to the STA BSSID */ 2932 uint32_t filtered_frames; /* count frames that were dumped in the 2933 * filtering process */ 2934 uint32_t non_channel_beacons; /* beacons with our bss id but not on 2935 * our serving channel */ 2936 uint32_t channel_beacons; /* beacons with our bss id and in our 2937 * serving channel */ 2938 uint32_t num_missed_bcon; /* number of missed beacons */ 2939 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 2940 * ADC was in saturation */ 2941 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 2942 * for INA */ 2943 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 2944 uint32_t interference_data_flag; /* flag for interference data 2945 * availability. 1 when data is 2946 * available. */ 2947 uint32_t channel_load; /* counts RX Enable time in uSec */ 2948 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 2949 * and CCK) counter */ 2950 uint32_t beacon_rssi_a; 2951 uint32_t beacon_rssi_b; 2952 uint32_t beacon_rssi_c; 2953 uint32_t beacon_energy_a; 2954 uint32_t beacon_energy_b; 2955 uint32_t beacon_energy_c; 2956 uint32_t num_bt_kills; 2957 uint32_t mac_id; 2958 uint32_t directed_data_mpdu; 2959 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 2960 2961 struct iwm_mvm_statistics_rx_phy { 2962 uint32_t ina_cnt; 2963 uint32_t fina_cnt; 2964 uint32_t plcp_err; 2965 uint32_t crc32_err; 2966 uint32_t overrun_err; 2967 uint32_t early_overrun_err; 2968 uint32_t crc32_good; 2969 uint32_t false_alarm_cnt; 2970 uint32_t fina_sync_err_cnt; 2971 uint32_t sfd_timeout; 2972 uint32_t fina_timeout; 2973 uint32_t unresponded_rts; 2974 uint32_t rxe_frame_limit_overrun; 2975 uint32_t sent_ack_cnt; 2976 uint32_t sent_cts_cnt; 2977 uint32_t sent_ba_rsp_cnt; 2978 uint32_t dsp_self_kill; 2979 uint32_t mh_format_err; 2980 uint32_t re_acq_main_rssi_sum; 2981 uint32_t reserved; 2982 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */ 2983 2984 struct iwm_mvm_statistics_rx_ht_phy { 2985 uint32_t plcp_err; 2986 uint32_t overrun_err; 2987 uint32_t early_overrun_err; 2988 uint32_t crc32_good; 2989 uint32_t crc32_err; 2990 uint32_t mh_format_err; 2991 uint32_t agg_crc32_good; 2992 uint32_t agg_mpdu_cnt; 2993 uint32_t agg_cnt; 2994 uint32_t unsupport_mcs; 2995 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 2996 2997 struct iwm_mvm_statistics_tx_non_phy { 2998 uint32_t preamble_cnt; 2999 uint32_t rx_detected_cnt; 3000 uint32_t bt_prio_defer_cnt; 3001 uint32_t bt_prio_kill_cnt; 3002 uint32_t few_bytes_cnt; 3003 uint32_t cts_timeout; 3004 uint32_t ack_timeout; 3005 uint32_t expected_ack_cnt; 3006 uint32_t actual_ack_cnt; 3007 uint32_t dump_msdu_cnt; 3008 uint32_t burst_abort_next_frame_mismatch_cnt; 3009 uint32_t burst_abort_missing_next_frame_cnt; 3010 uint32_t cts_timeout_collision; 3011 uint32_t ack_or_ba_timeout_collision; 3012 } __packed; /* IWM_STATISTICS_TX_NON_PHY_API_S_VER_3 */ 3013 3014 #define IWM_MAX_CHAINS 3 3015 3016 struct iwm_mvm_statistics_tx_non_phy_agg { 3017 uint32_t ba_timeout; 3018 uint32_t ba_reschedule_frames; 3019 uint32_t scd_query_agg_frame_cnt; 3020 uint32_t scd_query_no_agg; 3021 uint32_t scd_query_agg; 3022 uint32_t scd_query_mismatch; 3023 uint32_t frame_not_ready; 3024 uint32_t underrun; 3025 uint32_t bt_prio_kill; 3026 uint32_t rx_ba_rsp_cnt; 3027 int8_t txpower[IWM_MAX_CHAINS]; 3028 int8_t reserved; 3029 uint32_t reserved2; 3030 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3031 3032 struct iwm_mvm_statistics_tx_channel_width { 3033 uint32_t ext_cca_narrow_ch20[1]; 3034 uint32_t ext_cca_narrow_ch40[2]; 3035 uint32_t ext_cca_narrow_ch80[3]; 3036 uint32_t ext_cca_narrow_ch160[4]; 3037 uint32_t last_tx_ch_width_indx; 3038 uint32_t rx_detected_per_ch_width[4]; 3039 uint32_t success_per_ch_width[4]; 3040 uint32_t fail_per_ch_width[4]; 3041 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3042 3043 struct iwm_mvm_statistics_tx { 3044 struct iwm_mvm_statistics_tx_non_phy general; 3045 struct iwm_mvm_statistics_tx_non_phy_agg agg; 3046 struct iwm_mvm_statistics_tx_channel_width channel_width; 3047 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */ 3048 3049 3050 struct iwm_mvm_statistics_bt_activity { 3051 uint32_t hi_priority_tx_req_cnt; 3052 uint32_t hi_priority_tx_denied_cnt; 3053 uint32_t lo_priority_tx_req_cnt; 3054 uint32_t lo_priority_tx_denied_cnt; 3055 uint32_t hi_priority_rx_req_cnt; 3056 uint32_t hi_priority_rx_denied_cnt; 3057 uint32_t lo_priority_rx_req_cnt; 3058 uint32_t lo_priority_rx_denied_cnt; 3059 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3060 3061 struct iwm_mvm_statistics_general_v8 { 3062 uint32_t radio_temperature; 3063 uint32_t radio_voltage; 3064 struct iwm_mvm_statistics_dbg dbg; 3065 uint32_t sleep_time; 3066 uint32_t slots_out; 3067 uint32_t slots_idle; 3068 uint32_t ttl_timestamp; 3069 struct iwm_mvm_statistics_div slow_div; 3070 uint32_t rx_enable_counter; 3071 /* 3072 * num_of_sos_states: 3073 * count the number of times we have to re-tune 3074 * in order to get out of bad PHY status 3075 */ 3076 uint32_t num_of_sos_states; 3077 uint32_t beacon_filtered; 3078 uint32_t missed_beacons; 3079 uint8_t beacon_filter_average_energy; 3080 uint8_t beacon_filter_reason; 3081 uint8_t beacon_filter_current_energy; 3082 uint8_t beacon_filter_reserved; 3083 uint32_t beacon_filter_delta_time; 3084 struct iwm_mvm_statistics_bt_activity bt_activity; 3085 uint64_t rx_time; 3086 uint64_t on_time_rf; 3087 uint64_t on_time_scan; 3088 uint64_t tx_time; 3089 uint32_t beacon_counter[IWM_NUM_MAC_INDEX]; 3090 uint8_t beacon_average_energy[IWM_NUM_MAC_INDEX]; 3091 uint8_t reserved[4 - (IWM_NUM_MAC_INDEX % 4)]; 3092 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_8 */ 3093 3094 struct iwm_mvm_statistics_rx { 3095 struct iwm_mvm_statistics_rx_phy ofdm; 3096 struct iwm_mvm_statistics_rx_phy cck; 3097 struct iwm_mvm_statistics_rx_non_phy general; 3098 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht; 3099 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */ 3100 3101 /* 3102 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3103 * 3104 * By default, uCode issues this notification after receiving a beacon 3105 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3106 * IWM_STATISTICS_CMD (0x9c), below. 3107 */ 3108 3109 struct iwm_notif_statistics_v10 { 3110 uint32_t flag; 3111 struct iwm_mvm_statistics_rx rx; 3112 struct iwm_mvm_statistics_tx tx; 3113 struct iwm_mvm_statistics_general_v8 general; 3114 } __packed; /* IWM_STATISTICS_NTFY_API_S_VER_10 */ 3115 3116 #define IWM_STATISTICS_FLG_CLEAR 0x1 3117 #define IWM_STATISTICS_FLG_DISABLE_NOTIF 0x2 3118 3119 struct iwm_statistics_cmd { 3120 uint32_t flags; 3121 } __packed; /* IWM_STATISTICS_CMD_API_S_VER_1 */ 3122 3123 /*********************************** 3124 * Smart Fifo API 3125 ***********************************/ 3126 /* Smart Fifo state */ 3127 enum iwm_sf_state { 3128 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */ 3129 IWM_SF_FULL_ON, 3130 IWM_SF_UNINIT, 3131 IWM_SF_INIT_OFF, 3132 IWM_SF_HW_NUM_STATES 3133 }; 3134 3135 /* Smart Fifo possible scenario */ 3136 enum iwm_sf_scenario { 3137 IWM_SF_SCENARIO_SINGLE_UNICAST, 3138 IWM_SF_SCENARIO_AGG_UNICAST, 3139 IWM_SF_SCENARIO_MULTICAST, 3140 IWM_SF_SCENARIO_BA_RESP, 3141 IWM_SF_SCENARIO_TX_RESP, 3142 IWM_SF_NUM_SCENARIO 3143 }; 3144 3145 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */ 3146 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3147 3148 /* smart FIFO default values */ 3149 #define IWM_SF_W_MARK_SISO 4096 3150 #define IWM_SF_W_MARK_MIMO2 8192 3151 #define IWM_SF_W_MARK_MIMO3 6144 3152 #define IWM_SF_W_MARK_LEGACY 4096 3153 #define IWM_SF_W_MARK_SCAN 4096 3154 3155 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3156 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3157 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3158 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3159 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3160 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3161 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3162 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3163 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3164 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3165 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3166 3167 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3168 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3169 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3170 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3171 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3172 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3173 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3174 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3175 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3176 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3177 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3178 3179 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3180 3181 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3182 3183 /** 3184 * Smart Fifo configuration command. 3185 * @state: smart fifo state, types listed in enum %iwm_sf_state. 3186 * @watermark: Minimum allowed available free space in RXF for transient state. 3187 * @long_delay_timeouts: aging and idle timer values for each scenario 3188 * in long delay state. 3189 * @full_on_timeouts: timer values for each scenario in full on state. 3190 */ 3191 struct iwm_sf_cfg_cmd { 3192 uint32_t state; 3193 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER]; 3194 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3195 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES]; 3196 } __packed; /* IWM_SF_CFG_API_S_VER_2 */ 3197 3198 enum iwm_ac { 3199 IWM_AC_BK, 3200 IWM_AC_BE, 3201 IWM_AC_VI, 3202 IWM_AC_VO, 3203 IWM_AC_NUM, 3204 }; 3205 3206 /** 3207 * enum iwm_mac_protection_flags - MAC context flags 3208 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3209 * this will require CCK RTS/CTS2self. 3210 * RTS/CTS will protect full burst time. 3211 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection 3212 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3213 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3214 */ 3215 enum iwm_mac_protection_flags { 3216 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3), 3217 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23), 3218 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24), 3219 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30), 3220 }; 3221 3222 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4) 3223 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3224 3225 /** 3226 * enum iwm_mac_types - Supported MAC types 3227 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type 3228 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3229 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3230 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3231 * @IWM_FW_MAC_TYPE_IBSS: IBSS 3232 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3233 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3234 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client 3235 * @IWM_FW_MAC_TYPE_GO: P2P GO 3236 * @IWM_FW_MAC_TYPE_TEST: ? 3237 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type 3238 */ 3239 enum iwm_mac_types { 3240 IWM_FW_MAC_TYPE_FIRST = 1, 3241 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST, 3242 IWM_FW_MAC_TYPE_LISTENER, 3243 IWM_FW_MAC_TYPE_PIBSS, 3244 IWM_FW_MAC_TYPE_IBSS, 3245 IWM_FW_MAC_TYPE_BSS_STA, 3246 IWM_FW_MAC_TYPE_P2P_DEVICE, 3247 IWM_FW_MAC_TYPE_P2P_STA, 3248 IWM_FW_MAC_TYPE_GO, 3249 IWM_FW_MAC_TYPE_TEST, 3250 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST 3251 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3252 3253 /** 3254 * enum iwm_tsf_id - TSF hw timer ID 3255 * @IWM_TSF_ID_A: use TSF A 3256 * @IWM_TSF_ID_B: use TSF B 3257 * @IWM_TSF_ID_C: use TSF C 3258 * @IWM_TSF_ID_D: use TSF D 3259 * @IWM_NUM_TSF_IDS: number of TSF timers available 3260 */ 3261 enum iwm_tsf_id { 3262 IWM_TSF_ID_A = 0, 3263 IWM_TSF_ID_B = 1, 3264 IWM_TSF_ID_C = 2, 3265 IWM_TSF_ID_D = 3, 3266 IWM_NUM_TSF_IDS = 4, 3267 }; /* IWM_TSF_ID_API_E_VER_1 */ 3268 3269 /** 3270 * struct iwm_mac_data_ap - configuration data for AP MAC context 3271 * @beacon_time: beacon transmit time in system time 3272 * @beacon_tsf: beacon transmit time in TSF 3273 * @bi: beacon interval in TU 3274 * @bi_reciprocal: 2^32 / bi 3275 * @dtim_interval: dtim transmit time in TU 3276 * @dtim_reciprocal: 2^32 / dtim_interval 3277 * @mcast_qid: queue ID for multicast traffic 3278 * @beacon_template: beacon template ID 3279 */ 3280 struct iwm_mac_data_ap { 3281 uint32_t beacon_time; 3282 uint64_t beacon_tsf; 3283 uint32_t bi; 3284 uint32_t bi_reciprocal; 3285 uint32_t dtim_interval; 3286 uint32_t dtim_reciprocal; 3287 uint32_t mcast_qid; 3288 uint32_t beacon_template; 3289 } __packed; /* AP_MAC_DATA_API_S_VER_1 */ 3290 3291 /** 3292 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context 3293 * @beacon_time: beacon transmit time in system time 3294 * @beacon_tsf: beacon transmit time in TSF 3295 * @bi: beacon interval in TU 3296 * @bi_reciprocal: 2^32 / bi 3297 * @beacon_template: beacon template ID 3298 */ 3299 struct iwm_mac_data_ibss { 3300 uint32_t beacon_time; 3301 uint64_t beacon_tsf; 3302 uint32_t bi; 3303 uint32_t bi_reciprocal; 3304 uint32_t beacon_template; 3305 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3306 3307 /** 3308 * struct iwm_mac_data_sta - configuration data for station MAC context 3309 * @is_assoc: 1 for associated state, 0 otherwise 3310 * @dtim_time: DTIM arrival time in system time 3311 * @dtim_tsf: DTIM arrival time in TSF 3312 * @bi: beacon interval in TU, applicable only when associated 3313 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3314 * @dtim_interval: DTIM interval in TU, applicable only when associated 3315 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3316 * @listen_interval: in beacon intervals, applicable only when associated 3317 * @assoc_id: unique ID assigned by the AP during association 3318 */ 3319 struct iwm_mac_data_sta { 3320 uint32_t is_assoc; 3321 uint32_t dtim_time; 3322 uint64_t dtim_tsf; 3323 uint32_t bi; 3324 uint32_t bi_reciprocal; 3325 uint32_t dtim_interval; 3326 uint32_t dtim_reciprocal; 3327 uint32_t listen_interval; 3328 uint32_t assoc_id; 3329 uint32_t assoc_beacon_arrive_time; 3330 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */ 3331 3332 /** 3333 * struct iwm_mac_data_go - configuration data for P2P GO MAC context 3334 * @ap: iwm_mac_data_ap struct with most config data 3335 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3336 * 0 indicates that there is no CT window. 3337 * @opp_ps_enabled: indicate that opportunistic PS allowed 3338 */ 3339 struct iwm_mac_data_go { 3340 struct iwm_mac_data_ap ap; 3341 uint32_t ctwin; 3342 uint32_t opp_ps_enabled; 3343 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3344 3345 /** 3346 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context 3347 * @sta: iwm_mac_data_sta struct with most config data 3348 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3349 * 0 indicates that there is no CT window. 3350 */ 3351 struct iwm_mac_data_p2p_sta { 3352 struct iwm_mac_data_sta sta; 3353 uint32_t ctwin; 3354 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3355 3356 /** 3357 * struct iwm_mac_data_pibss - Pseudo IBSS config data 3358 * @stats_interval: interval in TU between statistics notifications to host. 3359 */ 3360 struct iwm_mac_data_pibss { 3361 uint32_t stats_interval; 3362 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3363 3364 /* 3365 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC 3366 * context. 3367 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3368 * other channels as well. This should be to true only in case that the 3369 * device is discoverable and there is an active GO. Note that setting this 3370 * field when not needed, will increase the number of interrupts and have 3371 * effect on the platform power, as this setting opens the Rx filters on 3372 * all macs. 3373 */ 3374 struct iwm_mac_data_p2p_dev { 3375 uint32_t is_disc_extended; 3376 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3377 3378 /** 3379 * enum iwm_mac_filter_flags - MAC context filter flags 3380 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames 3381 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3382 * control frames to the host 3383 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3384 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3385 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3386 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3387 * (in station mode when associated) 3388 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3389 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3390 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3391 */ 3392 enum iwm_mac_filter_flags { 3393 IWM_MAC_FILTER_IN_PROMISC = (1 << 0), 3394 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1), 3395 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2), 3396 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3), 3397 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4), 3398 IWM_MAC_FILTER_IN_BEACON = (1 << 6), 3399 IWM_MAC_FILTER_OUT_BCAST = (1 << 8), 3400 IWM_MAC_FILTER_IN_CRC32 = (1 << 11), 3401 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12), 3402 }; 3403 3404 /** 3405 * enum iwm_mac_qos_flags - QoS flags 3406 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? 3407 * @IWM_MAC_QOS_FLG_TGN: HT is enabled 3408 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ? 3409 * 3410 */ 3411 enum iwm_mac_qos_flags { 3412 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0), 3413 IWM_MAC_QOS_FLG_TGN = (1 << 1), 3414 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4), 3415 }; 3416 3417 /** 3418 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD 3419 * @cw_min: Contention window, start value in numbers of slots. 3420 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3421 * @cw_max: Contention window, max value in numbers of slots. 3422 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3423 * @aifsn: Number of slots in Arbitration Interframe Space (before 3424 * performing random backoff timing prior to Tx). Device default 1. 3425 * @fifos_mask: FIFOs used by this MAC for this AC 3426 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3427 * 3428 * One instance of this config struct for each of 4 EDCA access categories 3429 * in struct iwm_qosparam_cmd. 3430 * 3431 * Device will automatically increase contention window by (2*CW) + 1 for each 3432 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3433 * value, to cap the CW value. 3434 */ 3435 struct iwm_ac_qos { 3436 uint16_t cw_min; 3437 uint16_t cw_max; 3438 uint8_t aifsn; 3439 uint8_t fifos_mask; 3440 uint16_t edca_txop; 3441 } __packed; /* IWM_AC_QOS_API_S_VER_2 */ 3442 3443 /** 3444 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts 3445 * ( IWM_MAC_CONTEXT_CMD = 0x28 ) 3446 * @id_and_color: ID and color of the MAC 3447 * @action: action to perform, one of IWM_FW_CTXT_ACTION_* 3448 * @mac_type: one of IWM_FW_MAC_TYPE_* 3449 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_* 3450 * @node_addr: MAC address 3451 * @bssid_addr: BSSID 3452 * @cck_rates: basic rates available for CCK 3453 * @ofdm_rates: basic rates available for OFDM 3454 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_* 3455 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3456 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3457 * @filter_flags: combination of IWM_MAC_FILTER_* 3458 * @qos_flags: from IWM_MAC_QOS_FLG_* 3459 * @ac: one iwm_mac_qos configuration for each AC 3460 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type 3461 */ 3462 struct iwm_mac_ctx_cmd { 3463 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3464 uint32_t id_and_color; 3465 uint32_t action; 3466 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3467 uint32_t mac_type; 3468 uint32_t tsf_id; 3469 uint8_t node_addr[6]; 3470 uint16_t reserved_for_node_addr; 3471 uint8_t bssid_addr[6]; 3472 uint16_t reserved_for_bssid_addr; 3473 uint32_t cck_rates; 3474 uint32_t ofdm_rates; 3475 uint32_t protection_flags; 3476 uint32_t cck_short_preamble; 3477 uint32_t short_slot; 3478 uint32_t filter_flags; 3479 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */ 3480 uint32_t qos_flags; 3481 struct iwm_ac_qos ac[IWM_AC_NUM+1]; 3482 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */ 3483 union { 3484 struct iwm_mac_data_ap ap; 3485 struct iwm_mac_data_go go; 3486 struct iwm_mac_data_sta sta; 3487 struct iwm_mac_data_p2p_sta p2p_sta; 3488 struct iwm_mac_data_p2p_dev p2p_dev; 3489 struct iwm_mac_data_pibss pibss; 3490 struct iwm_mac_data_ibss ibss; 3491 }; 3492 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */ 3493 3494 static inline uint32_t iwm_mvm_reciprocal(uint32_t v) 3495 { 3496 if (!v) 3497 return 0; 3498 return 0xFFFFFFFF / v; 3499 } 3500 3501 #define IWM_NONQOS_SEQ_GET 0x1 3502 #define IWM_NONQOS_SEQ_SET 0x2 3503 struct iwm_nonqos_seq_query_cmd { 3504 uint32_t get_set_flag; 3505 uint32_t mac_id_n_color; 3506 uint16_t value; 3507 uint16_t reserved; 3508 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */ 3509 3510 /* Power Management Commands, Responses, Notifications */ 3511 3512 /** 3513 * enum iwm_ltr_config_flags - masks for LTR config command flags 3514 * @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 3515 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 3516 * memory access 3517 * @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 3518 * reg change 3519 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 3520 * D0 to D3 3521 * @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 3522 * @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 3523 * @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 3524 */ 3525 enum iwm_ltr_config_flags { 3526 IWM_LTR_CFG_FLAG_FEATURE_ENABLE = (1 << 0), 3527 IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS = (1 << 1), 3528 IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH = (1 << 2), 3529 IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 = (1 << 3), 3530 IWM_LTR_CFG_FLAG_SW_SET_SHORT = (1 << 4), 3531 IWM_LTR_CFG_FLAG_SW_SET_LONG = (1 << 5), 3532 IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD = (1 << 6), 3533 }; 3534 3535 /** 3536 * struct iwm_ltr_config_cmd_v1 - configures the LTR 3537 * @flags: See %enum iwm_ltr_config_flags 3538 */ 3539 struct iwm_ltr_config_cmd_v1 { 3540 uint32_t flags; 3541 uint32_t static_long; 3542 uint32_t static_short; 3543 } __packed; /* LTR_CAPABLE_API_S_VER_1 */ 3544 3545 #define IWM_LTR_VALID_STATES_NUM 4 3546 3547 /** 3548 * struct iwm_ltr_config_cmd - configures the LTR 3549 * @flags: See %enum iwm_ltr_config_flags 3550 * @static_long: 3551 * @static_short: 3552 * @ltr_cfg_values: 3553 * @ltr_short_idle_timeout: 3554 */ 3555 struct iwm_ltr_config_cmd { 3556 uint32_t flags; 3557 uint32_t static_long; 3558 uint32_t static_short; 3559 uint32_t ltr_cfg_values[IWM_LTR_VALID_STATES_NUM]; 3560 uint32_t ltr_short_idle_timeout; 3561 } __packed; /* LTR_CAPABLE_API_S_VER_2 */ 3562 3563 /* Radio LP RX Energy Threshold measured in dBm */ 3564 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75 3565 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3566 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3567 3568 /** 3569 * enum iwm_scan_flags - masks for power table command flags 3570 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3571 * receiver and transmitter. '0' - does not allow. 3572 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3573 * '1' Driver enables PM (use rest of parameters) 3574 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3575 * '1' PM could sleep over DTIM till listen Interval. 3576 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3577 * access categories are both delivery and trigger enabled. 3578 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3579 * PBW Snoozing enabled 3580 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3581 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3582 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3583 * detection enablement 3584 */ 3585 enum iwm_power_flags { 3586 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3587 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1), 3588 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2), 3589 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5), 3590 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8), 3591 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9), 3592 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11), 3593 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12), 3594 }; 3595 3596 #define IWM_POWER_VEC_SIZE 5 3597 3598 /** 3599 * struct iwm_powertable_cmd - legacy power command. Beside old API support this 3600 * is used also with a new power API for device wide power settings. 3601 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3602 * 3603 * @flags: Power table command flags from IWM_POWER_FLAGS_* 3604 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3605 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3606 * set regardless of power scheme or current power state. 3607 * FW use this value also when PM is disabled. 3608 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3609 * PSM transition - legacy PM 3610 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3611 * PSM transition - legacy PM 3612 * @sleep_interval: not in use 3613 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3614 * is set. For example, if it is required to skip over 3615 * one DTIM, this value need to be set to 2 (DTIM periods). 3616 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3617 * Default: 80dbm 3618 */ 3619 struct iwm_powertable_cmd { 3620 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3621 uint16_t flags; 3622 uint8_t keep_alive_seconds; 3623 uint8_t debug_flags; 3624 uint32_t rx_data_timeout; 3625 uint32_t tx_data_timeout; 3626 uint32_t sleep_interval[IWM_POWER_VEC_SIZE]; 3627 uint32_t skip_dtim_periods; 3628 uint32_t lprx_rssi_threshold; 3629 } __packed; 3630 3631 /** 3632 * enum iwm_device_power_flags - masks for device power command flags 3633 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3634 * receiver and transmitter. '0' - does not allow. 3635 */ 3636 enum iwm_device_power_flags { 3637 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0), 3638 }; 3639 3640 /** 3641 * struct iwm_device_power_cmd - device wide power command. 3642 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response) 3643 * 3644 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_* 3645 */ 3646 struct iwm_device_power_cmd { 3647 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3648 uint16_t flags; 3649 uint16_t reserved; 3650 } __packed; 3651 3652 /** 3653 * struct iwm_mac_power_cmd - New power command containing uAPSD support 3654 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3655 * @id_and_color: MAC contex identifier 3656 * @flags: Power table command flags from POWER_FLAGS_* 3657 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3658 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3659 * set regardless of power scheme or current power state. 3660 * FW use this value also when PM is disabled. 3661 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3662 * PSM transition - legacy PM 3663 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3664 * PSM transition - legacy PM 3665 * @sleep_interval: not in use 3666 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3667 * is set. For example, if it is required to skip over 3668 * one DTIM, this value need to be set to 2 (DTIM periods). 3669 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3670 * PSM transition - uAPSD 3671 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3672 * PSM transition - uAPSD 3673 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3674 * Default: 80dbm 3675 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3676 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3677 * from the AP [msec] 3678 * @snooze_window: A window of time in which PBW snoozing insures that all 3679 * packets received. It is also the minimum time from last 3680 * received unicast RX packet, before client stops snoozing 3681 * for data. [msec] 3682 * @snooze_step: TBD 3683 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3684 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3685 * each corresponding AC. 3686 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3687 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3688 * values. 3689 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3690 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3691 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3692 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3693 * @limited_ps_threshold: 3694 */ 3695 struct iwm_mac_power_cmd { 3696 /* CONTEXT_DESC_API_T_VER_1 */ 3697 uint32_t id_and_color; 3698 3699 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 3700 uint16_t flags; 3701 uint16_t keep_alive_seconds; 3702 uint32_t rx_data_timeout; 3703 uint32_t tx_data_timeout; 3704 uint32_t rx_data_timeout_uapsd; 3705 uint32_t tx_data_timeout_uapsd; 3706 uint8_t lprx_rssi_threshold; 3707 uint8_t skip_dtim_periods; 3708 uint16_t snooze_interval; 3709 uint16_t snooze_window; 3710 uint8_t snooze_step; 3711 uint8_t qndp_tid; 3712 uint8_t uapsd_ac_flags; 3713 uint8_t uapsd_max_sp; 3714 uint8_t heavy_tx_thld_packets; 3715 uint8_t heavy_rx_thld_packets; 3716 uint8_t heavy_tx_thld_percentage; 3717 uint8_t heavy_rx_thld_percentage; 3718 uint8_t limited_ps_threshold; 3719 uint8_t reserved; 3720 } __packed; 3721 3722 /* 3723 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when 3724 * associated AP is identified as improperly implementing uAPSD protocol. 3725 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 3726 * @sta_id: index of station in uCode's station table - associated AP ID in 3727 * this context. 3728 */ 3729 struct iwm_uapsd_misbehaving_ap_notif { 3730 uint32_t sta_id; 3731 uint8_t mac_id; 3732 uint8_t reserved[3]; 3733 } __packed; 3734 3735 /** 3736 * struct iwm_beacon_filter_cmd 3737 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 3738 * @id_and_color: MAC contex identifier 3739 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 3740 * to driver if delta in Energy values calculated for this and last 3741 * passed beacon is greater than this threshold. Zero value means that 3742 * the Energy change is ignored for beacon filtering, and beacon will 3743 * not be forced to be sent to driver regardless of this delta. Typical 3744 * energy delta 5dB. 3745 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 3746 * Send beacon to driver if delta in Energy values calculated for this 3747 * and last passed beacon is greater than this threshold. Zero value 3748 * means that the Energy change is ignored for beacon filtering while in 3749 * Roaming state, typical energy delta 1dB. 3750 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 3751 * calculated for current beacon is less than the threshold, use 3752 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 3753 * Threshold. Typical energy threshold is -72dBm. 3754 * @bf_temp_threshold: This threshold determines the type of temperature 3755 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 3756 * If the current temperature is above this threshold - Fast filter 3757 * will be used, If the current temperature is below this threshold - 3758 * Slow filter will be used. 3759 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 3760 * calculated for this and the last passed beacon is greater than this 3761 * threshold. Zero value means that the temperature change is ignored for 3762 * beacon filtering; beacons will not be forced to be sent to driver 3763 * regardless of whether its temperature has been changed. 3764 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 3765 * calculated for this and the last passed beacon is greater than this 3766 * threshold. Zero value means that the temperature change is ignored for 3767 * beacon filtering; beacons will not be forced to be sent to driver 3768 * regardless of whether its temperature has been changed. 3769 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 3770 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed 3771 * for a specific period of time. Units: Beacons. 3772 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 3773 * for a longer period of time then this escape-timeout. Units: Beacons. 3774 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 3775 */ 3776 struct iwm_beacon_filter_cmd { 3777 uint32_t bf_energy_delta; 3778 uint32_t bf_roaming_energy_delta; 3779 uint32_t bf_roaming_state; 3780 uint32_t bf_temp_threshold; 3781 uint32_t bf_temp_fast_filter; 3782 uint32_t bf_temp_slow_filter; 3783 uint32_t bf_enable_beacon_filter; 3784 uint32_t bf_debug_flag; 3785 uint32_t bf_escape_timer; 3786 uint32_t ba_escape_timer; 3787 uint32_t ba_enable_beacon_abort; 3788 } __packed; 3789 3790 /* Beacon filtering and beacon abort */ 3791 #define IWM_BF_ENERGY_DELTA_DEFAULT 5 3792 #define IWM_BF_ENERGY_DELTA_MAX 255 3793 #define IWM_BF_ENERGY_DELTA_MIN 0 3794 3795 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 3796 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255 3797 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0 3798 3799 #define IWM_BF_ROAMING_STATE_DEFAULT 72 3800 #define IWM_BF_ROAMING_STATE_MAX 255 3801 #define IWM_BF_ROAMING_STATE_MIN 0 3802 3803 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112 3804 #define IWM_BF_TEMP_THRESHOLD_MAX 255 3805 #define IWM_BF_TEMP_THRESHOLD_MIN 0 3806 3807 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1 3808 #define IWM_BF_TEMP_FAST_FILTER_MAX 255 3809 #define IWM_BF_TEMP_FAST_FILTER_MIN 0 3810 3811 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5 3812 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255 3813 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0 3814 3815 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1 3816 3817 #define IWM_BF_DEBUG_FLAG_DEFAULT 0 3818 3819 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50 3820 #define IWM_BF_ESCAPE_TIMER_MAX 1024 3821 #define IWM_BF_ESCAPE_TIMER_MIN 0 3822 3823 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6 3824 #define IWM_BA_ESCAPE_TIMER_D3 9 3825 #define IWM_BA_ESCAPE_TIMER_MAX 1024 3826 #define IWM_BA_ESCAPE_TIMER_MIN 0 3827 3828 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1 3829 3830 #define IWM_BF_CMD_CONFIG_DEFAULTS \ 3831 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \ 3832 .bf_roaming_energy_delta = \ 3833 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 3834 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \ 3835 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \ 3836 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \ 3837 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \ 3838 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \ 3839 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \ 3840 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT) 3841 3842 /* 3843 * These serve as indexes into 3844 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT]; 3845 * TODO: avoid overlap between legacy and HT rates 3846 */ 3847 enum { 3848 IWM_RATE_1M_INDEX = 0, 3849 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX, 3850 IWM_RATE_2M_INDEX, 3851 IWM_RATE_5M_INDEX, 3852 IWM_RATE_11M_INDEX, 3853 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX, 3854 IWM_RATE_6M_INDEX, 3855 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX, 3856 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX, 3857 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX, 3858 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX, 3859 IWM_RATE_9M_INDEX, 3860 IWM_RATE_12M_INDEX, 3861 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX, 3862 IWM_RATE_18M_INDEX, 3863 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX, 3864 IWM_RATE_24M_INDEX, 3865 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX, 3866 IWM_RATE_36M_INDEX, 3867 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX, 3868 IWM_RATE_48M_INDEX, 3869 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX, 3870 IWM_RATE_54M_INDEX, 3871 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX, 3872 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX, 3873 IWM_RATE_60M_INDEX, 3874 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX, 3875 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX, 3876 IWM_RATE_MCS_8_INDEX, 3877 IWM_RATE_MCS_9_INDEX, 3878 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX, 3879 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1, 3880 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1, 3881 }; 3882 3883 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX)) 3884 3885 /* fw API values for legacy bit rates, both OFDM and CCK */ 3886 enum { 3887 IWM_RATE_6M_PLCP = 13, 3888 IWM_RATE_9M_PLCP = 15, 3889 IWM_RATE_12M_PLCP = 5, 3890 IWM_RATE_18M_PLCP = 7, 3891 IWM_RATE_24M_PLCP = 9, 3892 IWM_RATE_36M_PLCP = 11, 3893 IWM_RATE_48M_PLCP = 1, 3894 IWM_RATE_54M_PLCP = 3, 3895 IWM_RATE_1M_PLCP = 10, 3896 IWM_RATE_2M_PLCP = 20, 3897 IWM_RATE_5M_PLCP = 55, 3898 IWM_RATE_11M_PLCP = 110, 3899 IWM_RATE_INVM_PLCP = -1, 3900 }; 3901 3902 /* 3903 * rate_n_flags bit fields 3904 * 3905 * The 32-bit value has different layouts in the low 8 bites depending on the 3906 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 3907 * for CCK and OFDM). 3908 * 3909 * High-throughput (HT) rate format 3910 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 3911 * Very High-throughput (VHT) rate format 3912 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 3913 * Legacy OFDM rate format for bits 7:0 3914 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 3915 * Legacy CCK rate format for bits 7:0: 3916 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 3917 */ 3918 3919 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 3920 #define IWM_RATE_MCS_HT_POS 8 3921 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS) 3922 3923 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 3924 #define IWM_RATE_MCS_CCK_POS 9 3925 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS) 3926 3927 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 3928 #define IWM_RATE_MCS_VHT_POS 26 3929 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS) 3930 3931 3932 /* 3933 * High-throughput (HT) rate format for bits 7:0 3934 * 3935 * 2-0: MCS rate base 3936 * 0) 6 Mbps 3937 * 1) 12 Mbps 3938 * 2) 18 Mbps 3939 * 3) 24 Mbps 3940 * 4) 36 Mbps 3941 * 5) 48 Mbps 3942 * 6) 54 Mbps 3943 * 7) 60 Mbps 3944 * 4-3: 0) Single stream (SISO) 3945 * 1) Dual stream (MIMO) 3946 * 2) Triple stream (MIMO) 3947 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 3948 * (bits 7-6 are zero) 3949 * 3950 * Together the low 5 bits work out to the MCS index because we don't 3951 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 3952 * streams and 16-23 have three streams. We could also support MCS 32 3953 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 3954 */ 3955 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7 3956 #define IWM_RATE_HT_MCS_NSS_POS 3 3957 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS) 3958 3959 /* Bit 10: (1) Use Green Field preamble */ 3960 #define IWM_RATE_HT_MCS_GF_POS 10 3961 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS) 3962 3963 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f 3964 3965 /* 3966 * Very High-throughput (VHT) rate format for bits 7:0 3967 * 3968 * 3-0: VHT MCS (0-9) 3969 * 5-4: number of streams - 1: 3970 * 0) Single stream (SISO) 3971 * 1) Dual stream (MIMO) 3972 * 2) Triple stream (MIMO) 3973 */ 3974 3975 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 3976 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf 3977 #define IWM_RATE_VHT_MCS_NSS_POS 4 3978 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS) 3979 3980 /* 3981 * Legacy OFDM rate format for bits 7:0 3982 * 3983 * 3-0: 0xD) 6 Mbps 3984 * 0xF) 9 Mbps 3985 * 0x5) 12 Mbps 3986 * 0x7) 18 Mbps 3987 * 0x9) 24 Mbps 3988 * 0xB) 36 Mbps 3989 * 0x1) 48 Mbps 3990 * 0x3) 54 Mbps 3991 * (bits 7-4 are 0) 3992 * 3993 * Legacy CCK rate format for bits 7:0: 3994 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 3995 * 3996 * 6-0: 10) 1 Mbps 3997 * 20) 2 Mbps 3998 * 55) 5.5 Mbps 3999 * 110) 11 Mbps 4000 * (bit 7 is 0) 4001 */ 4002 #define IWM_RATE_LEGACY_RATE_MSK 0xff 4003 4004 4005 /* 4006 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4007 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4008 */ 4009 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11 4010 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4011 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4012 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4013 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4014 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS) 4015 4016 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4017 #define IWM_RATE_MCS_SGI_POS 13 4018 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS) 4019 4020 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4021 #define IWM_RATE_MCS_ANT_POS 14 4022 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS) 4023 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS) 4024 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS) 4025 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \ 4026 IWM_RATE_MCS_ANT_B_MSK) 4027 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \ 4028 IWM_RATE_MCS_ANT_C_MSK) 4029 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK 4030 #define IWM_RATE_MCS_ANT_NUM 3 4031 4032 /* Bit 17-18: (0) SS, (1) SS*2 */ 4033 #define IWM_RATE_MCS_STBC_POS 17 4034 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS) 4035 4036 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4037 #define IWM_RATE_MCS_BF_POS 19 4038 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS) 4039 4040 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4041 #define IWM_RATE_MCS_ZLF_POS 20 4042 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS) 4043 4044 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4045 #define IWM_RATE_MCS_DUP_POS 24 4046 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS) 4047 4048 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4049 #define IWM_RATE_MCS_LDPC_POS 27 4050 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS) 4051 4052 4053 /* Link Quality definitions */ 4054 4055 /* # entries in rate scale table to support Tx retries */ 4056 #define IWM_LQ_MAX_RETRY_NUM 16 4057 4058 /* Link quality command flags bit fields */ 4059 4060 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4061 #define IWM_LQ_FLAG_USE_RTS_POS 0 4062 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS) 4063 4064 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4065 #define IWM_LQ_FLAG_COLOR_POS 1 4066 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS) 4067 4068 /* Bit 4-5: Tx RTS BW Signalling 4069 * (0) No RTS BW signalling 4070 * (1) Static BW signalling 4071 * (2) Dynamic BW signalling 4072 */ 4073 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4 4074 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4075 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4076 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS) 4077 4078 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4079 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4080 */ 4081 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6 4082 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS) 4083 4084 /* Single Stream Tx Parameters (lq_cmd->ss_params) 4085 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be 4086 * used for single stream Tx. 4087 */ 4088 4089 /* Bit 0-1: Max STBC streams allowed. Can be 0-3. 4090 * (0) - No STBC allowed 4091 * (1) - 2x1 STBC allowed (HT/VHT) 4092 * (2) - 4x2 STBC allowed (HT/VHT) 4093 * (3) - 3x2 STBC allowed (HT only) 4094 * All our chips are at most 2 antennas so only (1) is valid for now. 4095 */ 4096 #define IWM_LQ_SS_STBC_ALLOWED_POS 0 4097 #define IWM_LQ_SS_STBC_ALLOWED_MSK (3 << IWM_LQ_SS_STBC_ALLOWED_MSK) 4098 4099 /* 2x1 STBC is allowed */ 4100 #define IWM_LQ_SS_STBC_1SS_ALLOWED (1 << IWM_LQ_SS_STBC_ALLOWED_POS) 4101 4102 /* Bit 2: Beamformer (VHT only) is allowed */ 4103 #define IWM_LQ_SS_BFER_ALLOWED_POS 2 4104 #define IWM_LQ_SS_BFER_ALLOWED (1 << IWM_LQ_SS_BFER_ALLOWED_POS) 4105 4106 /* Bit 3: Force BFER or STBC for testing 4107 * If this is set: 4108 * If BFER is allowed then force the ucode to choose BFER else 4109 * If STBC is allowed then force the ucode to choose STBC over SISO 4110 */ 4111 #define IWM_LQ_SS_FORCE_POS 3 4112 #define IWM_LQ_SS_FORCE (1 << IWM_LQ_SS_FORCE_POS) 4113 4114 /* Bit 31: ss_params field is valid. Used for FW backward compatibility 4115 * with other drivers which don't support the ss_params API yet 4116 */ 4117 #define IWM_LQ_SS_PARAMS_VALID_POS 31 4118 #define IWM_LQ_SS_PARAMS_VALID (1 << IWM_LQ_SS_PARAMS_VALID_POS) 4119 4120 /** 4121 * struct iwm_lq_cmd - link quality command 4122 * @sta_id: station to update 4123 * @control: not used 4124 * @flags: combination of IWM_LQ_FLAG_* 4125 * @mimo_delim: the first SISO index in rs_table, which separates MIMO 4126 * and SISO rates 4127 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD). 4128 * Should be ANT_[ABC] 4129 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC] 4130 * @initial_rate_index: first index from rs_table per AC category 4131 * @agg_time_limit: aggregation max time threshold in usec/100, meaning 4132 * value of 100 is one usec. Range is 100 to 8000 4133 * @agg_disable_start_th: try-count threshold for starting aggregation. 4134 * If a frame has higher try-count, it should not be selected for 4135 * starting an aggregation sequence. 4136 * @agg_frame_cnt_limit: max frame count in an aggregation. 4137 * 0: no limit 4138 * 1: no aggregation (one frame per aggregation) 4139 * 2 - 0x3f: maximal number of frames (up to 3f == 63) 4140 * @rs_table: array of rates for each TX try, each is rate_n_flags, 4141 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP 4142 * @ss_params: single stream features. declare whether STBC or BFER are allowed. 4143 */ 4144 struct iwm_lq_cmd { 4145 uint8_t sta_id; 4146 uint8_t reduced_tpc; 4147 uint16_t control; 4148 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */ 4149 uint8_t flags; 4150 uint8_t mimo_delim; 4151 uint8_t single_stream_ant_msk; 4152 uint8_t dual_stream_ant_msk; 4153 uint8_t initial_rate_index[IWM_AC_NUM]; 4154 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */ 4155 uint16_t agg_time_limit; 4156 uint8_t agg_disable_start_th; 4157 uint8_t agg_frame_cnt_limit; 4158 uint32_t reserved2; 4159 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM]; 4160 uint32_t ss_params; 4161 }; /* LINK_QUALITY_CMD_API_S_VER_1 */ 4162 4163 /** 4164 * enum iwm_tx_flags - bitmasks for tx_flags in TX command 4165 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4166 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station 4167 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4168 * Otherwise, use rate_n_flags from the TX command 4169 * @IWM_TX_CMD_FLG_BA: this frame is a block ack 4170 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4171 * Must set IWM_TX_CMD_FLG_ACK with this flag. 4172 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4173 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4174 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4175 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4176 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4177 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4178 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4179 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4180 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4181 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4182 * Should be set for beacons and probe responses 4183 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4184 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4185 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4186 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4187 * Should be set for 26/30 length MAC headers 4188 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4189 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4190 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4191 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4192 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4193 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4194 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4195 */ 4196 enum iwm_tx_flags { 4197 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0), 4198 IWM_TX_CMD_FLG_ACK = (1 << 3), 4199 IWM_TX_CMD_FLG_STA_RATE = (1 << 4), 4200 IWM_TX_CMD_FLG_BA = (1 << 5), 4201 IWM_TX_CMD_FLG_BAR = (1 << 6), 4202 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7), 4203 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8), 4204 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9), 4205 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10), 4206 IWM_TX_CMD_FLG_BT_DIS = (1 << 12), 4207 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13), 4208 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14), 4209 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15), 4210 IWM_TX_CMD_FLG_TSF = (1 << 16), 4211 IWM_TX_CMD_FLG_CALIB = (1 << 17), 4212 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18), 4213 IWM_TX_CMD_FLG_AGG_START = (1 << 19), 4214 IWM_TX_CMD_FLG_MH_PAD = (1 << 20), 4215 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21), 4216 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23), 4217 IWM_TX_CMD_FLG_DUR = (1 << 25), 4218 IWM_TX_CMD_FLG_FW_DROP = (1 << 26), 4219 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27), 4220 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28), 4221 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31) 4222 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */ 4223 4224 /** 4225 * enum iwm_tx_pm_timeouts - pm timeout values in TX command 4226 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode 4227 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU 4228 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec 4229 */ 4230 enum iwm_tx_pm_timeouts { 4231 IWM_PM_FRAME_NONE = 0, 4232 IWM_PM_FRAME_MGMT = 2, 4233 IWM_PM_FRAME_ASSOC = 3, 4234 }; 4235 4236 /* 4237 * TX command security control 4238 */ 4239 #define IWM_TX_CMD_SEC_WEP 0x01 4240 #define IWM_TX_CMD_SEC_CCM 0x02 4241 #define IWM_TX_CMD_SEC_TKIP 0x03 4242 #define IWM_TX_CMD_SEC_EXT 0x04 4243 #define IWM_TX_CMD_SEC_MSK 0x07 4244 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4245 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4246 #define IWM_TX_CMD_SEC_KEY128 0x08 4247 4248 /* TODO: how does these values are OK with only 16 bit variable??? */ 4249 /* 4250 * TX command next frame info 4251 * 4252 * bits 0:2 - security control (IWM_TX_CMD_SEC_*) 4253 * bit 3 - immediate ACK required 4254 * bit 4 - rate is taken from STA table 4255 * bit 5 - frame belongs to BA stream 4256 * bit 6 - immediate BA response expected 4257 * bit 7 - unused 4258 * bits 8:15 - Station ID 4259 * bits 16:31 - rate 4260 */ 4261 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4262 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4263 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4264 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4265 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4266 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4267 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4268 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4269 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16) 4270 4271 /* 4272 * TX command Frame life time in us - to be written in pm_frame_timeout 4273 */ 4274 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4275 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4276 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4277 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4278 4279 /* 4280 * TID for non QoS frames - to be written in tid_tspec 4281 */ 4282 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT 4283 4284 /* 4285 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4286 */ 4287 #define IWM_DEFAULT_TX_RETRY 15 4288 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3 4289 #define IWM_RTS_DFAULT_RETRY_LIMIT 60 4290 #define IWM_BAR_DFAULT_RETRY_LIMIT 60 4291 #define IWM_LOW_RETRY_LIMIT 7 4292 4293 /* TODO: complete documentation for try_cnt and btkill_cnt */ 4294 /** 4295 * struct iwm_tx_cmd - TX command struct to FW 4296 * ( IWM_TX_CMD = 0x1c ) 4297 * @len: in bytes of the payload, see below for details 4298 * @next_frame_len: same as len, but for next frame (0 if not applicable) 4299 * Used for fragmentation and bursting, but not in 11n aggregation. 4300 * @tx_flags: combination of IWM_TX_CMD_FLG_* 4301 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is 4302 * cleared. Combination of IWM_RATE_MCS_* 4303 * @sta_id: index of destination station in FW station table 4304 * @sec_ctl: security control, IWM_TX_CMD_SEC_* 4305 * @initial_rate_index: index into the rate table for initial TX attempt. 4306 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames. 4307 * @key: security key 4308 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_* 4309 * @life_time: frame life time (usecs??) 4310 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt + 4311 * btkill_cnd + reserved), first 32 bits. "0" disables usage. 4312 * @dram_msb_ptr: upper bits of the scratch physical address 4313 * @rts_retry_limit: max attempts for RTS 4314 * @data_retry_limit: max attempts to send the data packet 4315 * @tid_spec: TID/tspec 4316 * @pm_frame_timeout: PM TX frame timeout 4317 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not 4318 * specified by HCCA protocol 4319 * 4320 * The byte count (both len and next_frame_len) includes MAC header 4321 * (24/26/30/32 bytes) 4322 * + 2 bytes pad if 26/30 header size 4323 * + 8 byte IV for CCM or TKIP (not used for WEP) 4324 * + Data payload 4325 * + 8-byte MIC (not used for CCM/WEP) 4326 * It does not include post-MAC padding, i.e., 4327 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes. 4328 * Range of len: 14-2342 bytes. 4329 * 4330 * After the struct fields the MAC header is placed, plus any padding, 4331 * and then the actial payload. 4332 */ 4333 struct iwm_tx_cmd { 4334 uint16_t len; 4335 uint16_t next_frame_len; 4336 uint32_t tx_flags; 4337 struct { 4338 uint8_t try_cnt; 4339 uint8_t btkill_cnt; 4340 uint16_t reserved; 4341 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */ 4342 uint32_t rate_n_flags; 4343 uint8_t sta_id; 4344 uint8_t sec_ctl; 4345 uint8_t initial_rate_index; 4346 uint8_t reserved2; 4347 uint8_t key[16]; 4348 uint16_t next_frame_flags; 4349 uint16_t reserved3; 4350 uint32_t life_time; 4351 uint32_t dram_lsb_ptr; 4352 uint8_t dram_msb_ptr; 4353 uint8_t rts_retry_limit; 4354 uint8_t data_retry_limit; 4355 uint8_t tid_tspec; 4356 uint16_t pm_frame_timeout; 4357 uint16_t driver_txop; 4358 uint8_t payload[0]; 4359 struct ieee80211_frame hdr[0]; 4360 } __packed; /* IWM_TX_CMD_API_S_VER_3 */ 4361 4362 /* 4363 * TX response related data 4364 */ 4365 4366 /* 4367 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx 4368 * @IWM_TX_STATUS_SUCCESS: 4369 * @IWM_TX_STATUS_DIRECT_DONE: 4370 * @IWM_TX_STATUS_POSTPONE_DELAY: 4371 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES: 4372 * @IWM_TX_STATUS_POSTPONE_BT_PRIO: 4373 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD: 4374 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK: 4375 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 4376 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT: 4377 * @IWM_TX_STATUS_FAIL_LONG_LIMIT: 4378 * @IWM_TX_STATUS_FAIL_UNDERRUN: 4379 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW: 4380 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH: 4381 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE: 4382 * @IWM_TX_STATUS_FAIL_DEST_PS: 4383 * @IWM_TX_STATUS_FAIL_HOST_ABORTED: 4384 * @IWM_TX_STATUS_FAIL_BT_RETRY: 4385 * @IWM_TX_STATUS_FAIL_STA_INVALID: 4386 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED: 4387 * @IWM_TX_STATUS_FAIL_TID_DISABLE: 4388 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED: 4389 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL: 4390 * @IWM_TX_STATUS_FAIL_FW_DROP: 4391 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4392 * STA table 4393 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT: 4394 * @IWM_TX_MODE_MSK: 4395 * @IWM_TX_MODE_NO_BURST: 4396 * @IWM_TX_MODE_IN_BURST_SEQ: 4397 * @IWM_TX_MODE_FIRST_IN_BURST: 4398 * @IWM_TX_QUEUE_NUM_MSK: 4399 * 4400 * Valid only if frame_count =1 4401 * TODO: complete documentation 4402 */ 4403 enum iwm_tx_status { 4404 IWM_TX_STATUS_MSK = 0x000000ff, 4405 IWM_TX_STATUS_SUCCESS = 0x01, 4406 IWM_TX_STATUS_DIRECT_DONE = 0x02, 4407 /* postpone TX */ 4408 IWM_TX_STATUS_POSTPONE_DELAY = 0x40, 4409 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41, 4410 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42, 4411 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43, 4412 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44, 4413 /* abort TX */ 4414 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81, 4415 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82, 4416 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83, 4417 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84, 4418 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85, 4419 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86, 4420 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87, 4421 IWM_TX_STATUS_FAIL_DEST_PS = 0x88, 4422 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89, 4423 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a, 4424 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b, 4425 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c, 4426 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d, 4427 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e, 4428 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f, 4429 IWM_TX_STATUS_FAIL_FW_DROP = 0x90, 4430 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91, 4431 IWM_TX_STATUS_INTERNAL_ABORT = 0x92, 4432 IWM_TX_MODE_MSK = 0x00000f00, 4433 IWM_TX_MODE_NO_BURST = 0x00000000, 4434 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100, 4435 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200, 4436 IWM_TX_QUEUE_NUM_MSK = 0x0001f000, 4437 IWM_TX_NARROW_BW_MSK = 0x00060000, 4438 IWM_TX_NARROW_BW_1DIV2 = 0x00020000, 4439 IWM_TX_NARROW_BW_1DIV4 = 0x00040000, 4440 IWM_TX_NARROW_BW_1DIV8 = 0x00060000, 4441 }; 4442 4443 /* 4444 * enum iwm_tx_agg_status - TX aggregation status 4445 * @IWM_AGG_TX_STATE_STATUS_MSK: 4446 * @IWM_AGG_TX_STATE_TRANSMITTED: 4447 * @IWM_AGG_TX_STATE_UNDERRUN: 4448 * @IWM_AGG_TX_STATE_BT_PRIO: 4449 * @IWM_AGG_TX_STATE_FEW_BYTES: 4450 * @IWM_AGG_TX_STATE_ABORT: 4451 * @IWM_AGG_TX_STATE_LAST_SENT_TTL: 4452 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT: 4453 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL: 4454 * @IWM_AGG_TX_STATE_SCD_QUERY: 4455 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32: 4456 * @IWM_AGG_TX_STATE_RESPONSE: 4457 * @IWM_AGG_TX_STATE_DUMP_TX: 4458 * @IWM_AGG_TX_STATE_DELAY_TX: 4459 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4460 * occur if tx failed for this frame when it was a member of a previous 4461 * aggregation block). If rate scaling is used, retry count indicates the 4462 * rate table entry used for all frames in the new agg. 4463 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4464 * this frame 4465 * 4466 * TODO: complete documentation 4467 */ 4468 enum iwm_tx_agg_status { 4469 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff, 4470 IWM_AGG_TX_STATE_TRANSMITTED = 0x000, 4471 IWM_AGG_TX_STATE_UNDERRUN = 0x001, 4472 IWM_AGG_TX_STATE_BT_PRIO = 0x002, 4473 IWM_AGG_TX_STATE_FEW_BYTES = 0x004, 4474 IWM_AGG_TX_STATE_ABORT = 0x008, 4475 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010, 4476 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020, 4477 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040, 4478 IWM_AGG_TX_STATE_SCD_QUERY = 0x080, 4479 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100, 4480 IWM_AGG_TX_STATE_RESPONSE = 0x1ff, 4481 IWM_AGG_TX_STATE_DUMP_TX = 0x200, 4482 IWM_AGG_TX_STATE_DELAY_TX = 0x400, 4483 IWM_AGG_TX_STATE_TRY_CNT_POS = 12, 4484 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS, 4485 }; 4486 4487 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \ 4488 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4489 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL) 4490 4491 /* 4492 * The mask below describes a status where we are absolutely sure that the MPDU 4493 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4494 * written the bytes to the TXE, but we know nothing about what the DSP did. 4495 */ 4496 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \ 4497 IWM_AGG_TX_STATE_ABORT | \ 4498 IWM_AGG_TX_STATE_SCD_QUERY) 4499 4500 /* 4501 * IWM_REPLY_TX = 0x1c (response) 4502 * 4503 * This response may be in one of two slightly different formats, indicated 4504 * by the frame_count field: 4505 * 4506 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4507 * frame. Multiple attempts, at various bit rates, may have been made for 4508 * this frame. 4509 * 4510 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4511 * frames that used block-acknowledge. All frames were transmitted at 4512 * same rate. Rate scaling may have been used if first frame in this new 4513 * agg block failed in previous agg block(s). 4514 * 4515 * Note that, for aggregation, ACK (block-ack) status is not delivered 4516 * here; block-ack has not been received by the time the device records 4517 * this status. 4518 * This status relates to reasons the tx might have been blocked or aborted 4519 * within the device, rather than whether it was received successfully by 4520 * the destination station. 4521 */ 4522 4523 /** 4524 * struct iwm_agg_tx_status - per packet TX aggregation status 4525 * @status: enum iwm_tx_agg_status 4526 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4527 */ 4528 struct iwm_agg_tx_status { 4529 uint16_t status; 4530 uint16_t sequence; 4531 } __packed; 4532 4533 /* 4534 * definitions for initial rate index field 4535 * bits [3:0] initial rate index 4536 * bits [6:4] rate table color, used for the initial rate 4537 * bit-7 invalid rate indication 4538 */ 4539 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4540 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4541 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80 4542 4543 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4544 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4545 4546 /** 4547 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet 4548 * ( IWM_REPLY_TX = 0x1c ) 4549 * @frame_count: 1 no aggregation, >1 aggregation 4550 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4551 * @failure_rts: num of failures due to unsuccessful RTS 4552 * @failure_frame: num failures due to no ACK (unused for agg) 4553 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4554 * Tx of all the batch. IWM_RATE_MCS_* 4555 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4556 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4557 * in usec. 4558 * @pa_status: tx power info 4559 * @pa_integ_res_a: tx power info 4560 * @pa_integ_res_b: tx power info 4561 * @pa_integ_res_c: tx power info 4562 * @measurement_req_id: tx power info 4563 * @tfd_info: TFD information set by the FH 4564 * @seq_ctl: sequence control from the Tx cmd 4565 * @byte_cnt: byte count from the Tx cmd 4566 * @tlc_info: TLC rate info 4567 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4568 * @frame_ctrl: frame control 4569 * @status: for non-agg: frame status IWM_TX_STATUS_* 4570 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields 4571 * follow this one, up to frame_count. 4572 * 4573 * After the array of statuses comes the SSN of the SCD. Look at 4574 * %iwm_mvm_get_scd_ssn for more details. 4575 */ 4576 struct iwm_mvm_tx_resp { 4577 uint8_t frame_count; 4578 uint8_t bt_kill_count; 4579 uint8_t failure_rts; 4580 uint8_t failure_frame; 4581 uint32_t initial_rate; 4582 uint16_t wireless_media_time; 4583 4584 uint8_t pa_status; 4585 uint8_t pa_integ_res_a[3]; 4586 uint8_t pa_integ_res_b[3]; 4587 uint8_t pa_integ_res_c[3]; 4588 uint16_t measurement_req_id; 4589 uint8_t reduced_tpc; 4590 uint8_t reserved; 4591 4592 uint32_t tfd_info; 4593 uint16_t seq_ctl; 4594 uint16_t byte_cnt; 4595 uint8_t tlc_info; 4596 uint8_t ra_tid; 4597 uint16_t frame_ctrl; 4598 4599 struct iwm_agg_tx_status status; 4600 } __packed; /* IWM_TX_RSP_API_S_VER_3 */ 4601 4602 /** 4603 * struct iwm_mvm_ba_notif - notifies about reception of BA 4604 * ( IWM_BA_NOTIF = 0xc5 ) 4605 * @sta_addr_lo32: lower 32 bits of the MAC address 4606 * @sta_addr_hi16: upper 16 bits of the MAC address 4607 * @sta_id: Index of recipient (BA-sending) station in fw's station table 4608 * @tid: tid of the session 4609 * @seq_ctl: 4610 * @bitmap: the bitmap of the BA notification as seen in the air 4611 * @scd_flow: the tx queue this BA relates to 4612 * @scd_ssn: the index of the last contiguously sent packet 4613 * @txed: number of Txed frames in this batch 4614 * @txed_2_done: number of Acked frames in this batch 4615 */ 4616 struct iwm_mvm_ba_notif { 4617 uint32_t sta_addr_lo32; 4618 uint16_t sta_addr_hi16; 4619 uint16_t reserved; 4620 4621 uint8_t sta_id; 4622 uint8_t tid; 4623 uint16_t seq_ctl; 4624 uint64_t bitmap; 4625 uint16_t scd_flow; 4626 uint16_t scd_ssn; 4627 uint8_t txed; 4628 uint8_t txed_2_done; 4629 uint16_t reserved1; 4630 } __packed; 4631 4632 /* 4633 * struct iwm_mac_beacon_cmd - beacon template command 4634 * @tx: the tx commands associated with the beacon frame 4635 * @template_id: currently equal to the mac context id of the coresponding 4636 * mac. 4637 * @tim_idx: the offset of the tim IE in the beacon 4638 * @tim_size: the length of the tim IE 4639 * @frame: the template of the beacon frame 4640 */ 4641 struct iwm_mac_beacon_cmd { 4642 struct iwm_tx_cmd tx; 4643 uint32_t template_id; 4644 uint32_t tim_idx; 4645 uint32_t tim_size; 4646 struct ieee80211_frame frame[0]; 4647 } __packed; 4648 4649 struct iwm_beacon_notif { 4650 struct iwm_mvm_tx_resp beacon_notify_hdr; 4651 uint64_t tsf; 4652 uint32_t ibss_mgr_status; 4653 } __packed; 4654 4655 /** 4656 * enum iwm_dump_control - dump (flush) control flags 4657 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 4658 * and the TFD queues are empty. 4659 */ 4660 enum iwm_dump_control { 4661 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1), 4662 }; 4663 4664 /** 4665 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command 4666 * @queues_ctl: bitmap of queues to flush 4667 * @flush_ctl: control flags 4668 * @reserved: reserved 4669 */ 4670 struct iwm_tx_path_flush_cmd { 4671 uint32_t queues_ctl; 4672 uint16_t flush_ctl; 4673 uint16_t reserved; 4674 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 4675 4676 /** 4677 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD 4678 * @tx_resp: the Tx response from the fw (agg or non-agg) 4679 * 4680 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 4681 * it can't know that everything will go well until the end of the AMPDU, it 4682 * can't know in advance the number of MPDUs that will be sent in the current 4683 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 4684 * Hence, it can't know in advance what the SSN of the SCD will be at the end 4685 * of the batch. This is why the SSN of the SCD is written at the end of the 4686 * whole struct at a variable offset. This function knows how to cope with the 4687 * variable offset and returns the SSN of the SCD. 4688 */ 4689 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp) 4690 { 4691 return le32_to_cpup((uint32_t *)&tx_resp->status + 4692 tx_resp->frame_count) & 0xfff; 4693 } 4694 4695 /** 4696 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command 4697 * @token: 4698 * @sta_id: station id 4699 * @tid: 4700 * @scd_queue: scheduler queue to confiug 4701 * @enable: 1 queue enable, 0 queue disable 4702 * @aggregate: 1 aggregated queue, 0 otherwise 4703 * @tx_fifo: %enum iwm_mvm_tx_fifo 4704 * @window: BA window size 4705 * @ssn: SSN for the BA agreement 4706 */ 4707 struct iwm_scd_txq_cfg_cmd { 4708 uint8_t token; 4709 uint8_t sta_id; 4710 uint8_t tid; 4711 uint8_t scd_queue; 4712 uint8_t enable; 4713 uint8_t aggregate; 4714 uint8_t tx_fifo; 4715 uint8_t window; 4716 uint16_t ssn; 4717 uint16_t reserved; 4718 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 4719 4720 /** 4721 * struct iwm_scd_txq_cfg_rsp 4722 * @token: taken from the command 4723 * @sta_id: station id from the command 4724 * @tid: tid from the command 4725 * @scd_queue: scd_queue from the command 4726 */ 4727 struct iwm_scd_txq_cfg_rsp { 4728 uint8_t token; 4729 uint8_t sta_id; 4730 uint8_t tid; 4731 uint8_t scd_queue; 4732 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 4733 4734 4735 /* Scan Commands, Responses, Notifications */ 4736 4737 /* Max number of IEs for direct SSID scans in a command */ 4738 #define IWM_PROBE_OPTION_MAX 20 4739 4740 /** 4741 * struct iwm_ssid_ie - directed scan network information element 4742 * 4743 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD, 4744 * selected by "type" bit field in struct iwm_scan_channel; 4745 * each channel may select different ssids from among the 20 entries. 4746 * SSID IEs get transmitted in reverse order of entry. 4747 */ 4748 struct iwm_ssid_ie { 4749 uint8_t id; 4750 uint8_t len; 4751 uint8_t ssid[IEEE80211_NWID_LEN]; 4752 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 4753 4754 /* scan offload */ 4755 #define IWM_SCAN_MAX_BLACKLIST_LEN 64 4756 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16 4757 #define IWM_SCAN_MAX_PROFILES 11 4758 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 4759 4760 /* Default watchdog (in MS) for scheduled scan iteration */ 4761 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 4762 4763 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 4764 #define IWM_CAN_ABORT_STATUS 1 4765 4766 #define IWM_FULL_SCAN_MULTIPLIER 5 4767 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3 4768 #define IWM_MAX_SCHED_SCAN_PLANS 2 4769 4770 /** 4771 * iwm_scan_schedule_lmac - schedule of scan offload 4772 * @delay: delay between iterations, in seconds. 4773 * @iterations: num of scan iterations 4774 * @full_scan_mul: number of partial scans before each full scan 4775 */ 4776 struct iwm_scan_schedule_lmac { 4777 uint16_t delay; 4778 uint8_t iterations; 4779 uint8_t full_scan_mul; 4780 } __packed; /* SCAN_SCHEDULE_API_S */ 4781 4782 /** 4783 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 4784 * @tx_flags: combination of TX_CMD_FLG_* 4785 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4786 * cleared. Combination of RATE_MCS_* 4787 * @sta_id: index of destination station in FW station table 4788 * @reserved: for alignment and future use 4789 */ 4790 struct iwm_scan_req_tx_cmd { 4791 uint32_t tx_flags; 4792 uint32_t rate_n_flags; 4793 uint8_t sta_id; 4794 uint8_t reserved[3]; 4795 } __packed; 4796 4797 enum iwm_scan_channel_flags_lmac { 4798 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27), 4799 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28), 4800 }; 4801 4802 /** 4803 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 4804 * @flags: bits 1-20: directed scan to i'th ssid 4805 * other bits &enum iwm_scan_channel_flags_lmac 4806 * @channel_number: channel number 1-13 etc 4807 * @iter_count: scan iteration on this channel 4808 * @iter_interval: interval in seconds between iterations on one channel 4809 */ 4810 struct iwm_scan_channel_cfg_lmac { 4811 uint32_t flags; 4812 uint16_t channel_num; 4813 uint16_t iter_count; 4814 uint32_t iter_interval; 4815 } __packed; 4816 4817 /* 4818 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 4819 * @offset: offset in the data block 4820 * @len: length of the segment 4821 */ 4822 struct iwm_scan_probe_segment { 4823 uint16_t offset; 4824 uint16_t len; 4825 } __packed; 4826 4827 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 4828 * @mac_header: first (and common) part of the probe 4829 * @band_data: band specific data 4830 * @common_data: last (and common) part of the probe 4831 * @buf: raw data block 4832 */ 4833 struct iwm_scan_probe_req { 4834 struct iwm_scan_probe_segment mac_header; 4835 struct iwm_scan_probe_segment band_data[2]; 4836 struct iwm_scan_probe_segment common_data; 4837 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 4838 } __packed; 4839 4840 enum iwm_scan_channel_flags { 4841 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0), 4842 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1), 4843 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2), 4844 }; 4845 4846 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 4847 * @flags: enum iwm_scan_channel_flags 4848 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 4849 * involved. 4850 * 1 - EBS is disabled. 4851 * 2 - every second scan will be full scan(and so on). 4852 */ 4853 struct iwm_scan_channel_opt { 4854 uint16_t flags; 4855 uint16_t non_ebs_ratio; 4856 } __packed; 4857 4858 /** 4859 * iwm_mvm_lmac_scan_flags 4860 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses 4861 * without filtering. 4862 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels 4863 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan 4864 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification 4865 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching 4866 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented 4867 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report 4868 * and DS parameter set IEs into probe requests. 4869 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 4870 * 1, 6 and 11. 4871 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches 4872 */ 4873 enum iwm_mvm_lmac_scan_flags { 4874 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0), 4875 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1), 4876 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2), 4877 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3), 4878 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4), 4879 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5), 4880 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6), 4881 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7), 4882 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9), 4883 }; 4884 4885 enum iwm_scan_priority { 4886 IWM_SCAN_PRIORITY_LOW, 4887 IWM_SCAN_PRIORITY_MEDIUM, 4888 IWM_SCAN_PRIORITY_HIGH, 4889 }; 4890 4891 /** 4892 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1 4893 * @reserved1: for alignment and future use 4894 * @channel_num: num of channels to scan 4895 * @active-dwell: dwell time for active channels 4896 * @passive-dwell: dwell time for passive channels 4897 * @fragmented-dwell: dwell time for fragmented passive scan 4898 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases) 4899 * @reserved2: for alignment and future use 4900 * @rx_chain_selct: PHY_RX_CHAIN_* flags 4901 * @scan_flags: &enum iwm_mvm_lmac_scan_flags 4902 * @max_out_time: max time (in TU) to be out of associated channel 4903 * @suspend_time: pause scan this long (TUs) when returning to service channel 4904 * @flags: RXON flags 4905 * @filter_flags: RXON filter 4906 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz 4907 * @direct_scan: list of SSIDs for directed active scan 4908 * @scan_prio: enum iwm_scan_priority 4909 * @iter_num: number of scan iterations 4910 * @delay: delay in seconds before first iteration 4911 * @schedule: two scheduling plans. The first one is finite, the second one can 4912 * be infinite. 4913 * @channel_opt: channel optimization options, for full and partial scan 4914 * @data: channel configuration and probe request packet. 4915 */ 4916 struct iwm_scan_req_lmac { 4917 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */ 4918 uint32_t reserved1; 4919 uint8_t n_channels; 4920 uint8_t active_dwell; 4921 uint8_t passive_dwell; 4922 uint8_t fragmented_dwell; 4923 uint8_t extended_dwell; 4924 uint8_t reserved2; 4925 uint16_t rx_chain_select; 4926 uint32_t scan_flags; 4927 uint32_t max_out_time; 4928 uint32_t suspend_time; 4929 /* RX_ON_FLAGS_API_S_VER_1 */ 4930 uint32_t flags; 4931 uint32_t filter_flags; 4932 struct iwm_scan_req_tx_cmd tx_cmd[2]; 4933 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 4934 uint32_t scan_prio; 4935 /* SCAN_REQ_PERIODIC_PARAMS_API_S */ 4936 uint32_t iter_num; 4937 uint32_t delay; 4938 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS]; 4939 struct iwm_scan_channel_opt channel_opt[2]; 4940 uint8_t data[]; 4941 } __packed; 4942 4943 /** 4944 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 4945 * @last_schedule_line: last schedule line executed (fast or regular) 4946 * @last_schedule_iteration: last scan iteration executed before scan abort 4947 * @status: enum iwm_scan_offload_complete_status 4948 * @ebs_status: EBS success status &enum iwm_scan_ebs_status 4949 * @time_after_last_iter; time in seconds elapsed after last iteration 4950 */ 4951 struct iwm_periodic_scan_complete { 4952 uint8_t last_schedule_line; 4953 uint8_t last_schedule_iteration; 4954 uint8_t status; 4955 uint8_t ebs_status; 4956 uint32_t time_after_last_iter; 4957 uint32_t reserved; 4958 } __packed; 4959 4960 /** 4961 * struct iwm_scan_results_notif - scan results for one channel - 4962 * SCAN_RESULT_NTF_API_S_VER_3 4963 * @channel: which channel the results are from 4964 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 4965 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request 4966 * @num_probe_not_sent: # of request that weren't sent due to not enough time 4967 * @duration: duration spent in channel, in usecs 4968 */ 4969 struct iwm_scan_results_notif { 4970 uint8_t channel; 4971 uint8_t band; 4972 uint8_t probe_status; 4973 uint8_t num_probe_not_sent; 4974 uint32_t duration; 4975 } __packed; 4976 4977 enum iwm_scan_framework_client { 4978 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0), 4979 IWM_SCAN_CLIENT_NETDETECT = (1 << 1), 4980 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2), 4981 }; 4982 4983 /** 4984 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S 4985 * @ssid: MAC address to filter out 4986 * @reported_rssi: AP rssi reported to the host 4987 * @client_bitmap: clients ignore this entry - enum scan_framework_client 4988 */ 4989 struct iwm_scan_offload_blacklist { 4990 uint8_t ssid[IEEE80211_ADDR_LEN]; 4991 uint8_t reported_rssi; 4992 uint8_t client_bitmap; 4993 } __packed; 4994 4995 enum iwm_scan_offload_network_type { 4996 IWM_NETWORK_TYPE_BSS = 1, 4997 IWM_NETWORK_TYPE_IBSS = 2, 4998 IWM_NETWORK_TYPE_ANY = 3, 4999 }; 5000 5001 enum iwm_scan_offload_band_selection { 5002 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4, 5003 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8, 5004 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc, 5005 }; 5006 5007 /** 5008 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S 5009 * @ssid_index: index to ssid list in fixed part 5010 * @unicast_cipher: encryption olgorithm to match - bitmap 5011 * @aut_alg: authentication olgorithm to match - bitmap 5012 * @network_type: enum iwm_scan_offload_network_type 5013 * @band_selection: enum iwm_scan_offload_band_selection 5014 * @client_bitmap: clients waiting for match - enum scan_framework_client 5015 */ 5016 struct iwm_scan_offload_profile { 5017 uint8_t ssid_index; 5018 uint8_t unicast_cipher; 5019 uint8_t auth_alg; 5020 uint8_t network_type; 5021 uint8_t band_selection; 5022 uint8_t client_bitmap; 5023 uint8_t reserved[2]; 5024 } __packed; 5025 5026 /** 5027 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5028 * @blaclist: AP list to filter off from scan results 5029 * @profiles: profiles to search for match 5030 * @blacklist_len: length of blacklist 5031 * @num_profiles: num of profiles in the list 5032 * @match_notify: clients waiting for match found notification 5033 * @pass_match: clients waiting for the results 5034 * @active_clients: active clients bitmap - enum scan_framework_client 5035 * @any_beacon_notify: clients waiting for match notification without match 5036 */ 5037 struct iwm_scan_offload_profile_cfg { 5038 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES]; 5039 uint8_t blacklist_len; 5040 uint8_t num_profiles; 5041 uint8_t match_notify; 5042 uint8_t pass_match; 5043 uint8_t active_clients; 5044 uint8_t any_beacon_notify; 5045 uint8_t reserved[2]; 5046 } __packed; 5047 5048 enum iwm_scan_offload_complete_status { 5049 IWM_SCAN_OFFLOAD_COMPLETED = 1, 5050 IWM_SCAN_OFFLOAD_ABORTED = 2, 5051 }; 5052 5053 enum iwm_scan_ebs_status { 5054 IWM_SCAN_EBS_SUCCESS, 5055 IWM_SCAN_EBS_FAILED, 5056 IWM_SCAN_EBS_CHAN_NOT_FOUND, 5057 IWM_SCAN_EBS_INACTIVE, 5058 }; 5059 5060 /** 5061 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels) 5062 * SCAN_COMPLETE_NTF_API_S_VER_3 5063 * @scanned_channels: number of channels scanned (and number of valid results) 5064 * @status: one of SCAN_COMP_STATUS_* 5065 * @bt_status: BT on/off status 5066 * @last_channel: last channel that was scanned 5067 * @tsf_low: TSF timer (lower half) in usecs 5068 * @tsf_high: TSF timer (higher half) in usecs 5069 * @results: an array of scan results, only "scanned_channels" of them are valid 5070 */ 5071 struct iwm_lmac_scan_complete_notif { 5072 uint8_t scanned_channels; 5073 uint8_t status; 5074 uint8_t bt_status; 5075 uint8_t last_channel; 5076 uint32_t tsf_low; 5077 uint32_t tsf_high; 5078 struct iwm_scan_results_notif results[]; 5079 } __packed; 5080 5081 5082 /* UMAC Scan API */ 5083 5084 /* The maximum of either of these cannot exceed 8, because we use an 5085 * 8-bit mask (see IWM_MVM_SCAN_MASK). 5086 */ 5087 #define IWM_MVM_MAX_UMAC_SCANS 8 5088 #define IWM_MVM_MAX_LMAC_SCANS 1 5089 5090 enum iwm_scan_config_flags { 5091 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0), 5092 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1), 5093 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2), 5094 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3), 5095 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8), 5096 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9), 5097 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10), 5098 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11), 5099 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12), 5100 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13), 5101 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14), 5102 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15), 5103 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16), 5104 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17), 5105 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18), 5106 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19), 5107 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20), 5108 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21), 5109 5110 /* Bits 26-31 are for num of channels in channel_array */ 5111 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5112 }; 5113 5114 enum iwm_scan_config_rates { 5115 /* OFDM basic rates */ 5116 IWM_SCAN_CONFIG_RATE_6M = (1 << 0), 5117 IWM_SCAN_CONFIG_RATE_9M = (1 << 1), 5118 IWM_SCAN_CONFIG_RATE_12M = (1 << 2), 5119 IWM_SCAN_CONFIG_RATE_18M = (1 << 3), 5120 IWM_SCAN_CONFIG_RATE_24M = (1 << 4), 5121 IWM_SCAN_CONFIG_RATE_36M = (1 << 5), 5122 IWM_SCAN_CONFIG_RATE_48M = (1 << 6), 5123 IWM_SCAN_CONFIG_RATE_54M = (1 << 7), 5124 /* CCK basic rates */ 5125 IWM_SCAN_CONFIG_RATE_1M = (1 << 8), 5126 IWM_SCAN_CONFIG_RATE_2M = (1 << 9), 5127 IWM_SCAN_CONFIG_RATE_5M = (1 << 10), 5128 IWM_SCAN_CONFIG_RATE_11M = (1 << 11), 5129 5130 /* Bits 16-27 are for supported rates */ 5131 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5132 }; 5133 5134 enum iwm_channel_flags { 5135 IWM_CHANNEL_FLAG_EBS = (1 << 0), 5136 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1), 5137 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2), 5138 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3), 5139 }; 5140 5141 /** 5142 * struct iwm_scan_config 5143 * @flags: enum scan_config_flags 5144 * @tx_chains: valid_tx antenna - ANT_* definitions 5145 * @rx_chains: valid_rx antenna - ANT_* definitions 5146 * @legacy_rates: default legacy rates - enum scan_config_rates 5147 * @out_of_channel_time: default max out of serving channel time 5148 * @suspend_time: default max suspend time 5149 * @dwell_active: default dwell time for active scan 5150 * @dwell_passive: default dwell time for passive scan 5151 * @dwell_fragmented: default dwell time for fragmented scan 5152 * @dwell_extended: default dwell time for channels 1, 6 and 11 5153 * @mac_addr: default mac address to be used in probes 5154 * @bcast_sta_id: the index of the station in the fw 5155 * @channel_flags: default channel flags - enum iwm_channel_flags 5156 * scan_config_channel_flag 5157 * @channel_array: default supported channels 5158 */ 5159 struct iwm_scan_config { 5160 uint32_t flags; 5161 uint32_t tx_chains; 5162 uint32_t rx_chains; 5163 uint32_t legacy_rates; 5164 uint32_t out_of_channel_time; 5165 uint32_t suspend_time; 5166 uint8_t dwell_active; 5167 uint8_t dwell_passive; 5168 uint8_t dwell_fragmented; 5169 uint8_t dwell_extended; 5170 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 5171 uint8_t bcast_sta_id; 5172 uint8_t channel_flags; 5173 uint8_t channel_array[]; 5174 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */ 5175 5176 /** 5177 * iwm_umac_scan_flags 5178 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5179 * can be preempted by other scan requests with higher priority. 5180 * The low priority scan will be resumed when the higher proirity scan is 5181 * completed. 5182 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5183 * when scan starts. 5184 */ 5185 enum iwm_umac_scan_flags { 5186 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0), 5187 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1), 5188 }; 5189 5190 enum iwm_umac_scan_uid_offsets { 5191 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0, 5192 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8, 5193 }; 5194 5195 enum iwm_umac_scan_general_flags { 5196 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0), 5197 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1), 5198 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2), 5199 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3), 5200 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4), 5201 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5), 5202 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6), 5203 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7), 5204 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8), 5205 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9), 5206 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10), 5207 }; 5208 5209 /** 5210 * struct iwm_scan_channel_cfg_umac 5211 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5212 * @channel_num: channel number 1-13 etc. 5213 * @iter_count: repetition count for the channel. 5214 * @iter_interval: interval between two scan iterations on one channel. 5215 */ 5216 struct iwm_scan_channel_cfg_umac { 5217 uint32_t flags; 5218 uint8_t channel_num; 5219 uint8_t iter_count; 5220 uint16_t iter_interval; 5221 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */ 5222 5223 /** 5224 * struct iwm_scan_umac_schedule 5225 * @interval: interval in seconds between scan iterations 5226 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5227 * @reserved: for alignment and future use 5228 */ 5229 struct iwm_scan_umac_schedule { 5230 uint16_t interval; 5231 uint8_t iter_count; 5232 uint8_t reserved; 5233 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5234 5235 /** 5236 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command 5237 * parameters following channels configuration array. 5238 * @schedule: two scheduling plans. 5239 * @delay: delay in TUs before starting the first scan iteration 5240 * @reserved: for future use and alignment 5241 * @preq: probe request with IEs blocks 5242 * @direct_scan: list of SSIDs for directed active scan 5243 */ 5244 struct iwm_scan_req_umac_tail { 5245 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5246 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS]; 5247 uint16_t delay; 5248 uint16_t reserved; 5249 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5250 struct iwm_scan_probe_req preq; 5251 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX]; 5252 } __packed; 5253 5254 /** 5255 * struct iwm_scan_req_umac 5256 * @flags: &enum iwm_umac_scan_flags 5257 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5258 * @ooc_priority: out of channel priority - &enum iwm_scan_priority 5259 * @general_flags: &enum iwm_umac_scan_general_flags 5260 * @extended_dwell: dwell time for channels 1, 6 and 11 5261 * @active_dwell: dwell time for active scan 5262 * @passive_dwell: dwell time for passive scan 5263 * @fragmented_dwell: dwell time for fragmented passive scan 5264 * @max_out_time: max out of serving channel time 5265 * @suspend_time: max suspend time 5266 * @scan_priority: scan internal prioritization &enum iwm_scan_priority 5267 * @channel_flags: &enum iwm_scan_channel_flags 5268 * @n_channels: num of channels in scan request 5269 * @reserved: for future use and alignment 5270 * @data: &struct iwm_scan_channel_cfg_umac and 5271 * &struct iwm_scan_req_umac_tail 5272 */ 5273 struct iwm_scan_req_umac { 5274 uint32_t flags; 5275 uint32_t uid; 5276 uint32_t ooc_priority; 5277 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5278 uint32_t general_flags; 5279 uint8_t extended_dwell; 5280 uint8_t active_dwell; 5281 uint8_t passive_dwell; 5282 uint8_t fragmented_dwell; 5283 uint32_t max_out_time; 5284 uint32_t suspend_time; 5285 uint32_t scan_priority; 5286 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5287 uint8_t channel_flags; 5288 uint8_t n_channels; 5289 uint16_t reserved; 5290 uint8_t data[]; 5291 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5292 5293 /** 5294 * struct iwm_umac_scan_abort 5295 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5296 * @flags: reserved 5297 */ 5298 struct iwm_umac_scan_abort { 5299 uint32_t uid; 5300 uint32_t flags; 5301 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5302 5303 /** 5304 * struct iwm_umac_scan_complete 5305 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5306 * @last_schedule: last scheduling line 5307 * @last_iter: last scan iteration number 5308 * @scan status: &enum iwm_scan_offload_complete_status 5309 * @ebs_status: &enum iwm_scan_ebs_status 5310 * @time_from_last_iter: time elapsed from last iteration 5311 * @reserved: for future use 5312 */ 5313 struct iwm_umac_scan_complete { 5314 uint32_t uid; 5315 uint8_t last_schedule; 5316 uint8_t last_iter; 5317 uint8_t status; 5318 uint8_t ebs_status; 5319 uint32_t time_from_last_iter; 5320 uint32_t reserved; 5321 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5322 5323 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5324 /** 5325 * struct iwm_scan_offload_profile_match - match information 5326 * @bssid: matched bssid 5327 * @channel: channel where the match occurred 5328 * @energy: 5329 * @matching_feature: 5330 * @matching_channels: bitmap of channels that matched, referencing 5331 * the channels passed in tue scan offload request 5332 */ 5333 struct iwm_scan_offload_profile_match { 5334 uint8_t bssid[IEEE80211_ADDR_LEN]; 5335 uint16_t reserved; 5336 uint8_t channel; 5337 uint8_t energy; 5338 uint8_t matching_feature; 5339 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5340 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5341 5342 /** 5343 * struct iwm_scan_offload_profiles_query - match results query response 5344 * @matched_profiles: bitmap of matched profiles, referencing the 5345 * matches passed in the scan offload request 5346 * @last_scan_age: age of the last offloaded scan 5347 * @n_scans_done: number of offloaded scans done 5348 * @gp2_d0u: GP2 when D0U occurred 5349 * @gp2_invoked: GP2 when scan offload was invoked 5350 * @resume_while_scanning: not used 5351 * @self_recovery: obsolete 5352 * @reserved: reserved 5353 * @matches: array of match information, one for each match 5354 */ 5355 struct iwm_scan_offload_profiles_query { 5356 uint32_t matched_profiles; 5357 uint32_t last_scan_age; 5358 uint32_t n_scans_done; 5359 uint32_t gp2_d0u; 5360 uint32_t gp2_invoked; 5361 uint8_t resume_while_scanning; 5362 uint8_t self_recovery; 5363 uint16_t reserved; 5364 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES]; 5365 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5366 5367 /** 5368 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration 5369 * @uid: scan id, &enum iwm_umac_scan_uid_offsets 5370 * @scanned_channels: number of channels scanned and number of valid elements in 5371 * results array 5372 * @status: one of SCAN_COMP_STATUS_* 5373 * @bt_status: BT on/off status 5374 * @last_channel: last channel that was scanned 5375 * @tsf_low: TSF timer (lower half) in usecs 5376 * @tsf_high: TSF timer (higher half) in usecs 5377 * @results: array of scan results, only "scanned_channels" of them are valid 5378 */ 5379 struct iwm_umac_scan_iter_complete_notif { 5380 uint32_t uid; 5381 uint8_t scanned_channels; 5382 uint8_t status; 5383 uint8_t bt_status; 5384 uint8_t last_channel; 5385 uint32_t tsf_low; 5386 uint32_t tsf_high; 5387 struct iwm_scan_results_notif results[]; 5388 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5389 5390 /* Please keep this enum *SORTED* by hex value. 5391 * Needed for binary search, otherwise a warning will be triggered. 5392 */ 5393 enum iwm_scan_subcmd_ids { 5394 IWM_GSCAN_START_CMD = 0x0, 5395 IWM_GSCAN_STOP_CMD = 0x1, 5396 IWM_GSCAN_SET_HOTLIST_CMD = 0x2, 5397 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3, 5398 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4, 5399 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5, 5400 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD, 5401 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE, 5402 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF, 5403 }; 5404 5405 /* STA API */ 5406 5407 /** 5408 * enum iwm_sta_flags - flags for the ADD_STA host command 5409 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: 5410 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA: 5411 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled 5412 * @IWM_STA_FLG_PS: set if STA is in Power Save 5413 * @IWM_STA_FLG_INVALID: set if STA is invalid 5414 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5415 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5416 * @IWM_STA_FLG_DRAIN_FLOW: drain flow 5417 * @IWM_STA_FLG_PAN: STA is for PAN interface 5418 * @IWM_STA_FLG_CLASS_AUTH: 5419 * @IWM_STA_FLG_CLASS_ASSOC: 5420 * @IWM_STA_FLG_CLASS_MIMO_PROT: 5421 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5422 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5423 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5424 * initialised by driver and can be updated by fw upon reception of 5425 * action frames that can change the channel width. When cleared the fw 5426 * will send all the frames in 20MHz even when FAT channel is requested. 5427 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5428 * driver and can be updated by fw upon reception of action frames. 5429 * @IWM_STA_FLG_MFP_EN: Management Frame Protection 5430 */ 5431 enum iwm_sta_flags { 5432 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3), 5433 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6), 5434 5435 IWM_STA_FLG_DISABLE_TX = (1 << 4), 5436 5437 IWM_STA_FLG_PS = (1 << 8), 5438 IWM_STA_FLG_DRAIN_FLOW = (1 << 12), 5439 IWM_STA_FLG_PAN = (1 << 13), 5440 IWM_STA_FLG_CLASS_AUTH = (1 << 14), 5441 IWM_STA_FLG_CLASS_ASSOC = (1 << 15), 5442 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17), 5443 5444 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19, 5445 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5446 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5447 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5448 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5449 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5450 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5451 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5452 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5453 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT), 5454 5455 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23, 5456 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5457 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5458 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5459 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5460 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT), 5461 5462 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26), 5463 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26), 5464 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26), 5465 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26), 5466 IWM_STA_FLG_FAT_EN_MSK = (3 << 26), 5467 5468 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28), 5469 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28), 5470 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28), 5471 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28), 5472 }; 5473 5474 /** 5475 * enum iwm_sta_key_flag - key flags for the ADD_STA host command 5476 * @IWM_STA_KEY_FLG_NO_ENC: no encryption 5477 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm 5478 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm 5479 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5480 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5481 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5482 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5483 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5484 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5485 * station info array (1 - n 1X mode) 5486 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key 5487 * @IWM_STA_KEY_NOT_VALID: key is invalid 5488 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5489 * @IWM_STA_KEY_MULTICAST: set for multical key 5490 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection 5491 */ 5492 enum iwm_sta_key_flag { 5493 IWM_STA_KEY_FLG_NO_ENC = (0 << 0), 5494 IWM_STA_KEY_FLG_WEP = (1 << 0), 5495 IWM_STA_KEY_FLG_CCM = (2 << 0), 5496 IWM_STA_KEY_FLG_TKIP = (3 << 0), 5497 IWM_STA_KEY_FLG_EXT = (4 << 0), 5498 IWM_STA_KEY_FLG_CMAC = (6 << 0), 5499 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0), 5500 IWM_STA_KEY_FLG_EN_MSK = (7 << 0), 5501 5502 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3), 5503 IWM_STA_KEY_FLG_KEYID_POS = 8, 5504 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS), 5505 IWM_STA_KEY_NOT_VALID = (1 << 11), 5506 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12), 5507 IWM_STA_KEY_MULTICAST = (1 << 14), 5508 IWM_STA_KEY_MFP = (1 << 15), 5509 }; 5510 5511 /** 5512 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed 5513 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 5514 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 5515 * @IWM_STA_MODIFY_TX_RATE: unused 5516 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 5517 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 5518 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 5519 * @IWM_STA_MODIFY_PROT_TH: 5520 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station 5521 */ 5522 enum iwm_sta_modify_flag { 5523 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0), 5524 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1), 5525 IWM_STA_MODIFY_TX_RATE = (1 << 2), 5526 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3), 5527 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4), 5528 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5), 5529 IWM_STA_MODIFY_PROT_TH = (1 << 6), 5530 IWM_STA_MODIFY_QUEUES = (1 << 7), 5531 }; 5532 5533 #define IWM_STA_MODE_MODIFY 1 5534 5535 /** 5536 * enum iwm_sta_sleep_flag - type of sleep of the station 5537 * @IWM_STA_SLEEP_STATE_AWAKE: 5538 * @IWM_STA_SLEEP_STATE_PS_POLL: 5539 * @IWM_STA_SLEEP_STATE_UAPSD: 5540 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on 5541 * (last) released frame 5542 */ 5543 enum iwm_sta_sleep_flag { 5544 IWM_STA_SLEEP_STATE_AWAKE = 0, 5545 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0), 5546 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1), 5547 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2), 5548 }; 5549 5550 /* STA ID and color bits definitions */ 5551 #define IWM_STA_ID_SEED (0x0f) 5552 #define IWM_STA_ID_POS (0) 5553 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS) 5554 5555 #define IWM_STA_COLOR_SEED (0x7) 5556 #define IWM_STA_COLOR_POS (4) 5557 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS) 5558 5559 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 5560 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS) 5561 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \ 5562 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS) 5563 5564 #define IWM_STA_KEY_MAX_NUM (16) 5565 #define IWM_STA_KEY_IDX_INVALID (0xff) 5566 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4) 5567 #define IWM_MAX_GLOBAL_KEYS (4) 5568 #define IWM_STA_KEY_LEN_WEP40 (5) 5569 #define IWM_STA_KEY_LEN_WEP104 (13) 5570 5571 /** 5572 * struct iwm_mvm_keyinfo - key information 5573 * @key_flags: type %iwm_sta_key_flag 5574 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5575 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5576 * @key_offset: key offset in the fw's key table 5577 * @key: 16-byte unicast decryption key 5578 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 5579 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 5580 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 5581 */ 5582 struct iwm_mvm_keyinfo { 5583 uint16_t key_flags; 5584 uint8_t tkip_rx_tsc_byte2; 5585 uint8_t reserved1; 5586 uint16_t tkip_rx_ttak[5]; 5587 uint8_t key_offset; 5588 uint8_t reserved2; 5589 uint8_t key[16]; 5590 uint64_t tx_secur_seq_cnt; 5591 uint64_t hw_tkip_mic_rx_key; 5592 uint64_t hw_tkip_mic_tx_key; 5593 } __packed; 5594 5595 #define IWM_ADD_STA_STATUS_MASK 0xFF 5596 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000 5597 #define IWM_ADD_STA_BAID_MASK 0x7F00 5598 #define IWM_ADD_STA_BAID_SHIFT 8 5599 5600 /** 5601 * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table. 5602 * ( REPLY_ADD_STA = 0x18 ) 5603 * @add_modify: 1: modify existing, 0: add new station 5604 * @awake_acs: 5605 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 5606 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field. 5607 * @mac_id_n_color: the Mac context this station belongs to 5608 * @addr[IEEE80211_ADDR_LEN]: station's MAC address 5609 * @sta_id: index of station in uCode's station table 5610 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave 5611 * alone. 1 - modify, 0 - don't change. 5612 * @station_flags: look at %iwm_sta_flags 5613 * @station_flags_msk: what of %station_flags have changed 5614 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 5615 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set 5616 * add_immediate_ba_ssn. 5617 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 5618 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field 5619 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 5620 * add_immediate_ba_tid. 5621 * @sleep_tx_count: number of packets to transmit to station even though it is 5622 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 5623 * keeps track of STA sleep state. 5624 * @sleep_state_flags: Look at %iwm_sta_sleep_flag. 5625 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 5626 * mac-addr. 5627 * @beamform_flags: beam forming controls 5628 * @tfd_queue_msk: tfd queues used by this station 5629 * 5630 * The device contains an internal table of per-station information, with info 5631 * on security keys, aggregation parameters, and Tx rates for initial Tx 5632 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD). 5633 * 5634 * ADD_STA sets up the table entry for one station, either creating a new 5635 * entry, or modifying a pre-existing one. 5636 */ 5637 struct iwm_mvm_add_sta_cmd { 5638 uint8_t add_modify; 5639 uint8_t awake_acs; 5640 uint16_t tid_disable_tx; 5641 uint32_t mac_id_n_color; 5642 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 5643 uint16_t reserved2; 5644 uint8_t sta_id; 5645 uint8_t modify_mask; 5646 uint16_t reserved3; 5647 uint32_t station_flags; 5648 uint32_t station_flags_msk; 5649 uint8_t add_immediate_ba_tid; 5650 uint8_t remove_immediate_ba_tid; 5651 uint16_t add_immediate_ba_ssn; 5652 uint16_t sleep_tx_count; 5653 uint16_t sleep_state_flags; 5654 uint16_t assoc_id; 5655 uint16_t beamform_flags; 5656 uint32_t tfd_queue_msk; 5657 } __packed; /* ADD_STA_CMD_API_S_VER_7 */ 5658 5659 /** 5660 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key 5661 * ( IWM_REPLY_ADD_STA_KEY = 0x17 ) 5662 * @sta_id: index of station in uCode's station table 5663 * @key_offset: key offset in key storage 5664 * @key_flags: type %iwm_sta_key_flag 5665 * @key: key material data 5666 * @key2: key material data 5667 * @rx_secur_seq_cnt: RX security sequence counter for the key 5668 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 5669 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 5670 */ 5671 struct iwm_mvm_add_sta_key_cmd { 5672 uint8_t sta_id; 5673 uint8_t key_offset; 5674 uint16_t key_flags; 5675 uint8_t key[16]; 5676 uint8_t key2[16]; 5677 uint8_t rx_secur_seq_cnt[16]; 5678 uint8_t tkip_rx_tsc_byte2; 5679 uint8_t reserved; 5680 uint16_t tkip_rx_ttak[5]; 5681 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */ 5682 5683 /** 5684 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command 5685 * @IWM_ADD_STA_SUCCESS: operation was executed successfully 5686 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 5687 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 5688 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 5689 * that doesn't exist. 5690 */ 5691 enum iwm_mvm_add_sta_rsp_status { 5692 IWM_ADD_STA_SUCCESS = 0x1, 5693 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2, 5694 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4, 5695 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8, 5696 }; 5697 5698 /** 5699 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table 5700 * ( IWM_REMOVE_STA = 0x19 ) 5701 * @sta_id: the station id of the station to be removed 5702 */ 5703 struct iwm_mvm_rm_sta_cmd { 5704 uint8_t sta_id; 5705 uint8_t reserved[3]; 5706 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */ 5707 5708 /** 5709 * struct iwm_mvm_mgmt_mcast_key_cmd 5710 * ( IWM_MGMT_MCAST_KEY = 0x1f ) 5711 * @ctrl_flags: %iwm_sta_key_flag 5712 * @IGTK: 5713 * @K1: IGTK master key 5714 * @K2: IGTK sub key 5715 * @sta_id: station ID that support IGTK 5716 * @key_id: 5717 * @receive_seq_cnt: initial RSC/PN needed for replay check 5718 */ 5719 struct iwm_mvm_mgmt_mcast_key_cmd { 5720 uint32_t ctrl_flags; 5721 uint8_t IGTK[16]; 5722 uint8_t K1[16]; 5723 uint8_t K2[16]; 5724 uint32_t key_id; 5725 uint32_t sta_id; 5726 uint64_t receive_seq_cnt; 5727 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 5728 5729 struct iwm_mvm_wep_key { 5730 uint8_t key_index; 5731 uint8_t key_offset; 5732 uint16_t reserved1; 5733 uint8_t key_size; 5734 uint8_t reserved2[3]; 5735 uint8_t key[16]; 5736 } __packed; 5737 5738 struct iwm_mvm_wep_key_cmd { 5739 uint32_t mac_id_n_color; 5740 uint8_t num_keys; 5741 uint8_t decryption_type; 5742 uint8_t flags; 5743 uint8_t reserved; 5744 struct iwm_mvm_wep_key wep_key[0]; 5745 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 5746 5747 /* 5748 * BT coex 5749 */ 5750 5751 enum iwm_bt_coex_mode { 5752 IWM_BT_COEX_DISABLE = 0x0, 5753 IWM_BT_COEX_NW = 0x1, 5754 IWM_BT_COEX_BT = 0x2, 5755 IWM_BT_COEX_WIFI = 0x3, 5756 }; /* BT_COEX_MODES_E */ 5757 5758 enum iwm_bt_coex_enabled_modules { 5759 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0), 5760 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1), 5761 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2), 5762 IWM_BT_COEX_CORUN_ENABLED = (1 << 3), 5763 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4), 5764 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 5765 5766 /** 5767 * struct iwm_bt_coex_cmd - bt coex configuration command 5768 * @mode: enum %iwm_bt_coex_mode 5769 * @enabled_modules: enum %iwm_bt_coex_enabled_modules 5770 * 5771 * The structure is used for the BT_COEX command. 5772 */ 5773 struct iwm_bt_coex_cmd { 5774 uint32_t mode; 5775 uint32_t enabled_modules; 5776 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 5777 5778 5779 /* 5780 * Location Aware Regulatory (LAR) API - MCC updates 5781 */ 5782 5783 /** 5784 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic 5785 * regulatory profile according to the given MCC (Mobile Country Code). 5786 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5787 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5788 * MCC in the cmd response will be the relevant MCC in the NVM. 5789 * @mcc: given mobile country code 5790 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5791 * @reserved: reserved for alignment 5792 */ 5793 struct iwm_mcc_update_cmd_v1 { 5794 uint16_t mcc; 5795 uint8_t source_id; 5796 uint8_t reserved; 5797 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */ 5798 5799 /** 5800 * struct iwm_mcc_update_cmd - Request the device to update geographic 5801 * regulatory profile according to the given MCC (Mobile Country Code). 5802 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5803 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5804 * MCC in the cmd response will be the relevant MCC in the NVM. 5805 * @mcc: given mobile country code 5806 * @source_id: the source from where we got the MCC, see iwm_mcc_source 5807 * @reserved: reserved for alignment 5808 * @key: integrity key for MCC API OEM testing 5809 * @reserved2: reserved 5810 */ 5811 struct iwm_mcc_update_cmd { 5812 uint16_t mcc; 5813 uint8_t source_id; 5814 uint8_t reserved; 5815 uint32_t key; 5816 uint32_t reserved2[5]; 5817 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 5818 5819 /** 5820 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD. 5821 * Contains the new channel control profile map, if changed, and the new MCC 5822 * (mobile country code). 5823 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5824 * @status: see &enum iwm_mcc_update_status 5825 * @mcc: the new applied MCC 5826 * @cap: capabilities for all channels which matches the MCC 5827 * @source_id: the MCC source, see iwm_mcc_source 5828 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5829 * channels, depending on platform) 5830 * @channels: channel control data map, DWORD for each channel. Only the first 5831 * 16bits are used. 5832 */ 5833 struct iwm_mcc_update_resp_v1 { 5834 uint32_t status; 5835 uint16_t mcc; 5836 uint8_t cap; 5837 uint8_t source_id; 5838 uint32_t n_channels; 5839 uint32_t channels[0]; 5840 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */ 5841 5842 /** 5843 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD. 5844 * Contains the new channel control profile map, if changed, and the new MCC 5845 * (mobile country code). 5846 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 5847 * @status: see &enum iwm_mcc_update_status 5848 * @mcc: the new applied MCC 5849 * @cap: capabilities for all channels which matches the MCC 5850 * @source_id: the MCC source, see iwm_mcc_source 5851 * @time: time elapsed from the MCC test start (in 30 seconds TU) 5852 * @reserved: reserved. 5853 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 5854 * channels, depending on platform) 5855 * @channels: channel control data map, DWORD for each channel. Only the first 5856 * 16bits are used. 5857 */ 5858 struct iwm_mcc_update_resp { 5859 uint32_t status; 5860 uint16_t mcc; 5861 uint8_t cap; 5862 uint8_t source_id; 5863 uint16_t time; 5864 uint16_t reserved; 5865 uint32_t n_channels; 5866 uint32_t channels[0]; 5867 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */ 5868 5869 /** 5870 * struct iwm_mcc_chub_notif - chub notifies of mcc change 5871 * (MCC_CHUB_UPDATE_CMD = 0xc9) 5872 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 5873 * the cellular and connectivity cores that gets updates of the mcc, and 5874 * notifies the ucode directly of any mcc change. 5875 * The ucode requests the driver to request the device to update geographic 5876 * regulatory profile according to the given MCC (Mobile Country Code). 5877 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 5878 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 5879 * MCC in the cmd response will be the relevant MCC in the NVM. 5880 * @mcc: given mobile country code 5881 * @source_id: identity of the change originator, see iwm_mcc_source 5882 * @reserved1: reserved for alignment 5883 */ 5884 struct iwm_mcc_chub_notif { 5885 uint16_t mcc; 5886 uint8_t source_id; 5887 uint8_t reserved1; 5888 } __packed; /* LAR_MCC_NOTIFY_S */ 5889 5890 enum iwm_mcc_update_status { 5891 IWM_MCC_RESP_NEW_CHAN_PROFILE, 5892 IWM_MCC_RESP_SAME_CHAN_PROFILE, 5893 IWM_MCC_RESP_INVALID, 5894 IWM_MCC_RESP_NVM_DISABLED, 5895 IWM_MCC_RESP_ILLEGAL, 5896 IWM_MCC_RESP_LOW_PRIORITY, 5897 IWM_MCC_RESP_TEST_MODE_ACTIVE, 5898 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE, 5899 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 5900 }; 5901 5902 enum iwm_mcc_source { 5903 IWM_MCC_SOURCE_OLD_FW = 0, 5904 IWM_MCC_SOURCE_ME = 1, 5905 IWM_MCC_SOURCE_BIOS = 2, 5906 IWM_MCC_SOURCE_3G_LTE_HOST = 3, 5907 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4, 5908 IWM_MCC_SOURCE_WIFI = 5, 5909 IWM_MCC_SOURCE_RESERVED = 6, 5910 IWM_MCC_SOURCE_DEFAULT = 7, 5911 IWM_MCC_SOURCE_UNINITIALIZED = 8, 5912 IWM_MCC_SOURCE_MCC_API = 9, 5913 IWM_MCC_SOURCE_GET_CURRENT = 0x10, 5914 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11, 5915 }; 5916 5917 /** 5918 * struct iwm_dts_measurement_notif_v1 - measurements notification 5919 * 5920 * @temp: the measured temperature 5921 * @voltage: the measured voltage 5922 */ 5923 struct iwm_dts_measurement_notif_v1 { 5924 int32_t temp; 5925 int32_t voltage; 5926 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/ 5927 5928 /** 5929 * struct iwm_dts_measurement_notif_v2 - measurements notification 5930 * 5931 * @temp: the measured temperature 5932 * @voltage: the measured voltage 5933 * @threshold_idx: the trip index that was crossed 5934 */ 5935 struct iwm_dts_measurement_notif_v2 { 5936 int32_t temp; 5937 int32_t voltage; 5938 int32_t threshold_idx; 5939 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */ 5940 5941 /* 5942 * Some cherry-picked definitions 5943 */ 5944 5945 #define IWM_FRAME_LIMIT 64 5946 5947 /* 5948 * These functions retrieve specific information from the id field in 5949 * the iwm_host_cmd struct which contains the command id, the group id, 5950 * and the version of the command and vice versa. 5951 */ 5952 static inline uint8_t 5953 iwm_cmd_opcode(uint32_t cmdid) 5954 { 5955 return cmdid & 0xff; 5956 } 5957 5958 static inline uint8_t 5959 iwm_cmd_groupid(uint32_t cmdid) 5960 { 5961 return ((cmdid & 0xff00) >> 8); 5962 } 5963 5964 static inline uint8_t 5965 iwm_cmd_version(uint32_t cmdid) 5966 { 5967 return ((cmdid & 0xff0000) >> 16); 5968 } 5969 5970 static inline uint32_t 5971 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 5972 { 5973 return opcode + (groupid << 8) + (version << 16); 5974 } 5975 5976 /* make uint16_t wide id out of uint8_t group and opcode */ 5977 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 5978 5979 /* due to the conversion, this group is special */ 5980 #define IWM_ALWAYS_LONG_GROUP 1 5981 5982 struct iwm_cmd_header { 5983 uint8_t code; 5984 uint8_t flags; 5985 uint8_t idx; 5986 uint8_t qid; 5987 } __packed; 5988 5989 struct iwm_cmd_header_wide { 5990 uint8_t opcode; 5991 uint8_t group_id; 5992 uint8_t idx; 5993 uint8_t qid; 5994 uint16_t length; 5995 uint8_t reserved; 5996 uint8_t version; 5997 } __packed; 5998 5999 /** 6000 * enum iwm_power_scheme 6001 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode 6002 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default) 6003 * @IWM_POWER_LEVEL_LP - Low Power 6004 */ 6005 enum iwm_power_scheme { 6006 IWM_POWER_SCHEME_CAM = 1, 6007 IWM_POWER_SCHEME_BPS, 6008 IWM_POWER_SCHEME_LP 6009 }; 6010 6011 #define IWM_DEF_CMD_PAYLOAD_SIZE 320 6012 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header)) 6013 #define IWM_CMD_FAILED_MSK 0x40 6014 6015 /** 6016 * struct iwm_device_cmd 6017 * 6018 * For allocation of the command and tx queues, this establishes the overall 6019 * size of the largest command we send to uCode, except for commands that 6020 * aren't fully copied and use other TFD space. 6021 */ 6022 struct iwm_device_cmd { 6023 union { 6024 struct { 6025 struct iwm_cmd_header hdr; 6026 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE]; 6027 }; 6028 struct { 6029 struct iwm_cmd_header_wide hdr_wide; 6030 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE - 6031 sizeof(struct iwm_cmd_header_wide) + 6032 sizeof(struct iwm_cmd_header)]; 6033 }; 6034 }; 6035 } __packed; 6036 6037 struct iwm_rx_packet { 6038 /* 6039 * The first 4 bytes of the RX frame header contain both the RX frame 6040 * size and some flags. 6041 * Bit fields: 6042 * 31: flag flush RB request 6043 * 30: flag ignore TC (terminal counter) request 6044 * 29: flag fast IRQ request 6045 * 28-14: Reserved 6046 * 13-00: RX frame size 6047 */ 6048 uint32_t len_n_flags; 6049 struct iwm_cmd_header hdr; 6050 uint8_t data[]; 6051 } __packed; 6052 6053 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6054 #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000 6055 #define IWM_FH_RSCSR_FRAME_ALIGN 0x40 6056 6057 static inline uint32_t 6058 iwm_rx_packet_len(const struct iwm_rx_packet *pkt) 6059 { 6060 6061 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK; 6062 } 6063 6064 static inline uint32_t 6065 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt) 6066 { 6067 6068 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr); 6069 } 6070 6071 6072 #define IWM_MIN_DBM -100 6073 #define IWM_MAX_DBM -33 /* realistic guess */ 6074 6075 #define IWM_READ(sc, reg) \ 6076 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6077 6078 #define IWM_WRITE(sc, reg, val) \ 6079 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6080 6081 #define IWM_WRITE_1(sc, reg, val) \ 6082 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6083 6084 #define IWM_SETBITS(sc, reg, mask) \ 6085 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask)) 6086 6087 #define IWM_CLRBITS(sc, reg, mask) \ 6088 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask)) 6089 6090 #define IWM_BARRIER_WRITE(sc) \ 6091 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6092 BUS_SPACE_BARRIER_WRITE) 6093 6094 #define IWM_BARRIER_READ_WRITE(sc) \ 6095 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6096 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6097 6098 #endif /* __IF_IWM_REG_H__ */ 6099