1 /*- 2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org> 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2011 Intel Corporation 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 /* 23 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 24 * adapters. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_wlan.h" 31 #include "opt_iwn.h" 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/sysctl.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/rman.h> 44 #include <sys/endian.h> 45 #include <sys/firmware.h> 46 #include <sys/limits.h> 47 #include <sys/module.h> 48 #include <sys/caps.h> 49 #include <sys/queue.h> 50 #include <sys/taskqueue.h> 51 #if defined(__DragonFly__) 52 #include <sys/device.h> 53 #endif 54 55 #if defined(__DragonFly__) 56 /* empty */ 57 #else 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <machine/clock.h> 61 #endif 62 63 #if defined(__DragonFly__) 64 #include <bus/pci/pcireg.h> 65 #include <bus/pci/pcivar.h> 66 #else 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 #endif 70 71 #include <net/if.h> 72 #include <net/if_var.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <netinet/in.h> 77 #include <netinet/if_ether.h> 78 79 #include <netproto/802_11/ieee80211_var.h> 80 #include <netproto/802_11/ieee80211_radiotap.h> 81 #include <netproto/802_11/ieee80211_regdomain.h> 82 #include <netproto/802_11/ieee80211_ratectl.h> 83 84 #include <dev/netif/iwn/if_iwnreg.h> 85 #include <dev/netif/iwn/if_iwnvar.h> 86 #include <dev/netif/iwn/if_iwn_devid.h> 87 #include <dev/netif/iwn/if_iwn_chip_cfg.h> 88 #include <dev/netif/iwn/if_iwn_debug.h> 89 #include <dev/netif/iwn/if_iwn_ioctl.h> 90 91 struct iwn_ident { 92 uint16_t vendor; 93 uint16_t device; 94 const char *name; 95 }; 96 97 static const struct iwn_ident iwn_ident_table[] = { 98 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 99 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 100 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 101 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 102 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 103 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 104 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 105 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 106 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 107 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 108 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 109 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 110 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 111 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 112 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */ 113 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 114 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 115 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 116 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 117 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 118 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 119 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" }, 120 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" }, 121 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" }, 122 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" }, 123 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 124 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 125 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 126 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 127 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 128 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 129 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 130 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 131 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 132 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 133 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 134 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 135 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 136 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 137 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 138 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 139 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" }, 140 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" }, 141 { 0, 0, NULL } 142 }; 143 144 static int iwn_probe(device_t); 145 static int iwn_attach(device_t); 146 static int iwn4965_attach(struct iwn_softc *, uint16_t); 147 static int iwn5000_attach(struct iwn_softc *, uint16_t); 148 static int iwn_config_specific(struct iwn_softc *, uint16_t); 149 static void iwn_radiotap_attach(struct iwn_softc *); 150 static void iwn_sysctlattach(struct iwn_softc *); 151 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 152 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 153 const uint8_t [IEEE80211_ADDR_LEN], 154 const uint8_t [IEEE80211_ADDR_LEN]); 155 static void iwn_vap_delete(struct ieee80211vap *); 156 static int iwn_detach(device_t); 157 static int iwn_shutdown(device_t); 158 static int iwn_suspend(device_t); 159 static int iwn_resume(device_t); 160 static int iwn_nic_lock(struct iwn_softc *); 161 static int iwn_eeprom_lock(struct iwn_softc *); 162 static int iwn_init_otprom(struct iwn_softc *); 163 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 164 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 165 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 166 void **, bus_size_t, bus_size_t); 167 static void iwn_dma_contig_free(struct iwn_dma_info *); 168 static int iwn_alloc_sched(struct iwn_softc *); 169 static void iwn_free_sched(struct iwn_softc *); 170 static int iwn_alloc_kw(struct iwn_softc *); 171 static void iwn_free_kw(struct iwn_softc *); 172 static int iwn_alloc_ict(struct iwn_softc *); 173 static void iwn_free_ict(struct iwn_softc *); 174 static int iwn_alloc_fwmem(struct iwn_softc *); 175 static void iwn_free_fwmem(struct iwn_softc *); 176 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 177 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 178 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 179 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 180 int); 181 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 182 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 183 static void iwn5000_ict_reset(struct iwn_softc *); 184 static int iwn_read_eeprom(struct iwn_softc *, 185 uint8_t macaddr[IEEE80211_ADDR_LEN]); 186 static void iwn4965_read_eeprom(struct iwn_softc *); 187 #ifdef IWN_DEBUG 188 static void iwn4965_print_power_group(struct iwn_softc *, int); 189 #endif 190 static void iwn5000_read_eeprom(struct iwn_softc *); 191 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 192 static void iwn_read_eeprom_band(struct iwn_softc *, int, int, int *, 193 struct ieee80211_channel[]); 194 static void iwn_read_eeprom_ht40(struct iwn_softc *, int, int, int *, 195 struct ieee80211_channel[]); 196 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 197 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 198 struct ieee80211_channel *); 199 static void iwn_getradiocaps(struct ieee80211com *, int, int *, 200 struct ieee80211_channel[]); 201 static int iwn_setregdomain(struct ieee80211com *, 202 struct ieee80211_regdomain *, int, 203 struct ieee80211_channel[]); 204 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 205 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 206 const uint8_t mac[IEEE80211_ADDR_LEN]); 207 static void iwn_newassoc(struct ieee80211_node *, int); 208 static int iwn_media_change(struct ifnet *); 209 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 210 static void iwn_calib_timeout(void *); 211 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 212 struct iwn_rx_data *); 213 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 214 struct iwn_rx_data *); 215 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 216 struct iwn_rx_data *); 217 static void iwn5000_rx_calib_results(struct iwn_softc *, 218 struct iwn_rx_desc *, struct iwn_rx_data *); 219 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 220 struct iwn_rx_data *); 221 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 222 struct iwn_rx_data *); 223 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 224 struct iwn_rx_data *); 225 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 226 uint8_t); 227 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, int, void *); 228 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 229 static void iwn_notif_intr(struct iwn_softc *); 230 static void iwn_wakeup_intr(struct iwn_softc *); 231 static void iwn_rftoggle_intr(struct iwn_softc *); 232 static void iwn_fatal_intr(struct iwn_softc *); 233 static void iwn_intr(void *); 234 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 235 uint16_t); 236 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 237 uint16_t); 238 #ifdef notyet 239 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 240 #endif 241 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 242 struct ieee80211_node *); 243 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 244 struct ieee80211_node *, 245 const struct ieee80211_bpf_params *params); 246 static void iwn_xmit_task(void *arg0, int pending); 247 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 248 const struct ieee80211_bpf_params *); 249 static int iwn_transmit(struct ieee80211com *, struct mbuf *); 250 static void iwn_watchdog(void *); 251 static int iwn_ioctl(struct ieee80211com *, u_long , void *); 252 static void iwn_parent(struct ieee80211com *); 253 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 254 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 255 int); 256 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 257 int); 258 static int iwn_set_link_quality(struct iwn_softc *, 259 struct ieee80211_node *); 260 static int iwn_add_broadcast_node(struct iwn_softc *, int); 261 static int iwn_updateedca(struct ieee80211com *); 262 static void iwn_update_mcast(struct ieee80211com *); 263 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 264 static int iwn_set_critical_temp(struct iwn_softc *); 265 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 266 static void iwn4965_power_calibration(struct iwn_softc *, int); 267 static int iwn4965_set_txpower(struct iwn_softc *, 268 struct ieee80211_channel *, int); 269 static int iwn5000_set_txpower(struct iwn_softc *, 270 struct ieee80211_channel *, int); 271 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 272 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 273 static int iwn_get_noise(const struct iwn_rx_general_stats *); 274 static int iwn4965_get_temperature(struct iwn_softc *); 275 static int iwn5000_get_temperature(struct iwn_softc *); 276 static int iwn_init_sensitivity(struct iwn_softc *); 277 static void iwn_collect_noise(struct iwn_softc *, 278 const struct iwn_rx_general_stats *); 279 static int iwn4965_init_gains(struct iwn_softc *); 280 static int iwn5000_init_gains(struct iwn_softc *); 281 static int iwn4965_set_gains(struct iwn_softc *); 282 static int iwn5000_set_gains(struct iwn_softc *); 283 static void iwn_tune_sensitivity(struct iwn_softc *, 284 const struct iwn_rx_stats *); 285 static void iwn_save_stats_counters(struct iwn_softc *, 286 const struct iwn_stats *); 287 static int iwn_send_sensitivity(struct iwn_softc *); 288 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *); 289 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 290 static int iwn_send_btcoex(struct iwn_softc *); 291 static int iwn_send_advanced_btcoex(struct iwn_softc *); 292 static int iwn5000_runtime_calib(struct iwn_softc *); 293 static int iwn_config(struct iwn_softc *); 294 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *, 295 struct ieee80211_scan_state *, struct ieee80211_channel *); 296 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 297 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 298 static int iwn_ampdu_rx_start(struct ieee80211_node *, 299 struct ieee80211_rx_ampdu *, int, int, int); 300 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 301 struct ieee80211_rx_ampdu *); 302 static int iwn_addba_request(struct ieee80211_node *, 303 struct ieee80211_tx_ampdu *, int, int, int); 304 static int iwn_addba_response(struct ieee80211_node *, 305 struct ieee80211_tx_ampdu *, int, int, int); 306 static int iwn_ampdu_tx_start(struct ieee80211com *, 307 struct ieee80211_node *, uint8_t); 308 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 309 struct ieee80211_tx_ampdu *); 310 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 311 struct ieee80211_node *, int, uint8_t, uint16_t); 312 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 313 uint8_t, uint16_t); 314 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 315 struct ieee80211_node *, int, uint8_t, uint16_t); 316 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 317 uint8_t, uint16_t); 318 static int iwn5000_query_calibration(struct iwn_softc *); 319 static int iwn5000_send_calibration(struct iwn_softc *); 320 static int iwn5000_send_wimax_coex(struct iwn_softc *); 321 static int iwn5000_crystal_calib(struct iwn_softc *); 322 static int iwn5000_temp_offset_calib(struct iwn_softc *); 323 static int iwn5000_temp_offset_calibv2(struct iwn_softc *); 324 static int iwn4965_post_alive(struct iwn_softc *); 325 static int iwn5000_post_alive(struct iwn_softc *); 326 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 327 int); 328 static int iwn4965_load_firmware(struct iwn_softc *); 329 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 330 const uint8_t *, int); 331 static int iwn5000_load_firmware(struct iwn_softc *); 332 static int iwn_read_firmware_leg(struct iwn_softc *, 333 struct iwn_fw_info *); 334 static int iwn_read_firmware_tlv(struct iwn_softc *, 335 struct iwn_fw_info *, uint16_t); 336 static int iwn_read_firmware(struct iwn_softc *); 337 static void iwn_unload_firmware(struct iwn_softc *); 338 static int iwn_clock_wait(struct iwn_softc *); 339 static int iwn_apm_init(struct iwn_softc *); 340 static void iwn_apm_stop_master(struct iwn_softc *); 341 static void iwn_apm_stop(struct iwn_softc *); 342 static int iwn4965_nic_config(struct iwn_softc *); 343 static int iwn5000_nic_config(struct iwn_softc *); 344 static int iwn_hw_prepare(struct iwn_softc *); 345 static int iwn_hw_init(struct iwn_softc *); 346 static void iwn_hw_stop(struct iwn_softc *); 347 static void iwn_radio_on(void *, int); 348 static void iwn_radio_off(void *, int); 349 static void iwn_panicked(void *, int); 350 static void iwn_init_locked(struct iwn_softc *); 351 static void iwn_init(struct iwn_softc *); 352 static void iwn_stop_locked(struct iwn_softc *); 353 static void iwn_stop(struct iwn_softc *); 354 static void iwn_scan_start(struct ieee80211com *); 355 static void iwn_scan_end(struct ieee80211com *); 356 static void iwn_set_channel(struct ieee80211com *); 357 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 358 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 359 #ifdef IWN_DEBUG 360 static char *iwn_get_csr_string(int); 361 static void iwn_debug_register(struct iwn_softc *); 362 #endif 363 364 static device_method_t iwn_methods[] = { 365 /* Device interface */ 366 DEVMETHOD(device_probe, iwn_probe), 367 DEVMETHOD(device_attach, iwn_attach), 368 DEVMETHOD(device_detach, iwn_detach), 369 DEVMETHOD(device_shutdown, iwn_shutdown), 370 DEVMETHOD(device_suspend, iwn_suspend), 371 DEVMETHOD(device_resume, iwn_resume), 372 373 DEVMETHOD_END 374 }; 375 376 static driver_t iwn_driver = { 377 "iwn", 378 iwn_methods, 379 sizeof(struct iwn_softc) 380 }; 381 static devclass_t iwn_devclass; 382 383 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL); 384 385 MODULE_VERSION(iwn, 1); 386 387 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 388 MODULE_DEPEND(iwn, pci, 1, 1, 1); 389 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 390 391 static d_ioctl_t iwn_cdev_ioctl; 392 static d_open_t iwn_cdev_open; 393 static d_close_t iwn_cdev_close; 394 395 static struct dev_ops iwn_cdevsw = { 396 #if defined(__DragonFly__) 397 /* none */ 398 { "iwn", 0, 0 }, 399 #else 400 .d_version = D_VERSION, 401 .d_flags = 0, 402 #endif 403 .d_open = iwn_cdev_open, 404 .d_close = iwn_cdev_close, 405 .d_ioctl = iwn_cdev_ioctl, 406 #if defined(__DragonFly__) 407 /* none */ 408 #else 409 .d_name = "iwn", 410 #endif 411 }; 412 413 static int 414 iwn_probe(device_t dev) 415 { 416 const struct iwn_ident *ident; 417 418 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 419 if (pci_get_vendor(dev) == ident->vendor && 420 pci_get_device(dev) == ident->device) { 421 device_set_desc(dev, ident->name); 422 return (BUS_PROBE_DEFAULT); 423 } 424 } 425 return ENXIO; 426 } 427 428 static int 429 iwn_is_3stream_device(struct iwn_softc *sc) 430 { 431 /* XXX for now only 5300, until the 5350 can be tested */ 432 if (sc->hw_type == IWN_HW_REV_TYPE_5300) 433 return (1); 434 return (0); 435 } 436 437 static int 438 iwn_attach(device_t dev) 439 { 440 struct iwn_softc *sc = device_get_softc(dev); 441 struct ieee80211com *ic; 442 int i, error, rid; 443 #if defined(__DragonFly__) 444 int irq_flags; 445 #endif 446 447 sc->sc_dev = dev; 448 449 #ifdef IWN_DEBUG 450 error = resource_int_value(device_get_name(sc->sc_dev), 451 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 452 if (error != 0) 453 sc->sc_debug = 0; 454 #else 455 sc->sc_debug = 0; 456 #endif 457 458 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 459 460 /* 461 * Get the offset of the PCI Express Capability Structure in PCI 462 * Configuration Space. 463 */ 464 #if defined(__DragonFly__) 465 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 466 #else 467 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 468 #endif 469 if (error != 0) { 470 device_printf(dev, "PCIe capability structure not found!\n"); 471 return error; 472 } 473 474 /* Clear device-specific "PCI retry timeout" register (41h). */ 475 pci_write_config(dev, 0x41, 0, 1); 476 477 /* Enable bus-mastering. */ 478 pci_enable_busmaster(dev); 479 480 rid = PCIR_BAR(0); 481 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 482 RF_ACTIVE); 483 if (sc->mem == NULL) { 484 device_printf(dev, "can't map mem space\n"); 485 error = ENOMEM; 486 return error; 487 } 488 sc->sc_st = rman_get_bustag(sc->mem); 489 sc->sc_sh = rman_get_bushandle(sc->mem); 490 491 #if defined(__DragonFly__) 492 pci_alloc_1intr(dev, 1, &rid, &irq_flags); 493 /* Install interrupt handler. */ 494 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, irq_flags); 495 #else 496 i = 1; 497 rid = 0; 498 if (pci_alloc_msi(dev, &i) == 0) 499 rid = 1; 500 /* Install interrupt handler. */ 501 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 502 (rid != 0 ? 0 : RF_SHAREABLE)); 503 #endif 504 if (sc->irq == NULL) { 505 device_printf(dev, "can't map interrupt\n"); 506 error = ENOMEM; 507 goto fail; 508 } 509 510 IWN_LOCK_INIT(sc); 511 512 /* Read hardware revision and attach. */ 513 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 514 & IWN_HW_REV_TYPE_MASK; 515 sc->subdevice_id = pci_get_subdevice(dev); 516 517 /* 518 * 4965 versus 5000 and later have different methods. 519 * Let's set those up first. 520 */ 521 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 522 error = iwn4965_attach(sc, pci_get_device(dev)); 523 else 524 error = iwn5000_attach(sc, pci_get_device(dev)); 525 if (error != 0) { 526 device_printf(dev, "could not attach device, error %d\n", 527 error); 528 goto fail; 529 } 530 531 /* 532 * Next, let's setup the various parameters of each NIC. 533 */ 534 error = iwn_config_specific(sc, pci_get_device(dev)); 535 if (error != 0) { 536 device_printf(dev, "could not attach device, error %d\n", 537 error); 538 goto fail; 539 } 540 541 if ((error = iwn_hw_prepare(sc)) != 0) { 542 device_printf(dev, "hardware not ready, error %d\n", error); 543 goto fail; 544 } 545 546 /* Allocate DMA memory for firmware transfers. */ 547 if ((error = iwn_alloc_fwmem(sc)) != 0) { 548 device_printf(dev, 549 "could not allocate memory for firmware, error %d\n", 550 error); 551 goto fail; 552 } 553 554 /* Allocate "Keep Warm" page. */ 555 if ((error = iwn_alloc_kw(sc)) != 0) { 556 device_printf(dev, 557 "could not allocate keep warm page, error %d\n", error); 558 goto fail; 559 } 560 561 /* Allocate ICT table for 5000 Series. */ 562 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 563 (error = iwn_alloc_ict(sc)) != 0) { 564 device_printf(dev, "could not allocate ICT table, error %d\n", 565 error); 566 goto fail; 567 } 568 569 /* Allocate TX scheduler "rings". */ 570 if ((error = iwn_alloc_sched(sc)) != 0) { 571 device_printf(dev, 572 "could not allocate TX scheduler rings, error %d\n", error); 573 goto fail; 574 } 575 576 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 577 for (i = 0; i < sc->ntxqs; i++) { 578 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 579 device_printf(dev, 580 "could not allocate TX ring %d, error %d\n", i, 581 error); 582 goto fail; 583 } 584 } 585 586 /* Allocate RX ring. */ 587 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 588 device_printf(dev, "could not allocate RX ring, error %d\n", 589 error); 590 goto fail; 591 } 592 593 /* Clear pending interrupts. */ 594 IWN_WRITE(sc, IWN_INT, 0xffffffff); 595 596 ic = &sc->sc_ic; 597 ic->ic_softc = sc; 598 ic->ic_name = device_get_nameunit(dev); 599 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 600 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 601 602 /* Set device capabilities. */ 603 ic->ic_caps = 604 IEEE80211_C_STA /* station mode supported */ 605 | IEEE80211_C_MONITOR /* monitor mode supported */ 606 #if 0 607 | IEEE80211_C_BGSCAN /* background scanning */ 608 #endif 609 | IEEE80211_C_TXPMGT /* tx power management */ 610 | IEEE80211_C_SHSLOT /* short slot time supported */ 611 | IEEE80211_C_WPA 612 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 613 #if 0 614 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 615 #endif 616 | IEEE80211_C_WME /* WME */ 617 | IEEE80211_C_PMGT /* Station-side power mgmt */ 618 ; 619 620 /* Read MAC address, channels, etc from EEPROM. */ 621 if ((error = iwn_read_eeprom(sc, ic->ic_macaddr)) != 0) { 622 device_printf(dev, "could not read EEPROM, error %d\n", 623 error); 624 goto fail; 625 } 626 627 /* Count the number of available chains. */ 628 sc->ntxchains = 629 ((sc->txchainmask >> 2) & 1) + 630 ((sc->txchainmask >> 1) & 1) + 631 ((sc->txchainmask >> 0) & 1); 632 sc->nrxchains = 633 ((sc->rxchainmask >> 2) & 1) + 634 ((sc->rxchainmask >> 1) & 1) + 635 ((sc->rxchainmask >> 0) & 1); 636 if (bootverbose) { 637 #if defined(__DragonFly__) 638 char ethstr[ETHER_ADDRSTRLEN+1]; 639 device_printf(dev, "MIMO %dT%dR, %.4s, address %s\n", 640 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 641 kether_ntoa(ic->ic_macaddr, ethstr)); 642 #else 643 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n", 644 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 645 ic->ic_macaddr, ":"); 646 #endif 647 } 648 649 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 650 ic->ic_rxstream = sc->nrxchains; 651 ic->ic_txstream = sc->ntxchains; 652 653 /* 654 * Some of the 3 antenna devices (ie, the 4965) only supports 655 * 2x2 operation. So correct the number of streams if 656 * it's not a 3-stream device. 657 */ 658 if (! iwn_is_3stream_device(sc)) { 659 if (ic->ic_rxstream > 2) 660 ic->ic_rxstream = 2; 661 if (ic->ic_txstream > 2) 662 ic->ic_txstream = 2; 663 } 664 665 ic->ic_htcaps = 666 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 667 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 668 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 669 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 670 #ifdef notyet 671 | IEEE80211_HTCAP_GREENFIELD 672 #if IWN_RBUF_SIZE == 8192 673 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 674 #else 675 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 676 #endif 677 #endif 678 /* s/w capabilities */ 679 | IEEE80211_HTC_HT /* HT operation */ 680 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 681 #ifdef notyet 682 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 683 #endif 684 ; 685 } 686 687 ieee80211_ifattach(ic); 688 ic->ic_vap_create = iwn_vap_create; 689 ic->ic_ioctl = iwn_ioctl; 690 ic->ic_parent = iwn_parent; 691 ic->ic_vap_delete = iwn_vap_delete; 692 ic->ic_transmit = iwn_transmit; 693 ic->ic_raw_xmit = iwn_raw_xmit; 694 ic->ic_node_alloc = iwn_node_alloc; 695 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 696 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 697 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 698 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 699 sc->sc_addba_request = ic->ic_addba_request; 700 ic->ic_addba_request = iwn_addba_request; 701 sc->sc_addba_response = ic->ic_addba_response; 702 ic->ic_addba_response = iwn_addba_response; 703 sc->sc_addba_stop = ic->ic_addba_stop; 704 ic->ic_addba_stop = iwn_ampdu_tx_stop; 705 ic->ic_newassoc = iwn_newassoc; 706 ic->ic_wme.wme_update = iwn_updateedca; 707 ic->ic_update_mcast = iwn_update_mcast; 708 ic->ic_scan_start = iwn_scan_start; 709 ic->ic_scan_end = iwn_scan_end; 710 ic->ic_set_channel = iwn_set_channel; 711 ic->ic_scan_curchan = iwn_scan_curchan; 712 ic->ic_scan_mindwell = iwn_scan_mindwell; 713 ic->ic_getradiocaps = iwn_getradiocaps; 714 ic->ic_setregdomain = iwn_setregdomain; 715 716 iwn_radiotap_attach(sc); 717 718 #if defined(__DragonFly__) 719 callout_init_lk(&sc->calib_to, &sc->sc_lk); 720 callout_init_lk(&sc->watchdog_to, &sc->sc_lk); 721 #else 722 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 723 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 724 #endif 725 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc); 726 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc); 727 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked, sc); 728 TASK_INIT(&sc->sc_xmit_task, 0, iwn_xmit_task, sc); 729 730 mbufq_init(&sc->sc_xmit_queue, 1024); 731 732 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK, 733 taskqueue_thread_enqueue, &sc->sc_tq); 734 #if defined(__DragonFly__) 735 error = taskqueue_start_threads(&sc->sc_tq, 1, TDPRI_KERN_DAEMON, 736 -1, "iwn_taskq"); 737 #else 738 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwn_taskq"); 739 #endif 740 if (error != 0) { 741 device_printf(dev, "can't start threads, error %d\n", error); 742 goto fail; 743 } 744 745 iwn_sysctlattach(sc); 746 747 /* 748 * Hook our interrupt after all initialization is complete. 749 */ 750 #if defined(__DragonFly__) 751 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE, 752 iwn_intr, sc, &sc->sc_ih, 753 &wlan_global_serializer); 754 #else 755 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 756 NULL, iwn_intr, sc, &sc->sc_ih); 757 #endif 758 if (error != 0) { 759 device_printf(dev, "can't establish interrupt, error %d\n", 760 error); 761 goto fail; 762 } 763 764 #if 0 765 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n", 766 __func__, 767 sizeof(struct iwn_stats), 768 sizeof(struct iwn_stats_bt)); 769 #endif 770 771 if (bootverbose) 772 ieee80211_announce(ic); 773 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 774 775 /* Add debug ioctl right at the end */ 776 sc->sc_cdev = make_dev(&iwn_cdevsw, device_get_unit(dev), 777 UID_ROOT, GID_WHEEL, 0600, "%s", device_get_nameunit(dev)); 778 if (sc->sc_cdev == NULL) { 779 device_printf(dev, "failed to create debug character device\n"); 780 } else { 781 sc->sc_cdev->si_drv1 = sc; 782 } 783 return 0; 784 fail: 785 iwn_detach(dev); 786 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 787 return error; 788 } 789 790 /* 791 * Define specific configuration based on device id and subdevice id 792 * pid : PCI device id 793 */ 794 static int 795 iwn_config_specific(struct iwn_softc *sc, uint16_t pid) 796 { 797 798 switch (pid) { 799 /* 4965 series */ 800 case IWN_DID_4965_1: 801 case IWN_DID_4965_2: 802 case IWN_DID_4965_3: 803 case IWN_DID_4965_4: 804 sc->base_params = &iwn4965_base_params; 805 sc->limits = &iwn4965_sensitivity_limits; 806 sc->fwname = "iwn4965fw"; 807 /* Override chains masks, ROM is known to be broken. */ 808 sc->txchainmask = IWN_ANT_AB; 809 sc->rxchainmask = IWN_ANT_ABC; 810 /* Enable normal btcoex */ 811 sc->sc_flags |= IWN_FLAG_BTCOEX; 812 break; 813 /* 1000 Series */ 814 case IWN_DID_1000_1: 815 case IWN_DID_1000_2: 816 switch(sc->subdevice_id) { 817 case IWN_SDID_1000_1: 818 case IWN_SDID_1000_2: 819 case IWN_SDID_1000_3: 820 case IWN_SDID_1000_4: 821 case IWN_SDID_1000_5: 822 case IWN_SDID_1000_6: 823 case IWN_SDID_1000_7: 824 case IWN_SDID_1000_8: 825 case IWN_SDID_1000_9: 826 case IWN_SDID_1000_10: 827 case IWN_SDID_1000_11: 828 case IWN_SDID_1000_12: 829 sc->limits = &iwn1000_sensitivity_limits; 830 sc->base_params = &iwn1000_base_params; 831 sc->fwname = "iwn1000fw"; 832 break; 833 default: 834 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 835 "0x%04x rev %d not supported (subdevice)\n", pid, 836 sc->subdevice_id,sc->hw_type); 837 return ENOTSUP; 838 } 839 break; 840 /* 6x00 Series */ 841 case IWN_DID_6x00_2: 842 case IWN_DID_6x00_4: 843 case IWN_DID_6x00_1: 844 case IWN_DID_6x00_3: 845 sc->fwname = "iwn6000fw"; 846 sc->limits = &iwn6000_sensitivity_limits; 847 switch(sc->subdevice_id) { 848 case IWN_SDID_6x00_1: 849 case IWN_SDID_6x00_2: 850 case IWN_SDID_6x00_8: 851 //iwl6000_3agn_cfg 852 sc->base_params = &iwn_6000_base_params; 853 break; 854 case IWN_SDID_6x00_3: 855 case IWN_SDID_6x00_6: 856 case IWN_SDID_6x00_9: 857 ////iwl6000i_2agn 858 case IWN_SDID_6x00_4: 859 case IWN_SDID_6x00_7: 860 case IWN_SDID_6x00_10: 861 //iwl6000i_2abg_cfg 862 case IWN_SDID_6x00_5: 863 //iwl6000i_2bg_cfg 864 sc->base_params = &iwn_6000i_base_params; 865 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 866 sc->txchainmask = IWN_ANT_BC; 867 sc->rxchainmask = IWN_ANT_BC; 868 break; 869 default: 870 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 871 "0x%04x rev %d not supported (subdevice)\n", pid, 872 sc->subdevice_id,sc->hw_type); 873 return ENOTSUP; 874 } 875 break; 876 /* 6x05 Series */ 877 case IWN_DID_6x05_1: 878 case IWN_DID_6x05_2: 879 switch(sc->subdevice_id) { 880 case IWN_SDID_6x05_1: 881 case IWN_SDID_6x05_4: 882 case IWN_SDID_6x05_6: 883 //iwl6005_2agn_cfg 884 case IWN_SDID_6x05_2: 885 case IWN_SDID_6x05_5: 886 case IWN_SDID_6x05_7: 887 //iwl6005_2abg_cfg 888 case IWN_SDID_6x05_3: 889 //iwl6005_2bg_cfg 890 case IWN_SDID_6x05_8: 891 case IWN_SDID_6x05_9: 892 //iwl6005_2agn_sff_cfg 893 case IWN_SDID_6x05_10: 894 //iwl6005_2agn_d_cfg 895 case IWN_SDID_6x05_11: 896 //iwl6005_2agn_mow1_cfg 897 case IWN_SDID_6x05_12: 898 //iwl6005_2agn_mow2_cfg 899 sc->fwname = "iwn6000g2afw"; 900 sc->limits = &iwn6000_sensitivity_limits; 901 sc->base_params = &iwn_6000g2_base_params; 902 break; 903 default: 904 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 905 "0x%04x rev %d not supported (subdevice)\n", pid, 906 sc->subdevice_id,sc->hw_type); 907 return ENOTSUP; 908 } 909 break; 910 /* 6x35 Series */ 911 case IWN_DID_6035_1: 912 case IWN_DID_6035_2: 913 switch(sc->subdevice_id) { 914 case IWN_SDID_6035_1: 915 case IWN_SDID_6035_2: 916 case IWN_SDID_6035_3: 917 case IWN_SDID_6035_4: 918 case IWN_SDID_6035_5: 919 sc->fwname = "iwn6000g2bfw"; 920 sc->limits = &iwn6235_sensitivity_limits; 921 sc->base_params = &iwn_6235_base_params; 922 break; 923 default: 924 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 925 "0x%04x rev %d not supported (subdevice)\n", pid, 926 sc->subdevice_id,sc->hw_type); 927 return ENOTSUP; 928 } 929 break; 930 /* 6x50 WiFi/WiMax Series */ 931 case IWN_DID_6050_1: 932 case IWN_DID_6050_2: 933 switch(sc->subdevice_id) { 934 case IWN_SDID_6050_1: 935 case IWN_SDID_6050_3: 936 case IWN_SDID_6050_5: 937 //iwl6050_2agn_cfg 938 case IWN_SDID_6050_2: 939 case IWN_SDID_6050_4: 940 case IWN_SDID_6050_6: 941 //iwl6050_2abg_cfg 942 sc->fwname = "iwn6050fw"; 943 sc->txchainmask = IWN_ANT_AB; 944 sc->rxchainmask = IWN_ANT_AB; 945 sc->limits = &iwn6000_sensitivity_limits; 946 sc->base_params = &iwn_6050_base_params; 947 break; 948 default: 949 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 950 "0x%04x rev %d not supported (subdevice)\n", pid, 951 sc->subdevice_id,sc->hw_type); 952 return ENOTSUP; 953 } 954 break; 955 /* 6150 WiFi/WiMax Series */ 956 case IWN_DID_6150_1: 957 case IWN_DID_6150_2: 958 switch(sc->subdevice_id) { 959 case IWN_SDID_6150_1: 960 case IWN_SDID_6150_3: 961 case IWN_SDID_6150_5: 962 // iwl6150_bgn_cfg 963 case IWN_SDID_6150_2: 964 case IWN_SDID_6150_4: 965 case IWN_SDID_6150_6: 966 //iwl6150_bg_cfg 967 sc->fwname = "iwn6050fw"; 968 sc->limits = &iwn6000_sensitivity_limits; 969 sc->base_params = &iwn_6150_base_params; 970 break; 971 default: 972 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 973 "0x%04x rev %d not supported (subdevice)\n", pid, 974 sc->subdevice_id,sc->hw_type); 975 return ENOTSUP; 976 } 977 break; 978 /* 6030 Series and 1030 Series */ 979 case IWN_DID_x030_1: 980 case IWN_DID_x030_2: 981 case IWN_DID_x030_3: 982 case IWN_DID_x030_4: 983 switch(sc->subdevice_id) { 984 case IWN_SDID_x030_1: 985 case IWN_SDID_x030_3: 986 case IWN_SDID_x030_5: 987 // iwl1030_bgn_cfg 988 case IWN_SDID_x030_2: 989 case IWN_SDID_x030_4: 990 case IWN_SDID_x030_6: 991 //iwl1030_bg_cfg 992 case IWN_SDID_x030_7: 993 case IWN_SDID_x030_10: 994 case IWN_SDID_x030_14: 995 //iwl6030_2agn_cfg 996 case IWN_SDID_x030_8: 997 case IWN_SDID_x030_11: 998 case IWN_SDID_x030_15: 999 // iwl6030_2bgn_cfg 1000 case IWN_SDID_x030_9: 1001 case IWN_SDID_x030_12: 1002 case IWN_SDID_x030_16: 1003 // iwl6030_2abg_cfg 1004 case IWN_SDID_x030_13: 1005 //iwl6030_2bg_cfg 1006 sc->fwname = "iwn6000g2bfw"; 1007 sc->limits = &iwn6000_sensitivity_limits; 1008 sc->base_params = &iwn_6000g2b_base_params; 1009 break; 1010 default: 1011 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1012 "0x%04x rev %d not supported (subdevice)\n", pid, 1013 sc->subdevice_id,sc->hw_type); 1014 return ENOTSUP; 1015 } 1016 break; 1017 /* 130 Series WiFi */ 1018 /* XXX: This series will need adjustment for rate. 1019 * see rx_with_siso_diversity in linux kernel 1020 */ 1021 case IWN_DID_130_1: 1022 case IWN_DID_130_2: 1023 switch(sc->subdevice_id) { 1024 case IWN_SDID_130_1: 1025 case IWN_SDID_130_3: 1026 case IWN_SDID_130_5: 1027 //iwl130_bgn_cfg 1028 case IWN_SDID_130_2: 1029 case IWN_SDID_130_4: 1030 case IWN_SDID_130_6: 1031 //iwl130_bg_cfg 1032 sc->fwname = "iwn6000g2bfw"; 1033 sc->limits = &iwn6000_sensitivity_limits; 1034 sc->base_params = &iwn_6000g2b_base_params; 1035 break; 1036 default: 1037 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1038 "0x%04x rev %d not supported (subdevice)\n", pid, 1039 sc->subdevice_id,sc->hw_type); 1040 return ENOTSUP; 1041 } 1042 break; 1043 /* 100 Series WiFi */ 1044 case IWN_DID_100_1: 1045 case IWN_DID_100_2: 1046 switch(sc->subdevice_id) { 1047 case IWN_SDID_100_1: 1048 case IWN_SDID_100_2: 1049 case IWN_SDID_100_3: 1050 case IWN_SDID_100_4: 1051 case IWN_SDID_100_5: 1052 case IWN_SDID_100_6: 1053 sc->limits = &iwn1000_sensitivity_limits; 1054 sc->base_params = &iwn1000_base_params; 1055 sc->fwname = "iwn100fw"; 1056 break; 1057 default: 1058 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1059 "0x%04x rev %d not supported (subdevice)\n", pid, 1060 sc->subdevice_id,sc->hw_type); 1061 return ENOTSUP; 1062 } 1063 break; 1064 1065 /* 105 Series */ 1066 /* XXX: This series will need adjustment for rate. 1067 * see rx_with_siso_diversity in linux kernel 1068 */ 1069 case IWN_DID_105_1: 1070 case IWN_DID_105_2: 1071 switch(sc->subdevice_id) { 1072 case IWN_SDID_105_1: 1073 case IWN_SDID_105_2: 1074 case IWN_SDID_105_3: 1075 //iwl105_bgn_cfg 1076 case IWN_SDID_105_4: 1077 //iwl105_bgn_d_cfg 1078 sc->limits = &iwn2030_sensitivity_limits; 1079 sc->base_params = &iwn2000_base_params; 1080 sc->fwname = "iwn105fw"; 1081 break; 1082 default: 1083 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1084 "0x%04x rev %d not supported (subdevice)\n", pid, 1085 sc->subdevice_id,sc->hw_type); 1086 return ENOTSUP; 1087 } 1088 break; 1089 1090 /* 135 Series */ 1091 /* XXX: This series will need adjustment for rate. 1092 * see rx_with_siso_diversity in linux kernel 1093 */ 1094 case IWN_DID_135_1: 1095 case IWN_DID_135_2: 1096 switch(sc->subdevice_id) { 1097 case IWN_SDID_135_1: 1098 case IWN_SDID_135_2: 1099 case IWN_SDID_135_3: 1100 sc->limits = &iwn2030_sensitivity_limits; 1101 sc->base_params = &iwn2030_base_params; 1102 sc->fwname = "iwn135fw"; 1103 break; 1104 default: 1105 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1106 "0x%04x rev %d not supported (subdevice)\n", pid, 1107 sc->subdevice_id,sc->hw_type); 1108 return ENOTSUP; 1109 } 1110 break; 1111 1112 /* 2x00 Series */ 1113 case IWN_DID_2x00_1: 1114 case IWN_DID_2x00_2: 1115 switch(sc->subdevice_id) { 1116 case IWN_SDID_2x00_1: 1117 case IWN_SDID_2x00_2: 1118 case IWN_SDID_2x00_3: 1119 //iwl2000_2bgn_cfg 1120 case IWN_SDID_2x00_4: 1121 //iwl2000_2bgn_d_cfg 1122 sc->limits = &iwn2030_sensitivity_limits; 1123 sc->base_params = &iwn2000_base_params; 1124 sc->fwname = "iwn2000fw"; 1125 break; 1126 default: 1127 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1128 "0x%04x rev %d not supported (subdevice) \n", 1129 pid, sc->subdevice_id, sc->hw_type); 1130 return ENOTSUP; 1131 } 1132 break; 1133 /* 2x30 Series */ 1134 case IWN_DID_2x30_1: 1135 case IWN_DID_2x30_2: 1136 switch(sc->subdevice_id) { 1137 case IWN_SDID_2x30_1: 1138 case IWN_SDID_2x30_3: 1139 case IWN_SDID_2x30_5: 1140 //iwl100_bgn_cfg 1141 case IWN_SDID_2x30_2: 1142 case IWN_SDID_2x30_4: 1143 case IWN_SDID_2x30_6: 1144 //iwl100_bg_cfg 1145 sc->limits = &iwn2030_sensitivity_limits; 1146 sc->base_params = &iwn2030_base_params; 1147 sc->fwname = "iwn2030fw"; 1148 break; 1149 default: 1150 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1151 "0x%04x rev %d not supported (subdevice)\n", pid, 1152 sc->subdevice_id,sc->hw_type); 1153 return ENOTSUP; 1154 } 1155 break; 1156 /* 5x00 Series */ 1157 case IWN_DID_5x00_1: 1158 case IWN_DID_5x00_2: 1159 case IWN_DID_5x00_3: 1160 case IWN_DID_5x00_4: 1161 sc->limits = &iwn5000_sensitivity_limits; 1162 sc->base_params = &iwn5000_base_params; 1163 sc->fwname = "iwn5000fw"; 1164 switch(sc->subdevice_id) { 1165 case IWN_SDID_5x00_1: 1166 case IWN_SDID_5x00_2: 1167 case IWN_SDID_5x00_3: 1168 case IWN_SDID_5x00_4: 1169 case IWN_SDID_5x00_9: 1170 case IWN_SDID_5x00_10: 1171 case IWN_SDID_5x00_11: 1172 case IWN_SDID_5x00_12: 1173 case IWN_SDID_5x00_17: 1174 case IWN_SDID_5x00_18: 1175 case IWN_SDID_5x00_19: 1176 case IWN_SDID_5x00_20: 1177 //iwl5100_agn_cfg 1178 sc->txchainmask = IWN_ANT_B; 1179 sc->rxchainmask = IWN_ANT_AB; 1180 break; 1181 case IWN_SDID_5x00_5: 1182 case IWN_SDID_5x00_6: 1183 case IWN_SDID_5x00_13: 1184 case IWN_SDID_5x00_14: 1185 case IWN_SDID_5x00_21: 1186 case IWN_SDID_5x00_22: 1187 //iwl5100_bgn_cfg 1188 sc->txchainmask = IWN_ANT_B; 1189 sc->rxchainmask = IWN_ANT_AB; 1190 break; 1191 case IWN_SDID_5x00_7: 1192 case IWN_SDID_5x00_8: 1193 case IWN_SDID_5x00_15: 1194 case IWN_SDID_5x00_16: 1195 case IWN_SDID_5x00_23: 1196 case IWN_SDID_5x00_24: 1197 //iwl5100_abg_cfg 1198 sc->txchainmask = IWN_ANT_B; 1199 sc->rxchainmask = IWN_ANT_AB; 1200 break; 1201 case IWN_SDID_5x00_25: 1202 case IWN_SDID_5x00_26: 1203 case IWN_SDID_5x00_27: 1204 case IWN_SDID_5x00_28: 1205 case IWN_SDID_5x00_29: 1206 case IWN_SDID_5x00_30: 1207 case IWN_SDID_5x00_31: 1208 case IWN_SDID_5x00_32: 1209 case IWN_SDID_5x00_33: 1210 case IWN_SDID_5x00_34: 1211 case IWN_SDID_5x00_35: 1212 case IWN_SDID_5x00_36: 1213 //iwl5300_agn_cfg 1214 sc->txchainmask = IWN_ANT_ABC; 1215 sc->rxchainmask = IWN_ANT_ABC; 1216 break; 1217 default: 1218 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1219 "0x%04x rev %d not supported (subdevice)\n", pid, 1220 sc->subdevice_id,sc->hw_type); 1221 return ENOTSUP; 1222 } 1223 break; 1224 /* 5x50 Series */ 1225 case IWN_DID_5x50_1: 1226 case IWN_DID_5x50_2: 1227 case IWN_DID_5x50_3: 1228 case IWN_DID_5x50_4: 1229 sc->limits = &iwn5000_sensitivity_limits; 1230 sc->base_params = &iwn5000_base_params; 1231 sc->fwname = "iwn5000fw"; 1232 switch(sc->subdevice_id) { 1233 case IWN_SDID_5x50_1: 1234 case IWN_SDID_5x50_2: 1235 case IWN_SDID_5x50_3: 1236 //iwl5350_agn_cfg 1237 sc->limits = &iwn5000_sensitivity_limits; 1238 sc->base_params = &iwn5000_base_params; 1239 sc->fwname = "iwn5000fw"; 1240 break; 1241 case IWN_SDID_5x50_4: 1242 case IWN_SDID_5x50_5: 1243 case IWN_SDID_5x50_8: 1244 case IWN_SDID_5x50_9: 1245 case IWN_SDID_5x50_10: 1246 case IWN_SDID_5x50_11: 1247 //iwl5150_agn_cfg 1248 case IWN_SDID_5x50_6: 1249 case IWN_SDID_5x50_7: 1250 case IWN_SDID_5x50_12: 1251 case IWN_SDID_5x50_13: 1252 //iwl5150_abg_cfg 1253 sc->limits = &iwn5000_sensitivity_limits; 1254 sc->fwname = "iwn5150fw"; 1255 sc->base_params = &iwn_5x50_base_params; 1256 break; 1257 default: 1258 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1259 "0x%04x rev %d not supported (subdevice)\n", pid, 1260 sc->subdevice_id,sc->hw_type); 1261 return ENOTSUP; 1262 } 1263 break; 1264 default: 1265 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x" 1266 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id, 1267 sc->hw_type); 1268 return ENOTSUP; 1269 } 1270 return 0; 1271 } 1272 1273 static int 1274 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 1275 { 1276 struct iwn_ops *ops = &sc->ops; 1277 1278 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1279 ops->load_firmware = iwn4965_load_firmware; 1280 ops->read_eeprom = iwn4965_read_eeprom; 1281 ops->post_alive = iwn4965_post_alive; 1282 ops->nic_config = iwn4965_nic_config; 1283 ops->update_sched = iwn4965_update_sched; 1284 ops->get_temperature = iwn4965_get_temperature; 1285 ops->get_rssi = iwn4965_get_rssi; 1286 ops->set_txpower = iwn4965_set_txpower; 1287 ops->init_gains = iwn4965_init_gains; 1288 ops->set_gains = iwn4965_set_gains; 1289 ops->add_node = iwn4965_add_node; 1290 ops->tx_done = iwn4965_tx_done; 1291 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 1292 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 1293 sc->ntxqs = IWN4965_NTXQUEUES; 1294 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 1295 sc->ndmachnls = IWN4965_NDMACHNLS; 1296 sc->broadcast_id = IWN4965_ID_BROADCAST; 1297 sc->rxonsz = IWN4965_RXONSZ; 1298 sc->schedsz = IWN4965_SCHEDSZ; 1299 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 1300 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 1301 sc->fwsz = IWN4965_FWSZ; 1302 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 1303 sc->limits = &iwn4965_sensitivity_limits; 1304 sc->fwname = "iwn4965fw"; 1305 /* Override chains masks, ROM is known to be broken. */ 1306 sc->txchainmask = IWN_ANT_AB; 1307 sc->rxchainmask = IWN_ANT_ABC; 1308 /* Enable normal btcoex */ 1309 sc->sc_flags |= IWN_FLAG_BTCOEX; 1310 1311 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1312 1313 return 0; 1314 } 1315 1316 static int 1317 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 1318 { 1319 struct iwn_ops *ops = &sc->ops; 1320 1321 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1322 1323 ops->load_firmware = iwn5000_load_firmware; 1324 ops->read_eeprom = iwn5000_read_eeprom; 1325 ops->post_alive = iwn5000_post_alive; 1326 ops->nic_config = iwn5000_nic_config; 1327 ops->update_sched = iwn5000_update_sched; 1328 ops->get_temperature = iwn5000_get_temperature; 1329 ops->get_rssi = iwn5000_get_rssi; 1330 ops->set_txpower = iwn5000_set_txpower; 1331 ops->init_gains = iwn5000_init_gains; 1332 ops->set_gains = iwn5000_set_gains; 1333 ops->add_node = iwn5000_add_node; 1334 ops->tx_done = iwn5000_tx_done; 1335 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 1336 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 1337 sc->ntxqs = IWN5000_NTXQUEUES; 1338 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 1339 sc->ndmachnls = IWN5000_NDMACHNLS; 1340 sc->broadcast_id = IWN5000_ID_BROADCAST; 1341 sc->rxonsz = IWN5000_RXONSZ; 1342 sc->schedsz = IWN5000_SCHEDSZ; 1343 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 1344 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 1345 sc->fwsz = IWN5000_FWSZ; 1346 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 1347 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 1348 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 1349 1350 return 0; 1351 } 1352 1353 /* 1354 * Attach the interface to 802.11 radiotap. 1355 */ 1356 static void 1357 iwn_radiotap_attach(struct iwn_softc *sc) 1358 { 1359 1360 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1361 ieee80211_radiotap_attach(&sc->sc_ic, 1362 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 1363 IWN_TX_RADIOTAP_PRESENT, 1364 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 1365 IWN_RX_RADIOTAP_PRESENT); 1366 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1367 } 1368 1369 static void 1370 iwn_sysctlattach(struct iwn_softc *sc) 1371 { 1372 #ifdef IWN_DEBUG 1373 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 1374 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 1375 1376 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1377 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 1378 "control debugging printfs"); 1379 #endif 1380 } 1381 1382 static struct ieee80211vap * 1383 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1384 enum ieee80211_opmode opmode, int flags, 1385 const uint8_t bssid[IEEE80211_ADDR_LEN], 1386 const uint8_t mac[IEEE80211_ADDR_LEN]) 1387 { 1388 struct iwn_softc *sc = ic->ic_softc; 1389 struct iwn_vap *ivp; 1390 struct ieee80211vap *vap; 1391 1392 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1393 return NULL; 1394 1395 ivp = kmalloc(sizeof(struct iwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1396 vap = &ivp->iv_vap; 1397 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1398 ivp->ctx = IWN_RXON_BSS_CTX; 1399 vap->iv_bmissthreshold = 10; /* override default */ 1400 /* Override with driver methods. */ 1401 ivp->iv_newstate = vap->iv_newstate; 1402 vap->iv_newstate = iwn_newstate; 1403 sc->ivap[IWN_RXON_BSS_CTX] = vap; 1404 1405 ieee80211_ratectl_init(vap); 1406 /* Complete setup. */ 1407 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status, 1408 mac); 1409 ic->ic_opmode = opmode; 1410 return vap; 1411 } 1412 1413 static void 1414 iwn_vap_delete(struct ieee80211vap *vap) 1415 { 1416 struct iwn_vap *ivp = IWN_VAP(vap); 1417 1418 ieee80211_ratectl_deinit(vap); 1419 ieee80211_vap_detach(vap); 1420 kfree(ivp, M_80211_VAP); 1421 } 1422 1423 static void 1424 iwn_xmit_queue_drain(struct iwn_softc *sc) 1425 { 1426 struct mbuf *m; 1427 struct ieee80211_node *ni; 1428 1429 IWN_LOCK_ASSERT(sc); 1430 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 1431 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1432 ieee80211_free_node(ni); 1433 m_freem(m); 1434 } 1435 } 1436 1437 static int 1438 iwn_xmit_queue_enqueue(struct iwn_softc *sc, struct mbuf *m) 1439 { 1440 1441 IWN_LOCK_ASSERT(sc); 1442 return (mbufq_enqueue(&sc->sc_xmit_queue, m)); 1443 } 1444 1445 static int 1446 iwn_detach(device_t dev) 1447 { 1448 struct iwn_softc *sc = device_get_softc(dev); 1449 int qid; 1450 1451 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1452 1453 if (sc->sc_ic.ic_softc != NULL) { 1454 /* Free the mbuf queue and node references */ 1455 IWN_LOCK(sc); 1456 iwn_xmit_queue_drain(sc); 1457 IWN_UNLOCK(sc); 1458 1459 ieee80211_draintask(&sc->sc_ic, &sc->sc_radioon_task); 1460 ieee80211_draintask(&sc->sc_ic, &sc->sc_radiooff_task); 1461 iwn_stop(sc); 1462 1463 #if defined(__DragonFly__) 1464 /* doesn't exist for DFly, DFly drains tasks on free */ 1465 #else 1466 taskqueue_drain_all(sc->sc_tq); 1467 #endif 1468 taskqueue_free(sc->sc_tq); 1469 1470 callout_drain(&sc->watchdog_to); 1471 callout_drain(&sc->calib_to); 1472 ieee80211_ifdetach(&sc->sc_ic); 1473 } 1474 1475 /* Uninstall interrupt handler. */ 1476 if (sc->irq != NULL) { 1477 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 1478 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 1479 sc->irq); 1480 pci_release_msi(dev); 1481 } 1482 1483 /* Free DMA resources. */ 1484 iwn_free_rx_ring(sc, &sc->rxq); 1485 for (qid = 0; qid < sc->ntxqs; qid++) 1486 iwn_free_tx_ring(sc, &sc->txq[qid]); 1487 iwn_free_sched(sc); 1488 iwn_free_kw(sc); 1489 if (sc->ict != NULL) 1490 iwn_free_ict(sc); 1491 iwn_free_fwmem(sc); 1492 1493 if (sc->mem != NULL) 1494 bus_release_resource(dev, SYS_RES_MEMORY, 1495 rman_get_rid(sc->mem), sc->mem); 1496 1497 if (sc->sc_cdev) { 1498 destroy_dev(sc->sc_cdev); 1499 sc->sc_cdev = NULL; 1500 } 1501 1502 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 1503 IWN_LOCK_DESTROY(sc); 1504 return 0; 1505 } 1506 1507 static int 1508 iwn_shutdown(device_t dev) 1509 { 1510 struct iwn_softc *sc = device_get_softc(dev); 1511 1512 iwn_stop(sc); 1513 return 0; 1514 } 1515 1516 static int 1517 iwn_suspend(device_t dev) 1518 { 1519 struct iwn_softc *sc = device_get_softc(dev); 1520 1521 ieee80211_suspend_all(&sc->sc_ic); 1522 return 0; 1523 } 1524 1525 static int 1526 iwn_resume(device_t dev) 1527 { 1528 struct iwn_softc *sc = device_get_softc(dev); 1529 1530 /* Clear device-specific "PCI retry timeout" register (41h). */ 1531 pci_write_config(dev, 0x41, 0, 1); 1532 1533 ieee80211_resume_all(&sc->sc_ic); 1534 return 0; 1535 } 1536 1537 static int 1538 iwn_nic_lock(struct iwn_softc *sc) 1539 { 1540 int ntries; 1541 1542 /* Request exclusive access to NIC. */ 1543 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1544 1545 /* Spin until we actually get the lock. */ 1546 for (ntries = 0; ntries < 1000; ntries++) { 1547 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1548 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1549 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1550 return 0; 1551 DELAY(10); 1552 } 1553 return ETIMEDOUT; 1554 } 1555 1556 static __inline void 1557 iwn_nic_unlock(struct iwn_softc *sc) 1558 { 1559 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1560 } 1561 1562 static __inline uint32_t 1563 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1564 { 1565 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1566 IWN_BARRIER_READ_WRITE(sc); 1567 return IWN_READ(sc, IWN_PRPH_RDATA); 1568 } 1569 1570 static __inline void 1571 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1572 { 1573 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1574 IWN_BARRIER_WRITE(sc); 1575 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1576 } 1577 1578 static __inline void 1579 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1580 { 1581 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1582 } 1583 1584 static __inline void 1585 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1586 { 1587 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1588 } 1589 1590 static __inline void 1591 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1592 const uint32_t *data, int count) 1593 { 1594 for (; count > 0; count--, data++, addr += 4) 1595 iwn_prph_write(sc, addr, *data); 1596 } 1597 1598 static __inline uint32_t 1599 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1600 { 1601 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1602 IWN_BARRIER_READ_WRITE(sc); 1603 return IWN_READ(sc, IWN_MEM_RDATA); 1604 } 1605 1606 static __inline void 1607 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1608 { 1609 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1610 IWN_BARRIER_WRITE(sc); 1611 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1612 } 1613 1614 static __inline void 1615 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1616 { 1617 uint32_t tmp; 1618 1619 tmp = iwn_mem_read(sc, addr & ~3); 1620 if (addr & 3) 1621 tmp = (tmp & 0x0000ffff) | data << 16; 1622 else 1623 tmp = (tmp & 0xffff0000) | data; 1624 iwn_mem_write(sc, addr & ~3, tmp); 1625 } 1626 1627 static __inline void 1628 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1629 int count) 1630 { 1631 for (; count > 0; count--, addr += 4) 1632 *data++ = iwn_mem_read(sc, addr); 1633 } 1634 1635 static __inline void 1636 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1637 int count) 1638 { 1639 for (; count > 0; count--, addr += 4) 1640 iwn_mem_write(sc, addr, val); 1641 } 1642 1643 static int 1644 iwn_eeprom_lock(struct iwn_softc *sc) 1645 { 1646 int i, ntries; 1647 1648 for (i = 0; i < 100; i++) { 1649 /* Request exclusive access to EEPROM. */ 1650 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1651 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1652 1653 /* Spin until we actually get the lock. */ 1654 for (ntries = 0; ntries < 100; ntries++) { 1655 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1656 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1657 return 0; 1658 DELAY(10); 1659 } 1660 } 1661 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1662 return ETIMEDOUT; 1663 } 1664 1665 static __inline void 1666 iwn_eeprom_unlock(struct iwn_softc *sc) 1667 { 1668 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1669 } 1670 1671 /* 1672 * Initialize access by host to One Time Programmable ROM. 1673 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1674 */ 1675 static int 1676 iwn_init_otprom(struct iwn_softc *sc) 1677 { 1678 uint16_t prev, base, next; 1679 int count, error; 1680 1681 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1682 1683 /* Wait for clock stabilization before accessing prph. */ 1684 if ((error = iwn_clock_wait(sc)) != 0) 1685 return error; 1686 1687 if ((error = iwn_nic_lock(sc)) != 0) 1688 return error; 1689 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1690 DELAY(5); 1691 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1692 iwn_nic_unlock(sc); 1693 1694 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1695 if (sc->base_params->shadow_ram_support) { 1696 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1697 IWN_RESET_LINK_PWR_MGMT_DIS); 1698 } 1699 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1700 /* Clear ECC status. */ 1701 IWN_SETBITS(sc, IWN_OTP_GP, 1702 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1703 1704 /* 1705 * Find the block before last block (contains the EEPROM image) 1706 * for HW without OTP shadow RAM. 1707 */ 1708 if (! sc->base_params->shadow_ram_support) { 1709 /* Switch to absolute addressing mode. */ 1710 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1711 base = prev = 0; 1712 for (count = 0; count < sc->base_params->max_ll_items; 1713 count++) { 1714 error = iwn_read_prom_data(sc, base, &next, 2); 1715 if (error != 0) 1716 return error; 1717 if (next == 0) /* End of linked-list. */ 1718 break; 1719 prev = base; 1720 base = le16toh(next); 1721 } 1722 if (count == 0 || count == sc->base_params->max_ll_items) 1723 return EIO; 1724 /* Skip "next" word. */ 1725 sc->prom_base = prev + 1; 1726 } 1727 1728 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1729 1730 return 0; 1731 } 1732 1733 static int 1734 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1735 { 1736 uint8_t *out = data; 1737 uint32_t val, tmp; 1738 int ntries; 1739 1740 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1741 1742 addr += sc->prom_base; 1743 for (; count > 0; count -= 2, addr++) { 1744 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1745 for (ntries = 0; ntries < 10; ntries++) { 1746 val = IWN_READ(sc, IWN_EEPROM); 1747 if (val & IWN_EEPROM_READ_VALID) 1748 break; 1749 DELAY(5); 1750 } 1751 if (ntries == 10) { 1752 device_printf(sc->sc_dev, 1753 "timeout reading ROM at 0x%x\n", addr); 1754 return ETIMEDOUT; 1755 } 1756 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1757 /* OTPROM, check for ECC errors. */ 1758 tmp = IWN_READ(sc, IWN_OTP_GP); 1759 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1760 device_printf(sc->sc_dev, 1761 "OTPROM ECC error at 0x%x\n", addr); 1762 return EIO; 1763 } 1764 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1765 /* Correctable ECC error, clear bit. */ 1766 IWN_SETBITS(sc, IWN_OTP_GP, 1767 IWN_OTP_GP_ECC_CORR_STTS); 1768 } 1769 } 1770 *out++ = val >> 16; 1771 if (count > 1) 1772 *out++ = val >> 24; 1773 } 1774 1775 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1776 1777 return 0; 1778 } 1779 1780 static void 1781 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1782 { 1783 if (error != 0) 1784 return; 1785 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1786 *(bus_addr_t *)arg = segs[0].ds_addr; 1787 } 1788 1789 static int 1790 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1791 void **kvap, bus_size_t size, bus_size_t alignment) 1792 { 1793 int error; 1794 1795 dma->tag = NULL; 1796 dma->size = size; 1797 1798 #if defined(__DragonFly__) 1799 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1800 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1801 1, size, 0, &dma->tag); 1802 #else 1803 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment, 1804 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1805 1, size, 0, NULL, NULL, &dma->tag); 1806 #endif 1807 if (error != 0) 1808 goto fail; 1809 1810 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1811 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1812 if (error != 0) 1813 goto fail; 1814 1815 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1816 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1817 if (error != 0) 1818 goto fail; 1819 1820 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1821 1822 if (kvap != NULL) 1823 *kvap = dma->vaddr; 1824 1825 return 0; 1826 1827 fail: iwn_dma_contig_free(dma); 1828 return error; 1829 } 1830 1831 static void 1832 iwn_dma_contig_free(struct iwn_dma_info *dma) 1833 { 1834 if (dma->vaddr != NULL) { 1835 bus_dmamap_sync(dma->tag, dma->map, 1836 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1837 bus_dmamap_unload(dma->tag, dma->map); 1838 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1839 dma->vaddr = NULL; 1840 } 1841 if (dma->tag != NULL) { 1842 bus_dma_tag_destroy(dma->tag); 1843 dma->tag = NULL; 1844 } 1845 } 1846 1847 static int 1848 iwn_alloc_sched(struct iwn_softc *sc) 1849 { 1850 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1851 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1852 sc->schedsz, 1024); 1853 } 1854 1855 static void 1856 iwn_free_sched(struct iwn_softc *sc) 1857 { 1858 iwn_dma_contig_free(&sc->sched_dma); 1859 } 1860 1861 static int 1862 iwn_alloc_kw(struct iwn_softc *sc) 1863 { 1864 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1865 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1866 } 1867 1868 static void 1869 iwn_free_kw(struct iwn_softc *sc) 1870 { 1871 iwn_dma_contig_free(&sc->kw_dma); 1872 } 1873 1874 static int 1875 iwn_alloc_ict(struct iwn_softc *sc) 1876 { 1877 /* ICT table must be aligned on a 4KB boundary. */ 1878 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1879 IWN_ICT_SIZE, 4096); 1880 } 1881 1882 static void 1883 iwn_free_ict(struct iwn_softc *sc) 1884 { 1885 iwn_dma_contig_free(&sc->ict_dma); 1886 } 1887 1888 static int 1889 iwn_alloc_fwmem(struct iwn_softc *sc) 1890 { 1891 /* Must be aligned on a 16-byte boundary. */ 1892 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1893 } 1894 1895 static void 1896 iwn_free_fwmem(struct iwn_softc *sc) 1897 { 1898 iwn_dma_contig_free(&sc->fw_dma); 1899 } 1900 1901 static int 1902 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1903 { 1904 bus_size_t size; 1905 int i, error; 1906 1907 ring->cur = 0; 1908 1909 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1910 1911 /* Allocate RX descriptors (256-byte aligned). */ 1912 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1913 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1914 size, 256); 1915 if (error != 0) { 1916 device_printf(sc->sc_dev, 1917 "%s: could not allocate RX ring DMA memory, error %d\n", 1918 __func__, error); 1919 goto fail; 1920 } 1921 1922 /* Allocate RX status area (16-byte aligned). */ 1923 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1924 sizeof (struct iwn_rx_status), 16); 1925 if (error != 0) { 1926 device_printf(sc->sc_dev, 1927 "%s: could not allocate RX status DMA memory, error %d\n", 1928 __func__, error); 1929 goto fail; 1930 } 1931 1932 /* Create RX buffer DMA tag. */ 1933 #if defined(__DragonFly__) 1934 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1935 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1936 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, 0, &ring->data_dmat); 1937 #else 1938 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 1939 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1940 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, 0, NULL, NULL, &ring->data_dmat); 1941 #endif 1942 if (error != 0) { 1943 device_printf(sc->sc_dev, 1944 "%s: could not create RX buf DMA tag, error %d\n", 1945 __func__, error); 1946 goto fail; 1947 } 1948 1949 /* 1950 * Allocate and map RX buffers. 1951 */ 1952 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1953 struct iwn_rx_data *data = &ring->data[i]; 1954 bus_addr_t paddr; 1955 1956 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1957 if (error != 0) { 1958 device_printf(sc->sc_dev, 1959 "%s: could not create RX buf DMA map, error %d\n", 1960 __func__, error); 1961 goto fail; 1962 } 1963 1964 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 1965 IWN_RBUF_SIZE); 1966 if (data->m == NULL) { 1967 device_printf(sc->sc_dev, 1968 "%s: could not allocate RX mbuf\n", __func__); 1969 error = ENOBUFS; 1970 goto fail; 1971 } 1972 1973 error = bus_dmamap_load(ring->data_dmat, data->map, 1974 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1975 &paddr, BUS_DMA_NOWAIT); 1976 if (error != 0 && error != EFBIG) { 1977 device_printf(sc->sc_dev, 1978 "%s: can't map mbuf, error %d\n", __func__, 1979 error); 1980 goto fail; 1981 } 1982 1983 /* Set physical address of RX buffer (256-byte aligned). */ 1984 ring->desc[i] = htole32(paddr >> 8); 1985 } 1986 1987 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1988 BUS_DMASYNC_PREWRITE); 1989 1990 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1991 1992 return 0; 1993 1994 fail: iwn_free_rx_ring(sc, ring); 1995 1996 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1997 1998 return error; 1999 } 2000 2001 static void 2002 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 2003 { 2004 int ntries; 2005 2006 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 2007 2008 if (iwn_nic_lock(sc) == 0) { 2009 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 2010 for (ntries = 0; ntries < 1000; ntries++) { 2011 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 2012 IWN_FH_RX_STATUS_IDLE) 2013 break; 2014 DELAY(10); 2015 } 2016 iwn_nic_unlock(sc); 2017 } 2018 ring->cur = 0; 2019 sc->last_rx_valid = 0; 2020 } 2021 2022 static void 2023 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 2024 { 2025 int i; 2026 2027 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2028 2029 iwn_dma_contig_free(&ring->desc_dma); 2030 iwn_dma_contig_free(&ring->stat_dma); 2031 2032 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 2033 struct iwn_rx_data *data = &ring->data[i]; 2034 2035 if (data->m != NULL) { 2036 bus_dmamap_sync(ring->data_dmat, data->map, 2037 BUS_DMASYNC_POSTREAD); 2038 bus_dmamap_unload(ring->data_dmat, data->map); 2039 m_freem(data->m); 2040 data->m = NULL; 2041 } 2042 if (data->map != NULL) 2043 bus_dmamap_destroy(ring->data_dmat, data->map); 2044 } 2045 if (ring->data_dmat != NULL) { 2046 bus_dma_tag_destroy(ring->data_dmat); 2047 ring->data_dmat = NULL; 2048 } 2049 } 2050 2051 static int 2052 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 2053 { 2054 bus_addr_t paddr; 2055 bus_size_t size; 2056 int i, error; 2057 2058 ring->qid = qid; 2059 ring->queued = 0; 2060 ring->cur = 0; 2061 2062 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2063 2064 /* Allocate TX descriptors (256-byte aligned). */ 2065 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 2066 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 2067 size, 256); 2068 if (error != 0) { 2069 device_printf(sc->sc_dev, 2070 "%s: could not allocate TX ring DMA memory, error %d\n", 2071 __func__, error); 2072 goto fail; 2073 } 2074 2075 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 2076 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 2077 size, 4); 2078 if (error != 0) { 2079 device_printf(sc->sc_dev, 2080 "%s: could not allocate TX cmd DMA memory, error %d\n", 2081 __func__, error); 2082 goto fail; 2083 } 2084 2085 #if defined(__DragonFly__) 2086 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 2087 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2088 IWN_MAX_SCATTER - 1, MCLBYTES, 0, &ring->data_dmat); 2089 #else 2090 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 2091 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2092 IWN_MAX_SCATTER - 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 2093 #endif 2094 if (error != 0) { 2095 device_printf(sc->sc_dev, 2096 "%s: could not create TX buf DMA tag, error %d\n", 2097 __func__, error); 2098 goto fail; 2099 } 2100 2101 paddr = ring->cmd_dma.paddr; 2102 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2103 struct iwn_tx_data *data = &ring->data[i]; 2104 2105 data->cmd_paddr = paddr; 2106 data->scratch_paddr = paddr + 12; 2107 paddr += sizeof (struct iwn_tx_cmd); 2108 2109 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 2110 if (error != 0) { 2111 device_printf(sc->sc_dev, 2112 "%s: could not create TX buf DMA map, error %d\n", 2113 __func__, error); 2114 goto fail; 2115 } 2116 } 2117 2118 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2119 2120 return 0; 2121 2122 fail: iwn_free_tx_ring(sc, ring); 2123 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2124 return error; 2125 } 2126 2127 static void 2128 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2129 { 2130 int i; 2131 2132 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 2133 2134 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2135 struct iwn_tx_data *data = &ring->data[i]; 2136 2137 if (data->m != NULL) { 2138 bus_dmamap_sync(ring->data_dmat, data->map, 2139 BUS_DMASYNC_POSTWRITE); 2140 bus_dmamap_unload(ring->data_dmat, data->map); 2141 m_freem(data->m); 2142 data->m = NULL; 2143 } 2144 if (data->ni != NULL) { 2145 ieee80211_free_node(data->ni); 2146 data->ni = NULL; 2147 } 2148 } 2149 /* Clear TX descriptors. */ 2150 memset(ring->desc, 0, ring->desc_dma.size); 2151 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2152 BUS_DMASYNC_PREWRITE); 2153 sc->qfullmsk &= ~(1 << ring->qid); 2154 ring->queued = 0; 2155 ring->cur = 0; 2156 } 2157 2158 static void 2159 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2160 { 2161 int i; 2162 2163 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2164 2165 iwn_dma_contig_free(&ring->desc_dma); 2166 iwn_dma_contig_free(&ring->cmd_dma); 2167 2168 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2169 struct iwn_tx_data *data = &ring->data[i]; 2170 2171 if (data->m != NULL) { 2172 bus_dmamap_sync(ring->data_dmat, data->map, 2173 BUS_DMASYNC_POSTWRITE); 2174 bus_dmamap_unload(ring->data_dmat, data->map); 2175 m_freem(data->m); 2176 } 2177 if (data->map != NULL) 2178 bus_dmamap_destroy(ring->data_dmat, data->map); 2179 } 2180 if (ring->data_dmat != NULL) { 2181 bus_dma_tag_destroy(ring->data_dmat); 2182 ring->data_dmat = NULL; 2183 } 2184 } 2185 2186 static void 2187 iwn5000_ict_reset(struct iwn_softc *sc) 2188 { 2189 /* Disable interrupts. */ 2190 IWN_WRITE(sc, IWN_INT_MASK, 0); 2191 2192 /* Reset ICT table. */ 2193 memset(sc->ict, 0, IWN_ICT_SIZE); 2194 sc->ict_cur = 0; 2195 2196 /* Set physical address of ICT table (4KB aligned). */ 2197 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 2198 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 2199 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 2200 2201 /* Enable periodic RX interrupt. */ 2202 sc->int_mask |= IWN_INT_RX_PERIODIC; 2203 /* Switch to ICT interrupt mode in driver. */ 2204 sc->sc_flags |= IWN_FLAG_USE_ICT; 2205 2206 /* Re-enable interrupts. */ 2207 IWN_WRITE(sc, IWN_INT, 0xffffffff); 2208 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2209 } 2210 2211 static int 2212 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2213 { 2214 struct iwn_ops *ops = &sc->ops; 2215 uint16_t val; 2216 int error; 2217 2218 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2219 2220 /* Check whether adapter has an EEPROM or an OTPROM. */ 2221 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 2222 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 2223 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 2224 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 2225 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 2226 2227 /* Adapter has to be powered on for EEPROM access to work. */ 2228 if ((error = iwn_apm_init(sc)) != 0) { 2229 device_printf(sc->sc_dev, 2230 "%s: could not power ON adapter, error %d\n", __func__, 2231 error); 2232 return error; 2233 } 2234 2235 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 2236 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 2237 return EIO; 2238 } 2239 if ((error = iwn_eeprom_lock(sc)) != 0) { 2240 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 2241 __func__, error); 2242 return error; 2243 } 2244 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 2245 if ((error = iwn_init_otprom(sc)) != 0) { 2246 device_printf(sc->sc_dev, 2247 "%s: could not initialize OTPROM, error %d\n", 2248 __func__, error); 2249 return error; 2250 } 2251 } 2252 2253 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 2254 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 2255 /* Check if HT support is bonded out. */ 2256 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 2257 sc->sc_flags |= IWN_FLAG_HAS_11N; 2258 2259 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 2260 sc->rfcfg = le16toh(val); 2261 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 2262 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 2263 if (sc->txchainmask == 0) 2264 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 2265 if (sc->rxchainmask == 0) 2266 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 2267 2268 /* Read MAC address. */ 2269 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 2270 2271 /* Read adapter-specific information from EEPROM. */ 2272 ops->read_eeprom(sc); 2273 2274 iwn_apm_stop(sc); /* Power OFF adapter. */ 2275 2276 iwn_eeprom_unlock(sc); 2277 2278 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2279 2280 return 0; 2281 } 2282 2283 static void 2284 iwn4965_read_eeprom(struct iwn_softc *sc) 2285 { 2286 uint32_t addr; 2287 uint16_t val; 2288 int i; 2289 2290 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2291 2292 /* Read regulatory domain (4 ASCII characters). */ 2293 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 2294 2295 /* Read the list of authorized channels (20MHz & 40MHz). */ 2296 for (i = 0; i < IWN_NBANDS - 1; i++) { 2297 addr = iwn4965_regulatory_bands[i]; 2298 iwn_read_eeprom_channels(sc, i, addr); 2299 } 2300 2301 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 2302 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 2303 sc->maxpwr2GHz = val & 0xff; 2304 sc->maxpwr5GHz = val >> 8; 2305 /* Check that EEPROM values are within valid range. */ 2306 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 2307 sc->maxpwr5GHz = 38; 2308 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 2309 sc->maxpwr2GHz = 38; 2310 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 2311 sc->maxpwr2GHz, sc->maxpwr5GHz); 2312 2313 /* Read samples for each TX power group. */ 2314 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 2315 sizeof sc->bands); 2316 2317 /* Read voltage at which samples were taken. */ 2318 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 2319 sc->eeprom_voltage = (int16_t)le16toh(val); 2320 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 2321 sc->eeprom_voltage); 2322 2323 #ifdef IWN_DEBUG 2324 /* Print samples. */ 2325 if (sc->sc_debug & IWN_DEBUG_ANY) { 2326 for (i = 0; i < IWN_NBANDS - 1; i++) 2327 iwn4965_print_power_group(sc, i); 2328 } 2329 #endif 2330 2331 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2332 } 2333 2334 #ifdef IWN_DEBUG 2335 static void 2336 iwn4965_print_power_group(struct iwn_softc *sc, int i) 2337 { 2338 struct iwn4965_eeprom_band *band = &sc->bands[i]; 2339 struct iwn4965_eeprom_chan_samples *chans = band->chans; 2340 int j, c; 2341 2342 kprintf("===band %d===\n", i); 2343 kprintf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 2344 kprintf("chan1 num=%d\n", chans[0].num); 2345 for (c = 0; c < 2; c++) { 2346 for (j = 0; j < IWN_NSAMPLES; j++) { 2347 kprintf("chain %d, sample %d: temp=%d gain=%d " 2348 "power=%d pa_det=%d\n", c, j, 2349 chans[0].samples[c][j].temp, 2350 chans[0].samples[c][j].gain, 2351 chans[0].samples[c][j].power, 2352 chans[0].samples[c][j].pa_det); 2353 } 2354 } 2355 kprintf("chan2 num=%d\n", chans[1].num); 2356 for (c = 0; c < 2; c++) { 2357 for (j = 0; j < IWN_NSAMPLES; j++) { 2358 kprintf("chain %d, sample %d: temp=%d gain=%d " 2359 "power=%d pa_det=%d\n", c, j, 2360 chans[1].samples[c][j].temp, 2361 chans[1].samples[c][j].gain, 2362 chans[1].samples[c][j].power, 2363 chans[1].samples[c][j].pa_det); 2364 } 2365 } 2366 } 2367 #endif 2368 2369 static void 2370 iwn5000_read_eeprom(struct iwn_softc *sc) 2371 { 2372 struct iwn5000_eeprom_calib_hdr hdr; 2373 int32_t volt; 2374 uint32_t base, addr; 2375 uint16_t val; 2376 int i; 2377 2378 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2379 2380 /* Read regulatory domain (4 ASCII characters). */ 2381 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2382 base = le16toh(val); 2383 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 2384 sc->eeprom_domain, 4); 2385 2386 /* Read the list of authorized channels (20MHz & 40MHz). */ 2387 for (i = 0; i < IWN_NBANDS - 1; i++) { 2388 addr = base + sc->base_params->regulatory_bands[i]; 2389 iwn_read_eeprom_channels(sc, i, addr); 2390 } 2391 2392 /* Read enhanced TX power information for 6000 Series. */ 2393 if (sc->base_params->enhanced_TX_power) 2394 iwn_read_eeprom_enhinfo(sc); 2395 2396 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 2397 base = le16toh(val); 2398 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 2399 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2400 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 2401 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 2402 sc->calib_ver = hdr.version; 2403 2404 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 2405 sc->eeprom_voltage = le16toh(hdr.volt); 2406 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2407 sc->eeprom_temp_high=le16toh(val); 2408 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2409 sc->eeprom_temp = le16toh(val); 2410 } 2411 2412 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 2413 /* Compute temperature offset. */ 2414 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2415 sc->eeprom_temp = le16toh(val); 2416 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2417 volt = le16toh(val); 2418 sc->temp_off = sc->eeprom_temp - (volt / -5); 2419 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 2420 sc->eeprom_temp, volt, sc->temp_off); 2421 } else { 2422 /* Read crystal calibration. */ 2423 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 2424 &sc->eeprom_crystal, sizeof (uint32_t)); 2425 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 2426 le32toh(sc->eeprom_crystal)); 2427 } 2428 2429 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2430 2431 } 2432 2433 /* 2434 * Translate EEPROM flags to net80211. 2435 */ 2436 static uint32_t 2437 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 2438 { 2439 uint32_t nflags; 2440 2441 nflags = 0; 2442 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 2443 nflags |= IEEE80211_CHAN_PASSIVE; 2444 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 2445 nflags |= IEEE80211_CHAN_NOADHOC; 2446 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 2447 nflags |= IEEE80211_CHAN_DFS; 2448 /* XXX apparently IBSS may still be marked */ 2449 nflags |= IEEE80211_CHAN_NOADHOC; 2450 } 2451 2452 return nflags; 2453 } 2454 2455 static void 2456 iwn_read_eeprom_band(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2457 struct ieee80211_channel chans[]) 2458 { 2459 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2460 const struct iwn_chan_band *band = &iwn_bands[n]; 2461 uint8_t bands[IEEE80211_MODE_BYTES]; 2462 uint8_t chan; 2463 int i, error, nflags; 2464 2465 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2466 2467 memset(bands, 0, sizeof(bands)); 2468 if (n == 0) { 2469 setbit(bands, IEEE80211_MODE_11B); 2470 setbit(bands, IEEE80211_MODE_11G); 2471 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2472 setbit(bands, IEEE80211_MODE_11NG); 2473 } else { 2474 setbit(bands, IEEE80211_MODE_11A); 2475 if (sc->sc_flags & IWN_FLAG_HAS_11N) 2476 setbit(bands, IEEE80211_MODE_11NA); 2477 } 2478 2479 for (i = 0; i < band->nchan; i++) { 2480 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2481 DPRINTF(sc, IWN_DEBUG_RESET, 2482 "skip chan %d flags 0x%x maxpwr %d\n", 2483 band->chan[i], channels[i].flags, 2484 channels[i].maxpwr); 2485 continue; 2486 } 2487 2488 chan = band->chan[i]; 2489 nflags = iwn_eeprom_channel_flags(&channels[i]); 2490 error = ieee80211_add_channel(chans, maxchans, nchans, 2491 chan, 0, channels[i].maxpwr, nflags, bands); 2492 if (error != 0) 2493 break; 2494 2495 /* Save maximum allowed TX power for this channel. */ 2496 /* XXX wrong */ 2497 sc->maxpwr[chan] = channels[i].maxpwr; 2498 2499 DPRINTF(sc, IWN_DEBUG_RESET, 2500 "add chan %d flags 0x%x maxpwr %d\n", chan, 2501 channels[i].flags, channels[i].maxpwr); 2502 } 2503 2504 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2505 2506 } 2507 2508 static void 2509 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n, int maxchans, int *nchans, 2510 struct ieee80211_channel chans[]) 2511 { 2512 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2513 const struct iwn_chan_band *band = &iwn_bands[n]; 2514 uint8_t chan; 2515 int i, error, nflags; 2516 2517 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2518 2519 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2520 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 2521 return; 2522 } 2523 2524 for (i = 0; i < band->nchan; i++) { 2525 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2526 DPRINTF(sc, IWN_DEBUG_RESET, 2527 "skip chan %d flags 0x%x maxpwr %d\n", 2528 band->chan[i], channels[i].flags, 2529 channels[i].maxpwr); 2530 continue; 2531 } 2532 2533 chan = band->chan[i]; 2534 nflags = iwn_eeprom_channel_flags(&channels[i]); 2535 nflags |= (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A); 2536 error = ieee80211_add_channel_ht40(chans, maxchans, nchans, 2537 chan, channels[i].maxpwr, nflags); 2538 switch (error) { 2539 case EINVAL: 2540 device_printf(sc->sc_dev, 2541 "%s: no entry for channel %d\n", __func__, chan); 2542 continue; 2543 case ENOENT: 2544 DPRINTF(sc, IWN_DEBUG_RESET, 2545 "%s: skip chan %d, extension channel not found\n", 2546 __func__, chan); 2547 continue; 2548 case ENOBUFS: 2549 device_printf(sc->sc_dev, 2550 "%s: channel table is full!\n", __func__); 2551 break; 2552 case 0: 2553 DPRINTF(sc, IWN_DEBUG_RESET, 2554 "add ht40 chan %d flags 0x%x maxpwr %d\n", 2555 chan, channels[i].flags, channels[i].maxpwr); 2556 /* FALLTHROUGH */ 2557 default: 2558 break; 2559 } 2560 } 2561 2562 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2563 2564 } 2565 2566 static void 2567 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 2568 { 2569 struct ieee80211com *ic = &sc->sc_ic; 2570 2571 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 2572 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 2573 2574 if (n < 5) { 2575 iwn_read_eeprom_band(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2576 ic->ic_channels); 2577 } else { 2578 iwn_read_eeprom_ht40(sc, n, IEEE80211_CHAN_MAX, &ic->ic_nchans, 2579 ic->ic_channels); 2580 } 2581 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 2582 } 2583 2584 static struct iwn_eeprom_chan * 2585 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 2586 { 2587 int band, chan, i, j; 2588 2589 if (IEEE80211_IS_CHAN_HT40(c)) { 2590 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 2591 if (IEEE80211_IS_CHAN_HT40D(c)) 2592 chan = c->ic_extieee; 2593 else 2594 chan = c->ic_ieee; 2595 for (i = 0; i < iwn_bands[band].nchan; i++) { 2596 if (iwn_bands[band].chan[i] == chan) 2597 return &sc->eeprom_channels[band][i]; 2598 } 2599 } else { 2600 for (j = 0; j < 5; j++) { 2601 for (i = 0; i < iwn_bands[j].nchan; i++) { 2602 if (iwn_bands[j].chan[i] == c->ic_ieee && 2603 ((j == 0) ^ IEEE80211_IS_CHAN_A(c)) == 1) 2604 return &sc->eeprom_channels[j][i]; 2605 } 2606 } 2607 } 2608 return NULL; 2609 } 2610 2611 static void 2612 iwn_getradiocaps(struct ieee80211com *ic, 2613 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2614 { 2615 struct iwn_softc *sc = ic->ic_softc; 2616 int i; 2617 2618 /* Parse the list of authorized channels. */ 2619 for (i = 0; i < 5 && *nchans < maxchans; i++) 2620 iwn_read_eeprom_band(sc, i, maxchans, nchans, chans); 2621 for (i = 5; i < IWN_NBANDS - 1 && *nchans < maxchans; i++) 2622 iwn_read_eeprom_ht40(sc, i, maxchans, nchans, chans); 2623 } 2624 2625 /* 2626 * Enforce flags read from EEPROM. 2627 */ 2628 static int 2629 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2630 int nchan, struct ieee80211_channel chans[]) 2631 { 2632 struct iwn_softc *sc = ic->ic_softc; 2633 int i; 2634 2635 for (i = 0; i < nchan; i++) { 2636 struct ieee80211_channel *c = &chans[i]; 2637 struct iwn_eeprom_chan *channel; 2638 2639 channel = iwn_find_eeprom_channel(sc, c); 2640 if (channel == NULL) { 2641 ic_printf(ic, "%s: invalid channel %u freq %u/0x%x\n", 2642 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2643 return EINVAL; 2644 } 2645 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2646 } 2647 2648 return 0; 2649 } 2650 2651 static void 2652 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2653 { 2654 struct iwn_eeprom_enhinfo enhinfo[35]; 2655 struct ieee80211com *ic = &sc->sc_ic; 2656 struct ieee80211_channel *c; 2657 uint16_t val, base; 2658 int8_t maxpwr; 2659 uint8_t flags; 2660 int i, j; 2661 2662 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2663 2664 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2665 base = le16toh(val); 2666 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2667 enhinfo, sizeof enhinfo); 2668 2669 for (i = 0; i < nitems(enhinfo); i++) { 2670 flags = enhinfo[i].flags; 2671 if (!(flags & IWN_ENHINFO_VALID)) 2672 continue; /* Skip invalid entries. */ 2673 2674 maxpwr = 0; 2675 if (sc->txchainmask & IWN_ANT_A) 2676 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2677 if (sc->txchainmask & IWN_ANT_B) 2678 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2679 if (sc->txchainmask & IWN_ANT_C) 2680 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2681 if (sc->ntxchains == 2) 2682 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2683 else if (sc->ntxchains == 3) 2684 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2685 2686 for (j = 0; j < ic->ic_nchans; j++) { 2687 c = &ic->ic_channels[j]; 2688 if ((flags & IWN_ENHINFO_5GHZ)) { 2689 if (!IEEE80211_IS_CHAN_A(c)) 2690 continue; 2691 } else if ((flags & IWN_ENHINFO_OFDM)) { 2692 if (!IEEE80211_IS_CHAN_G(c)) 2693 continue; 2694 } else if (!IEEE80211_IS_CHAN_B(c)) 2695 continue; 2696 if ((flags & IWN_ENHINFO_HT40)) { 2697 if (!IEEE80211_IS_CHAN_HT40(c)) 2698 continue; 2699 } else { 2700 if (IEEE80211_IS_CHAN_HT40(c)) 2701 continue; 2702 } 2703 if (enhinfo[i].chan != 0 && 2704 enhinfo[i].chan != c->ic_ieee) 2705 continue; 2706 2707 DPRINTF(sc, IWN_DEBUG_RESET, 2708 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2709 c->ic_flags, maxpwr / 2); 2710 c->ic_maxregpower = maxpwr / 2; 2711 c->ic_maxpower = maxpwr; 2712 } 2713 } 2714 2715 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2716 2717 } 2718 2719 static struct ieee80211_node * 2720 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2721 { 2722 return kmalloc(sizeof (struct iwn_node), M_80211_NODE, 2723 M_INTWAIT | M_ZERO); 2724 } 2725 2726 static __inline int 2727 rate2plcp(int rate) 2728 { 2729 switch (rate & 0xff) { 2730 case 12: return 0xd; 2731 case 18: return 0xf; 2732 case 24: return 0x5; 2733 case 36: return 0x7; 2734 case 48: return 0x9; 2735 case 72: return 0xb; 2736 case 96: return 0x1; 2737 case 108: return 0x3; 2738 case 2: return 10; 2739 case 4: return 20; 2740 case 11: return 55; 2741 case 22: return 110; 2742 } 2743 return 0; 2744 } 2745 2746 static int 2747 iwn_get_1stream_tx_antmask(struct iwn_softc *sc) 2748 { 2749 2750 return IWN_LSB(sc->txchainmask); 2751 } 2752 2753 static int 2754 iwn_get_2stream_tx_antmask(struct iwn_softc *sc) 2755 { 2756 int tx; 2757 2758 /* 2759 * The '2 stream' setup is a bit .. odd. 2760 * 2761 * For NICs that support only 1 antenna, default to IWN_ANT_AB or 2762 * the firmware panics (eg Intel 5100.) 2763 * 2764 * For NICs that support two antennas, we use ANT_AB. 2765 * 2766 * For NICs that support three antennas, we use the two that 2767 * wasn't the default one. 2768 * 2769 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict 2770 * this to only one antenna. 2771 */ 2772 2773 /* Default - transmit on the other antennas */ 2774 tx = (sc->txchainmask & ~IWN_LSB(sc->txchainmask)); 2775 2776 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */ 2777 if (tx == 0) 2778 tx = IWN_ANT_AB; 2779 2780 /* 2781 * If the NIC is a two-stream TX NIC, configure the TX mask to 2782 * the default chainmask 2783 */ 2784 else if (sc->ntxchains == 2) 2785 tx = sc->txchainmask; 2786 2787 return (tx); 2788 } 2789 2790 2791 2792 /* 2793 * Calculate the required PLCP value from the given rate, 2794 * to the given node. 2795 * 2796 * This will take the node configuration (eg 11n, rate table 2797 * setup, etc) into consideration. 2798 */ 2799 static uint32_t 2800 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2801 uint8_t rate) 2802 { 2803 struct ieee80211com *ic = ni->ni_ic; 2804 uint32_t plcp = 0; 2805 int ridx; 2806 2807 /* 2808 * If it's an MCS rate, let's set the plcp correctly 2809 * and set the relevant flags based on the node config. 2810 */ 2811 if (rate & IEEE80211_RATE_MCS) { 2812 /* 2813 * Set the initial PLCP value to be between 0->31 for 2814 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2815 * flag. 2816 */ 2817 plcp = IEEE80211_RV(rate) | IWN_RFLAG_MCS; 2818 2819 /* 2820 * XXX the following should only occur if both 2821 * the local configuration _and_ the remote node 2822 * advertise these capabilities. Thus this code 2823 * may need fixing! 2824 */ 2825 2826 /* 2827 * Set the channel width and guard interval. 2828 */ 2829 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2830 plcp |= IWN_RFLAG_HT40; 2831 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2832 plcp |= IWN_RFLAG_SGI; 2833 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) { 2834 plcp |= IWN_RFLAG_SGI; 2835 } 2836 2837 /* 2838 * Ensure the selected rate matches the link quality 2839 * table entries being used. 2840 */ 2841 if (rate > 0x8f) 2842 plcp |= IWN_RFLAG_ANT(sc->txchainmask); 2843 else if (rate > 0x87) 2844 plcp |= IWN_RFLAG_ANT(iwn_get_2stream_tx_antmask(sc)); 2845 else 2846 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2847 } else { 2848 /* 2849 * Set the initial PLCP - fine for both 2850 * OFDM and CCK rates. 2851 */ 2852 plcp = rate2plcp(rate); 2853 2854 /* Set CCK flag if it's CCK */ 2855 2856 /* XXX It would be nice to have a method 2857 * to map the ridx -> phy table entry 2858 * so we could just query that, rather than 2859 * this hack to check against IWN_RIDX_OFDM6. 2860 */ 2861 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2862 rate & IEEE80211_RATE_VAL); 2863 if (ridx < IWN_RIDX_OFDM6 && 2864 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2865 plcp |= IWN_RFLAG_CCK; 2866 2867 /* Set antenna configuration */ 2868 /* XXX TODO: is this the right antenna to use for legacy? */ 2869 plcp |= IWN_RFLAG_ANT(iwn_get_1stream_tx_antmask(sc)); 2870 } 2871 2872 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2873 __func__, 2874 rate, 2875 plcp); 2876 2877 return (htole32(plcp)); 2878 } 2879 2880 static void 2881 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2882 { 2883 /* Doesn't do anything at the moment */ 2884 } 2885 2886 static int 2887 iwn_media_change(struct ifnet *ifp) 2888 { 2889 int error; 2890 2891 error = ieee80211_media_change(ifp); 2892 /* NB: only the fixed rate can change and that doesn't need a reset */ 2893 return (error == ENETRESET ? 0 : error); 2894 } 2895 2896 static int 2897 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2898 { 2899 struct iwn_vap *ivp = IWN_VAP(vap); 2900 struct ieee80211com *ic = vap->iv_ic; 2901 struct iwn_softc *sc = ic->ic_softc; 2902 int error = 0; 2903 2904 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2905 2906 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2907 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2908 2909 IEEE80211_UNLOCK(ic); 2910 IWN_LOCK(sc); 2911 #if defined(__DragonFly__) 2912 callout_cancel(&sc->calib_to); 2913 #else 2914 callout_stop(&sc->calib_to); 2915 #endif 2916 2917 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2918 2919 switch (nstate) { 2920 case IEEE80211_S_ASSOC: 2921 if (vap->iv_state != IEEE80211_S_RUN) 2922 break; 2923 /* FALLTHROUGH */ 2924 case IEEE80211_S_AUTH: 2925 if (vap->iv_state == IEEE80211_S_AUTH) 2926 break; 2927 2928 /* 2929 * !AUTH -> AUTH transition requires state reset to handle 2930 * reassociations correctly. 2931 */ 2932 sc->rxon->associd = 0; 2933 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2934 sc->calib.state = IWN_CALIB_STATE_INIT; 2935 2936 /* Wait until we hear a beacon before we transmit */ 2937 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2938 sc->sc_beacon_wait = 1; 2939 2940 if ((error = iwn_auth(sc, vap)) != 0) { 2941 device_printf(sc->sc_dev, 2942 "%s: could not move to auth state\n", __func__); 2943 } 2944 break; 2945 2946 case IEEE80211_S_RUN: 2947 /* 2948 * RUN -> RUN transition; Just restart the timers. 2949 */ 2950 if (vap->iv_state == IEEE80211_S_RUN) { 2951 sc->calib_cnt = 0; 2952 break; 2953 } 2954 2955 /* Wait until we hear a beacon before we transmit */ 2956 if (IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan)) 2957 sc->sc_beacon_wait = 1; 2958 2959 /* 2960 * !RUN -> RUN requires setting the association id 2961 * which is done with a firmware cmd. We also defer 2962 * starting the timers until that work is done. 2963 */ 2964 if ((error = iwn_run(sc, vap)) != 0) { 2965 device_printf(sc->sc_dev, 2966 "%s: could not move to run state\n", __func__); 2967 } 2968 break; 2969 2970 case IEEE80211_S_INIT: 2971 sc->calib.state = IWN_CALIB_STATE_INIT; 2972 /* 2973 * Purge the xmit queue so we don't have old frames 2974 * during a new association attempt. 2975 */ 2976 sc->sc_beacon_wait = 0; 2977 iwn_xmit_queue_drain(sc); 2978 break; 2979 2980 default: 2981 break; 2982 } 2983 IWN_UNLOCK(sc); 2984 IEEE80211_LOCK(ic); 2985 if (error != 0){ 2986 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2987 return error; 2988 } 2989 2990 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2991 2992 return ivp->iv_newstate(vap, nstate, arg); 2993 } 2994 2995 static void 2996 iwn_calib_timeout(void *arg) 2997 { 2998 struct iwn_softc *sc = arg; 2999 3000 IWN_LOCK_ASSERT(sc); 3001 3002 /* Force automatic TX power calibration every 60 secs. */ 3003 if (++sc->calib_cnt >= 120) { 3004 uint32_t flags = 0; 3005 3006 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 3007 "sending request for statistics"); 3008 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 3009 sizeof flags, 1); 3010 sc->calib_cnt = 0; 3011 } 3012 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 3013 sc); 3014 } 3015 3016 /* 3017 * Process an RX_PHY firmware notification. This is usually immediately 3018 * followed by an MPDU_RX_DONE notification. 3019 */ 3020 static void 3021 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3022 struct iwn_rx_data *data) 3023 { 3024 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 3025 3026 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 3027 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3028 3029 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 3030 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 3031 sc->last_rx_valid = 1; 3032 } 3033 3034 /* 3035 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 3036 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 3037 */ 3038 static void 3039 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3040 struct iwn_rx_data *data) 3041 { 3042 struct iwn_ops *ops = &sc->ops; 3043 struct ieee80211com *ic = &sc->sc_ic; 3044 struct iwn_rx_ring *ring = &sc->rxq; 3045 struct ieee80211_frame *wh; 3046 struct ieee80211_node *ni; 3047 struct mbuf *m, *m1; 3048 struct iwn_rx_stat *stat; 3049 caddr_t head; 3050 bus_addr_t paddr; 3051 uint32_t flags; 3052 int error, len, rssi, nf; 3053 3054 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3055 3056 if (desc->type == IWN_MPDU_RX_DONE) { 3057 /* Check for prior RX_PHY notification. */ 3058 if (!sc->last_rx_valid) { 3059 DPRINTF(sc, IWN_DEBUG_ANY, 3060 "%s: missing RX_PHY\n", __func__); 3061 return; 3062 } 3063 stat = &sc->last_rx_stat; 3064 } else 3065 stat = (struct iwn_rx_stat *)(desc + 1); 3066 3067 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3068 3069 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 3070 device_printf(sc->sc_dev, 3071 "%s: invalid RX statistic header, len %d\n", __func__, 3072 stat->cfg_phy_len); 3073 return; 3074 } 3075 if (desc->type == IWN_MPDU_RX_DONE) { 3076 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 3077 head = (caddr_t)(mpdu + 1); 3078 len = le16toh(mpdu->len); 3079 } else { 3080 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 3081 len = le16toh(stat->len); 3082 } 3083 3084 flags = le32toh(*(uint32_t *)(head + len)); 3085 3086 /* Discard frames with a bad FCS early. */ 3087 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 3088 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 3089 __func__, flags); 3090 #if defined(__DragonFly__) 3091 ++ic->ic_ierrors; 3092 #else 3093 counter_u64_add(ic->ic_ierrors, 1); 3094 #endif 3095 return; 3096 } 3097 /* Discard frames that are too short. */ 3098 if (len < sizeof (struct ieee80211_frame_ack)) { 3099 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 3100 __func__, len); 3101 #if defined(__DragonFly__) 3102 ++ic->ic_ierrors; 3103 #else 3104 counter_u64_add(ic->ic_ierrors, 1); 3105 #endif 3106 return; 3107 } 3108 3109 m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 3110 if (m1 == NULL) { 3111 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 3112 __func__); 3113 #if defined(__DragonFly__) 3114 ++ic->ic_ierrors; 3115 #else 3116 counter_u64_add(ic->ic_ierrors, 1); 3117 #endif 3118 return; 3119 } 3120 bus_dmamap_unload(ring->data_dmat, data->map); 3121 3122 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 3123 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3124 if (error != 0 && error != EFBIG) { 3125 device_printf(sc->sc_dev, 3126 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 3127 m_freem(m1); 3128 3129 /* Try to reload the old mbuf. */ 3130 error = bus_dmamap_load(ring->data_dmat, data->map, 3131 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 3132 &paddr, BUS_DMA_NOWAIT); 3133 if (error != 0 && error != EFBIG) { 3134 panic("%s: could not load old RX mbuf", __func__); 3135 } 3136 /* Physical address may have changed. */ 3137 ring->desc[ring->cur] = htole32(paddr >> 8); 3138 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map, 3139 BUS_DMASYNC_PREWRITE); 3140 #if defined(__DragonFly__) 3141 ++ic->ic_ierrors; 3142 #else 3143 counter_u64_add(ic->ic_ierrors, 1); 3144 #endif 3145 return; 3146 } 3147 3148 m = data->m; 3149 data->m = m1; 3150 /* Update RX descriptor. */ 3151 ring->desc[ring->cur] = htole32(paddr >> 8); 3152 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3153 BUS_DMASYNC_PREWRITE); 3154 3155 /* Finalize mbuf. */ 3156 m->m_data = head; 3157 m->m_pkthdr.len = m->m_len = len; 3158 3159 /* Grab a reference to the source node. */ 3160 wh = mtod(m, struct ieee80211_frame *); 3161 if (len >= sizeof(struct ieee80211_frame_min)) 3162 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3163 else 3164 ni = NULL; 3165 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 3166 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 3167 3168 rssi = ops->get_rssi(sc, stat); 3169 3170 if (ieee80211_radiotap_active(ic)) { 3171 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 3172 3173 tap->wr_flags = 0; 3174 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 3175 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3176 tap->wr_dbm_antsignal = (int8_t)rssi; 3177 tap->wr_dbm_antnoise = (int8_t)nf; 3178 tap->wr_tsft = stat->tstamp; 3179 switch (stat->rate) { 3180 /* CCK rates. */ 3181 case 10: tap->wr_rate = 2; break; 3182 case 20: tap->wr_rate = 4; break; 3183 case 55: tap->wr_rate = 11; break; 3184 case 110: tap->wr_rate = 22; break; 3185 /* OFDM rates. */ 3186 case 0xd: tap->wr_rate = 12; break; 3187 case 0xf: tap->wr_rate = 18; break; 3188 case 0x5: tap->wr_rate = 24; break; 3189 case 0x7: tap->wr_rate = 36; break; 3190 case 0x9: tap->wr_rate = 48; break; 3191 case 0xb: tap->wr_rate = 72; break; 3192 case 0x1: tap->wr_rate = 96; break; 3193 case 0x3: tap->wr_rate = 108; break; 3194 /* Unknown rate: should not happen. */ 3195 default: tap->wr_rate = 0; 3196 } 3197 } 3198 3199 /* 3200 * If it's a beacon and we're waiting, then do the 3201 * wakeup. This should unblock raw_xmit/start. 3202 */ 3203 if (sc->sc_beacon_wait) { 3204 uint8_t type, subtype; 3205 /* NB: Re-assign wh */ 3206 wh = mtod(m, struct ieee80211_frame *); 3207 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3208 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3209 /* 3210 * This assumes at this point we've received our own 3211 * beacon. 3212 */ 3213 DPRINTF(sc, IWN_DEBUG_TRACE, 3214 "%s: beacon_wait, type=%d, subtype=%d\n", 3215 __func__, type, subtype); 3216 if (type == IEEE80211_FC0_TYPE_MGT && 3217 subtype == IEEE80211_FC0_SUBTYPE_BEACON) { 3218 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3219 "%s: waking things up\n", __func__); 3220 /* queue taskqueue to transmit! */ 3221 taskqueue_enqueue(sc->sc_tq, &sc->sc_xmit_task); 3222 } 3223 } 3224 3225 IWN_UNLOCK(sc); 3226 3227 /* Send the frame to the 802.11 layer. */ 3228 if (ni != NULL) { 3229 if (ni->ni_flags & IEEE80211_NODE_HT) 3230 m->m_flags |= M_AMPDU; 3231 (void)ieee80211_input(ni, m, rssi - nf, nf); 3232 /* Node is no longer needed. */ 3233 ieee80211_free_node(ni); 3234 } else 3235 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 3236 3237 IWN_LOCK(sc); 3238 3239 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3240 3241 } 3242 3243 /* Process an incoming Compressed BlockAck. */ 3244 static void 3245 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3246 struct iwn_rx_data *data) 3247 { 3248 struct iwn_ops *ops = &sc->ops; 3249 struct iwn_node *wn; 3250 struct ieee80211_node *ni; 3251 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 3252 struct iwn_tx_ring *txq; 3253 struct iwn_tx_data *txdata; 3254 struct ieee80211_tx_ampdu *tap; 3255 struct mbuf *m; 3256 uint64_t bitmap; 3257 uint16_t ssn; 3258 uint8_t tid; 3259 int ackfailcnt = 0, i, lastidx, qid, *res, shift; 3260 int tx_ok = 0, tx_err = 0; 3261 3262 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s begin\n", __func__); 3263 3264 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3265 3266 qid = le16toh(ba->qid); 3267 txq = &sc->txq[ba->qid]; 3268 tap = sc->qid2tap[ba->qid]; 3269 tid = tap->txa_tid; 3270 wn = (void *)tap->txa_ni; 3271 3272 res = NULL; 3273 ssn = 0; 3274 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3275 res = tap->txa_private; 3276 ssn = tap->txa_start & 0xfff; 3277 } 3278 3279 for (lastidx = le16toh(ba->ssn) & 0xff; txq->read != lastidx;) { 3280 txdata = &txq->data[txq->read]; 3281 3282 /* Unmap and free mbuf. */ 3283 bus_dmamap_sync(txq->data_dmat, txdata->map, 3284 BUS_DMASYNC_POSTWRITE); 3285 bus_dmamap_unload(txq->data_dmat, txdata->map); 3286 m = txdata->m, txdata->m = NULL; 3287 ni = txdata->ni, txdata->ni = NULL; 3288 3289 KASSERT(ni != NULL, ("no node")); 3290 KASSERT(m != NULL, ("no mbuf")); 3291 3292 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: freeing m=%p\n", __func__, m); 3293 ieee80211_tx_complete(ni, m, 1); 3294 3295 txq->queued--; 3296 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 3297 } 3298 3299 if (txq->queued == 0 && res != NULL) { 3300 iwn_nic_lock(sc); 3301 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3302 iwn_nic_unlock(sc); 3303 sc->qid2tap[qid] = NULL; 3304 kfree(res, M_DEVBUF); 3305 return; 3306 } 3307 3308 if (wn->agg[tid].bitmap == 0) 3309 return; 3310 3311 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 3312 if (shift < 0) 3313 shift += 0x100; 3314 3315 if (wn->agg[tid].nframes > (64 - shift)) 3316 return; 3317 3318 /* 3319 * Walk the bitmap and calculate how many successful and failed 3320 * attempts are made. 3321 * 3322 * Yes, the rate control code doesn't know these are A-MPDU 3323 * subframes and that it's okay to fail some of these. 3324 */ 3325 ni = tap->txa_ni; 3326 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap; 3327 for (i = 0; bitmap; i++) { 3328 if ((bitmap & 1) == 0) { 3329 tx_err ++; 3330 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3331 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 3332 } else { 3333 tx_ok ++; 3334 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3335 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 3336 } 3337 bitmap >>= 1; 3338 } 3339 3340 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, 3341 "->%s: end; %d ok; %d err\n",__func__, tx_ok, tx_err); 3342 3343 } 3344 3345 /* 3346 * Process a CALIBRATION_RESULT notification sent by the initialization 3347 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 3348 */ 3349 static void 3350 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3351 struct iwn_rx_data *data) 3352 { 3353 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 3354 int len, idx = -1; 3355 3356 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3357 3358 /* Runtime firmware should not send such a notification. */ 3359 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 3360 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received after clib done\n", 3361 __func__); 3362 return; 3363 } 3364 len = (le32toh(desc->len) & 0x3fff) - 4; 3365 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3366 3367 switch (calib->code) { 3368 case IWN5000_PHY_CALIB_DC: 3369 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC) 3370 idx = 0; 3371 break; 3372 case IWN5000_PHY_CALIB_LO: 3373 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO) 3374 idx = 1; 3375 break; 3376 case IWN5000_PHY_CALIB_TX_IQ: 3377 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ) 3378 idx = 2; 3379 break; 3380 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 3381 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC) 3382 idx = 3; 3383 break; 3384 case IWN5000_PHY_CALIB_BASE_BAND: 3385 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND) 3386 idx = 4; 3387 break; 3388 } 3389 if (idx == -1) /* Ignore other results. */ 3390 return; 3391 3392 /* Save calibration result. */ 3393 if (sc->calibcmd[idx].buf != NULL) 3394 kfree(sc->calibcmd[idx].buf, M_DEVBUF); 3395 sc->calibcmd[idx].buf = kmalloc(len, M_DEVBUF, M_INTWAIT); 3396 if (sc->calibcmd[idx].buf == NULL) { 3397 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3398 "not enough memory for calibration result %d\n", 3399 calib->code); 3400 return; 3401 } 3402 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3403 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len); 3404 sc->calibcmd[idx].len = len; 3405 memcpy(sc->calibcmd[idx].buf, calib, len); 3406 } 3407 3408 static void 3409 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib, 3410 struct iwn_stats *stats, int len) 3411 { 3412 struct iwn_stats_bt *stats_bt; 3413 struct iwn_stats *lstats; 3414 3415 /* 3416 * First - check whether the length is the bluetooth or normal. 3417 * 3418 * If it's normal - just copy it and bump out. 3419 * Otherwise we have to convert things. 3420 */ 3421 3422 if (len == sizeof(struct iwn_stats) + 4) { 3423 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3424 sc->last_stat_valid = 1; 3425 return; 3426 } 3427 3428 /* 3429 * If it's not the bluetooth size - log, then just copy. 3430 */ 3431 if (len != sizeof(struct iwn_stats_bt) + 4) { 3432 DPRINTF(sc, IWN_DEBUG_STATS, 3433 "%s: size of rx statistics (%d) not an expected size!\n", 3434 __func__, 3435 len); 3436 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3437 sc->last_stat_valid = 1; 3438 return; 3439 } 3440 3441 /* 3442 * Ok. Time to copy. 3443 */ 3444 stats_bt = (struct iwn_stats_bt *) stats; 3445 lstats = &sc->last_stat; 3446 3447 /* flags */ 3448 lstats->flags = stats_bt->flags; 3449 /* rx_bt */ 3450 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm, 3451 sizeof(struct iwn_rx_phy_stats)); 3452 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck, 3453 sizeof(struct iwn_rx_phy_stats)); 3454 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common, 3455 sizeof(struct iwn_rx_general_stats)); 3456 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht, 3457 sizeof(struct iwn_rx_ht_phy_stats)); 3458 /* tx */ 3459 memcpy(&lstats->tx, &stats_bt->tx, 3460 sizeof(struct iwn_tx_stats)); 3461 /* general */ 3462 memcpy(&lstats->general, &stats_bt->general, 3463 sizeof(struct iwn_general_stats)); 3464 3465 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */ 3466 sc->last_stat_valid = 1; 3467 } 3468 3469 /* 3470 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 3471 * The latter is sent by the firmware after each received beacon. 3472 */ 3473 static void 3474 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3475 struct iwn_rx_data *data) 3476 { 3477 struct iwn_ops *ops = &sc->ops; 3478 struct ieee80211com *ic = &sc->sc_ic; 3479 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3480 struct iwn_calib_state *calib = &sc->calib; 3481 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 3482 struct iwn_stats *lstats; 3483 int temp; 3484 3485 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3486 3487 /* Ignore statistics received during a scan. */ 3488 if (vap->iv_state != IEEE80211_S_RUN || 3489 (ic->ic_flags & IEEE80211_F_SCAN)){ 3490 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 3491 __func__); 3492 return; 3493 } 3494 3495 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3496 3497 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS, 3498 "%s: received statistics, cmd %d, len %d\n", 3499 __func__, desc->type, le16toh(desc->len)); 3500 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 3501 3502 /* 3503 * Collect/track general statistics for reporting. 3504 * 3505 * This takes care of ensuring that the bluetooth sized message 3506 * will be correctly converted to the legacy sized message. 3507 */ 3508 iwn_stats_update(sc, calib, stats, le16toh(desc->len)); 3509 3510 /* 3511 * And now, let's take a reference of it to use! 3512 */ 3513 lstats = &sc->last_stat; 3514 3515 /* Test if temperature has changed. */ 3516 if (lstats->general.temp != sc->rawtemp) { 3517 /* Convert "raw" temperature to degC. */ 3518 sc->rawtemp = stats->general.temp; 3519 temp = ops->get_temperature(sc); 3520 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 3521 __func__, temp); 3522 3523 /* Update TX power if need be (4965AGN only). */ 3524 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3525 iwn4965_power_calibration(sc, temp); 3526 } 3527 3528 if (desc->type != IWN_BEACON_STATISTICS) 3529 return; /* Reply to a statistics request. */ 3530 3531 sc->noise = iwn_get_noise(&lstats->rx.general); 3532 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 3533 3534 /* Test that RSSI and noise are present in stats report. */ 3535 if (le32toh(lstats->rx.general.flags) != 1) { 3536 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 3537 "received statistics without RSSI"); 3538 return; 3539 } 3540 3541 if (calib->state == IWN_CALIB_STATE_ASSOC) 3542 iwn_collect_noise(sc, &lstats->rx.general); 3543 else if (calib->state == IWN_CALIB_STATE_RUN) { 3544 iwn_tune_sensitivity(sc, &lstats->rx); 3545 /* 3546 * XXX TODO: Only run the RX recovery if we're associated! 3547 */ 3548 iwn_check_rx_recovery(sc, lstats); 3549 iwn_save_stats_counters(sc, lstats); 3550 } 3551 3552 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3553 } 3554 3555 /* 3556 * Save the relevant statistic counters for the next calibration 3557 * pass. 3558 */ 3559 static void 3560 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs) 3561 { 3562 struct iwn_calib_state *calib = &sc->calib; 3563 3564 /* Save counters values for next call. */ 3565 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp); 3566 calib->fa_cck = le32toh(rs->rx.cck.fa); 3567 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp); 3568 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp); 3569 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa); 3570 3571 /* Last time we received these tick values */ 3572 sc->last_calib_ticks = ticks; 3573 } 3574 3575 /* 3576 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 3577 * and 5000 adapters have different incompatible TX status formats. 3578 */ 3579 static void 3580 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3581 struct iwn_rx_data *data) 3582 { 3583 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 3584 struct iwn_tx_ring *ring; 3585 int qid; 3586 3587 qid = desc->qid & 0xf; 3588 ring = &sc->txq[qid]; 3589 3590 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3591 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3592 __func__, desc->qid, desc->idx, 3593 stat->rtsfailcnt, 3594 stat->ackfailcnt, 3595 stat->btkillcnt, 3596 stat->rate, le16toh(stat->duration), 3597 le32toh(stat->status)); 3598 3599 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3600 if (qid >= sc->firstaggqueue) { 3601 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3602 stat->ackfailcnt, &stat->status); 3603 } else { 3604 iwn_tx_done(sc, desc, stat->ackfailcnt, 3605 le32toh(stat->status) & 0xff); 3606 } 3607 } 3608 3609 static void 3610 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3611 struct iwn_rx_data *data) 3612 { 3613 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 3614 struct iwn_tx_ring *ring; 3615 int qid; 3616 3617 qid = desc->qid & 0xf; 3618 ring = &sc->txq[qid]; 3619 3620 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3621 "qid %d idx %d RTS retries %d ACK retries %d nkill %d rate %x duration %d status %x\n", 3622 __func__, desc->qid, desc->idx, 3623 stat->rtsfailcnt, 3624 stat->ackfailcnt, 3625 stat->btkillcnt, 3626 stat->rate, le16toh(stat->duration), 3627 le32toh(stat->status)); 3628 3629 #ifdef notyet 3630 /* Reset TX scheduler slot. */ 3631 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 3632 #endif 3633 3634 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3635 if (qid >= sc->firstaggqueue) { 3636 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3637 stat->ackfailcnt, &stat->status); 3638 } else { 3639 iwn_tx_done(sc, desc, stat->ackfailcnt, 3640 le16toh(stat->status) & 0xff); 3641 } 3642 } 3643 3644 /* 3645 * Adapter-independent backend for TX_DONE firmware notifications. 3646 */ 3647 static void 3648 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 3649 uint8_t status) 3650 { 3651 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 3652 struct iwn_tx_data *data = &ring->data[desc->idx]; 3653 struct mbuf *m; 3654 struct ieee80211_node *ni; 3655 struct ieee80211vap *vap; 3656 3657 KASSERT(data->ni != NULL, ("no node")); 3658 3659 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3660 3661 /* Unmap and free mbuf. */ 3662 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 3663 bus_dmamap_unload(ring->data_dmat, data->map); 3664 m = data->m, data->m = NULL; 3665 ni = data->ni, data->ni = NULL; 3666 vap = ni->ni_vap; 3667 3668 /* 3669 * Update rate control statistics for the node. 3670 */ 3671 if (status & IWN_TX_FAIL) 3672 ieee80211_ratectl_tx_complete(vap, ni, 3673 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 3674 else 3675 ieee80211_ratectl_tx_complete(vap, ni, 3676 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 3677 3678 /* 3679 * Channels marked for "radar" require traffic to be received 3680 * to unlock before we can transmit. Until traffic is seen 3681 * any attempt to transmit is returned immediately with status 3682 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 3683 * happen on first authenticate after scanning. To workaround 3684 * this we ignore a failure of this sort in AUTH state so the 3685 * 802.11 layer will fall back to using a timeout to wait for 3686 * the AUTH reply. This allows the firmware time to see 3687 * traffic so a subsequent retry of AUTH succeeds. It's 3688 * unclear why the firmware does not maintain state for 3689 * channels recently visited as this would allow immediate 3690 * use of the channel after a scan (where we see traffic). 3691 */ 3692 if (status == IWN_TX_FAIL_TX_LOCKED && 3693 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 3694 ieee80211_tx_complete(ni, m, 0); 3695 else 3696 ieee80211_tx_complete(ni, m, 3697 (status & IWN_TX_FAIL) != 0); 3698 3699 sc->sc_tx_timer = 0; 3700 if (--ring->queued < IWN_TX_RING_LOMARK) 3701 sc->qfullmsk &= ~(1 << ring->qid); 3702 3703 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3704 } 3705 3706 /* 3707 * Process a "command done" firmware notification. This is where we wakeup 3708 * processes waiting for a synchronous command completion. 3709 */ 3710 static void 3711 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3712 { 3713 struct iwn_tx_ring *ring; 3714 struct iwn_tx_data *data; 3715 int cmd_queue_num; 3716 3717 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 3718 cmd_queue_num = IWN_PAN_CMD_QUEUE; 3719 else 3720 cmd_queue_num = IWN_CMD_QUEUE_NUM; 3721 3722 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num) 3723 return; /* Not a command ack. */ 3724 3725 ring = &sc->txq[cmd_queue_num]; 3726 data = &ring->data[desc->idx]; 3727 3728 /* If the command was mapped in an mbuf, free it. */ 3729 if (data->m != NULL) { 3730 bus_dmamap_sync(ring->data_dmat, data->map, 3731 BUS_DMASYNC_POSTWRITE); 3732 bus_dmamap_unload(ring->data_dmat, data->map); 3733 m_freem(data->m); 3734 data->m = NULL; 3735 } 3736 wakeup(&ring->desc[desc->idx]); 3737 } 3738 3739 static void 3740 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 3741 int ackfailcnt, void *stat) 3742 { 3743 struct iwn_ops *ops = &sc->ops; 3744 struct iwn_tx_ring *ring = &sc->txq[qid]; 3745 struct iwn_tx_data *data; 3746 struct mbuf *m; 3747 struct iwn_node *wn; 3748 struct ieee80211_node *ni; 3749 struct ieee80211_tx_ampdu *tap; 3750 uint64_t bitmap; 3751 uint32_t *status = stat; 3752 uint16_t *aggstatus = stat; 3753 uint16_t ssn; 3754 uint8_t tid; 3755 int bit, i, lastidx, *res, seqno, shift, start; 3756 3757 /* XXX TODO: status is le16 field! Grr */ 3758 3759 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3760 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: nframes=%d, status=0x%08x\n", 3761 __func__, 3762 nframes, 3763 *status); 3764 3765 tap = sc->qid2tap[qid]; 3766 tid = tap->txa_tid; 3767 wn = (void *)tap->txa_ni; 3768 ni = tap->txa_ni; 3769 3770 /* 3771 * XXX TODO: ACK and RTS failures would be nice here! 3772 */ 3773 3774 /* 3775 * A-MPDU single frame status - if we failed to transmit it 3776 * in A-MPDU, then it may be a permanent failure. 3777 * 3778 * XXX TODO: check what the Linux iwlwifi driver does here; 3779 * there's some permanent and temporary failures that may be 3780 * handled differently. 3781 */ 3782 if (nframes == 1) { 3783 if ((*status & 0xff) != 1 && (*status & 0xff) != 2) { 3784 #ifdef NOT_YET 3785 kprintf("ieee80211_send_bar()\n"); 3786 #endif 3787 /* 3788 * If we completely fail a transmit, make sure a 3789 * notification is pushed up to the rate control 3790 * layer. 3791 */ 3792 ieee80211_ratectl_tx_complete(ni->ni_vap, 3793 ni, 3794 IEEE80211_RATECTL_TX_FAILURE, 3795 &ackfailcnt, 3796 NULL); 3797 } else { 3798 /* 3799 * If nframes=1, then we won't be getting a BA for 3800 * this frame. Ensure that we correctly update the 3801 * rate control code with how many retries were 3802 * needed to send it. 3803 */ 3804 ieee80211_ratectl_tx_complete(ni->ni_vap, 3805 ni, 3806 IEEE80211_RATECTL_TX_SUCCESS, 3807 &ackfailcnt, 3808 NULL); 3809 } 3810 } 3811 3812 bitmap = 0; 3813 start = idx; 3814 for (i = 0; i < nframes; i++) { 3815 if (le16toh(aggstatus[i * 2]) & 0xc) 3816 continue; 3817 3818 idx = le16toh(aggstatus[2*i + 1]) & 0xff; 3819 bit = idx - start; 3820 shift = 0; 3821 if (bit >= 64) { 3822 shift = 0x100 - idx + start; 3823 bit = 0; 3824 start = idx; 3825 } else if (bit <= -64) 3826 bit = 0x100 - start + idx; 3827 else if (bit < 0) { 3828 shift = start - idx; 3829 start = idx; 3830 bit = 0; 3831 } 3832 bitmap = bitmap << shift; 3833 bitmap |= 1ULL << bit; 3834 } 3835 tap = sc->qid2tap[qid]; 3836 tid = tap->txa_tid; 3837 wn = (void *)tap->txa_ni; 3838 wn->agg[tid].bitmap = bitmap; 3839 wn->agg[tid].startidx = start; 3840 wn->agg[tid].nframes = nframes; 3841 3842 res = NULL; 3843 ssn = 0; 3844 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3845 res = tap->txa_private; 3846 ssn = tap->txa_start & 0xfff; 3847 } 3848 3849 /* This is going nframes DWORDS into the descriptor? */ 3850 seqno = le32toh(*(status + nframes)) & 0xfff; 3851 for (lastidx = (seqno & 0xff); ring->read != lastidx;) { 3852 data = &ring->data[ring->read]; 3853 3854 /* Unmap and free mbuf. */ 3855 bus_dmamap_sync(ring->data_dmat, data->map, 3856 BUS_DMASYNC_POSTWRITE); 3857 bus_dmamap_unload(ring->data_dmat, data->map); 3858 m = data->m, data->m = NULL; 3859 ni = data->ni, data->ni = NULL; 3860 3861 KASSERT(ni != NULL, ("no node")); 3862 KASSERT(m != NULL, ("no mbuf")); 3863 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: freeing m=%p\n", __func__, m); 3864 ieee80211_tx_complete(ni, m, 1); 3865 3866 ring->queued--; 3867 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT; 3868 } 3869 3870 if (ring->queued == 0 && res != NULL) { 3871 iwn_nic_lock(sc); 3872 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3873 iwn_nic_unlock(sc); 3874 sc->qid2tap[qid] = NULL; 3875 kfree(res, M_DEVBUF); 3876 return; 3877 } 3878 3879 sc->sc_tx_timer = 0; 3880 if (ring->queued < IWN_TX_RING_LOMARK) 3881 sc->qfullmsk &= ~(1 << ring->qid); 3882 3883 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3884 } 3885 3886 /* 3887 * Process an INT_FH_RX or INT_SW_RX interrupt. 3888 */ 3889 static void 3890 iwn_notif_intr(struct iwn_softc *sc) 3891 { 3892 struct iwn_ops *ops = &sc->ops; 3893 struct ieee80211com *ic = &sc->sc_ic; 3894 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3895 uint16_t hw; 3896 3897 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 3898 BUS_DMASYNC_POSTREAD); 3899 3900 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 3901 while (sc->rxq.cur != hw) { 3902 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 3903 struct iwn_rx_desc *desc; 3904 3905 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3906 BUS_DMASYNC_POSTREAD); 3907 desc = mtod(data->m, struct iwn_rx_desc *); 3908 3909 DPRINTF(sc, IWN_DEBUG_RECV, 3910 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n", 3911 __func__, sc->rxq.cur, desc->qid & 0xf, desc->idx, desc->flags, 3912 desc->type, iwn_intr_str(desc->type), 3913 le16toh(desc->len)); 3914 3915 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */ 3916 iwn_cmd_done(sc, desc); 3917 3918 switch (desc->type) { 3919 case IWN_RX_PHY: 3920 iwn_rx_phy(sc, desc, data); 3921 break; 3922 3923 case IWN_RX_DONE: /* 4965AGN only. */ 3924 case IWN_MPDU_RX_DONE: 3925 /* An 802.11 frame has been received. */ 3926 iwn_rx_done(sc, desc, data); 3927 break; 3928 3929 case IWN_RX_COMPRESSED_BA: 3930 /* A Compressed BlockAck has been received. */ 3931 iwn_rx_compressed_ba(sc, desc, data); 3932 break; 3933 3934 case IWN_TX_DONE: 3935 /* An 802.11 frame has been transmitted. */ 3936 ops->tx_done(sc, desc, data); 3937 break; 3938 3939 case IWN_RX_STATISTICS: 3940 case IWN_BEACON_STATISTICS: 3941 iwn_rx_statistics(sc, desc, data); 3942 break; 3943 3944 case IWN_BEACON_MISSED: 3945 { 3946 struct iwn_beacon_missed *miss = 3947 (struct iwn_beacon_missed *)(desc + 1); 3948 int misses; 3949 3950 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3951 BUS_DMASYNC_POSTREAD); 3952 misses = le32toh(miss->consecutive); 3953 3954 DPRINTF(sc, IWN_DEBUG_STATE, 3955 "%s: beacons missed %d/%d\n", __func__, 3956 misses, le32toh(miss->total)); 3957 /* 3958 * If more than 5 consecutive beacons are missed, 3959 * reinitialize the sensitivity state machine. 3960 */ 3961 if (vap->iv_state == IEEE80211_S_RUN && 3962 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 3963 if (misses > 5) 3964 (void)iwn_init_sensitivity(sc); 3965 if (misses >= vap->iv_bmissthreshold) { 3966 IWN_UNLOCK(sc); 3967 ieee80211_beacon_miss(ic); 3968 IWN_LOCK(sc); 3969 } 3970 } 3971 break; 3972 } 3973 case IWN_UC_READY: 3974 { 3975 struct iwn_ucode_info *uc = 3976 (struct iwn_ucode_info *)(desc + 1); 3977 3978 /* The microcontroller is ready. */ 3979 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3980 BUS_DMASYNC_POSTREAD); 3981 DPRINTF(sc, IWN_DEBUG_RESET, 3982 "microcode alive notification version=%d.%d " 3983 "subtype=%x alive=%x\n", uc->major, uc->minor, 3984 uc->subtype, le32toh(uc->valid)); 3985 3986 if (le32toh(uc->valid) != 1) { 3987 device_printf(sc->sc_dev, 3988 "microcontroller initialization failed"); 3989 break; 3990 } 3991 if (uc->subtype == IWN_UCODE_INIT) { 3992 /* Save microcontroller report. */ 3993 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 3994 } 3995 /* Save the address of the error log in SRAM. */ 3996 sc->errptr = le32toh(uc->errptr); 3997 break; 3998 } 3999 case IWN_STATE_CHANGED: 4000 { 4001 /* 4002 * State change allows hardware switch change to be 4003 * noted. However, we handle this in iwn_intr as we 4004 * get both the enable/disble intr. 4005 */ 4006 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 4007 BUS_DMASYNC_POSTREAD); 4008 #ifdef IWN_DEBUG 4009 uint32_t *status = (uint32_t *)(desc + 1); 4010 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE, 4011 "state changed to %x\n", 4012 le32toh(*status)); 4013 #endif 4014 break; 4015 } 4016 case IWN_START_SCAN: 4017 { 4018 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 4019 BUS_DMASYNC_POSTREAD); 4020 #ifdef IWN_DEBUG 4021 struct iwn_start_scan *scan = 4022 (struct iwn_start_scan *)(desc + 1); 4023 DPRINTF(sc, IWN_DEBUG_ANY, 4024 "%s: scanning channel %d status %x\n", 4025 __func__, scan->chan, le32toh(scan->status)); 4026 #endif 4027 break; 4028 } 4029 case IWN_STOP_SCAN: 4030 { 4031 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 4032 BUS_DMASYNC_POSTREAD); 4033 #ifdef IWN_DEBUG 4034 struct iwn_stop_scan *scan = 4035 (struct iwn_stop_scan *)(desc + 1); 4036 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN, 4037 "scan finished nchan=%d status=%d chan=%d\n", 4038 scan->nchan, scan->status, scan->chan); 4039 #endif 4040 sc->sc_is_scanning = 0; 4041 IWN_UNLOCK(sc); 4042 ieee80211_scan_next(vap); 4043 IWN_LOCK(sc); 4044 break; 4045 } 4046 case IWN5000_CALIBRATION_RESULT: 4047 iwn5000_rx_calib_results(sc, desc, data); 4048 break; 4049 4050 case IWN5000_CALIBRATION_DONE: 4051 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 4052 wakeup(sc); 4053 break; 4054 } 4055 4056 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 4057 } 4058 4059 /* Tell the firmware what we have processed. */ 4060 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 4061 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 4062 } 4063 4064 /* 4065 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 4066 * from power-down sleep mode. 4067 */ 4068 static void 4069 iwn_wakeup_intr(struct iwn_softc *sc) 4070 { 4071 int qid; 4072 4073 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 4074 __func__); 4075 4076 /* Wakeup RX and TX rings. */ 4077 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 4078 for (qid = 0; qid < sc->ntxqs; qid++) { 4079 struct iwn_tx_ring *ring = &sc->txq[qid]; 4080 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 4081 } 4082 } 4083 4084 static void 4085 iwn_rftoggle_intr(struct iwn_softc *sc) 4086 { 4087 struct ieee80211com *ic = &sc->sc_ic; 4088 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 4089 4090 IWN_LOCK_ASSERT(sc); 4091 4092 device_printf(sc->sc_dev, "RF switch: radio %s\n", 4093 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 4094 if (tmp & IWN_GP_CNTRL_RFKILL) 4095 ieee80211_runtask(ic, &sc->sc_radioon_task); 4096 else 4097 ieee80211_runtask(ic, &sc->sc_radiooff_task); 4098 } 4099 4100 /* 4101 * Dump the error log of the firmware when a firmware panic occurs. Although 4102 * we can't debug the firmware because it is neither open source nor free, it 4103 * can help us to identify certain classes of problems. 4104 */ 4105 static void 4106 iwn_fatal_intr(struct iwn_softc *sc) 4107 { 4108 struct iwn_fw_dump dump; 4109 int i; 4110 4111 IWN_LOCK_ASSERT(sc); 4112 4113 /* Force a complete recalibration on next init. */ 4114 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 4115 4116 /* Check that the error log address is valid. */ 4117 if (sc->errptr < IWN_FW_DATA_BASE || 4118 sc->errptr + sizeof (dump) > 4119 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 4120 kprintf("%s: bad firmware error log address 0x%08x\n", __func__, 4121 sc->errptr); 4122 return; 4123 } 4124 if (iwn_nic_lock(sc) != 0) { 4125 kprintf("%s: could not read firmware error log\n", __func__); 4126 return; 4127 } 4128 /* Read firmware error log from SRAM. */ 4129 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 4130 sizeof (dump) / sizeof (uint32_t)); 4131 iwn_nic_unlock(sc); 4132 4133 if (dump.valid == 0) { 4134 kprintf("%s: firmware error log is empty\n", __func__); 4135 return; 4136 } 4137 kprintf("firmware error log:\n"); 4138 kprintf(" error type = \"%s\" (0x%08X)\n", 4139 (dump.id < nitems(iwn_fw_errmsg)) ? 4140 iwn_fw_errmsg[dump.id] : "UNKNOWN", 4141 dump.id); 4142 kprintf(" program counter = 0x%08X\n", dump.pc); 4143 kprintf(" source line = 0x%08X\n", dump.src_line); 4144 kprintf(" error data = 0x%08X%08X\n", 4145 dump.error_data[0], dump.error_data[1]); 4146 kprintf(" branch link = 0x%08X%08X\n", 4147 dump.branch_link[0], dump.branch_link[1]); 4148 kprintf(" interrupt link = 0x%08X%08X\n", 4149 dump.interrupt_link[0], dump.interrupt_link[1]); 4150 kprintf(" time = %u\n", dump.time[0]); 4151 4152 /* Dump driver status (TX and RX rings) while we're here. */ 4153 kprintf("driver status:\n"); 4154 for (i = 0; i < sc->ntxqs; i++) { 4155 struct iwn_tx_ring *ring = &sc->txq[i]; 4156 kprintf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 4157 i, ring->qid, ring->cur, ring->queued); 4158 } 4159 kprintf(" rx ring: cur=%d\n", sc->rxq.cur); 4160 } 4161 4162 static void 4163 iwn_intr(void *arg) 4164 { 4165 struct iwn_softc *sc = arg; 4166 uint32_t r1, r2, tmp; 4167 4168 IWN_LOCK(sc); 4169 4170 /* Disable interrupts. */ 4171 IWN_WRITE(sc, IWN_INT_MASK, 0); 4172 4173 /* Read interrupts from ICT (fast) or from registers (slow). */ 4174 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4175 tmp = 0; 4176 while (sc->ict[sc->ict_cur] != 0) { 4177 tmp |= sc->ict[sc->ict_cur]; 4178 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 4179 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 4180 } 4181 tmp = le32toh(tmp); 4182 if (tmp == 0xffffffff) /* Shouldn't happen. */ 4183 tmp = 0; 4184 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 4185 tmp |= 0x8000; 4186 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 4187 r2 = 0; /* Unused. */ 4188 } else { 4189 r1 = IWN_READ(sc, IWN_INT); 4190 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) { 4191 IWN_UNLOCK(sc); 4192 return; /* Hardware gone! */ 4193 } 4194 r2 = IWN_READ(sc, IWN_FH_INT); 4195 } 4196 4197 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 4198 , r1, r2); 4199 4200 if (r1 == 0 && r2 == 0) 4201 goto done; /* Interrupt not for us. */ 4202 4203 /* Acknowledge interrupts. */ 4204 IWN_WRITE(sc, IWN_INT, r1); 4205 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 4206 IWN_WRITE(sc, IWN_FH_INT, r2); 4207 4208 if (r1 & IWN_INT_RF_TOGGLED) { 4209 iwn_rftoggle_intr(sc); 4210 goto done; 4211 } 4212 if (r1 & IWN_INT_CT_REACHED) { 4213 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 4214 __func__); 4215 } 4216 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 4217 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 4218 __func__); 4219 #ifdef IWN_DEBUG 4220 iwn_debug_register(sc); 4221 #endif 4222 /* Dump firmware error log and stop. */ 4223 iwn_fatal_intr(sc); 4224 4225 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task); 4226 goto done; 4227 } 4228 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 4229 (r2 & IWN_FH_INT_RX)) { 4230 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4231 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 4232 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 4233 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4234 IWN_INT_PERIODIC_DIS); 4235 iwn_notif_intr(sc); 4236 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 4237 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4238 IWN_INT_PERIODIC_ENA); 4239 } 4240 } else 4241 iwn_notif_intr(sc); 4242 } 4243 4244 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 4245 if (sc->sc_flags & IWN_FLAG_USE_ICT) 4246 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 4247 wakeup(sc); /* FH DMA transfer completed. */ 4248 } 4249 4250 if (r1 & IWN_INT_ALIVE) 4251 wakeup(sc); /* Firmware is alive. */ 4252 4253 if (r1 & IWN_INT_WAKEUP) 4254 iwn_wakeup_intr(sc); 4255 4256 done: 4257 /* Re-enable interrupts. */ 4258 if (sc->sc_flags & IWN_FLAG_RUNNING) 4259 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4260 4261 IWN_UNLOCK(sc); 4262 } 4263 4264 /* 4265 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 4266 * 5000 adapters use a slightly different format). 4267 */ 4268 static void 4269 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4270 uint16_t len) 4271 { 4272 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 4273 4274 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4275 4276 *w = htole16(len + 8); 4277 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4278 BUS_DMASYNC_PREWRITE); 4279 if (idx < IWN_SCHED_WINSZ) { 4280 *(w + IWN_TX_RING_COUNT) = *w; 4281 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4282 BUS_DMASYNC_PREWRITE); 4283 } 4284 } 4285 4286 static void 4287 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4288 uint16_t len) 4289 { 4290 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4291 4292 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4293 4294 *w = htole16(id << 12 | (len + 8)); 4295 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4296 BUS_DMASYNC_PREWRITE); 4297 if (idx < IWN_SCHED_WINSZ) { 4298 *(w + IWN_TX_RING_COUNT) = *w; 4299 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4300 BUS_DMASYNC_PREWRITE); 4301 } 4302 } 4303 4304 #ifdef notyet 4305 static void 4306 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 4307 { 4308 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4309 4310 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4311 4312 *w = (*w & htole16(0xf000)) | htole16(1); 4313 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4314 BUS_DMASYNC_PREWRITE); 4315 if (idx < IWN_SCHED_WINSZ) { 4316 *(w + IWN_TX_RING_COUNT) = *w; 4317 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4318 BUS_DMASYNC_PREWRITE); 4319 } 4320 } 4321 #endif 4322 4323 /* 4324 * Check whether OFDM 11g protection will be enabled for the given rate. 4325 * 4326 * The original driver code only enabled protection for OFDM rates. 4327 * It didn't check to see whether it was operating in 11a or 11bg mode. 4328 */ 4329 static int 4330 iwn_check_rate_needs_protection(struct iwn_softc *sc, 4331 struct ieee80211vap *vap, uint8_t rate) 4332 { 4333 struct ieee80211com *ic = vap->iv_ic; 4334 4335 /* 4336 * Not in 2GHz mode? Then there's no need to enable OFDM 4337 * 11bg protection. 4338 */ 4339 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { 4340 return (0); 4341 } 4342 4343 /* 4344 * 11bg protection not enabled? Then don't use it. 4345 */ 4346 if ((ic->ic_flags & IEEE80211_F_USEPROT) == 0) 4347 return (0); 4348 4349 /* 4350 * If it's an 11n rate - no protection. 4351 * We'll do it via a specific 11n check. 4352 */ 4353 if (rate & IEEE80211_RATE_MCS) { 4354 return (0); 4355 } 4356 4357 /* 4358 * Do a rate table lookup. If the PHY is CCK, 4359 * don't do protection. 4360 */ 4361 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK) 4362 return (0); 4363 4364 /* 4365 * Yup, enable protection. 4366 */ 4367 return (1); 4368 } 4369 4370 /* 4371 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into 4372 * the link quality table that reflects this particular entry. 4373 */ 4374 static int 4375 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni, 4376 uint8_t rate) 4377 { 4378 struct ieee80211_rateset *rs; 4379 int is_11n; 4380 int nr; 4381 int i; 4382 uint8_t cmp_rate; 4383 4384 /* 4385 * Figure out if we're using 11n or not here. 4386 */ 4387 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) 4388 is_11n = 1; 4389 else 4390 is_11n = 0; 4391 4392 /* 4393 * Use the correct rate table. 4394 */ 4395 if (is_11n) { 4396 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 4397 nr = ni->ni_htrates.rs_nrates; 4398 } else { 4399 rs = &ni->ni_rates; 4400 nr = rs->rs_nrates; 4401 } 4402 4403 /* 4404 * Find the relevant link quality entry in the table. 4405 */ 4406 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) { 4407 /* 4408 * The link quality table index starts at 0 == highest 4409 * rate, so we walk the rate table backwards. 4410 */ 4411 cmp_rate = rs->rs_rates[(nr - 1) - i]; 4412 if (rate & IEEE80211_RATE_MCS) 4413 cmp_rate |= IEEE80211_RATE_MCS; 4414 4415 #if 0 4416 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n", 4417 __func__, 4418 i, 4419 nr, 4420 rate, 4421 cmp_rate); 4422 #endif 4423 4424 if (cmp_rate == rate) 4425 return (i); 4426 } 4427 4428 /* Failed? Start at the end */ 4429 return (IWN_MAX_TX_RETRIES - 1); 4430 } 4431 4432 static int 4433 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 4434 { 4435 struct iwn_ops *ops = &sc->ops; 4436 const struct ieee80211_txparam *tp; 4437 struct ieee80211vap *vap = ni->ni_vap; 4438 struct ieee80211com *ic = ni->ni_ic; 4439 struct iwn_node *wn = (void *)ni; 4440 struct iwn_tx_ring *ring; 4441 struct iwn_tx_desc *desc; 4442 struct iwn_tx_data *data; 4443 struct iwn_tx_cmd *cmd; 4444 struct iwn_cmd_data *tx; 4445 struct ieee80211_frame *wh; 4446 struct ieee80211_key *k = NULL; 4447 struct mbuf *m1; 4448 uint32_t flags; 4449 uint16_t qos; 4450 u_int hdrlen; 4451 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4452 uint8_t tid, type; 4453 int ac, i, totlen, error, pad, nsegs = 0, rate; 4454 4455 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4456 4457 IWN_LOCK_ASSERT(sc); 4458 4459 wh = mtod(m, struct ieee80211_frame *); 4460 hdrlen = ieee80211_anyhdrsize(wh); 4461 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4462 4463 /* Select EDCA Access Category and TX ring for this frame. */ 4464 if (IEEE80211_QOS_HAS_SEQ(wh)) { 4465 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 4466 tid = qos & IEEE80211_QOS_TID; 4467 } else { 4468 qos = 0; 4469 tid = 0; 4470 } 4471 ac = M_WME_GETAC(m); 4472 if (m->m_flags & M_AMPDU_MPDU) { 4473 uint16_t seqno; 4474 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 4475 4476 if (!IEEE80211_AMPDU_RUNNING(tap)) { 4477 return EINVAL; 4478 } 4479 4480 /* 4481 * Queue this frame to the hardware ring that we've 4482 * negotiated AMPDU TX on. 4483 * 4484 * Note that the sequence number must match the TX slot 4485 * being used! 4486 */ 4487 ac = *(int *)tap->txa_private; 4488 seqno = ni->ni_txseqs[tid]; 4489 *(uint16_t *)wh->i_seq = 4490 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 4491 ring = &sc->txq[ac]; 4492 if ((seqno % 256) != ring->cur) { 4493 device_printf(sc->sc_dev, 4494 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n", 4495 __func__, 4496 m, 4497 seqno, 4498 seqno % 256, 4499 ring->cur); 4500 } 4501 ni->ni_txseqs[tid]++; 4502 } 4503 ring = &sc->txq[ac]; 4504 desc = &ring->desc[ring->cur]; 4505 data = &ring->data[ring->cur]; 4506 4507 /* Choose a TX rate index. */ 4508 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 4509 if (type == IEEE80211_FC0_TYPE_MGT) 4510 rate = tp->mgmtrate; 4511 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 4512 rate = tp->mcastrate; 4513 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 4514 rate = tp->ucastrate; 4515 else if (m->m_flags & M_EAPOL) 4516 rate = tp->mgmtrate; 4517 else { 4518 /* XXX pass pktlen */ 4519 (void) ieee80211_ratectl_rate(ni, NULL, 0); 4520 rate = ni->ni_txrate; 4521 } 4522 4523 /* Encrypt the frame if need be. */ 4524 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 4525 /* Retrieve key for TX. */ 4526 k = ieee80211_crypto_encap(ni, m); 4527 if (k == NULL) { 4528 return ENOBUFS; 4529 } 4530 /* 802.11 header may have moved. */ 4531 wh = mtod(m, struct ieee80211_frame *); 4532 } 4533 totlen = m->m_pkthdr.len; 4534 4535 if (ieee80211_radiotap_active_vap(vap)) { 4536 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4537 4538 tap->wt_flags = 0; 4539 tap->wt_rate = rate; 4540 if (k != NULL) 4541 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4542 4543 ieee80211_radiotap_tx(vap, m); 4544 } 4545 4546 /* Prepare TX firmware command. */ 4547 cmd = &ring->cmd[ring->cur]; 4548 cmd->code = IWN_CMD_TX_DATA; 4549 cmd->flags = 0; 4550 cmd->qid = ring->qid; 4551 cmd->idx = ring->cur; 4552 4553 tx = (struct iwn_cmd_data *)cmd->data; 4554 /* NB: No need to clear tx, all fields are reinitialized here. */ 4555 tx->scratch = 0; /* clear "scratch" area */ 4556 4557 flags = 0; 4558 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4559 /* Unicast frame, check if an ACK is expected. */ 4560 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 4561 IEEE80211_QOS_ACKPOLICY_NOACK) 4562 flags |= IWN_TX_NEED_ACK; 4563 } 4564 if ((wh->i_fc[0] & 4565 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 4566 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 4567 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 4568 4569 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 4570 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 4571 4572 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 4573 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4574 /* NB: Group frames are sent using CCK in 802.11b/g. */ 4575 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 4576 flags |= IWN_TX_NEED_RTS; 4577 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) { 4578 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4579 flags |= IWN_TX_NEED_CTS; 4580 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4581 flags |= IWN_TX_NEED_RTS; 4582 } else if ((rate & IEEE80211_RATE_MCS) && 4583 (ic->ic_htprotmode == IEEE80211_PROT_RTSCTS)) { 4584 flags |= IWN_TX_NEED_RTS; 4585 } 4586 4587 /* XXX HT protection? */ 4588 4589 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 4590 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4591 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4592 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 4593 flags |= IWN_TX_NEED_PROTECTION; 4594 } else 4595 flags |= IWN_TX_FULL_TXOP; 4596 } 4597 } 4598 4599 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4600 type != IEEE80211_FC0_TYPE_DATA) 4601 tx->id = sc->broadcast_id; 4602 else 4603 tx->id = wn->id; 4604 4605 if (type == IEEE80211_FC0_TYPE_MGT) { 4606 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4607 4608 /* Tell HW to set timestamp in probe responses. */ 4609 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4610 flags |= IWN_TX_INSERT_TSTAMP; 4611 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4612 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4613 tx->timeout = htole16(3); 4614 else 4615 tx->timeout = htole16(2); 4616 } else 4617 tx->timeout = htole16(0); 4618 4619 if (hdrlen & 3) { 4620 /* First segment length must be a multiple of 4. */ 4621 flags |= IWN_TX_NEED_PADDING; 4622 pad = 4 - (hdrlen & 3); 4623 } else 4624 pad = 0; 4625 4626 tx->len = htole16(totlen); 4627 tx->tid = tid; 4628 tx->rts_ntries = 60; 4629 tx->data_ntries = 15; 4630 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4631 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4632 if (tx->id == sc->broadcast_id) { 4633 /* Group or management frame. */ 4634 tx->linkq = 0; 4635 } else { 4636 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate); 4637 flags |= IWN_TX_LINKQ; /* enable MRR */ 4638 } 4639 4640 /* Set physical address of "scratch area". */ 4641 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4642 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4643 4644 /* Copy 802.11 header in TX command. */ 4645 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4646 4647 /* Trim 802.11 header. */ 4648 m_adj(m, hdrlen); 4649 tx->security = 0; 4650 tx->flags = htole32(flags); 4651 4652 #if defined(__DragonFly__) 4653 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 4654 data->map, m, 4655 segs, IWN_MAX_SCATTER - 1, 4656 &nsegs, BUS_DMA_NOWAIT); 4657 #else 4658 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4659 &nsegs, BUS_DMA_NOWAIT); 4660 #endif 4661 if (error != 0) { 4662 if (error != EFBIG) { 4663 device_printf(sc->sc_dev, 4664 "%s: can't map mbuf (error %d)\n", __func__, error); 4665 return error; 4666 } 4667 /* Too many DMA segments, linearize mbuf. */ 4668 #if defined(__DragonFly__) 4669 m1 = m_defrag(m, M_NOWAIT); 4670 #else 4671 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4672 #endif 4673 if (m1 == NULL) { 4674 device_printf(sc->sc_dev, 4675 "%s: could not defrag mbuf\n", __func__); 4676 return ENOBUFS; 4677 } 4678 m = m1; 4679 4680 #if defined(__DragonFly__) 4681 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 4682 data->map, m, 4683 segs, IWN_MAX_SCATTER - 1, 4684 &nsegs, BUS_DMA_NOWAIT); 4685 #else 4686 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4687 segs, &nsegs, BUS_DMA_NOWAIT); 4688 #endif 4689 if (error != 0) { 4690 device_printf(sc->sc_dev, 4691 "%s: can't map mbuf (error %d)\n", __func__, error); 4692 return error; 4693 } 4694 } 4695 4696 data->m = m; 4697 data->ni = ni; 4698 4699 DPRINTF(sc, IWN_DEBUG_XMIT, 4700 "%s: qid %d idx %d len %d nsegs %d flags 0x%08x rate 0x%04x plcp 0x%08x\n", 4701 __func__, 4702 ring->qid, 4703 ring->cur, 4704 m->m_pkthdr.len, 4705 nsegs, 4706 flags, 4707 rate, 4708 tx->rate); 4709 4710 /* Fill TX descriptor. */ 4711 desc->nsegs = 1; 4712 if (m->m_len != 0) 4713 desc->nsegs += nsegs; 4714 /* First DMA segment is used by the TX command. */ 4715 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4716 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4717 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4718 /* Other DMA segments are for data payload. */ 4719 seg = &segs[0]; 4720 for (i = 1; i <= nsegs; i++) { 4721 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4722 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4723 seg->ds_len << 4); 4724 seg++; 4725 } 4726 4727 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4728 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4729 BUS_DMASYNC_PREWRITE); 4730 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4731 BUS_DMASYNC_PREWRITE); 4732 4733 /* Update TX scheduler. */ 4734 if (ring->qid >= sc->firstaggqueue) 4735 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4736 4737 /* Kick TX ring. */ 4738 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4739 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4740 4741 /* Mark TX ring as full if we reach a certain threshold. */ 4742 if (++ring->queued > IWN_TX_RING_HIMARK) 4743 sc->qfullmsk |= 1 << ring->qid; 4744 4745 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4746 4747 return 0; 4748 } 4749 4750 static int 4751 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 4752 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 4753 { 4754 struct iwn_ops *ops = &sc->ops; 4755 struct ieee80211vap *vap = ni->ni_vap; 4756 struct iwn_tx_cmd *cmd; 4757 struct iwn_cmd_data *tx; 4758 struct ieee80211_frame *wh; 4759 struct iwn_tx_ring *ring; 4760 struct iwn_tx_desc *desc; 4761 struct iwn_tx_data *data; 4762 struct mbuf *m1; 4763 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4764 uint32_t flags; 4765 u_int hdrlen; 4766 int ac, totlen, error, pad, nsegs = 0, i, rate; 4767 uint8_t type; 4768 4769 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4770 4771 IWN_LOCK_ASSERT(sc); 4772 4773 wh = mtod(m, struct ieee80211_frame *); 4774 hdrlen = ieee80211_anyhdrsize(wh); 4775 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4776 4777 ac = params->ibp_pri & 3; 4778 4779 ring = &sc->txq[ac]; 4780 desc = &ring->desc[ring->cur]; 4781 data = &ring->data[ring->cur]; 4782 4783 /* Choose a TX rate. */ 4784 rate = params->ibp_rate0; 4785 totlen = m->m_pkthdr.len; 4786 4787 /* Prepare TX firmware command. */ 4788 cmd = &ring->cmd[ring->cur]; 4789 cmd->code = IWN_CMD_TX_DATA; 4790 cmd->flags = 0; 4791 cmd->qid = ring->qid; 4792 cmd->idx = ring->cur; 4793 4794 tx = (struct iwn_cmd_data *)cmd->data; 4795 /* NB: No need to clear tx, all fields are reinitialized here. */ 4796 tx->scratch = 0; /* clear "scratch" area */ 4797 4798 flags = 0; 4799 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 4800 flags |= IWN_TX_NEED_ACK; 4801 if (params->ibp_flags & IEEE80211_BPF_RTS) { 4802 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4803 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4804 flags &= ~IWN_TX_NEED_RTS; 4805 flags |= IWN_TX_NEED_PROTECTION; 4806 } else 4807 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 4808 } 4809 if (params->ibp_flags & IEEE80211_BPF_CTS) { 4810 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4811 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4812 flags &= ~IWN_TX_NEED_CTS; 4813 flags |= IWN_TX_NEED_PROTECTION; 4814 } else 4815 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 4816 } 4817 if (type == IEEE80211_FC0_TYPE_MGT) { 4818 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4819 4820 /* Tell HW to set timestamp in probe responses. */ 4821 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4822 flags |= IWN_TX_INSERT_TSTAMP; 4823 4824 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4825 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4826 tx->timeout = htole16(3); 4827 else 4828 tx->timeout = htole16(2); 4829 } else 4830 tx->timeout = htole16(0); 4831 4832 if (hdrlen & 3) { 4833 /* First segment length must be a multiple of 4. */ 4834 flags |= IWN_TX_NEED_PADDING; 4835 pad = 4 - (hdrlen & 3); 4836 } else 4837 pad = 0; 4838 4839 if (ieee80211_radiotap_active_vap(vap)) { 4840 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4841 4842 tap->wt_flags = 0; 4843 tap->wt_rate = rate; 4844 4845 ieee80211_radiotap_tx(vap, m); 4846 } 4847 4848 tx->len = htole16(totlen); 4849 tx->tid = 0; 4850 tx->id = sc->broadcast_id; 4851 tx->rts_ntries = params->ibp_try1; 4852 tx->data_ntries = params->ibp_try0; 4853 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4854 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4855 4856 /* Group or management frame. */ 4857 tx->linkq = 0; 4858 4859 /* Set physical address of "scratch area". */ 4860 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4861 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4862 4863 /* Copy 802.11 header in TX command. */ 4864 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4865 4866 /* Trim 802.11 header. */ 4867 m_adj(m, hdrlen); 4868 tx->security = 0; 4869 tx->flags = htole32(flags); 4870 4871 #if defined(__DragonFly__) 4872 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map, 4873 m, segs, IWN_MAX_SCATTER - 1, 4874 &nsegs, BUS_DMA_NOWAIT); 4875 #else 4876 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs, 4877 &nsegs, BUS_DMA_NOWAIT); 4878 #endif 4879 if (error != 0) { 4880 if (error != EFBIG) { 4881 device_printf(sc->sc_dev, 4882 "%s: can't map mbuf (error %d)\n", __func__, error); 4883 return error; 4884 } 4885 /* Too many DMA segments, linearize mbuf. */ 4886 #if defined(__DragonFly__) 4887 m1 = m_defrag(m, M_NOWAIT); 4888 #else 4889 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER - 1); 4890 #endif 4891 if (m1 == NULL) { 4892 device_printf(sc->sc_dev, 4893 "%s: could not defrag mbuf\n", __func__); 4894 return ENOBUFS; 4895 } 4896 m = m1; 4897 4898 #if defined(__DragonFly__) 4899 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 4900 data->map, m, 4901 segs, IWN_MAX_SCATTER - 1, 4902 &nsegs, BUS_DMA_NOWAIT); 4903 #else 4904 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, 4905 segs, &nsegs, BUS_DMA_NOWAIT); 4906 #endif 4907 if (error != 0) { 4908 device_printf(sc->sc_dev, 4909 "%s: can't map mbuf (error %d)\n", __func__, error); 4910 return error; 4911 } 4912 } 4913 4914 data->m = m; 4915 data->ni = ni; 4916 4917 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 4918 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 4919 4920 /* Fill TX descriptor. */ 4921 desc->nsegs = 1; 4922 if (m->m_len != 0) 4923 desc->nsegs += nsegs; 4924 /* First DMA segment is used by the TX command. */ 4925 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4926 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4927 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4928 /* Other DMA segments are for data payload. */ 4929 seg = &segs[0]; 4930 for (i = 1; i <= nsegs; i++) { 4931 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4932 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4933 seg->ds_len << 4); 4934 seg++; 4935 } 4936 4937 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4938 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4939 BUS_DMASYNC_PREWRITE); 4940 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4941 BUS_DMASYNC_PREWRITE); 4942 4943 /* Update TX scheduler. */ 4944 if (ring->qid >= sc->firstaggqueue) 4945 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4946 4947 /* Kick TX ring. */ 4948 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4949 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4950 4951 /* Mark TX ring as full if we reach a certain threshold. */ 4952 if (++ring->queued > IWN_TX_RING_HIMARK) 4953 sc->qfullmsk |= 1 << ring->qid; 4954 4955 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4956 4957 return 0; 4958 } 4959 4960 static void 4961 iwn_xmit_task(void *arg0, int pending) 4962 { 4963 struct iwn_softc *sc = arg0; 4964 struct ieee80211_node *ni; 4965 struct mbuf *m; 4966 int error; 4967 struct ieee80211_bpf_params p; 4968 int have_p; 4969 4970 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: called\n", __func__); 4971 4972 IWN_LOCK(sc); 4973 /* 4974 * Dequeue frames, attempt to transmit, 4975 * then disable beaconwait when we're done. 4976 */ 4977 while ((m = mbufq_dequeue(&sc->sc_xmit_queue)) != NULL) { 4978 have_p = 0; 4979 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4980 4981 /* Get xmit params if appropriate */ 4982 if (ieee80211_get_xmit_params(m, &p) == 0) 4983 have_p = 1; 4984 4985 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: m=%p, have_p=%d\n", 4986 __func__, m, have_p); 4987 4988 /* If we have xmit params, use them */ 4989 if (have_p) 4990 error = iwn_tx_data_raw(sc, m, ni, &p); 4991 else 4992 error = iwn_tx_data(sc, m, ni); 4993 4994 if (error != 0) { 4995 if_inc_counter(ni->ni_vap->iv_ifp, 4996 IFCOUNTER_OERRORS, 1); 4997 ieee80211_free_node(ni); 4998 m_freem(m); 4999 } 5000 } 5001 5002 sc->sc_beacon_wait = 0; 5003 IWN_UNLOCK(sc); 5004 } 5005 5006 /* 5007 * raw frame xmit - free node/reference if failed. 5008 */ 5009 static int 5010 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 5011 const struct ieee80211_bpf_params *params) 5012 { 5013 struct ieee80211com *ic = ni->ni_ic; 5014 struct iwn_softc *sc = ic->ic_softc; 5015 int error = 0; 5016 5017 DPRINTF(sc, IWN_DEBUG_XMIT | IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5018 5019 IWN_LOCK(sc); 5020 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0) { 5021 m_freem(m); 5022 IWN_UNLOCK(sc); 5023 return (ENETDOWN); 5024 } 5025 5026 /* queue frame if we have to */ 5027 if (sc->sc_beacon_wait) { 5028 if (iwn_xmit_queue_enqueue(sc, m) != 0) { 5029 m_freem(m); 5030 IWN_UNLOCK(sc); 5031 return (ENOBUFS); 5032 } 5033 /* Queued, so just return OK */ 5034 IWN_UNLOCK(sc); 5035 return (0); 5036 } 5037 5038 if (params == NULL) { 5039 /* 5040 * Legacy path; interpret frame contents to decide 5041 * precisely how to send the frame. 5042 */ 5043 error = iwn_tx_data(sc, m, ni); 5044 } else { 5045 /* 5046 * Caller supplied explicit parameters to use in 5047 * sending the frame. 5048 */ 5049 error = iwn_tx_data_raw(sc, m, ni, params); 5050 } 5051 if (error == 0) 5052 sc->sc_tx_timer = 5; 5053 else 5054 m_freem(m); 5055 5056 IWN_UNLOCK(sc); 5057 5058 DPRINTF(sc, IWN_DEBUG_TRACE | IWN_DEBUG_XMIT, "->%s: end\n",__func__); 5059 5060 return (error); 5061 } 5062 5063 /* 5064 * transmit - don't free mbuf if failed; don't free node ref if failed. 5065 */ 5066 static int 5067 iwn_transmit(struct ieee80211com *ic, struct mbuf *m) 5068 { 5069 struct iwn_softc *sc = ic->ic_softc; 5070 struct ieee80211_node *ni; 5071 int error; 5072 5073 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 5074 5075 IWN_LOCK(sc); 5076 if ((sc->sc_flags & IWN_FLAG_RUNNING) == 0 || sc->sc_beacon_wait) { 5077 IWN_UNLOCK(sc); 5078 return (ENXIO); 5079 } 5080 5081 if (sc->qfullmsk) { 5082 IWN_UNLOCK(sc); 5083 return (ENOBUFS); 5084 } 5085 5086 error = iwn_tx_data(sc, m, ni); 5087 if (!error) 5088 sc->sc_tx_timer = 5; 5089 IWN_UNLOCK(sc); 5090 return (error); 5091 } 5092 5093 static void 5094 iwn_watchdog(void *arg) 5095 { 5096 struct iwn_softc *sc = arg; 5097 struct ieee80211com *ic = &sc->sc_ic; 5098 5099 IWN_LOCK_ASSERT(sc); 5100 5101 KASSERT(sc->sc_flags & IWN_FLAG_RUNNING, ("not running")); 5102 5103 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5104 5105 if (sc->sc_tx_timer > 0) { 5106 if (--sc->sc_tx_timer == 0) { 5107 ic_printf(ic, "device timeout\n"); 5108 ieee80211_restart_all(ic); 5109 return; 5110 } 5111 } 5112 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 5113 } 5114 5115 #if defined(__DragonFly__) 5116 static int 5117 iwn_cdev_open(struct dev_open_args *ap) 5118 #else 5119 static int 5120 iwn_cdev_open(struct cdev *dev, int flags, int type, struct thread *td) 5121 #endif 5122 { 5123 5124 return (0); 5125 } 5126 5127 #if defined(__DragonFly__) 5128 static int 5129 iwn_cdev_close(struct dev_close_args *ap) 5130 #else 5131 static int 5132 iwn_cdev_close(struct cdev *dev, int flags, int type, struct thread *td) 5133 #endif 5134 { 5135 5136 return (0); 5137 } 5138 5139 #if defined(__DragonFly__) 5140 static int 5141 iwn_cdev_ioctl(struct dev_ioctl_args *ap) 5142 { 5143 cdev_t dev = ap->a_head.a_dev; 5144 unsigned long cmd = ap->a_cmd; 5145 caddr_t data = ap->a_data; 5146 struct thread *td = curthread; 5147 #else 5148 static int 5149 iwn_cdev_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag, 5150 struct thread *td) 5151 { 5152 #endif 5153 int rc; 5154 struct iwn_softc *sc = dev->si_drv1; 5155 struct iwn_ioctl_data *d; 5156 5157 rc = caps_priv_check((td ? td->td_ucred : NULL), 5158 SYSCAP_NODRIVER | __SYSCAP_NULLCRED); 5159 if (rc != 0) 5160 return (0); 5161 5162 switch (cmd) { 5163 case SIOCGIWNSTATS: 5164 d = (struct iwn_ioctl_data *) data; 5165 IWN_LOCK(sc); 5166 /* XXX validate permissions/memory/etc? */ 5167 rc = copyout(&sc->last_stat, d->dst_addr, sizeof(struct iwn_stats)); 5168 IWN_UNLOCK(sc); 5169 break; 5170 case SIOCZIWNSTATS: 5171 IWN_LOCK(sc); 5172 memset(&sc->last_stat, 0, sizeof(struct iwn_stats)); 5173 IWN_UNLOCK(sc); 5174 break; 5175 default: 5176 rc = EINVAL; 5177 break; 5178 } 5179 return (rc); 5180 } 5181 5182 static int 5183 iwn_ioctl(struct ieee80211com *ic, u_long cmd, void *data) 5184 { 5185 5186 return (ENOTTY); 5187 } 5188 5189 static void 5190 iwn_parent(struct ieee80211com *ic) 5191 { 5192 struct iwn_softc *sc = ic->ic_softc; 5193 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 5194 int startall = 0, stop = 0; 5195 5196 IWN_LOCK(sc); 5197 if (ic->ic_nrunning > 0) { 5198 if (!(sc->sc_flags & IWN_FLAG_RUNNING)) { 5199 iwn_init_locked(sc); 5200 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 5201 startall = 1; 5202 else 5203 stop = 1; 5204 } 5205 } else if (sc->sc_flags & IWN_FLAG_RUNNING) 5206 iwn_stop_locked(sc); 5207 IWN_UNLOCK(sc); 5208 if (startall) 5209 ieee80211_start_all(ic); 5210 else if (vap != NULL && stop) 5211 ieee80211_stop(vap); 5212 } 5213 5214 /* 5215 * Send a command to the firmware. 5216 */ 5217 static int 5218 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 5219 { 5220 struct iwn_tx_ring *ring; 5221 struct iwn_tx_desc *desc; 5222 struct iwn_tx_data *data; 5223 struct iwn_tx_cmd *cmd; 5224 struct mbuf *m; 5225 bus_addr_t paddr; 5226 int totlen, error; 5227 int cmd_queue_num; 5228 5229 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5230 5231 if (async == 0) 5232 IWN_LOCK_ASSERT(sc); 5233 5234 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 5235 cmd_queue_num = IWN_PAN_CMD_QUEUE; 5236 else 5237 cmd_queue_num = IWN_CMD_QUEUE_NUM; 5238 5239 ring = &sc->txq[cmd_queue_num]; 5240 desc = &ring->desc[ring->cur]; 5241 data = &ring->data[ring->cur]; 5242 totlen = 4 + size; 5243 5244 if (size > sizeof cmd->data) { 5245 /* Command is too large to fit in a descriptor. */ 5246 if (totlen > MCLBYTES) 5247 return EINVAL; 5248 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 5249 if (m == NULL) 5250 return ENOMEM; 5251 cmd = mtod(m, struct iwn_tx_cmd *); 5252 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 5253 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 5254 if (error != 0) { 5255 m_freem(m); 5256 return error; 5257 } 5258 data->m = m; 5259 } else { 5260 cmd = &ring->cmd[ring->cur]; 5261 paddr = data->cmd_paddr; 5262 } 5263 5264 cmd->code = code; 5265 cmd->flags = 0; 5266 cmd->qid = ring->qid; 5267 cmd->idx = ring->cur; 5268 memcpy(cmd->data, buf, size); 5269 5270 desc->nsegs = 1; 5271 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 5272 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 5273 5274 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 5275 __func__, iwn_intr_str(cmd->code), cmd->code, 5276 cmd->flags, cmd->qid, cmd->idx); 5277 5278 if (size > sizeof cmd->data) { 5279 bus_dmamap_sync(ring->data_dmat, data->map, 5280 BUS_DMASYNC_PREWRITE); 5281 } else { 5282 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 5283 BUS_DMASYNC_PREWRITE); 5284 } 5285 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 5286 BUS_DMASYNC_PREWRITE); 5287 5288 /* Kick command ring. */ 5289 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 5290 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 5291 5292 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5293 5294 #if defined(__DragonFly__) 5295 return async ? 0 : lksleep(desc, &sc->sc_lk, PCATCH, "iwncmd", hz); 5296 #else 5297 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz); 5298 #endif 5299 } 5300 5301 static int 5302 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5303 { 5304 struct iwn4965_node_info hnode; 5305 caddr_t src, dst; 5306 5307 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5308 5309 /* 5310 * We use the node structure for 5000 Series internally (it is 5311 * a superset of the one for 4965AGN). We thus copy the common 5312 * fields before sending the command. 5313 */ 5314 src = (caddr_t)node; 5315 dst = (caddr_t)&hnode; 5316 memcpy(dst, src, 48); 5317 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 5318 memcpy(dst + 48, src + 72, 20); 5319 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 5320 } 5321 5322 static int 5323 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5324 { 5325 5326 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5327 5328 /* Direct mapping. */ 5329 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 5330 } 5331 5332 static int 5333 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 5334 { 5335 struct iwn_node *wn = (void *)ni; 5336 struct ieee80211_rateset *rs; 5337 struct iwn_cmd_link_quality linkq; 5338 int i, rate, txrate; 5339 int is_11n; 5340 5341 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5342 5343 memset(&linkq, 0, sizeof linkq); 5344 linkq.id = wn->id; 5345 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5346 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5347 5348 linkq.ampdu_max = 32; /* XXX negotiated? */ 5349 linkq.ampdu_threshold = 3; 5350 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5351 5352 DPRINTF(sc, IWN_DEBUG_XMIT, 5353 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n", 5354 __func__, 5355 linkq.antmsk_1stream, 5356 linkq.antmsk_2stream, 5357 sc->ntxchains); 5358 5359 /* 5360 * Are we using 11n rates? Ensure the channel is 5361 * 11n _and_ we have some 11n rates, or don't 5362 * try. 5363 */ 5364 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) { 5365 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 5366 is_11n = 1; 5367 } else { 5368 rs = &ni->ni_rates; 5369 is_11n = 0; 5370 } 5371 5372 /* Start at highest available bit-rate. */ 5373 /* 5374 * XXX this is all very dirty! 5375 */ 5376 if (is_11n) 5377 txrate = ni->ni_htrates.rs_nrates - 1; 5378 else 5379 txrate = rs->rs_nrates - 1; 5380 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 5381 uint32_t plcp; 5382 5383 /* 5384 * XXX TODO: ensure the last two slots are the two lowest 5385 * rate entries, just for now. 5386 */ 5387 if (i == 14 || i == 15) 5388 txrate = 0; 5389 5390 if (is_11n) 5391 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate]; 5392 else 5393 rate = IEEE80211_RV(rs->rs_rates[txrate]); 5394 5395 /* Do rate -> PLCP config mapping */ 5396 plcp = iwn_rate_to_plcp(sc, ni, rate); 5397 linkq.retry[i] = plcp; 5398 DPRINTF(sc, IWN_DEBUG_XMIT, 5399 "%s: i=%d, txrate=%d, rate=0x%02x, plcp=0x%08x\n", 5400 __func__, 5401 i, 5402 txrate, 5403 rate, 5404 le32toh(plcp)); 5405 5406 /* 5407 * The mimo field is an index into the table which 5408 * indicates the first index where it and subsequent entries 5409 * will not be using MIMO. 5410 * 5411 * Since we're filling linkq from 0..15 and we're filling 5412 * from the highest MCS rates to the lowest rates, if we 5413 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie, 5414 * the next entry.) That way if the next entry is a non-MIMO 5415 * entry, we're already pointing at it. 5416 */ 5417 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 5418 IEEE80211_RV(le32toh(plcp)) > 7) 5419 linkq.mimo = i + 1; 5420 5421 /* Next retry at immediate lower bit-rate. */ 5422 if (txrate > 0) 5423 txrate--; 5424 } 5425 /* 5426 * If we reached the end of the list and indeed we hit 5427 * all MIMO rates (eg 5300 doing MCS23-15) then yes, 5428 * set mimo to 15. Setting it to 16 panics the firmware. 5429 */ 5430 if (linkq.mimo > 15) 5431 linkq.mimo = 15; 5432 5433 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: mimo = %d\n", __func__, linkq.mimo); 5434 5435 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5436 5437 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 5438 } 5439 5440 /* 5441 * Broadcast node is used to send group-addressed and management frames. 5442 */ 5443 static int 5444 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 5445 { 5446 struct iwn_ops *ops = &sc->ops; 5447 struct ieee80211com *ic = &sc->sc_ic; 5448 struct iwn_node_info node; 5449 struct iwn_cmd_link_quality linkq; 5450 uint8_t txant; 5451 int i, error; 5452 5453 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5454 5455 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5456 5457 memset(&node, 0, sizeof node); 5458 IEEE80211_ADDR_COPY(node.macaddr, ieee80211broadcastaddr); 5459 node.id = sc->broadcast_id; 5460 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 5461 if ((error = ops->add_node(sc, &node, async)) != 0) 5462 return error; 5463 5464 /* Use the first valid TX antenna. */ 5465 txant = IWN_LSB(sc->txchainmask); 5466 5467 memset(&linkq, 0, sizeof linkq); 5468 linkq.id = sc->broadcast_id; 5469 linkq.antmsk_1stream = iwn_get_1stream_tx_antmask(sc); 5470 linkq.antmsk_2stream = iwn_get_2stream_tx_antmask(sc); 5471 linkq.ampdu_max = 64; 5472 linkq.ampdu_threshold = 3; 5473 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5474 5475 /* Use lowest mandatory bit-rate. */ 5476 /* XXX rate table lookup? */ 5477 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 5478 linkq.retry[0] = htole32(0xd); 5479 else 5480 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 5481 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 5482 /* Use same bit-rate for all TX retries. */ 5483 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 5484 linkq.retry[i] = linkq.retry[0]; 5485 } 5486 5487 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5488 5489 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 5490 } 5491 5492 static int 5493 iwn_updateedca(struct ieee80211com *ic) 5494 { 5495 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 5496 struct iwn_softc *sc = ic->ic_softc; 5497 struct iwn_edca_params cmd; 5498 int aci; 5499 5500 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5501 5502 memset(&cmd, 0, sizeof cmd); 5503 cmd.flags = htole32(IWN_EDCA_UPDATE); 5504 5505 IEEE80211_LOCK(ic); 5506 for (aci = 0; aci < WME_NUM_AC; aci++) { 5507 const struct wmeParams *ac = 5508 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 5509 cmd.ac[aci].aifsn = ac->wmep_aifsn; 5510 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 5511 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 5512 cmd.ac[aci].txoplimit = 5513 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 5514 } 5515 IEEE80211_UNLOCK(ic); 5516 5517 IWN_LOCK(sc); 5518 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5519 IWN_UNLOCK(sc); 5520 5521 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5522 5523 return 0; 5524 #undef IWN_EXP2 5525 } 5526 5527 static void 5528 iwn_update_mcast(struct ieee80211com *ic) 5529 { 5530 /* Ignore */ 5531 } 5532 5533 static void 5534 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 5535 { 5536 struct iwn_cmd_led led; 5537 5538 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5539 5540 #if 0 5541 /* XXX don't set LEDs during scan? */ 5542 if (sc->sc_is_scanning) 5543 return; 5544 #endif 5545 5546 /* Clear microcode LED ownership. */ 5547 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 5548 5549 led.which = which; 5550 led.unit = htole32(10000); /* on/off in unit of 100ms */ 5551 led.off = off; 5552 led.on = on; 5553 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 5554 } 5555 5556 /* 5557 * Set the critical temperature at which the firmware will stop the radio 5558 * and notify us. 5559 */ 5560 static int 5561 iwn_set_critical_temp(struct iwn_softc *sc) 5562 { 5563 struct iwn_critical_temp crit; 5564 int32_t temp; 5565 5566 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5567 5568 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 5569 5570 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 5571 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 5572 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 5573 temp = IWN_CTOK(110); 5574 else 5575 temp = 110; 5576 memset(&crit, 0, sizeof crit); 5577 crit.tempR = htole32(temp); 5578 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 5579 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 5580 } 5581 5582 static int 5583 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 5584 { 5585 struct iwn_cmd_timing cmd; 5586 uint64_t val, mod; 5587 5588 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5589 5590 memset(&cmd, 0, sizeof cmd); 5591 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 5592 cmd.bintval = htole16(ni->ni_intval); 5593 cmd.lintval = htole16(10); 5594 5595 /* Compute remaining time until next beacon. */ 5596 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 5597 mod = le64toh(cmd.tstamp) % val; 5598 cmd.binitval = htole32((uint32_t)(val - mod)); 5599 5600 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 5601 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 5602 5603 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 5604 } 5605 5606 static void 5607 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 5608 { 5609 struct ieee80211com *ic = &sc->sc_ic; 5610 5611 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5612 5613 /* Adjust TX power if need be (delta >= 3 degC). */ 5614 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 5615 __func__, sc->temp, temp); 5616 if (abs(temp - sc->temp) >= 3) { 5617 /* Record temperature of last calibration. */ 5618 sc->temp = temp; 5619 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 5620 } 5621 } 5622 5623 /* 5624 * Set TX power for current channel (each rate has its own power settings). 5625 * This function takes into account the regulatory information from EEPROM, 5626 * the current temperature and the current voltage. 5627 */ 5628 static int 5629 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 5630 int async) 5631 { 5632 /* Fixed-point arithmetic division using a n-bit fractional part. */ 5633 #define fdivround(a, b, n) \ 5634 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 5635 /* Linear interpolation. */ 5636 #define interpolate(x, x1, y1, x2, y2, n) \ 5637 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 5638 5639 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 5640 struct iwn_ucode_info *uc = &sc->ucode_info; 5641 struct iwn4965_cmd_txpower cmd; 5642 struct iwn4965_eeprom_chan_samples *chans; 5643 const uint8_t *rf_gain, *dsp_gain; 5644 int32_t vdiff, tdiff; 5645 int i, c, grp, maxpwr; 5646 uint8_t chan; 5647 5648 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5649 /* Retrieve current channel from last RXON. */ 5650 chan = sc->rxon->chan; 5651 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 5652 chan); 5653 5654 memset(&cmd, 0, sizeof cmd); 5655 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 5656 cmd.chan = chan; 5657 5658 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 5659 maxpwr = sc->maxpwr5GHz; 5660 rf_gain = iwn4965_rf_gain_5ghz; 5661 dsp_gain = iwn4965_dsp_gain_5ghz; 5662 } else { 5663 maxpwr = sc->maxpwr2GHz; 5664 rf_gain = iwn4965_rf_gain_2ghz; 5665 dsp_gain = iwn4965_dsp_gain_2ghz; 5666 } 5667 5668 /* Compute voltage compensation. */ 5669 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 5670 if (vdiff > 0) 5671 vdiff *= 2; 5672 if (abs(vdiff) > 2) 5673 vdiff = 0; 5674 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5675 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 5676 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 5677 5678 /* Get channel attenuation group. */ 5679 if (chan <= 20) /* 1-20 */ 5680 grp = 4; 5681 else if (chan <= 43) /* 34-43 */ 5682 grp = 0; 5683 else if (chan <= 70) /* 44-70 */ 5684 grp = 1; 5685 else if (chan <= 124) /* 71-124 */ 5686 grp = 2; 5687 else /* 125-200 */ 5688 grp = 3; 5689 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5690 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 5691 5692 /* Get channel sub-band. */ 5693 for (i = 0; i < IWN_NBANDS; i++) 5694 if (sc->bands[i].lo != 0 && 5695 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 5696 break; 5697 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 5698 return EINVAL; 5699 chans = sc->bands[i].chans; 5700 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5701 "%s: chan %d sub-band=%d\n", __func__, chan, i); 5702 5703 for (c = 0; c < 2; c++) { 5704 uint8_t power, gain, temp; 5705 int maxchpwr, pwr, ridx, idx; 5706 5707 power = interpolate(chan, 5708 chans[0].num, chans[0].samples[c][1].power, 5709 chans[1].num, chans[1].samples[c][1].power, 1); 5710 gain = interpolate(chan, 5711 chans[0].num, chans[0].samples[c][1].gain, 5712 chans[1].num, chans[1].samples[c][1].gain, 1); 5713 temp = interpolate(chan, 5714 chans[0].num, chans[0].samples[c][1].temp, 5715 chans[1].num, chans[1].samples[c][1].temp, 1); 5716 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5717 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 5718 __func__, c, power, gain, temp); 5719 5720 /* Compute temperature compensation. */ 5721 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 5722 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5723 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 5724 __func__, tdiff, sc->temp, temp); 5725 5726 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 5727 /* Convert dBm to half-dBm. */ 5728 maxchpwr = sc->maxpwr[chan] * 2; 5729 if ((ridx / 8) & 1) 5730 maxchpwr -= 6; /* MIMO 2T: -3dB */ 5731 5732 pwr = maxpwr; 5733 5734 /* Adjust TX power based on rate. */ 5735 if ((ridx % 8) == 5) 5736 pwr -= 15; /* OFDM48: -7.5dB */ 5737 else if ((ridx % 8) == 6) 5738 pwr -= 17; /* OFDM54: -8.5dB */ 5739 else if ((ridx % 8) == 7) 5740 pwr -= 20; /* OFDM60: -10dB */ 5741 else 5742 pwr -= 10; /* Others: -5dB */ 5743 5744 /* Do not exceed channel max TX power. */ 5745 if (pwr > maxchpwr) 5746 pwr = maxchpwr; 5747 5748 idx = gain - (pwr - power) - tdiff - vdiff; 5749 if ((ridx / 8) & 1) /* MIMO */ 5750 idx += (int32_t)le32toh(uc->atten[grp][c]); 5751 5752 if (cmd.band == 0) 5753 idx += 9; /* 5GHz */ 5754 if (ridx == IWN_RIDX_MAX) 5755 idx += 5; /* CCK */ 5756 5757 /* Make sure idx stays in a valid range. */ 5758 if (idx < 0) 5759 idx = 0; 5760 else if (idx > IWN4965_MAX_PWR_INDEX) 5761 idx = IWN4965_MAX_PWR_INDEX; 5762 5763 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5764 "%s: Tx chain %d, rate idx %d: power=%d\n", 5765 __func__, c, ridx, idx); 5766 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 5767 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 5768 } 5769 } 5770 5771 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5772 "%s: set tx power for chan %d\n", __func__, chan); 5773 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 5774 5775 #undef interpolate 5776 #undef fdivround 5777 } 5778 5779 static int 5780 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 5781 int async) 5782 { 5783 struct iwn5000_cmd_txpower cmd; 5784 int cmdid; 5785 5786 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5787 5788 /* 5789 * TX power calibration is handled automatically by the firmware 5790 * for 5000 Series. 5791 */ 5792 memset(&cmd, 0, sizeof cmd); 5793 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 5794 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 5795 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 5796 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 5797 "%s: setting TX power; rev=%d\n", 5798 __func__, 5799 IWN_UCODE_API(sc->ucode_rev)); 5800 if (IWN_UCODE_API(sc->ucode_rev) == 1) 5801 cmdid = IWN_CMD_TXPOWER_DBM_V1; 5802 else 5803 cmdid = IWN_CMD_TXPOWER_DBM; 5804 return iwn_cmd(sc, cmdid, &cmd, sizeof cmd, async); 5805 } 5806 5807 /* 5808 * Retrieve the maximum RSSI (in dBm) among receivers. 5809 */ 5810 static int 5811 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5812 { 5813 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 5814 uint8_t mask, agc; 5815 int rssi; 5816 5817 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5818 5819 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5820 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5821 5822 rssi = 0; 5823 if (mask & IWN_ANT_A) 5824 rssi = MAX(rssi, phy->rssi[0]); 5825 if (mask & IWN_ANT_B) 5826 rssi = MAX(rssi, phy->rssi[2]); 5827 if (mask & IWN_ANT_C) 5828 rssi = MAX(rssi, phy->rssi[4]); 5829 5830 DPRINTF(sc, IWN_DEBUG_RECV, 5831 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 5832 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 5833 rssi - agc - IWN_RSSI_TO_DBM); 5834 return rssi - agc - IWN_RSSI_TO_DBM; 5835 } 5836 5837 static int 5838 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5839 { 5840 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 5841 uint8_t agc; 5842 int rssi; 5843 5844 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5845 5846 agc = (le32toh(phy->agc) >> 9) & 0x7f; 5847 5848 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 5849 le16toh(phy->rssi[1]) & 0xff); 5850 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 5851 5852 DPRINTF(sc, IWN_DEBUG_RECV, 5853 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 5854 phy->rssi[0], phy->rssi[1], phy->rssi[2], 5855 rssi - agc - IWN_RSSI_TO_DBM); 5856 return rssi - agc - IWN_RSSI_TO_DBM; 5857 } 5858 5859 /* 5860 * Retrieve the average noise (in dBm) among receivers. 5861 */ 5862 static int 5863 iwn_get_noise(const struct iwn_rx_general_stats *stats) 5864 { 5865 int i, total, nbant, noise; 5866 5867 total = nbant = 0; 5868 for (i = 0; i < 3; i++) { 5869 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 5870 continue; 5871 total += noise; 5872 nbant++; 5873 } 5874 /* There should be at least one antenna but check anyway. */ 5875 return (nbant == 0) ? -127 : (total / nbant) - 107; 5876 } 5877 5878 /* 5879 * Compute temperature (in degC) from last received statistics. 5880 */ 5881 static int 5882 iwn4965_get_temperature(struct iwn_softc *sc) 5883 { 5884 struct iwn_ucode_info *uc = &sc->ucode_info; 5885 int32_t r1, r2, r3, r4, temp; 5886 5887 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5888 5889 r1 = le32toh(uc->temp[0].chan20MHz); 5890 r2 = le32toh(uc->temp[1].chan20MHz); 5891 r3 = le32toh(uc->temp[2].chan20MHz); 5892 r4 = le32toh(sc->rawtemp); 5893 5894 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 5895 return 0; 5896 5897 /* Sign-extend 23-bit R4 value to 32-bit. */ 5898 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 5899 /* Compute temperature in Kelvin. */ 5900 temp = (259 * (r4 - r2)) / (r3 - r1); 5901 temp = (temp * 97) / 100 + 8; 5902 5903 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 5904 IWN_KTOC(temp)); 5905 return IWN_KTOC(temp); 5906 } 5907 5908 static int 5909 iwn5000_get_temperature(struct iwn_softc *sc) 5910 { 5911 int32_t temp; 5912 5913 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5914 5915 /* 5916 * Temperature is not used by the driver for 5000 Series because 5917 * TX power calibration is handled by firmware. 5918 */ 5919 temp = le32toh(sc->rawtemp); 5920 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 5921 temp = (temp / -5) + sc->temp_off; 5922 temp = IWN_KTOC(temp); 5923 } 5924 return temp; 5925 } 5926 5927 /* 5928 * Initialize sensitivity calibration state machine. 5929 */ 5930 static int 5931 iwn_init_sensitivity(struct iwn_softc *sc) 5932 { 5933 struct iwn_ops *ops = &sc->ops; 5934 struct iwn_calib_state *calib = &sc->calib; 5935 uint32_t flags; 5936 int error; 5937 5938 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5939 5940 /* Reset calibration state machine. */ 5941 memset(calib, 0, sizeof (*calib)); 5942 calib->state = IWN_CALIB_STATE_INIT; 5943 calib->cck_state = IWN_CCK_STATE_HIFA; 5944 /* Set initial correlation values. */ 5945 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 5946 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 5947 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 5948 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 5949 calib->cck_x4 = 125; 5950 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 5951 calib->energy_cck = sc->limits->energy_cck; 5952 5953 /* Write initial sensitivity. */ 5954 if ((error = iwn_send_sensitivity(sc)) != 0) 5955 return error; 5956 5957 /* Write initial gains. */ 5958 if ((error = ops->init_gains(sc)) != 0) 5959 return error; 5960 5961 /* Request statistics at each beacon interval. */ 5962 flags = 0; 5963 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 5964 __func__); 5965 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 5966 } 5967 5968 /* 5969 * Collect noise and RSSI statistics for the first 20 beacons received 5970 * after association and use them to determine connected antennas and 5971 * to set differential gains. 5972 */ 5973 static void 5974 iwn_collect_noise(struct iwn_softc *sc, 5975 const struct iwn_rx_general_stats *stats) 5976 { 5977 struct iwn_ops *ops = &sc->ops; 5978 struct iwn_calib_state *calib = &sc->calib; 5979 struct ieee80211com *ic = &sc->sc_ic; 5980 uint32_t val; 5981 int i; 5982 5983 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5984 5985 /* Accumulate RSSI and noise for all 3 antennas. */ 5986 for (i = 0; i < 3; i++) { 5987 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 5988 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 5989 } 5990 /* NB: We update differential gains only once after 20 beacons. */ 5991 if (++calib->nbeacons < 20) 5992 return; 5993 5994 /* Determine highest average RSSI. */ 5995 val = MAX(calib->rssi[0], calib->rssi[1]); 5996 val = MAX(calib->rssi[2], val); 5997 5998 /* Determine which antennas are connected. */ 5999 sc->chainmask = sc->rxchainmask; 6000 for (i = 0; i < 3; i++) 6001 if (val - calib->rssi[i] > 15 * 20) 6002 sc->chainmask &= ~(1 << i); 6003 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6004 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 6005 __func__, sc->rxchainmask, sc->chainmask); 6006 6007 /* If none of the TX antennas are connected, keep at least one. */ 6008 if ((sc->chainmask & sc->txchainmask) == 0) 6009 sc->chainmask |= IWN_LSB(sc->txchainmask); 6010 6011 (void)ops->set_gains(sc); 6012 calib->state = IWN_CALIB_STATE_RUN; 6013 6014 #ifdef notyet 6015 /* XXX Disable RX chains with no antennas connected. */ 6016 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 6017 if (sc->sc_is_scanning) 6018 device_printf(sc->sc_dev, 6019 "%s: is_scanning set, before RXON\n", 6020 __func__); 6021 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 6022 #endif 6023 6024 /* Enable power-saving mode if requested by user. */ 6025 if (ic->ic_flags & IEEE80211_F_PMGTON) 6026 (void)iwn_set_pslevel(sc, 0, 3, 1); 6027 6028 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6029 6030 } 6031 6032 static int 6033 iwn4965_init_gains(struct iwn_softc *sc) 6034 { 6035 struct iwn_phy_calib_gain cmd; 6036 6037 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6038 6039 memset(&cmd, 0, sizeof cmd); 6040 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6041 /* Differential gains initially set to 0 for all 3 antennas. */ 6042 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6043 "%s: setting initial differential gains\n", __func__); 6044 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6045 } 6046 6047 static int 6048 iwn5000_init_gains(struct iwn_softc *sc) 6049 { 6050 struct iwn_phy_calib cmd; 6051 6052 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6053 6054 memset(&cmd, 0, sizeof cmd); 6055 cmd.code = sc->reset_noise_gain; 6056 cmd.ngroups = 1; 6057 cmd.isvalid = 1; 6058 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6059 "%s: setting initial differential gains\n", __func__); 6060 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6061 } 6062 6063 static int 6064 iwn4965_set_gains(struct iwn_softc *sc) 6065 { 6066 struct iwn_calib_state *calib = &sc->calib; 6067 struct iwn_phy_calib_gain cmd; 6068 int i, delta, noise; 6069 6070 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6071 6072 /* Get minimal noise among connected antennas. */ 6073 noise = INT_MAX; /* NB: There's at least one antenna. */ 6074 for (i = 0; i < 3; i++) 6075 if (sc->chainmask & (1 << i)) 6076 noise = MIN(calib->noise[i], noise); 6077 6078 memset(&cmd, 0, sizeof cmd); 6079 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 6080 /* Set differential gains for connected antennas. */ 6081 for (i = 0; i < 3; i++) { 6082 if (sc->chainmask & (1 << i)) { 6083 /* Compute attenuation (in unit of 1.5dB). */ 6084 delta = (noise - (int32_t)calib->noise[i]) / 30; 6085 /* NB: delta <= 0 */ 6086 /* Limit to [-4.5dB,0]. */ 6087 cmd.gain[i] = MIN(abs(delta), 3); 6088 if (delta < 0) 6089 cmd.gain[i] |= 1 << 2; /* sign bit */ 6090 } 6091 } 6092 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6093 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 6094 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 6095 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6096 } 6097 6098 static int 6099 iwn5000_set_gains(struct iwn_softc *sc) 6100 { 6101 struct iwn_calib_state *calib = &sc->calib; 6102 struct iwn_phy_calib_gain cmd; 6103 int i, ant, div, delta; 6104 6105 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 6106 6107 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 6108 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 6109 6110 memset(&cmd, 0, sizeof cmd); 6111 cmd.code = sc->noise_gain; 6112 cmd.ngroups = 1; 6113 cmd.isvalid = 1; 6114 /* Get first available RX antenna as referential. */ 6115 ant = IWN_LSB(sc->rxchainmask); 6116 /* Set differential gains for other antennas. */ 6117 for (i = ant + 1; i < 3; i++) { 6118 if (sc->chainmask & (1 << i)) { 6119 /* The delta is relative to antenna "ant". */ 6120 delta = ((int32_t)calib->noise[ant] - 6121 (int32_t)calib->noise[i]) / div; 6122 /* Limit to [-4.5dB,+4.5dB]. */ 6123 cmd.gain[i - 1] = MIN(abs(delta), 3); 6124 if (delta < 0) 6125 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 6126 } 6127 } 6128 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_XMIT, 6129 "setting differential gains Ant B/C: %x/%x (%x)\n", 6130 cmd.gain[0], cmd.gain[1], sc->chainmask); 6131 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 6132 } 6133 6134 /* 6135 * Tune RF RX sensitivity based on the number of false alarms detected 6136 * during the last beacon period. 6137 */ 6138 static void 6139 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 6140 { 6141 #define inc(val, inc, max) \ 6142 if ((val) < (max)) { \ 6143 if ((val) < (max) - (inc)) \ 6144 (val) += (inc); \ 6145 else \ 6146 (val) = (max); \ 6147 needs_update = 1; \ 6148 } 6149 #define dec(val, dec, min) \ 6150 if ((val) > (min)) { \ 6151 if ((val) > (min) + (dec)) \ 6152 (val) -= (dec); \ 6153 else \ 6154 (val) = (min); \ 6155 needs_update = 1; \ 6156 } 6157 6158 const struct iwn_sensitivity_limits *limits = sc->limits; 6159 struct iwn_calib_state *calib = &sc->calib; 6160 uint32_t val, rxena, fa; 6161 uint32_t energy[3], energy_min; 6162 uint8_t noise[3], noise_ref; 6163 int i, needs_update = 0; 6164 6165 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6166 6167 /* Check that we've been enabled long enough. */ 6168 if ((rxena = le32toh(stats->general.load)) == 0){ 6169 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 6170 return; 6171 } 6172 6173 /* Compute number of false alarms since last call for OFDM. */ 6174 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6175 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 6176 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6177 6178 if (fa > 50 * rxena) { 6179 /* High false alarm count, decrease sensitivity. */ 6180 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6181 "%s: OFDM high false alarm count: %u\n", __func__, fa); 6182 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 6183 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 6184 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 6185 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 6186 6187 } else if (fa < 5 * rxena) { 6188 /* Low false alarm count, increase sensitivity. */ 6189 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6190 "%s: OFDM low false alarm count: %u\n", __func__, fa); 6191 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 6192 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 6193 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 6194 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 6195 } 6196 6197 /* Compute maximum noise among 3 receivers. */ 6198 for (i = 0; i < 3; i++) 6199 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 6200 val = MAX(noise[0], noise[1]); 6201 val = MAX(noise[2], val); 6202 /* Insert it into our samples table. */ 6203 calib->noise_samples[calib->cur_noise_sample] = val; 6204 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 6205 6206 /* Compute maximum noise among last 20 samples. */ 6207 noise_ref = calib->noise_samples[0]; 6208 for (i = 1; i < 20; i++) 6209 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 6210 6211 /* Compute maximum energy among 3 receivers. */ 6212 for (i = 0; i < 3; i++) 6213 energy[i] = le32toh(stats->general.energy[i]); 6214 val = MIN(energy[0], energy[1]); 6215 val = MIN(energy[2], val); 6216 /* Insert it into our samples table. */ 6217 calib->energy_samples[calib->cur_energy_sample] = val; 6218 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 6219 6220 /* Compute minimum energy among last 10 samples. */ 6221 energy_min = calib->energy_samples[0]; 6222 for (i = 1; i < 10; i++) 6223 energy_min = MAX(energy_min, calib->energy_samples[i]); 6224 energy_min += 6; 6225 6226 /* Compute number of false alarms since last call for CCK. */ 6227 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 6228 fa += le32toh(stats->cck.fa) - calib->fa_cck; 6229 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 6230 6231 if (fa > 50 * rxena) { 6232 /* High false alarm count, decrease sensitivity. */ 6233 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6234 "%s: CCK high false alarm count: %u\n", __func__, fa); 6235 calib->cck_state = IWN_CCK_STATE_HIFA; 6236 calib->low_fa = 0; 6237 6238 if (calib->cck_x4 > 160) { 6239 calib->noise_ref = noise_ref; 6240 if (calib->energy_cck > 2) 6241 dec(calib->energy_cck, 2, energy_min); 6242 } 6243 if (calib->cck_x4 < 160) { 6244 calib->cck_x4 = 161; 6245 needs_update = 1; 6246 } else 6247 inc(calib->cck_x4, 3, limits->max_cck_x4); 6248 6249 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 6250 6251 } else if (fa < 5 * rxena) { 6252 /* Low false alarm count, increase sensitivity. */ 6253 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6254 "%s: CCK low false alarm count: %u\n", __func__, fa); 6255 calib->cck_state = IWN_CCK_STATE_LOFA; 6256 calib->low_fa++; 6257 6258 if (calib->cck_state != IWN_CCK_STATE_INIT && 6259 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 6260 calib->low_fa > 100)) { 6261 inc(calib->energy_cck, 2, limits->min_energy_cck); 6262 dec(calib->cck_x4, 3, limits->min_cck_x4); 6263 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 6264 } 6265 } else { 6266 /* Not worth to increase or decrease sensitivity. */ 6267 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6268 "%s: CCK normal false alarm count: %u\n", __func__, fa); 6269 calib->low_fa = 0; 6270 calib->noise_ref = noise_ref; 6271 6272 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 6273 /* Previous interval had many false alarms. */ 6274 dec(calib->energy_cck, 8, energy_min); 6275 } 6276 calib->cck_state = IWN_CCK_STATE_INIT; 6277 } 6278 6279 if (needs_update) 6280 (void)iwn_send_sensitivity(sc); 6281 6282 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6283 6284 #undef dec 6285 #undef inc 6286 } 6287 6288 static int 6289 iwn_send_sensitivity(struct iwn_softc *sc) 6290 { 6291 struct iwn_calib_state *calib = &sc->calib; 6292 struct iwn_enhanced_sensitivity_cmd cmd; 6293 int len; 6294 6295 memset(&cmd, 0, sizeof cmd); 6296 len = sizeof (struct iwn_sensitivity_cmd); 6297 cmd.which = IWN_SENSITIVITY_WORKTBL; 6298 /* OFDM modulation. */ 6299 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 6300 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 6301 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 6302 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 6303 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 6304 cmd.energy_ofdm_th = htole16(62); 6305 /* CCK modulation. */ 6306 cmd.corr_cck_x4 = htole16(calib->cck_x4); 6307 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 6308 cmd.energy_cck = htole16(calib->energy_cck); 6309 /* Barker modulation: use default values. */ 6310 cmd.corr_barker = htole16(190); 6311 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 6312 6313 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6314 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 6315 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 6316 calib->ofdm_mrc_x4, calib->cck_x4, 6317 calib->cck_mrc_x4, calib->energy_cck); 6318 6319 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 6320 goto send; 6321 /* Enhanced sensitivity settings. */ 6322 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 6323 cmd.ofdm_det_slope_mrc = htole16(668); 6324 cmd.ofdm_det_icept_mrc = htole16(4); 6325 cmd.ofdm_det_slope = htole16(486); 6326 cmd.ofdm_det_icept = htole16(37); 6327 cmd.cck_det_slope_mrc = htole16(853); 6328 cmd.cck_det_icept_mrc = htole16(4); 6329 cmd.cck_det_slope = htole16(476); 6330 cmd.cck_det_icept = htole16(99); 6331 send: 6332 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 6333 } 6334 6335 /* 6336 * Look at the increase of PLCP errors over time; if it exceeds 6337 * a programmed threshold then trigger an RF retune. 6338 */ 6339 static void 6340 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs) 6341 { 6342 int32_t delta_ofdm, delta_ht, delta_cck; 6343 struct iwn_calib_state *calib = &sc->calib; 6344 int delta_ticks, cur_ticks; 6345 int delta_msec; 6346 int thresh; 6347 6348 /* 6349 * Calculate the difference between the current and 6350 * previous statistics. 6351 */ 6352 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck; 6353 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6354 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht; 6355 6356 /* 6357 * Calculate the delta in time between successive statistics 6358 * messages. Yes, it can roll over; so we make sure that 6359 * this doesn't happen. 6360 * 6361 * XXX go figure out what to do about rollover 6362 * XXX go figure out what to do if ticks rolls over to -ve instead! 6363 * XXX go stab signed integer overflow undefined-ness in the face. 6364 */ 6365 cur_ticks = ticks; 6366 delta_ticks = cur_ticks - sc->last_calib_ticks; 6367 6368 /* 6369 * If any are negative, then the firmware likely reset; so just 6370 * bail. We'll pick this up next time. 6371 */ 6372 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0) 6373 return; 6374 6375 /* 6376 * delta_ticks is in ticks; we need to convert it up to milliseconds 6377 * so we can do some useful math with it. 6378 */ 6379 delta_msec = ticks_to_msecs(delta_ticks); 6380 6381 /* 6382 * Calculate what our threshold is given the current delta_msec. 6383 */ 6384 thresh = sc->base_params->plcp_err_threshold * delta_msec; 6385 6386 DPRINTF(sc, IWN_DEBUG_STATE, 6387 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n", 6388 __func__, 6389 delta_msec, 6390 delta_cck, 6391 delta_ofdm, 6392 delta_ht, 6393 (delta_msec + delta_cck + delta_ofdm + delta_ht), 6394 thresh); 6395 6396 /* 6397 * If we need a retune, then schedule a single channel scan 6398 * to a channel that isn't the currently active one! 6399 * 6400 * The math from linux iwlwifi: 6401 * 6402 * if ((delta * 100 / msecs) > threshold) 6403 */ 6404 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) { 6405 DPRINTF(sc, IWN_DEBUG_ANY, 6406 "%s: PLCP error threshold raw (%d) comparison (%d) " 6407 "over limit (%d); retune!\n", 6408 __func__, 6409 (delta_cck + delta_ofdm + delta_ht), 6410 (delta_cck + delta_ofdm + delta_ht) * 100, 6411 thresh); 6412 } 6413 } 6414 6415 /* 6416 * Set STA mode power saving level (between 0 and 5). 6417 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 6418 */ 6419 static int 6420 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 6421 { 6422 struct iwn_pmgt_cmd cmd; 6423 const struct iwn_pmgt *pmgt; 6424 uint32_t max, skip_dtim; 6425 uint32_t reg; 6426 int i; 6427 6428 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 6429 "%s: dtim=%d, level=%d, async=%d\n", 6430 __func__, 6431 dtim, 6432 level, 6433 async); 6434 6435 /* Select which PS parameters to use. */ 6436 if (dtim <= 2) 6437 pmgt = &iwn_pmgt[0][level]; 6438 else if (dtim <= 10) 6439 pmgt = &iwn_pmgt[1][level]; 6440 else 6441 pmgt = &iwn_pmgt[2][level]; 6442 6443 memset(&cmd, 0, sizeof cmd); 6444 if (level != 0) /* not CAM */ 6445 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 6446 if (level == 5) 6447 cmd.flags |= htole16(IWN_PS_FAST_PD); 6448 /* Retrieve PCIe Active State Power Management (ASPM). */ 6449 #if defined(__DragonFly__) 6450 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINKCTRL, 4); 6451 if (!(reg & PCIEM_LNKCTL_ASPM_L0S)) /* L0s Entry disabled. */ 6452 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6453 #else 6454 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 6455 if (!(reg & PCIEM_LINK_CTL_ASPMC_L0S)) /* L0s Entry disabled. */ 6456 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6457 #endif 6458 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 6459 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 6460 6461 if (dtim == 0) { 6462 dtim = 1; 6463 skip_dtim = 0; 6464 } else 6465 skip_dtim = pmgt->skip_dtim; 6466 if (skip_dtim != 0) { 6467 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 6468 max = pmgt->intval[4]; 6469 if (max == (uint32_t)-1) 6470 max = dtim * (skip_dtim + 1); 6471 else if (max > dtim) 6472 max = rounddown(max, dtim); 6473 } else 6474 max = dtim; 6475 for (i = 0; i < 5; i++) 6476 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 6477 6478 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 6479 level); 6480 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 6481 } 6482 6483 static int 6484 iwn_send_btcoex(struct iwn_softc *sc) 6485 { 6486 struct iwn_bluetooth cmd; 6487 6488 memset(&cmd, 0, sizeof cmd); 6489 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 6490 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 6491 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 6492 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 6493 __func__); 6494 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 6495 } 6496 6497 static int 6498 iwn_send_advanced_btcoex(struct iwn_softc *sc) 6499 { 6500 static const uint32_t btcoex_3wire[12] = { 6501 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 6502 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 6503 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 6504 }; 6505 struct iwn6000_btcoex_config btconfig; 6506 struct iwn2000_btcoex_config btconfig2k; 6507 struct iwn_btcoex_priotable btprio; 6508 struct iwn_btcoex_prot btprot; 6509 int error, i; 6510 uint8_t flags; 6511 6512 memset(&btconfig, 0, sizeof btconfig); 6513 memset(&btconfig2k, 0, sizeof btconfig2k); 6514 6515 flags = IWN_BT_FLAG_COEX6000_MODE_3W << 6516 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2 6517 6518 if (sc->base_params->bt_sco_disable) 6519 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6520 else 6521 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6522 6523 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION; 6524 6525 /* Default flags result is 145 as old value */ 6526 6527 /* 6528 * Flags value has to be review. Values must change if we 6529 * which to disable it 6530 */ 6531 if (sc->base_params->bt_session_2) { 6532 btconfig2k.flags = flags; 6533 btconfig2k.max_kill = 5; 6534 btconfig2k.bt3_t7_timer = 1; 6535 btconfig2k.kill_ack = htole32(0xffff0000); 6536 btconfig2k.kill_cts = htole32(0xffff0000); 6537 btconfig2k.sample_time = 2; 6538 btconfig2k.bt3_t2_timer = 0xc; 6539 6540 for (i = 0; i < 12; i++) 6541 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]); 6542 btconfig2k.valid = htole16(0xff); 6543 btconfig2k.prio_boost = htole32(0xf0); 6544 DPRINTF(sc, IWN_DEBUG_RESET, 6545 "%s: configuring advanced bluetooth coexistence" 6546 " session 2, flags : 0x%x\n", 6547 __func__, 6548 flags); 6549 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k, 6550 sizeof(btconfig2k), 1); 6551 } else { 6552 btconfig.flags = flags; 6553 btconfig.max_kill = 5; 6554 btconfig.bt3_t7_timer = 1; 6555 btconfig.kill_ack = htole32(0xffff0000); 6556 btconfig.kill_cts = htole32(0xffff0000); 6557 btconfig.sample_time = 2; 6558 btconfig.bt3_t2_timer = 0xc; 6559 6560 for (i = 0; i < 12; i++) 6561 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 6562 btconfig.valid = htole16(0xff); 6563 btconfig.prio_boost = 0xf0; 6564 DPRINTF(sc, IWN_DEBUG_RESET, 6565 "%s: configuring advanced bluetooth coexistence," 6566 " flags : 0x%x\n", 6567 __func__, 6568 flags); 6569 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 6570 sizeof(btconfig), 1); 6571 } 6572 6573 if (error != 0) 6574 return error; 6575 6576 memset(&btprio, 0, sizeof btprio); 6577 btprio.calib_init1 = 0x6; 6578 btprio.calib_init2 = 0x7; 6579 btprio.calib_periodic_low1 = 0x2; 6580 btprio.calib_periodic_low2 = 0x3; 6581 btprio.calib_periodic_high1 = 0x4; 6582 btprio.calib_periodic_high2 = 0x5; 6583 btprio.dtim = 0x6; 6584 btprio.scan52 = 0x8; 6585 btprio.scan24 = 0xa; 6586 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 6587 1); 6588 if (error != 0) 6589 return error; 6590 6591 /* Force BT state machine change. */ 6592 memset(&btprot, 0, sizeof btprot); 6593 btprot.open = 1; 6594 btprot.type = 1; 6595 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6596 if (error != 0) 6597 return error; 6598 btprot.open = 0; 6599 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6600 } 6601 6602 static int 6603 iwn5000_runtime_calib(struct iwn_softc *sc) 6604 { 6605 struct iwn5000_calib_config cmd; 6606 6607 memset(&cmd, 0, sizeof cmd); 6608 cmd.ucode.once.enable = 0xffffffff; 6609 cmd.ucode.once.start = IWN5000_CALIB_DC; 6610 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6611 "%s: configuring runtime calibration\n", __func__); 6612 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 6613 } 6614 6615 static uint32_t 6616 iwn_get_rxon_ht_flags(struct iwn_softc *sc, struct ieee80211_channel *c) 6617 { 6618 struct ieee80211com *ic = &sc->sc_ic; 6619 uint32_t htflags = 0; 6620 6621 if (! IEEE80211_IS_CHAN_HT(c)) 6622 return (0); 6623 6624 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 6625 6626 if (IEEE80211_IS_CHAN_HT40(c)) { 6627 switch (ic->ic_curhtprotmode) { 6628 case IEEE80211_HTINFO_OPMODE_HT20PR: 6629 htflags |= IWN_RXON_HT_MODEPURE40; 6630 break; 6631 default: 6632 htflags |= IWN_RXON_HT_MODEMIXED; 6633 break; 6634 } 6635 } 6636 if (IEEE80211_IS_CHAN_HT40D(c)) 6637 htflags |= IWN_RXON_HT_HT40MINUS; 6638 6639 return (htflags); 6640 } 6641 6642 static int 6643 iwn_config(struct iwn_softc *sc) 6644 { 6645 struct iwn_ops *ops = &sc->ops; 6646 struct ieee80211com *ic = &sc->sc_ic; 6647 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 6648 const uint8_t *macaddr; 6649 uint32_t txmask; 6650 uint16_t rxchain; 6651 int error; 6652 6653 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6654 6655 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) 6656 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) { 6657 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are" 6658 " exclusive each together. Review NIC config file. Conf" 6659 " : 0x%08x Flags : 0x%08x \n", __func__, 6660 sc->base_params->calib_need, 6661 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET | 6662 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)); 6663 return (EINVAL); 6664 } 6665 6666 /* Compute temperature calib if needed. Will be send by send calib */ 6667 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) { 6668 error = iwn5000_temp_offset_calib(sc); 6669 if (error != 0) { 6670 device_printf(sc->sc_dev, 6671 "%s: could not set temperature offset\n", __func__); 6672 return (error); 6673 } 6674 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 6675 error = iwn5000_temp_offset_calibv2(sc); 6676 if (error != 0) { 6677 device_printf(sc->sc_dev, 6678 "%s: could not compute temperature offset v2\n", 6679 __func__); 6680 return (error); 6681 } 6682 } 6683 6684 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6685 /* Configure runtime DC calibration. */ 6686 error = iwn5000_runtime_calib(sc); 6687 if (error != 0) { 6688 device_printf(sc->sc_dev, 6689 "%s: could not configure runtime calibration\n", 6690 __func__); 6691 return error; 6692 } 6693 } 6694 6695 /* Configure valid TX chains for >=5000 Series. */ 6696 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6697 IWN_UCODE_API(sc->ucode_rev) > 1) { 6698 txmask = htole32(sc->txchainmask); 6699 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6700 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 6701 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 6702 sizeof txmask, 0); 6703 if (error != 0) { 6704 device_printf(sc->sc_dev, 6705 "%s: could not configure valid TX chains, " 6706 "error %d\n", __func__, error); 6707 return error; 6708 } 6709 } 6710 6711 /* Configure bluetooth coexistence. */ 6712 error = 0; 6713 6714 /* Configure bluetooth coexistence if needed. */ 6715 if (sc->base_params->bt_mode == IWN_BT_ADVANCED) 6716 error = iwn_send_advanced_btcoex(sc); 6717 if (sc->base_params->bt_mode == IWN_BT_SIMPLE) 6718 error = iwn_send_btcoex(sc); 6719 6720 if (error != 0) { 6721 device_printf(sc->sc_dev, 6722 "%s: could not configure bluetooth coexistence, error %d\n", 6723 __func__, error); 6724 return error; 6725 } 6726 6727 /* Set mode, channel, RX filter and enable RX. */ 6728 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6729 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 6730 macaddr = vap ? vap->iv_myaddr : ic->ic_macaddr; 6731 IEEE80211_ADDR_COPY(sc->rxon->myaddr, macaddr); 6732 IEEE80211_ADDR_COPY(sc->rxon->wlap, macaddr); 6733 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 6734 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6735 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 6736 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6737 switch (ic->ic_opmode) { 6738 case IEEE80211_M_STA: 6739 sc->rxon->mode = IWN_MODE_STA; 6740 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 6741 break; 6742 case IEEE80211_M_MONITOR: 6743 sc->rxon->mode = IWN_MODE_MONITOR; 6744 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST | 6745 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 6746 break; 6747 default: 6748 /* Should not get there. */ 6749 break; 6750 } 6751 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 6752 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 6753 sc->rxon->ht_single_mask = 0xff; 6754 sc->rxon->ht_dual_mask = 0xff; 6755 sc->rxon->ht_triple_mask = 0xff; 6756 /* 6757 * In active association mode, ensure that 6758 * all the receive chains are enabled. 6759 * 6760 * Since we're not yet doing SMPS, don't allow the 6761 * number of idle RX chains to be less than the active 6762 * number. 6763 */ 6764 rxchain = 6765 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6766 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 6767 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 6768 sc->rxon->rxchain = htole16(rxchain); 6769 DPRINTF(sc, IWN_DEBUG_RESET | IWN_DEBUG_XMIT, 6770 "%s: rxchainmask=0x%x, nrxchains=%d\n", 6771 __func__, 6772 sc->rxchainmask, 6773 sc->nrxchains); 6774 6775 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 6776 6777 DPRINTF(sc, IWN_DEBUG_RESET, 6778 "%s: setting configuration; flags=0x%08x\n", 6779 __func__, le32toh(sc->rxon->flags)); 6780 if (sc->sc_is_scanning) 6781 device_printf(sc->sc_dev, 6782 "%s: is_scanning set, before RXON\n", 6783 __func__); 6784 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 0); 6785 if (error != 0) { 6786 device_printf(sc->sc_dev, "%s: RXON command failed\n", 6787 __func__); 6788 return error; 6789 } 6790 6791 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 6792 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 6793 __func__); 6794 return error; 6795 } 6796 6797 /* Configuration has changed, set TX power accordingly. */ 6798 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) { 6799 device_printf(sc->sc_dev, "%s: could not set TX power\n", 6800 __func__); 6801 return error; 6802 } 6803 6804 if ((error = iwn_set_critical_temp(sc)) != 0) { 6805 device_printf(sc->sc_dev, 6806 "%s: could not set critical temperature\n", __func__); 6807 return error; 6808 } 6809 6810 /* Set power saving level to CAM during initialization. */ 6811 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 6812 device_printf(sc->sc_dev, 6813 "%s: could not set power saving level\n", __func__); 6814 return error; 6815 } 6816 6817 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6818 6819 return 0; 6820 } 6821 6822 static uint16_t 6823 iwn_get_active_dwell_time(struct iwn_softc *sc, 6824 struct ieee80211_channel *c, uint8_t n_probes) 6825 { 6826 /* No channel? Default to 2GHz settings */ 6827 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6828 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 6829 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 6830 } 6831 6832 /* 5GHz dwell time */ 6833 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 6834 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 6835 } 6836 6837 /* 6838 * Limit the total dwell time to 85% of the beacon interval. 6839 * 6840 * Returns the dwell time in milliseconds. 6841 */ 6842 static uint16_t 6843 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 6844 { 6845 struct ieee80211com *ic = &sc->sc_ic; 6846 struct ieee80211vap *vap = NULL; 6847 int bintval = 0; 6848 6849 /* bintval is in TU (1.024mS) */ 6850 if (! TAILQ_EMPTY(&ic->ic_vaps)) { 6851 vap = TAILQ_FIRST(&ic->ic_vaps); 6852 bintval = vap->iv_bss->ni_intval; 6853 } 6854 6855 /* 6856 * If it's non-zero, we should calculate the minimum of 6857 * it and the DWELL_BASE. 6858 * 6859 * XXX Yes, the math should take into account that bintval 6860 * is 1.024mS, not 1mS.. 6861 */ 6862 if (bintval > 0) { 6863 DPRINTF(sc, IWN_DEBUG_SCAN, 6864 "%s: bintval=%d\n", 6865 __func__, 6866 bintval); 6867 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 6868 } 6869 6870 /* No association context? Default */ 6871 return (IWN_PASSIVE_DWELL_BASE); 6872 } 6873 6874 static uint16_t 6875 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c) 6876 { 6877 uint16_t passive; 6878 6879 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6880 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 6881 } else { 6882 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 6883 } 6884 6885 /* Clamp to the beacon interval if we're associated */ 6886 return (iwn_limit_dwell(sc, passive)); 6887 } 6888 6889 static int 6890 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap, 6891 struct ieee80211_scan_state *ss, struct ieee80211_channel *c) 6892 { 6893 struct ieee80211com *ic = &sc->sc_ic; 6894 struct ieee80211_node *ni = vap->iv_bss; 6895 struct iwn_scan_hdr *hdr; 6896 struct iwn_cmd_data *tx; 6897 struct iwn_scan_essid *essid; 6898 struct iwn_scan_chan *chan; 6899 struct ieee80211_frame *wh; 6900 struct ieee80211_rateset *rs; 6901 uint8_t *buf, *frm; 6902 uint16_t rxchain; 6903 uint8_t txant; 6904 int buflen, error; 6905 int is_active; 6906 uint16_t dwell_active, dwell_passive; 6907 uint32_t extra, scan_service_time; 6908 6909 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6910 6911 /* 6912 * We are absolutely not allowed to send a scan command when another 6913 * scan command is pending. 6914 */ 6915 if (sc->sc_is_scanning) { 6916 device_printf(sc->sc_dev, "%s: called whilst scanning!\n", 6917 __func__); 6918 return (EAGAIN); 6919 } 6920 6921 /* Assign the scan channel */ 6922 c = ic->ic_curchan; 6923 6924 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6925 buf = kmalloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_INTWAIT | M_ZERO); 6926 if (buf == NULL) { 6927 device_printf(sc->sc_dev, 6928 "%s: could not allocate buffer for scan command\n", 6929 __func__); 6930 return ENOMEM; 6931 } 6932 hdr = (struct iwn_scan_hdr *)buf; 6933 /* 6934 * Move to the next channel if no frames are received within 10ms 6935 * after sending the probe request. 6936 */ 6937 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 6938 hdr->quiet_threshold = htole16(1); /* min # of packets */ 6939 /* 6940 * Max needs to be greater than active and passive and quiet! 6941 * It's also in microseconds! 6942 */ 6943 hdr->max_svc = htole32(250 * 1024); 6944 6945 /* 6946 * Reset scan: interval=100 6947 * Normal scan: interval=becaon interval 6948 * suspend_time: 100 (TU) 6949 * 6950 */ 6951 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22; 6952 //scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024); 6953 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */ 6954 hdr->pause_svc = htole32(scan_service_time); 6955 6956 /* Select antennas for scanning. */ 6957 rxchain = 6958 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6959 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 6960 IWN_RXCHAIN_DRIVER_FORCE; 6961 if (IEEE80211_IS_CHAN_A(c) && 6962 sc->hw_type == IWN_HW_REV_TYPE_4965) { 6963 /* Ant A must be avoided in 5GHz because of an HW bug. */ 6964 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 6965 } else /* Use all available RX antennas. */ 6966 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 6967 hdr->rxchain = htole16(rxchain); 6968 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 6969 6970 tx = (struct iwn_cmd_data *)(hdr + 1); 6971 tx->flags = htole32(IWN_TX_AUTO_SEQ); 6972 tx->id = sc->broadcast_id; 6973 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 6974 6975 if (IEEE80211_IS_CHAN_5GHZ(c)) { 6976 /* Send probe requests at 6Mbps. */ 6977 tx->rate = htole32(0xd); 6978 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 6979 } else { 6980 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 6981 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 6982 sc->rxon->associd && sc->rxon->chan > 14) 6983 tx->rate = htole32(0xd); 6984 else { 6985 /* Send probe requests at 1Mbps. */ 6986 tx->rate = htole32(10 | IWN_RFLAG_CCK); 6987 } 6988 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 6989 } 6990 /* Use the first valid TX antenna. */ 6991 txant = IWN_LSB(sc->txchainmask); 6992 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 6993 6994 /* 6995 * Only do active scanning if we're announcing a probe request 6996 * for a given SSID (or more, if we ever add it to the driver.) 6997 */ 6998 is_active = 0; 6999 7000 /* 7001 * If we're scanning for a specific SSID, add it to the command. 7002 * 7003 * XXX maybe look at adding support for scanning multiple SSIDs? 7004 */ 7005 essid = (struct iwn_scan_essid *)(tx + 1); 7006 if (ss != NULL) { 7007 if (ss->ss_ssid[0].len != 0) { 7008 essid[0].id = IEEE80211_ELEMID_SSID; 7009 essid[0].len = ss->ss_ssid[0].len; 7010 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 7011 } 7012 7013 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n", 7014 __func__, 7015 ss->ss_ssid[0].len, 7016 ss->ss_ssid[0].len, 7017 ss->ss_ssid[0].ssid); 7018 7019 if (ss->ss_nssid > 0) 7020 is_active = 1; 7021 } 7022 7023 /* 7024 * Build a probe request frame. Most of the following code is a 7025 * copy & paste of what is done in net80211. 7026 */ 7027 wh = (struct ieee80211_frame *)(essid + 20); 7028 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 7029 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 7030 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 7031 IEEE80211_ADDR_COPY(wh->i_addr1, vap->iv_ifp->if_broadcastaddr); 7032 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(vap->iv_ifp)); 7033 IEEE80211_ADDR_COPY(wh->i_addr3, vap->iv_ifp->if_broadcastaddr); 7034 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 7035 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 7036 7037 frm = (uint8_t *)(wh + 1); 7038 frm = ieee80211_add_ssid(frm, NULL, 0); 7039 frm = ieee80211_add_rates(frm, rs); 7040 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 7041 frm = ieee80211_add_xrates(frm, rs); 7042 if (ic->ic_htcaps & IEEE80211_HTC_HT) 7043 frm = ieee80211_add_htcap(frm, ni); 7044 7045 /* Set length of probe request. */ 7046 tx->len = htole16(frm - (uint8_t *)wh); 7047 7048 /* 7049 * If active scanning is requested but a certain channel is 7050 * marked passive, we can do active scanning if we detect 7051 * transmissions. 7052 * 7053 * There is an issue with some firmware versions that triggers 7054 * a sysassert on a "good CRC threshold" of zero (== disabled), 7055 * on a radar channel even though this means that we should NOT 7056 * send probes. 7057 * 7058 * The "good CRC threshold" is the number of frames that we 7059 * need to receive during our dwell time on a channel before 7060 * sending out probes -- setting this to a huge value will 7061 * mean we never reach it, but at the same time work around 7062 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 7063 * here instead of IWL_GOOD_CRC_TH_DISABLED. 7064 * 7065 * This was fixed in later versions along with some other 7066 * scan changes, and the threshold behaves as a flag in those 7067 * versions. 7068 */ 7069 7070 /* 7071 * If we're doing active scanning, set the crc_threshold 7072 * to a suitable value. This is different to active veruss 7073 * passive scanning depending upon the channel flags; the 7074 * firmware will obey that particular check for us. 7075 */ 7076 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 7077 hdr->crc_threshold = is_active ? 7078 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 7079 else 7080 hdr->crc_threshold = is_active ? 7081 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 7082 7083 chan = (struct iwn_scan_chan *)frm; 7084 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 7085 chan->flags = 0; 7086 if (ss->ss_nssid > 0) 7087 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 7088 chan->dsp_gain = 0x6e; 7089 7090 /* 7091 * Set the passive/active flag depending upon the channel mode. 7092 * XXX TODO: take the is_active flag into account as well? 7093 */ 7094 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 7095 chan->flags |= htole32(IWN_CHAN_PASSIVE); 7096 else 7097 chan->flags |= htole32(IWN_CHAN_ACTIVE); 7098 7099 /* 7100 * Calculate the active/passive dwell times. 7101 */ 7102 7103 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid); 7104 dwell_passive = iwn_get_passive_dwell_time(sc, c); 7105 7106 /* Make sure they're valid */ 7107 if (dwell_passive <= dwell_active) 7108 dwell_passive = dwell_active + 1; 7109 7110 chan->active = htole16(dwell_active); 7111 chan->passive = htole16(dwell_passive); 7112 7113 if (IEEE80211_IS_CHAN_5GHZ(c)) 7114 chan->rf_gain = 0x3b; 7115 else 7116 chan->rf_gain = 0x28; 7117 7118 DPRINTF(sc, IWN_DEBUG_STATE, 7119 "%s: chan %u flags 0x%x rf_gain 0x%x " 7120 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x " 7121 "isactive=%d numssid=%d\n", __func__, 7122 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 7123 dwell_active, dwell_passive, scan_service_time, 7124 hdr->crc_threshold, is_active, ss->ss_nssid); 7125 7126 hdr->nchan++; 7127 chan++; 7128 buflen = (uint8_t *)chan - buf; 7129 hdr->len = htole16(buflen); 7130 7131 if (sc->sc_is_scanning) { 7132 device_printf(sc->sc_dev, 7133 "%s: called with is_scanning set!\n", 7134 __func__); 7135 } 7136 sc->sc_is_scanning = 1; 7137 7138 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 7139 hdr->nchan); 7140 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 7141 kfree(buf, M_DEVBUF); 7142 7143 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7144 7145 return error; 7146 } 7147 7148 static int 7149 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 7150 { 7151 struct iwn_ops *ops = &sc->ops; 7152 struct ieee80211com *ic = &sc->sc_ic; 7153 struct ieee80211_node *ni = vap->iv_bss; 7154 int error; 7155 7156 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7157 7158 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7159 /* Update adapter configuration. */ 7160 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7161 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7162 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7163 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7164 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7165 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7166 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7167 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7168 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7169 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7170 sc->rxon->cck_mask = 0; 7171 sc->rxon->ofdm_mask = 0x15; 7172 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7173 sc->rxon->cck_mask = 0x03; 7174 sc->rxon->ofdm_mask = 0; 7175 } else { 7176 /* Assume 802.11b/g. */ 7177 sc->rxon->cck_mask = 0x03; 7178 sc->rxon->ofdm_mask = 0x15; 7179 } 7180 7181 /* try HT */ 7182 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ic->ic_curchan)); 7183 7184 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 7185 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 7186 sc->rxon->ofdm_mask); 7187 if (sc->sc_is_scanning) 7188 device_printf(sc->sc_dev, 7189 "%s: is_scanning set, before RXON\n", 7190 __func__); 7191 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 7192 if (error != 0) { 7193 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 7194 __func__, error); 7195 return error; 7196 } 7197 7198 /* Configuration has changed, set TX power accordingly. */ 7199 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 7200 device_printf(sc->sc_dev, 7201 "%s: could not set TX power, error %d\n", __func__, error); 7202 return error; 7203 } 7204 /* 7205 * Reconfiguring RXON clears the firmware nodes table so we must 7206 * add the broadcast node again. 7207 */ 7208 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 7209 device_printf(sc->sc_dev, 7210 "%s: could not add broadcast node, error %d\n", __func__, 7211 error); 7212 return error; 7213 } 7214 7215 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7216 7217 return 0; 7218 } 7219 7220 static int 7221 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 7222 { 7223 struct iwn_ops *ops = &sc->ops; 7224 struct ieee80211com *ic = &sc->sc_ic; 7225 struct ieee80211_node *ni = vap->iv_bss; 7226 struct iwn_node_info node; 7227 int error; 7228 7229 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7230 7231 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 7232 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 7233 /* Link LED blinks while monitoring. */ 7234 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 7235 return 0; 7236 } 7237 if ((error = iwn_set_timing(sc, ni)) != 0) { 7238 device_printf(sc->sc_dev, 7239 "%s: could not set timing, error %d\n", __func__, error); 7240 return error; 7241 } 7242 7243 /* Update adapter configuration. */ 7244 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 7245 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 7246 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 7247 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 7248 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 7249 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 7250 if (ic->ic_flags & IEEE80211_F_SHSLOT) 7251 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 7252 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 7253 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 7254 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 7255 sc->rxon->cck_mask = 0; 7256 sc->rxon->ofdm_mask = 0x15; 7257 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 7258 sc->rxon->cck_mask = 0x03; 7259 sc->rxon->ofdm_mask = 0; 7260 } else { 7261 /* Assume 802.11b/g. */ 7262 sc->rxon->cck_mask = 0x0f; 7263 sc->rxon->ofdm_mask = 0x15; 7264 } 7265 /* try HT */ 7266 sc->rxon->flags |= htole32(iwn_get_rxon_ht_flags(sc, ni->ni_chan)); 7267 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 7268 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x, curhtprotmode=%d\n", 7269 sc->rxon->chan, le32toh(sc->rxon->flags), ic->ic_curhtprotmode); 7270 if (sc->sc_is_scanning) 7271 device_printf(sc->sc_dev, 7272 "%s: is_scanning set, before RXON\n", 7273 __func__); 7274 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 7275 if (error != 0) { 7276 device_printf(sc->sc_dev, 7277 "%s: could not update configuration, error %d\n", __func__, 7278 error); 7279 return error; 7280 } 7281 7282 /* Configuration has changed, set TX power accordingly. */ 7283 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 7284 device_printf(sc->sc_dev, 7285 "%s: could not set TX power, error %d\n", __func__, error); 7286 return error; 7287 } 7288 7289 /* Fake a join to initialize the TX rate. */ 7290 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 7291 iwn_newassoc(ni, 1); 7292 7293 /* Add BSS node. */ 7294 memset(&node, 0, sizeof node); 7295 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 7296 node.id = IWN_ID_BSS; 7297 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 7298 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 7299 case IEEE80211_HTCAP_SMPS_ENA: 7300 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 7301 break; 7302 case IEEE80211_HTCAP_SMPS_DYNAMIC: 7303 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 7304 break; 7305 } 7306 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 7307 IWN_AMDPU_DENSITY(5)); /* 4us */ 7308 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 7309 node.htflags |= htole32(IWN_NODE_HT40); 7310 } 7311 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 7312 error = ops->add_node(sc, &node, 1); 7313 if (error != 0) { 7314 device_printf(sc->sc_dev, 7315 "%s: could not add BSS node, error %d\n", __func__, error); 7316 return error; 7317 } 7318 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 7319 __func__, node.id); 7320 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 7321 device_printf(sc->sc_dev, 7322 "%s: could not setup link quality for node %d, error %d\n", 7323 __func__, node.id, error); 7324 return error; 7325 } 7326 7327 if ((error = iwn_init_sensitivity(sc)) != 0) { 7328 device_printf(sc->sc_dev, 7329 "%s: could not set sensitivity, error %d\n", __func__, 7330 error); 7331 return error; 7332 } 7333 /* Start periodic calibration timer. */ 7334 sc->calib.state = IWN_CALIB_STATE_ASSOC; 7335 sc->calib_cnt = 0; 7336 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 7337 sc); 7338 7339 /* Link LED always on while associated. */ 7340 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 7341 7342 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7343 7344 return 0; 7345 } 7346 7347 /* 7348 * This function is called by upper layer when an ADDBA request is received 7349 * from another STA and before the ADDBA response is sent. 7350 */ 7351 static int 7352 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 7353 int baparamset, int batimeout, int baseqctl) 7354 { 7355 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 7356 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7357 struct iwn_ops *ops = &sc->ops; 7358 struct iwn_node *wn = (void *)ni; 7359 struct iwn_node_info node; 7360 uint16_t ssn; 7361 uint8_t tid; 7362 int error; 7363 7364 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7365 7366 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 7367 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 7368 7369 memset(&node, 0, sizeof node); 7370 node.id = wn->id; 7371 node.control = IWN_NODE_UPDATE; 7372 node.flags = IWN_FLAG_SET_ADDBA; 7373 node.addba_tid = tid; 7374 node.addba_ssn = htole16(ssn); 7375 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 7376 wn->id, tid, ssn); 7377 error = ops->add_node(sc, &node, 1); 7378 if (error != 0) 7379 return error; 7380 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 7381 #undef MS 7382 } 7383 7384 /* 7385 * This function is called by upper layer on teardown of an HT-immediate 7386 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 7387 */ 7388 static void 7389 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 7390 { 7391 struct ieee80211com *ic = ni->ni_ic; 7392 struct iwn_softc *sc = ic->ic_softc; 7393 struct iwn_ops *ops = &sc->ops; 7394 struct iwn_node *wn = (void *)ni; 7395 struct iwn_node_info node; 7396 uint8_t tid; 7397 7398 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7399 7400 /* XXX: tid as an argument */ 7401 for (tid = 0; tid < WME_NUM_TID; tid++) { 7402 if (&ni->ni_rx_ampdu[tid] == rap) 7403 break; 7404 } 7405 7406 memset(&node, 0, sizeof node); 7407 node.id = wn->id; 7408 node.control = IWN_NODE_UPDATE; 7409 node.flags = IWN_FLAG_SET_DELBA; 7410 node.delba_tid = tid; 7411 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 7412 (void)ops->add_node(sc, &node, 1); 7413 sc->sc_ampdu_rx_stop(ni, rap); 7414 } 7415 7416 static int 7417 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7418 int dialogtoken, int baparamset, int batimeout) 7419 { 7420 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7421 int qid; 7422 7423 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7424 7425 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 7426 if (sc->qid2tap[qid] == NULL) 7427 break; 7428 } 7429 if (qid == sc->ntxqs) { 7430 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 7431 __func__); 7432 return 0; 7433 } 7434 tap->txa_private = kmalloc(sizeof(int), M_DEVBUF, M_INTWAIT); 7435 if (tap->txa_private == NULL) { 7436 device_printf(sc->sc_dev, 7437 "%s: failed to alloc TX aggregation structure\n", __func__); 7438 return 0; 7439 } 7440 sc->qid2tap[qid] = tap; 7441 *(int *)tap->txa_private = qid; 7442 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 7443 batimeout); 7444 } 7445 7446 static int 7447 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7448 int code, int baparamset, int batimeout) 7449 { 7450 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7451 int qid = *(int *)tap->txa_private; 7452 uint8_t tid = tap->txa_tid; 7453 int ret; 7454 7455 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7456 7457 if (code == IEEE80211_STATUS_SUCCESS) { 7458 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 7459 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 7460 if (ret != 1) 7461 return ret; 7462 } else { 7463 sc->qid2tap[qid] = NULL; 7464 kfree(tap->txa_private, M_DEVBUF); 7465 tap->txa_private = NULL; 7466 } 7467 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 7468 } 7469 7470 /* 7471 * This function is called by upper layer when an ADDBA response is received 7472 * from another STA. 7473 */ 7474 static int 7475 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 7476 uint8_t tid) 7477 { 7478 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 7479 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7480 struct iwn_ops *ops = &sc->ops; 7481 struct iwn_node *wn = (void *)ni; 7482 struct iwn_node_info node; 7483 int error, qid; 7484 7485 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7486 7487 /* Enable TX for the specified RA/TID. */ 7488 wn->disable_tid &= ~(1 << tid); 7489 memset(&node, 0, sizeof node); 7490 node.id = wn->id; 7491 node.control = IWN_NODE_UPDATE; 7492 node.flags = IWN_FLAG_SET_DISABLE_TID; 7493 node.disable_tid = htole16(wn->disable_tid); 7494 error = ops->add_node(sc, &node, 1); 7495 if (error != 0) 7496 return 0; 7497 7498 if ((error = iwn_nic_lock(sc)) != 0) 7499 return 0; 7500 qid = *(int *)tap->txa_private; 7501 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 7502 __func__, wn->id, tid, tap->txa_start, qid); 7503 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 7504 iwn_nic_unlock(sc); 7505 7506 iwn_set_link_quality(sc, ni); 7507 return 1; 7508 } 7509 7510 static void 7511 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 7512 { 7513 struct iwn_softc *sc = ni->ni_ic->ic_softc; 7514 struct iwn_ops *ops = &sc->ops; 7515 uint8_t tid = tap->txa_tid; 7516 int qid; 7517 7518 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7519 7520 sc->sc_addba_stop(ni, tap); 7521 7522 if (tap->txa_private == NULL) 7523 return; 7524 7525 qid = *(int *)tap->txa_private; 7526 if (sc->txq[qid].queued != 0) 7527 return; 7528 if (iwn_nic_lock(sc) != 0) 7529 return; 7530 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 7531 iwn_nic_unlock(sc); 7532 sc->qid2tap[qid] = NULL; 7533 kfree(tap->txa_private, M_DEVBUF); 7534 tap->txa_private = NULL; 7535 } 7536 7537 static void 7538 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7539 int qid, uint8_t tid, uint16_t ssn) 7540 { 7541 struct iwn_node *wn = (void *)ni; 7542 7543 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7544 7545 /* Stop TX scheduler while we're changing its configuration. */ 7546 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7547 IWN4965_TXQ_STATUS_CHGACT); 7548 7549 /* Assign RA/TID translation to the queue. */ 7550 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 7551 wn->id << 4 | tid); 7552 7553 /* Enable chain-building mode for the queue. */ 7554 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 7555 7556 /* Set starting sequence number from the ADDBA request. */ 7557 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7558 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7559 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7560 7561 /* Set scheduler window size. */ 7562 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 7563 IWN_SCHED_WINSZ); 7564 /* Set scheduler frame limit. */ 7565 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7566 IWN_SCHED_LIMIT << 16); 7567 7568 /* Enable interrupts for the queue. */ 7569 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7570 7571 /* Mark the queue as active. */ 7572 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7573 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 7574 iwn_tid2fifo[tid] << 1); 7575 } 7576 7577 static void 7578 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7579 { 7580 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7581 7582 /* Stop TX scheduler while we're changing its configuration. */ 7583 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7584 IWN4965_TXQ_STATUS_CHGACT); 7585 7586 /* Set starting sequence number from the ADDBA request. */ 7587 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7588 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7589 7590 /* Disable interrupts for the queue. */ 7591 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7592 7593 /* Mark the queue as inactive. */ 7594 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7595 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 7596 } 7597 7598 static void 7599 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7600 int qid, uint8_t tid, uint16_t ssn) 7601 { 7602 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7603 7604 struct iwn_node *wn = (void *)ni; 7605 7606 /* Stop TX scheduler while we're changing its configuration. */ 7607 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7608 IWN5000_TXQ_STATUS_CHGACT); 7609 7610 /* Assign RA/TID translation to the queue. */ 7611 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 7612 wn->id << 4 | tid); 7613 7614 /* Enable chain-building mode for the queue. */ 7615 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 7616 7617 /* Enable aggregation for the queue. */ 7618 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7619 7620 /* Set starting sequence number from the ADDBA request. */ 7621 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7622 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7623 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7624 7625 /* Set scheduler window size and frame limit. */ 7626 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7627 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7628 7629 /* Enable interrupts for the queue. */ 7630 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7631 7632 /* Mark the queue as active. */ 7633 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7634 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 7635 } 7636 7637 static void 7638 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7639 { 7640 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7641 7642 /* Stop TX scheduler while we're changing its configuration. */ 7643 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7644 IWN5000_TXQ_STATUS_CHGACT); 7645 7646 /* Disable aggregation for the queue. */ 7647 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7648 7649 /* Set starting sequence number from the ADDBA request. */ 7650 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7651 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7652 7653 /* Disable interrupts for the queue. */ 7654 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7655 7656 /* Mark the queue as inactive. */ 7657 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7658 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 7659 } 7660 7661 /* 7662 * Query calibration tables from the initialization firmware. We do this 7663 * only once at first boot. Called from a process context. 7664 */ 7665 static int 7666 iwn5000_query_calibration(struct iwn_softc *sc) 7667 { 7668 struct iwn5000_calib_config cmd; 7669 int error; 7670 7671 memset(&cmd, 0, sizeof cmd); 7672 cmd.ucode.once.enable = htole32(0xffffffff); 7673 cmd.ucode.once.start = htole32(0xffffffff); 7674 cmd.ucode.once.send = htole32(0xffffffff); 7675 cmd.ucode.flags = htole32(0xffffffff); 7676 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 7677 __func__); 7678 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 7679 if (error != 0) 7680 return error; 7681 7682 /* Wait at most two seconds for calibration to complete. */ 7683 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 7684 #if defined(__DragonFly__) 7685 error = lksleep(sc, &sc->sc_lk, PCATCH, "iwncal", 2 * hz); 7686 #else 7687 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz); 7688 #endif 7689 return error; 7690 } 7691 7692 /* 7693 * Send calibration results to the runtime firmware. These results were 7694 * obtained on first boot from the initialization firmware. 7695 */ 7696 static int 7697 iwn5000_send_calibration(struct iwn_softc *sc) 7698 { 7699 int idx, error; 7700 7701 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) { 7702 if (!(sc->base_params->calib_need & (1<<idx))) { 7703 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7704 "No need of calib %d\n", 7705 idx); 7706 continue; /* no need for this calib */ 7707 } 7708 if (sc->calibcmd[idx].buf == NULL) { 7709 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7710 "Need calib idx : %d but no available data\n", 7711 idx); 7712 continue; 7713 } 7714 7715 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7716 "send calibration result idx=%d len=%d\n", idx, 7717 sc->calibcmd[idx].len); 7718 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 7719 sc->calibcmd[idx].len, 0); 7720 if (error != 0) { 7721 device_printf(sc->sc_dev, 7722 "%s: could not send calibration result, error %d\n", 7723 __func__, error); 7724 return error; 7725 } 7726 } 7727 return 0; 7728 } 7729 7730 static int 7731 iwn5000_send_wimax_coex(struct iwn_softc *sc) 7732 { 7733 struct iwn5000_wimax_coex wimax; 7734 7735 #if 0 7736 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 7737 /* Enable WiMAX coexistence for combo adapters. */ 7738 wimax.flags = 7739 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 7740 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 7741 IWN_WIMAX_COEX_STA_TABLE_VALID | 7742 IWN_WIMAX_COEX_ENABLE; 7743 memcpy(wimax.events, iwn6050_wimax_events, 7744 sizeof iwn6050_wimax_events); 7745 } else 7746 #endif 7747 { 7748 /* Disable WiMAX coexistence. */ 7749 wimax.flags = 0; 7750 memset(wimax.events, 0, sizeof wimax.events); 7751 } 7752 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 7753 __func__); 7754 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 7755 } 7756 7757 static int 7758 iwn5000_crystal_calib(struct iwn_softc *sc) 7759 { 7760 struct iwn5000_phy_calib_crystal cmd; 7761 7762 memset(&cmd, 0, sizeof cmd); 7763 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 7764 cmd.ngroups = 1; 7765 cmd.isvalid = 1; 7766 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 7767 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 7768 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 7769 cmd.cap_pin[0], cmd.cap_pin[1]); 7770 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7771 } 7772 7773 static int 7774 iwn5000_temp_offset_calib(struct iwn_softc *sc) 7775 { 7776 struct iwn5000_phy_calib_temp_offset cmd; 7777 7778 memset(&cmd, 0, sizeof cmd); 7779 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7780 cmd.ngroups = 1; 7781 cmd.isvalid = 1; 7782 if (sc->eeprom_temp != 0) 7783 cmd.offset = htole16(sc->eeprom_temp); 7784 else 7785 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 7786 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 7787 le16toh(cmd.offset)); 7788 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7789 } 7790 7791 static int 7792 iwn5000_temp_offset_calibv2(struct iwn_softc *sc) 7793 { 7794 struct iwn5000_phy_calib_temp_offsetv2 cmd; 7795 7796 memset(&cmd, 0, sizeof cmd); 7797 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7798 cmd.ngroups = 1; 7799 cmd.isvalid = 1; 7800 if (sc->eeprom_temp != 0) { 7801 cmd.offset_low = htole16(sc->eeprom_temp); 7802 cmd.offset_high = htole16(sc->eeprom_temp_high); 7803 } else { 7804 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 7805 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 7806 } 7807 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 7808 7809 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7810 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n", 7811 le16toh(cmd.offset_low), 7812 le16toh(cmd.offset_high), 7813 le16toh(cmd.burnt_voltage_ref)); 7814 7815 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7816 } 7817 7818 /* 7819 * This function is called after the runtime firmware notifies us of its 7820 * readiness (called in a process context). 7821 */ 7822 static int 7823 iwn4965_post_alive(struct iwn_softc *sc) 7824 { 7825 int error, qid; 7826 7827 if ((error = iwn_nic_lock(sc)) != 0) 7828 return error; 7829 7830 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7831 7832 /* Clear TX scheduler state in SRAM. */ 7833 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7834 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 7835 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 7836 7837 /* Set physical address of TX scheduler rings (1KB aligned). */ 7838 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7839 7840 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7841 7842 /* Disable chain mode for all our 16 queues. */ 7843 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 7844 7845 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 7846 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 7847 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7848 7849 /* Set scheduler window size. */ 7850 iwn_mem_write(sc, sc->sched_base + 7851 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 7852 /* Set scheduler frame limit. */ 7853 iwn_mem_write(sc, sc->sched_base + 7854 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7855 IWN_SCHED_LIMIT << 16); 7856 } 7857 7858 /* Enable interrupts for all our 16 queues. */ 7859 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 7860 /* Identify TX FIFO rings (0-7). */ 7861 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 7862 7863 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7864 for (qid = 0; qid < 7; qid++) { 7865 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 7866 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7867 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 7868 } 7869 iwn_nic_unlock(sc); 7870 return 0; 7871 } 7872 7873 /* 7874 * This function is called after the initialization or runtime firmware 7875 * notifies us of its readiness (called in a process context). 7876 */ 7877 static int 7878 iwn5000_post_alive(struct iwn_softc *sc) 7879 { 7880 int error, qid; 7881 7882 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7883 7884 /* Switch to using ICT interrupt mode. */ 7885 iwn5000_ict_reset(sc); 7886 7887 if ((error = iwn_nic_lock(sc)) != 0){ 7888 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 7889 return error; 7890 } 7891 7892 /* Clear TX scheduler state in SRAM. */ 7893 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7894 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 7895 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 7896 7897 /* Set physical address of TX scheduler rings (1KB aligned). */ 7898 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7899 7900 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7901 7902 /* Enable chain mode for all queues, except command queue. */ 7903 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 7904 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf); 7905 else 7906 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 7907 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 7908 7909 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 7910 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 7911 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7912 7913 iwn_mem_write(sc, sc->sched_base + 7914 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 7915 /* Set scheduler window size and frame limit. */ 7916 iwn_mem_write(sc, sc->sched_base + 7917 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7918 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7919 } 7920 7921 /* Enable interrupts for all our 20 queues. */ 7922 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 7923 /* Identify TX FIFO rings (0-7). */ 7924 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 7925 7926 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7927 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) { 7928 /* Mark TX rings as active. */ 7929 for (qid = 0; qid < 11; qid++) { 7930 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 }; 7931 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7932 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7933 } 7934 } else { 7935 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7936 for (qid = 0; qid < 7; qid++) { 7937 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 7938 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7939 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7940 } 7941 } 7942 iwn_nic_unlock(sc); 7943 7944 /* Configure WiMAX coexistence for combo adapters. */ 7945 error = iwn5000_send_wimax_coex(sc); 7946 if (error != 0) { 7947 device_printf(sc->sc_dev, 7948 "%s: could not configure WiMAX coexistence, error %d\n", 7949 __func__, error); 7950 return error; 7951 } 7952 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 7953 /* Perform crystal calibration. */ 7954 error = iwn5000_crystal_calib(sc); 7955 if (error != 0) { 7956 device_printf(sc->sc_dev, 7957 "%s: crystal calibration failed, error %d\n", 7958 __func__, error); 7959 return error; 7960 } 7961 } 7962 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 7963 /* Query calibration from the initialization firmware. */ 7964 if ((error = iwn5000_query_calibration(sc)) != 0) { 7965 device_printf(sc->sc_dev, 7966 "%s: could not query calibration, error %d\n", 7967 __func__, error); 7968 return error; 7969 } 7970 /* 7971 * We have the calibration results now, reboot with the 7972 * runtime firmware (call ourselves recursively!) 7973 */ 7974 iwn_hw_stop(sc); 7975 error = iwn_hw_init(sc); 7976 } else { 7977 /* Send calibration results to runtime firmware. */ 7978 error = iwn5000_send_calibration(sc); 7979 } 7980 7981 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7982 7983 return error; 7984 } 7985 7986 /* 7987 * The firmware boot code is small and is intended to be copied directly into 7988 * the NIC internal memory (no DMA transfer). 7989 */ 7990 static int 7991 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 7992 { 7993 int error, ntries; 7994 7995 size /= sizeof (uint32_t); 7996 7997 if ((error = iwn_nic_lock(sc)) != 0) 7998 return error; 7999 8000 /* Copy microcode image into NIC memory. */ 8001 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 8002 (const uint32_t *)ucode, size); 8003 8004 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 8005 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 8006 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 8007 8008 /* Start boot load now. */ 8009 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 8010 8011 /* Wait for transfer to complete. */ 8012 for (ntries = 0; ntries < 1000; ntries++) { 8013 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 8014 IWN_BSM_WR_CTRL_START)) 8015 break; 8016 DELAY(10); 8017 } 8018 if (ntries == 1000) { 8019 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8020 __func__); 8021 iwn_nic_unlock(sc); 8022 return ETIMEDOUT; 8023 } 8024 8025 /* Enable boot after power up. */ 8026 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 8027 8028 iwn_nic_unlock(sc); 8029 return 0; 8030 } 8031 8032 static int 8033 iwn4965_load_firmware(struct iwn_softc *sc) 8034 { 8035 struct iwn_fw_info *fw = &sc->fw; 8036 struct iwn_dma_info *dma = &sc->fw_dma; 8037 int error; 8038 8039 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 8040 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 8041 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8042 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8043 fw->init.text, fw->init.textsz); 8044 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8045 8046 /* Tell adapter where to find initialization sections. */ 8047 if ((error = iwn_nic_lock(sc)) != 0) 8048 return error; 8049 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8050 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 8051 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8052 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8053 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 8054 iwn_nic_unlock(sc); 8055 8056 /* Load firmware boot code. */ 8057 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 8058 if (error != 0) { 8059 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 8060 __func__); 8061 return error; 8062 } 8063 /* Now press "execute". */ 8064 IWN_WRITE(sc, IWN_RESET, 0); 8065 8066 /* Wait at most one second for first alive notification. */ 8067 #if defined(__DragonFly__) 8068 if ((error = lksleep(sc, &sc->sc_lk, PCATCH, "iwninit", hz)) != 0) { 8069 #else 8070 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8071 #endif 8072 device_printf(sc->sc_dev, 8073 "%s: timeout waiting for adapter to initialize, error %d\n", 8074 __func__, error); 8075 return error; 8076 } 8077 8078 /* Retrieve current temperature for initial TX power calibration. */ 8079 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 8080 sc->temp = iwn4965_get_temperature(sc); 8081 8082 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 8083 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 8084 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8085 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 8086 fw->main.text, fw->main.textsz); 8087 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8088 8089 /* Tell adapter where to find runtime sections. */ 8090 if ((error = iwn_nic_lock(sc)) != 0) 8091 return error; 8092 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 8093 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 8094 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 8095 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 8096 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 8097 IWN_FW_UPDATED | fw->main.textsz); 8098 iwn_nic_unlock(sc); 8099 8100 return 0; 8101 } 8102 8103 static int 8104 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 8105 const uint8_t *section, int size) 8106 { 8107 struct iwn_dma_info *dma = &sc->fw_dma; 8108 int error; 8109 8110 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8111 8112 /* Copy firmware section into pre-allocated DMA-safe memory. */ 8113 memcpy(dma->vaddr, section, size); 8114 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 8115 8116 if ((error = iwn_nic_lock(sc)) != 0) 8117 return error; 8118 8119 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8120 IWN_FH_TX_CONFIG_DMA_PAUSE); 8121 8122 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 8123 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 8124 IWN_LOADDR(dma->paddr)); 8125 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 8126 IWN_HIADDR(dma->paddr) << 28 | size); 8127 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 8128 IWN_FH_TXBUF_STATUS_TBNUM(1) | 8129 IWN_FH_TXBUF_STATUS_TBIDX(1) | 8130 IWN_FH_TXBUF_STATUS_TFBD_VALID); 8131 8132 /* Kick Flow Handler to start DMA transfer. */ 8133 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 8134 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 8135 8136 iwn_nic_unlock(sc); 8137 8138 /* Wait at most five seconds for FH DMA transfer to complete. */ 8139 #if defined(__DragonFly__) 8140 return lksleep(sc, &sc->sc_lk, PCATCH, "iwninit", 5 * hz); 8141 #else 8142 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz); 8143 #endif 8144 } 8145 8146 static int 8147 iwn5000_load_firmware(struct iwn_softc *sc) 8148 { 8149 struct iwn_fw_part *fw; 8150 int error; 8151 8152 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8153 8154 /* Load the initialization firmware on first boot only. */ 8155 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 8156 &sc->fw.main : &sc->fw.init; 8157 8158 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 8159 fw->text, fw->textsz); 8160 if (error != 0) { 8161 device_printf(sc->sc_dev, 8162 "%s: could not load firmware %s section, error %d\n", 8163 __func__, ".text", error); 8164 return error; 8165 } 8166 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 8167 fw->data, fw->datasz); 8168 if (error != 0) { 8169 device_printf(sc->sc_dev, 8170 "%s: could not load firmware %s section, error %d\n", 8171 __func__, ".data", error); 8172 return error; 8173 } 8174 8175 /* Now press "execute". */ 8176 IWN_WRITE(sc, IWN_RESET, 0); 8177 return 0; 8178 } 8179 8180 /* 8181 * Extract text and data sections from a legacy firmware image. 8182 */ 8183 static int 8184 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 8185 { 8186 const uint32_t *ptr; 8187 size_t hdrlen = 24; 8188 uint32_t rev; 8189 8190 ptr = (const uint32_t *)fw->data; 8191 rev = le32toh(*ptr++); 8192 8193 sc->ucode_rev = rev; 8194 8195 /* Check firmware API version. */ 8196 if (IWN_FW_API(rev) <= 1) { 8197 device_printf(sc->sc_dev, 8198 "%s: bad firmware, need API version >=2\n", __func__); 8199 return EINVAL; 8200 } 8201 if (IWN_FW_API(rev) >= 3) { 8202 /* Skip build number (version 2 header). */ 8203 hdrlen += 4; 8204 ptr++; 8205 } 8206 if (fw->size < hdrlen) { 8207 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8208 __func__, fw->size); 8209 return EINVAL; 8210 } 8211 fw->main.textsz = le32toh(*ptr++); 8212 fw->main.datasz = le32toh(*ptr++); 8213 fw->init.textsz = le32toh(*ptr++); 8214 fw->init.datasz = le32toh(*ptr++); 8215 fw->boot.textsz = le32toh(*ptr++); 8216 8217 /* Check that all firmware sections fit. */ 8218 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 8219 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 8220 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8221 __func__, fw->size); 8222 return EINVAL; 8223 } 8224 8225 /* Get pointers to firmware sections. */ 8226 fw->main.text = (const uint8_t *)ptr; 8227 fw->main.data = fw->main.text + fw->main.textsz; 8228 fw->init.text = fw->main.data + fw->main.datasz; 8229 fw->init.data = fw->init.text + fw->init.textsz; 8230 fw->boot.text = fw->init.data + fw->init.datasz; 8231 return 0; 8232 } 8233 8234 /* 8235 * Extract text and data sections from a TLV firmware image. 8236 */ 8237 static int 8238 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 8239 uint16_t alt) 8240 { 8241 const struct iwn_fw_tlv_hdr *hdr; 8242 const struct iwn_fw_tlv *tlv; 8243 const uint8_t *ptr, *end; 8244 uint64_t altmask; 8245 uint32_t len, tmp; 8246 8247 if (fw->size < sizeof (*hdr)) { 8248 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8249 __func__, fw->size); 8250 return EINVAL; 8251 } 8252 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 8253 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 8254 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 8255 __func__, le32toh(hdr->signature)); 8256 return EINVAL; 8257 } 8258 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 8259 le32toh(hdr->build)); 8260 sc->ucode_rev = le32toh(hdr->rev); 8261 8262 /* 8263 * Select the closest supported alternative that is less than 8264 * or equal to the specified one. 8265 */ 8266 altmask = le64toh(hdr->altmask); 8267 while (alt > 0 && !(altmask & (1ULL << alt))) 8268 alt--; /* Downgrade. */ 8269 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 8270 8271 ptr = (const uint8_t *)(hdr + 1); 8272 end = (const uint8_t *)(fw->data + fw->size); 8273 8274 /* Parse type-length-value fields. */ 8275 while (ptr + sizeof (*tlv) <= end) { 8276 tlv = (const struct iwn_fw_tlv *)ptr; 8277 len = le32toh(tlv->len); 8278 8279 ptr += sizeof (*tlv); 8280 if (ptr + len > end) { 8281 device_printf(sc->sc_dev, 8282 "%s: firmware too short: %zu bytes\n", __func__, 8283 fw->size); 8284 return EINVAL; 8285 } 8286 /* Skip other alternatives. */ 8287 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 8288 goto next; 8289 8290 switch (le16toh(tlv->type)) { 8291 case IWN_FW_TLV_MAIN_TEXT: 8292 fw->main.text = ptr; 8293 fw->main.textsz = len; 8294 break; 8295 case IWN_FW_TLV_MAIN_DATA: 8296 fw->main.data = ptr; 8297 fw->main.datasz = len; 8298 break; 8299 case IWN_FW_TLV_INIT_TEXT: 8300 fw->init.text = ptr; 8301 fw->init.textsz = len; 8302 break; 8303 case IWN_FW_TLV_INIT_DATA: 8304 fw->init.data = ptr; 8305 fw->init.datasz = len; 8306 break; 8307 case IWN_FW_TLV_BOOT_TEXT: 8308 fw->boot.text = ptr; 8309 fw->boot.textsz = len; 8310 break; 8311 case IWN_FW_TLV_ENH_SENS: 8312 if (!len) 8313 sc->sc_flags |= IWN_FLAG_ENH_SENS; 8314 break; 8315 case IWN_FW_TLV_PHY_CALIB: 8316 tmp = le32toh(*ptr); 8317 if (tmp < 253) { 8318 sc->reset_noise_gain = tmp; 8319 sc->noise_gain = tmp + 1; 8320 } 8321 break; 8322 case IWN_FW_TLV_PAN: 8323 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 8324 DPRINTF(sc, IWN_DEBUG_RESET, 8325 "PAN Support found: %d\n", 1); 8326 break; 8327 case IWN_FW_TLV_FLAGS: 8328 if (len < sizeof(uint32_t)) 8329 break; 8330 if (len % sizeof(uint32_t)) 8331 break; 8332 sc->tlv_feature_flags = le32toh(*ptr); 8333 DPRINTF(sc, IWN_DEBUG_RESET, 8334 "%s: feature: 0x%08x\n", 8335 __func__, 8336 sc->tlv_feature_flags); 8337 break; 8338 case IWN_FW_TLV_PBREQ_MAXLEN: 8339 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 8340 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 8341 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 8342 case IWN_FW_TLV_INIT_EVTLOG_PTR: 8343 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 8344 case IWN_FW_TLV_INIT_ERRLOG_PTR: 8345 case IWN_FW_TLV_WOWLAN_INST: 8346 case IWN_FW_TLV_WOWLAN_DATA: 8347 DPRINTF(sc, IWN_DEBUG_RESET, 8348 "TLV type %d recognized but not handled\n", 8349 le16toh(tlv->type)); 8350 break; 8351 default: 8352 DPRINTF(sc, IWN_DEBUG_RESET, 8353 "TLV type %d not handled\n", le16toh(tlv->type)); 8354 break; 8355 } 8356 next: /* TLV fields are 32-bit aligned. */ 8357 ptr += (len + 3) & ~3; 8358 } 8359 return 0; 8360 } 8361 8362 static int 8363 iwn_read_firmware(struct iwn_softc *sc) 8364 { 8365 struct iwn_fw_info *fw = &sc->fw; 8366 int error; 8367 8368 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8369 8370 IWN_UNLOCK(sc); 8371 8372 memset(fw, 0, sizeof (*fw)); 8373 8374 /* Read firmware image from filesystem. */ 8375 sc->fw_fp = firmware_get(sc->fwname); 8376 if (sc->fw_fp == NULL) { 8377 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 8378 __func__, sc->fwname); 8379 IWN_LOCK(sc); 8380 return EINVAL; 8381 } 8382 IWN_LOCK(sc); 8383 8384 fw->size = sc->fw_fp->datasize; 8385 fw->data = (const uint8_t *)sc->fw_fp->data; 8386 if (fw->size < sizeof (uint32_t)) { 8387 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8388 __func__, fw->size); 8389 error = EINVAL; 8390 goto fail; 8391 } 8392 8393 /* Retrieve text and data sections. */ 8394 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 8395 error = iwn_read_firmware_leg(sc, fw); 8396 else 8397 error = iwn_read_firmware_tlv(sc, fw, 1); 8398 if (error != 0) { 8399 device_printf(sc->sc_dev, 8400 "%s: could not read firmware sections, error %d\n", 8401 __func__, error); 8402 goto fail; 8403 } 8404 8405 device_printf(sc->sc_dev, "%s: ucode rev=0x%08x\n", __func__, sc->ucode_rev); 8406 8407 /* Make sure text and data sections fit in hardware memory. */ 8408 if (fw->main.textsz > sc->fw_text_maxsz || 8409 fw->main.datasz > sc->fw_data_maxsz || 8410 fw->init.textsz > sc->fw_text_maxsz || 8411 fw->init.datasz > sc->fw_data_maxsz || 8412 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 8413 (fw->boot.textsz & 3) != 0) { 8414 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 8415 __func__); 8416 error = EINVAL; 8417 goto fail; 8418 } 8419 8420 /* We can proceed with loading the firmware. */ 8421 return 0; 8422 8423 fail: iwn_unload_firmware(sc); 8424 return error; 8425 } 8426 8427 static void 8428 iwn_unload_firmware(struct iwn_softc *sc) 8429 { 8430 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8431 sc->fw_fp = NULL; 8432 } 8433 8434 static int 8435 iwn_clock_wait(struct iwn_softc *sc) 8436 { 8437 int ntries; 8438 8439 /* Set "initialization complete" bit. */ 8440 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8441 8442 /* Wait for clock stabilization. */ 8443 for (ntries = 0; ntries < 2500; ntries++) { 8444 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 8445 return 0; 8446 DELAY(10); 8447 } 8448 device_printf(sc->sc_dev, 8449 "%s: timeout waiting for clock stabilization\n", __func__); 8450 return ETIMEDOUT; 8451 } 8452 8453 static int 8454 iwn_apm_init(struct iwn_softc *sc) 8455 { 8456 uint32_t reg; 8457 int error; 8458 8459 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8460 8461 /* Disable L0s exit timer (NMI bug workaround). */ 8462 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 8463 /* Don't wait for ICH L0s (ICH bug workaround). */ 8464 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 8465 8466 /* Set FH wait threshold to max (HW bug under stress workaround). */ 8467 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 8468 8469 /* Enable HAP INTA to move adapter from L1a to L0s. */ 8470 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 8471 8472 /* Retrieve PCIe Active State Power Management (ASPM). */ 8473 #if defined(__DragonFly__) 8474 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINKCTRL, 4); 8475 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8476 if (reg & PCIEM_LNKCTL_ASPM_L1) /* L1 Entry enabled. */ 8477 #else 8478 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 8479 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8480 if (reg & PCIEM_LINK_CTL_ASPMC_L1) /* L1 Entry enabled. */ 8481 #endif 8482 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8483 else 8484 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8485 8486 if (sc->base_params->pll_cfg_val) 8487 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val); 8488 8489 /* Wait for clock stabilization before accessing prph. */ 8490 if ((error = iwn_clock_wait(sc)) != 0) 8491 return error; 8492 8493 if ((error = iwn_nic_lock(sc)) != 0) 8494 return error; 8495 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 8496 /* Enable DMA and BSM (Bootstrap State Machine). */ 8497 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8498 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 8499 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 8500 } else { 8501 /* Enable DMA. */ 8502 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8503 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8504 } 8505 DELAY(20); 8506 /* Disable L1-Active. */ 8507 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 8508 iwn_nic_unlock(sc); 8509 8510 return 0; 8511 } 8512 8513 static void 8514 iwn_apm_stop_master(struct iwn_softc *sc) 8515 { 8516 int ntries; 8517 8518 /* Stop busmaster DMA activity. */ 8519 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 8520 for (ntries = 0; ntries < 100; ntries++) { 8521 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 8522 return; 8523 DELAY(10); 8524 } 8525 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 8526 } 8527 8528 static void 8529 iwn_apm_stop(struct iwn_softc *sc) 8530 { 8531 iwn_apm_stop_master(sc); 8532 8533 /* Reset the entire device. */ 8534 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 8535 DELAY(10); 8536 /* Clear "initialization complete" bit. */ 8537 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8538 } 8539 8540 static int 8541 iwn4965_nic_config(struct iwn_softc *sc) 8542 { 8543 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8544 8545 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 8546 /* 8547 * I don't believe this to be correct but this is what the 8548 * vendor driver is doing. Probably the bits should not be 8549 * shifted in IWN_RFCFG_*. 8550 */ 8551 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8552 IWN_RFCFG_TYPE(sc->rfcfg) | 8553 IWN_RFCFG_STEP(sc->rfcfg) | 8554 IWN_RFCFG_DASH(sc->rfcfg)); 8555 } 8556 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8557 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8558 return 0; 8559 } 8560 8561 static int 8562 iwn5000_nic_config(struct iwn_softc *sc) 8563 { 8564 uint32_t tmp; 8565 int error; 8566 8567 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8568 8569 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 8570 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8571 IWN_RFCFG_TYPE(sc->rfcfg) | 8572 IWN_RFCFG_STEP(sc->rfcfg) | 8573 IWN_RFCFG_DASH(sc->rfcfg)); 8574 } 8575 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8576 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8577 8578 if ((error = iwn_nic_lock(sc)) != 0) 8579 return error; 8580 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 8581 8582 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 8583 /* 8584 * Select first Switching Voltage Regulator (1.32V) to 8585 * solve a stability issue related to noisy DC2DC line 8586 * in the silicon of 1000 Series. 8587 */ 8588 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 8589 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 8590 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 8591 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 8592 } 8593 iwn_nic_unlock(sc); 8594 8595 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 8596 /* Use internal power amplifier only. */ 8597 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 8598 } 8599 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) { 8600 /* Indicate that ROM calibration version is >=6. */ 8601 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 8602 } 8603 if (sc->base_params->additional_gp_drv_bit) 8604 IWN_SETBITS(sc, IWN_GP_DRIVER, 8605 sc->base_params->additional_gp_drv_bit); 8606 return 0; 8607 } 8608 8609 /* 8610 * Take NIC ownership over Intel Active Management Technology (AMT). 8611 */ 8612 static int 8613 iwn_hw_prepare(struct iwn_softc *sc) 8614 { 8615 int ntries; 8616 8617 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8618 8619 /* Check if hardware is ready. */ 8620 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8621 for (ntries = 0; ntries < 5; ntries++) { 8622 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8623 IWN_HW_IF_CONFIG_NIC_READY) 8624 return 0; 8625 DELAY(10); 8626 } 8627 8628 /* Hardware not ready, force into ready state. */ 8629 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 8630 for (ntries = 0; ntries < 15000; ntries++) { 8631 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 8632 IWN_HW_IF_CONFIG_PREPARE_DONE)) 8633 break; 8634 DELAY(10); 8635 } 8636 if (ntries == 15000) 8637 return ETIMEDOUT; 8638 8639 /* Hardware should be ready now. */ 8640 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8641 for (ntries = 0; ntries < 5; ntries++) { 8642 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8643 IWN_HW_IF_CONFIG_NIC_READY) 8644 return 0; 8645 DELAY(10); 8646 } 8647 return ETIMEDOUT; 8648 } 8649 8650 static int 8651 iwn_hw_init(struct iwn_softc *sc) 8652 { 8653 struct iwn_ops *ops = &sc->ops; 8654 int error, chnl, qid; 8655 8656 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8657 8658 /* Clear pending interrupts. */ 8659 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8660 8661 if ((error = iwn_apm_init(sc)) != 0) { 8662 device_printf(sc->sc_dev, 8663 "%s: could not power ON adapter, error %d\n", __func__, 8664 error); 8665 return error; 8666 } 8667 8668 /* Select VMAIN power source. */ 8669 if ((error = iwn_nic_lock(sc)) != 0) 8670 return error; 8671 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 8672 iwn_nic_unlock(sc); 8673 8674 /* Perform adapter-specific initialization. */ 8675 if ((error = ops->nic_config(sc)) != 0) 8676 return error; 8677 8678 /* Initialize RX ring. */ 8679 if ((error = iwn_nic_lock(sc)) != 0) 8680 return error; 8681 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 8682 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 8683 /* Set physical address of RX ring (256-byte aligned). */ 8684 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 8685 /* Set physical address of RX status (16-byte aligned). */ 8686 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 8687 /* Enable RX. */ 8688 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 8689 IWN_FH_RX_CONFIG_ENA | 8690 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 8691 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 8692 IWN_FH_RX_CONFIG_SINGLE_FRAME | 8693 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 8694 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 8695 iwn_nic_unlock(sc); 8696 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 8697 8698 if ((error = iwn_nic_lock(sc)) != 0) 8699 return error; 8700 8701 /* Initialize TX scheduler. */ 8702 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8703 8704 /* Set physical address of "keep warm" page (16-byte aligned). */ 8705 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 8706 8707 /* Initialize TX rings. */ 8708 for (qid = 0; qid < sc->ntxqs; qid++) { 8709 struct iwn_tx_ring *txq = &sc->txq[qid]; 8710 8711 /* Set physical address of TX ring (256-byte aligned). */ 8712 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 8713 txq->desc_dma.paddr >> 8); 8714 } 8715 iwn_nic_unlock(sc); 8716 8717 /* Enable DMA channels. */ 8718 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8719 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 8720 IWN_FH_TX_CONFIG_DMA_ENA | 8721 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 8722 } 8723 8724 /* Clear "radio off" and "commands blocked" bits. */ 8725 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8726 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 8727 8728 /* Clear pending interrupts. */ 8729 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8730 /* Enable interrupt coalescing. */ 8731 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 8732 /* Enable interrupts. */ 8733 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8734 8735 /* _Really_ make sure "radio off" bit is cleared! */ 8736 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8737 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8738 8739 /* Enable shadow registers. */ 8740 if (sc->base_params->shadow_reg_enable) 8741 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 8742 8743 if ((error = ops->load_firmware(sc)) != 0) { 8744 device_printf(sc->sc_dev, 8745 "%s: could not load firmware, error %d\n", __func__, 8746 error); 8747 return error; 8748 } 8749 /* Wait at most one second for firmware alive notification. */ 8750 #if defined(__DragonFly__) 8751 if ((error = lksleep(sc, &sc->sc_lk, PCATCH, "iwninit", hz)) != 0) { 8752 #else 8753 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) { 8754 #endif 8755 device_printf(sc->sc_dev, 8756 "%s: timeout waiting for adapter to initialize, error %d\n", 8757 __func__, error); 8758 return error; 8759 } 8760 /* Do post-firmware initialization. */ 8761 8762 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8763 8764 return ops->post_alive(sc); 8765 } 8766 8767 static void 8768 iwn_hw_stop(struct iwn_softc *sc) 8769 { 8770 int chnl, qid, ntries; 8771 8772 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8773 8774 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 8775 8776 /* Disable interrupts. */ 8777 IWN_WRITE(sc, IWN_INT_MASK, 0); 8778 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8779 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 8780 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8781 8782 /* Make sure we no longer hold the NIC lock. */ 8783 iwn_nic_unlock(sc); 8784 8785 /* Stop TX scheduler. */ 8786 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8787 8788 /* Stop all DMA channels. */ 8789 if (iwn_nic_lock(sc) == 0) { 8790 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8791 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 8792 for (ntries = 0; ntries < 200; ntries++) { 8793 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 8794 IWN_FH_TX_STATUS_IDLE(chnl)) 8795 break; 8796 DELAY(10); 8797 } 8798 } 8799 iwn_nic_unlock(sc); 8800 } 8801 8802 /* Stop RX ring. */ 8803 iwn_reset_rx_ring(sc, &sc->rxq); 8804 8805 /* Reset all TX rings. */ 8806 for (qid = 0; qid < sc->ntxqs; qid++) 8807 iwn_reset_tx_ring(sc, &sc->txq[qid]); 8808 8809 if (iwn_nic_lock(sc) == 0) { 8810 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 8811 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8812 iwn_nic_unlock(sc); 8813 } 8814 DELAY(5); 8815 /* Power OFF adapter. */ 8816 iwn_apm_stop(sc); 8817 } 8818 8819 static void 8820 iwn_radio_on(void *arg0, int pending) 8821 { 8822 struct iwn_softc *sc = arg0; 8823 struct ieee80211com *ic = &sc->sc_ic; 8824 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8825 8826 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8827 8828 if (vap != NULL) { 8829 iwn_init(sc); 8830 ieee80211_init(vap); 8831 } 8832 } 8833 8834 static void 8835 iwn_radio_off(void *arg0, int pending) 8836 { 8837 struct iwn_softc *sc = arg0; 8838 struct ieee80211com *ic = &sc->sc_ic; 8839 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8840 8841 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8842 8843 iwn_stop(sc); 8844 if (vap != NULL) 8845 ieee80211_stop(vap); 8846 8847 /* Enable interrupts to get RF toggle notification. */ 8848 IWN_LOCK(sc); 8849 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8850 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8851 IWN_UNLOCK(sc); 8852 } 8853 8854 static void 8855 iwn_panicked(void *arg0, int pending) 8856 { 8857 struct iwn_softc *sc = arg0; 8858 struct ieee80211com *ic = &sc->sc_ic; 8859 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8860 #if 0 8861 int error; 8862 #endif 8863 8864 if (vap == NULL) { 8865 kprintf("%s: null vap\n", __func__); 8866 return; 8867 } 8868 8869 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 8870 "restarting\n", __func__, vap->iv_state); 8871 8872 /* 8873 * This is not enough work. We need to also reinitialise 8874 * the correct transmit state for aggregation enabled queues, 8875 * which has a very specific requirement of 8876 * ring index = 802.11 seqno % 256. If we don't do this (which 8877 * we definitely don't!) then the firmware will just panic again. 8878 */ 8879 #if 1 8880 ieee80211_restart_all(ic); 8881 #else 8882 IWN_LOCK(sc); 8883 8884 iwn_stop_locked(sc); 8885 iwn_init_locked(sc); 8886 if (vap->iv_state >= IEEE80211_S_AUTH && 8887 (error = iwn_auth(sc, vap)) != 0) { 8888 device_printf(sc->sc_dev, 8889 "%s: could not move to auth state\n", __func__); 8890 } 8891 if (vap->iv_state >= IEEE80211_S_RUN && 8892 (error = iwn_run(sc, vap)) != 0) { 8893 device_printf(sc->sc_dev, 8894 "%s: could not move to run state\n", __func__); 8895 } 8896 8897 IWN_UNLOCK(sc); 8898 #endif 8899 } 8900 8901 static void 8902 iwn_init_locked(struct iwn_softc *sc) 8903 { 8904 int error; 8905 8906 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8907 8908 IWN_LOCK_ASSERT(sc); 8909 8910 sc->sc_flags |= IWN_FLAG_RUNNING; 8911 8912 if ((error = iwn_hw_prepare(sc)) != 0) { 8913 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 8914 __func__, error); 8915 goto fail; 8916 } 8917 8918 /* Initialize interrupt mask to default value. */ 8919 sc->int_mask = IWN_INT_MASK_DEF; 8920 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8921 8922 /* Check that the radio is not disabled by hardware switch. */ 8923 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 8924 device_printf(sc->sc_dev, 8925 "radio is disabled by hardware switch\n"); 8926 /* Enable interrupts to get RF toggle notifications. */ 8927 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8928 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8929 return; 8930 } 8931 8932 /* Read firmware images from the filesystem. */ 8933 if ((error = iwn_read_firmware(sc)) != 0) { 8934 device_printf(sc->sc_dev, 8935 "%s: could not read firmware, error %d\n", __func__, 8936 error); 8937 goto fail; 8938 } 8939 8940 /* Initialize hardware and upload firmware. */ 8941 error = iwn_hw_init(sc); 8942 iwn_unload_firmware(sc); 8943 if (error != 0) { 8944 device_printf(sc->sc_dev, 8945 "%s: could not initialize hardware, error %d\n", __func__, 8946 error); 8947 goto fail; 8948 } 8949 8950 /* Configure adapter now that it is ready. */ 8951 if ((error = iwn_config(sc)) != 0) { 8952 device_printf(sc->sc_dev, 8953 "%s: could not configure device, error %d\n", __func__, 8954 error); 8955 goto fail; 8956 } 8957 8958 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc); 8959 8960 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8961 8962 return; 8963 8964 fail: 8965 sc->sc_flags &= ~IWN_FLAG_RUNNING; 8966 iwn_stop_locked(sc); 8967 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 8968 } 8969 8970 static void 8971 iwn_init(struct iwn_softc *sc) 8972 { 8973 8974 IWN_LOCK(sc); 8975 iwn_init_locked(sc); 8976 IWN_UNLOCK(sc); 8977 8978 if (sc->sc_flags & IWN_FLAG_RUNNING) 8979 ieee80211_start_all(&sc->sc_ic); 8980 } 8981 8982 static void 8983 iwn_stop_locked(struct iwn_softc *sc) 8984 { 8985 8986 IWN_LOCK_ASSERT(sc); 8987 8988 sc->sc_is_scanning = 0; 8989 sc->sc_tx_timer = 0; 8990 #if defined(__DragonFly__) 8991 callout_cancel(&sc->watchdog_to); 8992 callout_cancel(&sc->calib_to); 8993 #else 8994 callout_stop(&sc->watchdog_to); 8995 callout_stop(&sc->calib_to); 8996 #endif 8997 sc->sc_flags &= ~IWN_FLAG_RUNNING; 8998 8999 /* Power OFF hardware. */ 9000 iwn_hw_stop(sc); 9001 } 9002 9003 static void 9004 iwn_stop(struct iwn_softc *sc) 9005 { 9006 IWN_LOCK(sc); 9007 iwn_stop_locked(sc); 9008 IWN_UNLOCK(sc); 9009 } 9010 9011 /* 9012 * Callback from net80211 to start a scan. 9013 */ 9014 static void 9015 iwn_scan_start(struct ieee80211com *ic) 9016 { 9017 struct iwn_softc *sc = ic->ic_softc; 9018 9019 IWN_LOCK(sc); 9020 /* make the link LED blink while we're scanning */ 9021 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 9022 IWN_UNLOCK(sc); 9023 } 9024 9025 /* 9026 * Callback from net80211 to terminate a scan. 9027 */ 9028 static void 9029 iwn_scan_end(struct ieee80211com *ic) 9030 { 9031 struct iwn_softc *sc = ic->ic_softc; 9032 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 9033 9034 IWN_LOCK(sc); 9035 if (vap->iv_state == IEEE80211_S_RUN) { 9036 /* Set link LED to ON status if we are associated */ 9037 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 9038 } 9039 IWN_UNLOCK(sc); 9040 } 9041 9042 /* 9043 * Callback from net80211 to force a channel change. 9044 */ 9045 static void 9046 iwn_set_channel(struct ieee80211com *ic) 9047 { 9048 const struct ieee80211_channel *c = ic->ic_curchan; 9049 struct iwn_softc *sc = ic->ic_softc; 9050 int error; 9051 9052 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 9053 9054 IWN_LOCK(sc); 9055 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 9056 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 9057 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 9058 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 9059 9060 /* 9061 * Only need to set the channel in Monitor mode. AP scanning and auth 9062 * are already taken care of by their respective firmware commands. 9063 */ 9064 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 9065 error = iwn_config(sc); 9066 if (error != 0) 9067 device_printf(sc->sc_dev, 9068 "%s: error %d settting channel\n", __func__, error); 9069 } 9070 IWN_UNLOCK(sc); 9071 } 9072 9073 /* 9074 * Callback from net80211 to start scanning of the current channel. 9075 */ 9076 static void 9077 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 9078 { 9079 struct ieee80211vap *vap = ss->ss_vap; 9080 struct ieee80211com *ic = vap->iv_ic; 9081 struct iwn_softc *sc = ic->ic_softc; 9082 int error; 9083 9084 IWN_LOCK(sc); 9085 error = iwn_scan(sc, vap, ss, ic->ic_curchan); 9086 IWN_UNLOCK(sc); 9087 if (error != 0) 9088 ieee80211_cancel_scan(vap); 9089 } 9090 9091 /* 9092 * Callback from net80211 to handle the minimum dwell time being met. 9093 * The intent is to terminate the scan but we just let the firmware 9094 * notify us when it's finished as we have no safe way to abort it. 9095 */ 9096 static void 9097 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 9098 { 9099 /* NB: don't try to abort scan; wait for firmware to finish */ 9100 } 9101 #ifdef IWN_DEBUG 9102 #define IWN_DESC(x) case x: return #x 9103 9104 /* 9105 * Translate CSR code to string 9106 */ 9107 static char *iwn_get_csr_string(int csr) 9108 { 9109 switch (csr) { 9110 IWN_DESC(IWN_HW_IF_CONFIG); 9111 IWN_DESC(IWN_INT_COALESCING); 9112 IWN_DESC(IWN_INT); 9113 IWN_DESC(IWN_INT_MASK); 9114 IWN_DESC(IWN_FH_INT); 9115 IWN_DESC(IWN_GPIO_IN); 9116 IWN_DESC(IWN_RESET); 9117 IWN_DESC(IWN_GP_CNTRL); 9118 IWN_DESC(IWN_HW_REV); 9119 IWN_DESC(IWN_EEPROM); 9120 IWN_DESC(IWN_EEPROM_GP); 9121 IWN_DESC(IWN_OTP_GP); 9122 IWN_DESC(IWN_GIO); 9123 IWN_DESC(IWN_GP_UCODE); 9124 IWN_DESC(IWN_GP_DRIVER); 9125 IWN_DESC(IWN_UCODE_GP1); 9126 IWN_DESC(IWN_UCODE_GP2); 9127 IWN_DESC(IWN_LED); 9128 IWN_DESC(IWN_DRAM_INT_TBL); 9129 IWN_DESC(IWN_GIO_CHICKEN); 9130 IWN_DESC(IWN_ANA_PLL); 9131 IWN_DESC(IWN_HW_REV_WA); 9132 IWN_DESC(IWN_DBG_HPET_MEM); 9133 default: 9134 return "UNKNOWN CSR"; 9135 } 9136 } 9137 9138 /* 9139 * This function print firmware register 9140 */ 9141 static void 9142 iwn_debug_register(struct iwn_softc *sc) 9143 { 9144 int i; 9145 static const uint32_t csr_tbl[] = { 9146 IWN_HW_IF_CONFIG, 9147 IWN_INT_COALESCING, 9148 IWN_INT, 9149 IWN_INT_MASK, 9150 IWN_FH_INT, 9151 IWN_GPIO_IN, 9152 IWN_RESET, 9153 IWN_GP_CNTRL, 9154 IWN_HW_REV, 9155 IWN_EEPROM, 9156 IWN_EEPROM_GP, 9157 IWN_OTP_GP, 9158 IWN_GIO, 9159 IWN_GP_UCODE, 9160 IWN_GP_DRIVER, 9161 IWN_UCODE_GP1, 9162 IWN_UCODE_GP2, 9163 IWN_LED, 9164 IWN_DRAM_INT_TBL, 9165 IWN_GIO_CHICKEN, 9166 IWN_ANA_PLL, 9167 IWN_HW_REV_WA, 9168 IWN_DBG_HPET_MEM, 9169 }; 9170 DPRINTF(sc, IWN_DEBUG_REGISTER, 9171 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 9172 "\n"); 9173 for (i = 0; i < nitems(csr_tbl); i++){ 9174 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 9175 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 9176 if ((i+1) % 3 == 0) 9177 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9178 } 9179 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 9180 } 9181 #endif 9182 9183 9184