1 /*- 2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org> 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2011 Intel Corporation 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 * $FreeBSD: head/sys/dev/iwn/if_iwn.c 258118 2013-11-14 07:27:00Z adrian $ 22 */ 23 24 /* 25 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 26 * adapters. 27 */ 28 29 #include "opt_wlan.h" 30 #include "opt_iwn.h" 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/stdbool.h> 41 #include <sys/bus.h> 42 #include <sys/rman.h> 43 #include <sys/endian.h> 44 #include <sys/firmware.h> 45 #include <sys/limits.h> 46 #include <sys/module.h> 47 #include <sys/queue.h> 48 #include <sys/taskqueue.h> 49 #include <sys/libkern.h> 50 51 #include <sys/resource.h> 52 #include <machine/clock.h> 53 54 #include <bus/pci/pcireg.h> 55 #include <bus/pci/pcivar.h> 56 57 #include <net/bpf.h> 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_arp.h> 61 #include <net/ifq_var.h> 62 #include <net/ethernet.h> 63 #include <net/if_dl.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 73 #include <netproto/802_11/ieee80211_var.h> 74 #include <netproto/802_11/ieee80211_radiotap.h> 75 #include <netproto/802_11/ieee80211_regdomain.h> 76 #include <netproto/802_11/ieee80211_ratectl.h> 77 78 #include "if_iwnreg.h" 79 #include "if_iwnvar.h" 80 #include "if_iwn_devid.h" 81 #include "if_iwn_chip_cfg.h" 82 #include "if_iwn_debug.h" 83 #include "if_iwn_ioctl.h" 84 85 #define IWN_LOCK(sc) 86 #define IWN_UNLOCK(sc) 87 88 struct iwn_ident { 89 uint16_t vendor; 90 uint16_t device; 91 const char *name; 92 }; 93 94 static const struct iwn_ident iwn_ident_table[] = { 95 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 96 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 97 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 98 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 99 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 100 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 101 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 102 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 103 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 104 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 105 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 106 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 107 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 108 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 109 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */ 110 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 111 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 112 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 113 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 114 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 115 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 116 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" }, 117 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" }, 118 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" }, 119 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" }, 120 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 121 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 122 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 123 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 124 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 125 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 126 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 127 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 128 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 129 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 130 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 131 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 132 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 133 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 134 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 135 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 136 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" }, 137 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" }, 138 { 0, 0, NULL } 139 }; 140 141 static int iwn_pci_probe(device_t); 142 static int iwn_pci_attach(device_t); 143 static int iwn4965_attach(struct iwn_softc *, uint16_t); 144 static int iwn5000_attach(struct iwn_softc *, uint16_t); 145 static int iwn_config_specific(struct iwn_softc *, uint16_t); 146 static void iwn_radiotap_attach(struct iwn_softc *); 147 static void iwn_sysctlattach(struct iwn_softc *); 148 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 149 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 150 const uint8_t [IEEE80211_ADDR_LEN], 151 const uint8_t [IEEE80211_ADDR_LEN]); 152 static void iwn_vap_delete(struct ieee80211vap *); 153 static int iwn_pci_detach(device_t); 154 static int iwn_pci_shutdown(device_t); 155 static int iwn_pci_suspend(device_t); 156 static int iwn_pci_resume(device_t); 157 static int iwn_nic_lock(struct iwn_softc *); 158 static int iwn_eeprom_lock(struct iwn_softc *); 159 static int iwn_init_otprom(struct iwn_softc *); 160 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 161 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 162 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 163 void **, bus_size_t, bus_size_t); 164 static void iwn_dma_contig_free(struct iwn_dma_info *); 165 static int iwn_alloc_sched(struct iwn_softc *); 166 static void iwn_free_sched(struct iwn_softc *); 167 static int iwn_alloc_kw(struct iwn_softc *); 168 static void iwn_free_kw(struct iwn_softc *); 169 static int iwn_alloc_ict(struct iwn_softc *); 170 static void iwn_free_ict(struct iwn_softc *); 171 static int iwn_alloc_fwmem(struct iwn_softc *); 172 static void iwn_free_fwmem(struct iwn_softc *); 173 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 174 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 175 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 176 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 177 int); 178 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 179 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 180 static void iwn5000_ict_reset(struct iwn_softc *); 181 static int iwn_read_eeprom(struct iwn_softc *, 182 uint8_t macaddr[IEEE80211_ADDR_LEN]); 183 static void iwn4965_read_eeprom(struct iwn_softc *); 184 #ifdef IWN_DEBUG 185 static void iwn4965_print_power_group(struct iwn_softc *, int); 186 #endif 187 static void iwn5000_read_eeprom(struct iwn_softc *); 188 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 189 static void iwn_read_eeprom_band(struct iwn_softc *, int); 190 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 191 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 192 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 193 struct ieee80211_channel *); 194 static int iwn_setregdomain(struct ieee80211com *, 195 struct ieee80211_regdomain *, int, 196 struct ieee80211_channel[]); 197 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 198 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 199 const uint8_t mac[IEEE80211_ADDR_LEN]); 200 static void iwn_newassoc(struct ieee80211_node *, int); 201 static int iwn_media_change(struct ifnet *); 202 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 203 static void iwn_calib_timeout(void *); 204 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 205 struct iwn_rx_data *); 206 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 207 struct iwn_rx_data *); 208 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 209 struct iwn_rx_data *); 210 static void iwn5000_rx_calib_results(struct iwn_softc *, 211 struct iwn_rx_desc *, struct iwn_rx_data *); 212 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 213 struct iwn_rx_data *); 214 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 215 struct iwn_rx_data *); 216 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 217 struct iwn_rx_data *); 218 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 219 uint8_t); 220 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *); 221 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 222 static void iwn_notif_intr(struct iwn_softc *); 223 static void iwn_wakeup_intr(struct iwn_softc *); 224 static void iwn_rftoggle_intr(struct iwn_softc *); 225 static void iwn_fatal_intr(struct iwn_softc *); 226 static void iwn_intr(void *); 227 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 228 uint16_t); 229 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 230 uint16_t); 231 #ifdef notyet 232 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 233 #endif 234 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 235 struct ieee80211_node *); 236 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 237 struct ieee80211_node *, 238 const struct ieee80211_bpf_params *params); 239 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 240 const struct ieee80211_bpf_params *); 241 static void iwn_start(struct ifnet *, struct ifaltq_subque *); 242 static void iwn_start_locked(struct ifnet *); 243 static void iwn_watchdog_timeout(void *); 244 static int iwn_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 245 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 246 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 247 int); 248 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 249 int); 250 static int iwn_set_link_quality(struct iwn_softc *, 251 struct ieee80211_node *); 252 static int iwn_add_broadcast_node(struct iwn_softc *, int); 253 static int iwn_updateedca(struct ieee80211com *); 254 static void iwn_update_mcast(struct ifnet *); 255 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 256 static int iwn_set_critical_temp(struct iwn_softc *); 257 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 258 static void iwn4965_power_calibration(struct iwn_softc *, int); 259 static int iwn4965_set_txpower(struct iwn_softc *, 260 struct ieee80211_channel *, int); 261 static int iwn5000_set_txpower(struct iwn_softc *, 262 struct ieee80211_channel *, int); 263 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 264 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 265 static int iwn_get_noise(const struct iwn_rx_general_stats *); 266 static int iwn4965_get_temperature(struct iwn_softc *); 267 static int iwn5000_get_temperature(struct iwn_softc *); 268 static int iwn_init_sensitivity(struct iwn_softc *); 269 static void iwn_collect_noise(struct iwn_softc *, 270 const struct iwn_rx_general_stats *); 271 static int iwn4965_init_gains(struct iwn_softc *); 272 static int iwn5000_init_gains(struct iwn_softc *); 273 static int iwn4965_set_gains(struct iwn_softc *); 274 static int iwn5000_set_gains(struct iwn_softc *); 275 static void iwn_tune_sensitivity(struct iwn_softc *, 276 const struct iwn_rx_stats *); 277 static void iwn_save_stats_counters(struct iwn_softc *, 278 const struct iwn_stats *); 279 static int iwn_send_sensitivity(struct iwn_softc *); 280 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *); 281 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 282 static int iwn_send_btcoex(struct iwn_softc *); 283 static int iwn_send_advanced_btcoex(struct iwn_softc *); 284 static int iwn5000_runtime_calib(struct iwn_softc *); 285 static int iwn_config(struct iwn_softc *); 286 static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int); 287 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *, 288 struct ieee80211_scan_state *, struct ieee80211_channel *); 289 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 290 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 291 static int iwn_ampdu_rx_start(struct ieee80211_node *, 292 struct ieee80211_rx_ampdu *, int, int, int); 293 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 294 struct ieee80211_rx_ampdu *); 295 static int iwn_addba_request(struct ieee80211_node *, 296 struct ieee80211_tx_ampdu *, int, int, int); 297 static int iwn_addba_response(struct ieee80211_node *, 298 struct ieee80211_tx_ampdu *, int, int, int); 299 static int iwn_ampdu_tx_start(struct ieee80211com *, 300 struct ieee80211_node *, uint8_t); 301 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 302 struct ieee80211_tx_ampdu *); 303 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 304 struct ieee80211_node *, int, uint8_t, uint16_t); 305 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 306 uint8_t, uint16_t); 307 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 308 struct ieee80211_node *, int, uint8_t, uint16_t); 309 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 310 uint8_t, uint16_t); 311 static int iwn5000_query_calibration(struct iwn_softc *); 312 static int iwn5000_send_calibration(struct iwn_softc *); 313 static int iwn5000_send_wimax_coex(struct iwn_softc *); 314 static int iwn5000_crystal_calib(struct iwn_softc *); 315 static int iwn5000_temp_offset_calib(struct iwn_softc *); 316 static int iwn5000_temp_offset_calibv2(struct iwn_softc *); 317 static int iwn4965_post_alive(struct iwn_softc *); 318 static int iwn5000_post_alive(struct iwn_softc *); 319 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 320 int); 321 static int iwn4965_load_firmware(struct iwn_softc *); 322 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 323 const uint8_t *, int); 324 static int iwn5000_load_firmware(struct iwn_softc *); 325 static int iwn_read_firmware_leg(struct iwn_softc *, 326 struct iwn_fw_info *); 327 static int iwn_read_firmware_tlv(struct iwn_softc *, 328 struct iwn_fw_info *, uint16_t); 329 static int iwn_read_firmware(struct iwn_softc *); 330 static int iwn_clock_wait(struct iwn_softc *); 331 static int iwn_apm_init(struct iwn_softc *); 332 static void iwn_apm_stop_master(struct iwn_softc *); 333 static void iwn_apm_stop(struct iwn_softc *); 334 static int iwn4965_nic_config(struct iwn_softc *); 335 static int iwn5000_nic_config(struct iwn_softc *); 336 static int iwn_hw_prepare(struct iwn_softc *); 337 static int iwn_hw_init(struct iwn_softc *); 338 static void iwn_hw_stop(struct iwn_softc *); 339 static void iwn_radio_on_task(void *, int); 340 static void iwn_radio_off_task(void *, int); 341 static void iwn_panicked_task(void *, int); 342 static void iwn_init_locked(struct iwn_softc *); 343 static void iwn_init(void *); 344 static void iwn_stop_locked(struct iwn_softc *); 345 static void iwn_scan_start(struct ieee80211com *); 346 static void iwn_scan_end(struct ieee80211com *); 347 static void iwn_set_channel(struct ieee80211com *); 348 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 349 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 350 static void iwn_hw_reset_task(void *, int); 351 #ifdef IWN_DEBUG 352 static char *iwn_get_csr_string(int); 353 static void iwn_debug_register(struct iwn_softc *); 354 #endif 355 356 static device_method_t iwn_methods[] = { 357 /* Device interface */ 358 DEVMETHOD(device_probe, iwn_pci_probe), 359 DEVMETHOD(device_attach, iwn_pci_attach), 360 DEVMETHOD(device_detach, iwn_pci_detach), 361 DEVMETHOD(device_shutdown, iwn_pci_shutdown), 362 DEVMETHOD(device_suspend, iwn_pci_suspend), 363 DEVMETHOD(device_resume, iwn_pci_resume), 364 365 DEVMETHOD_END 366 }; 367 368 static driver_t iwn_driver = { 369 "iwn", 370 iwn_methods, 371 sizeof(struct iwn_softc) 372 }; 373 static devclass_t iwn_devclass; 374 375 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL); 376 377 MODULE_VERSION(iwn, 1); 378 379 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 380 MODULE_DEPEND(iwn, pci, 1, 1, 1); 381 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 382 MODULE_DEPEND(iwn, wlan_amrr, 1, 1, 1); 383 384 static int 385 iwn_pci_probe(device_t dev) 386 { 387 const struct iwn_ident *ident; 388 389 /* no wlan serializer needed */ 390 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 391 if (pci_get_vendor(dev) == ident->vendor && 392 pci_get_device(dev) == ident->device) { 393 device_set_desc(dev, ident->name); 394 return (BUS_PROBE_DEFAULT); 395 } 396 } 397 return ENXIO; 398 } 399 400 static int 401 iwn_pci_attach(device_t dev) 402 { 403 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 404 struct ieee80211com *ic; 405 struct ifnet *ifp; 406 int i, error, rid; 407 uint8_t macaddr[IEEE80211_ADDR_LEN]; 408 char ethstr[ETHER_ADDRSTRLEN + 1]; 409 410 wlan_serialize_enter(); 411 412 sc->sc_dev = dev; 413 sc->sc_dmat = NULL; 414 415 if (bus_dma_tag_create(sc->sc_dmat, 416 1, 0, 417 BUS_SPACE_MAXADDR_32BIT, 418 BUS_SPACE_MAXADDR, 419 NULL, NULL, 420 BUS_SPACE_MAXSIZE, 421 IWN_MAX_SCATTER, 422 BUS_SPACE_MAXSIZE, 423 BUS_DMA_ALLOCNOW, 424 &sc->sc_dmat)) { 425 device_printf(dev, "cannot allocate DMA tag\n"); 426 error = ENOMEM; 427 goto fail; 428 } 429 430 /* prepare sysctl tree for use in sub modules */ 431 sysctl_ctx_init(&sc->sc_sysctl_ctx); 432 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx, 433 SYSCTL_STATIC_CHILDREN(_hw), 434 OID_AUTO, 435 device_get_nameunit(sc->sc_dev), 436 CTLFLAG_RD, 0, ""); 437 438 #ifdef IWN_DEBUG 439 error = resource_int_value(device_get_name(sc->sc_dev), 440 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 441 if (error != 0) 442 sc->sc_debug = 0; 443 #else 444 sc->sc_debug = 0; 445 #endif 446 447 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 448 449 /* 450 * Get the offset of the PCI Express Capability Structure in PCI 451 * Configuration Space. 452 */ 453 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 454 if (error != 0) { 455 device_printf(dev, "PCIe capability structure not found!\n"); 456 goto fail2; 457 } 458 459 /* Clear device-specific "PCI retry timeout" register (41h). */ 460 pci_write_config(dev, 0x41, 0, 1); 461 462 /* Enable bus-mastering. */ 463 pci_enable_busmaster(dev); 464 465 rid = PCIR_BAR(0); 466 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 467 RF_ACTIVE); 468 if (sc->mem == NULL) { 469 device_printf(dev, "can't map mem space\n"); 470 error = ENOMEM; 471 goto fail2; 472 } 473 sc->sc_st = rman_get_bustag(sc->mem); 474 sc->sc_sh = rman_get_bushandle(sc->mem); 475 476 rid = 0; 477 #ifdef OLD_MSI 478 i = 1; 479 if (pci_alloc_msi(dev, &i) == 0) 480 rid = 1; 481 #endif 482 /* Install interrupt handler. */ 483 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 484 (rid != 0 ? 0 : RF_SHAREABLE)); 485 if (sc->irq == NULL) { 486 device_printf(dev, "can't map interrupt\n"); 487 error = ENOMEM; 488 goto fail; 489 } 490 491 /* Read hardware revision and attach. */ 492 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 493 & IWN_HW_REV_TYPE_MASK; 494 sc->subdevice_id = pci_get_subdevice(dev); 495 /* 496 * 4965 versus 5000 and later have different methods. 497 * Let's set those up first. 498 */ 499 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 500 error = iwn4965_attach(sc, pci_get_device(dev)); 501 else 502 error = iwn5000_attach(sc, pci_get_device(dev)); 503 if (error != 0) { 504 device_printf(dev, "could not attach device, error %d\n", 505 error); 506 goto fail; 507 } 508 509 /* 510 * Next, let's setup the various parameters of each NIC. 511 */ 512 error = iwn_config_specific(sc, pci_get_device(dev)); 513 if (error != 0) { 514 device_printf(dev, "could not attach device, error %d\n", 515 error); 516 goto fail; 517 } 518 519 if ((error = iwn_hw_prepare(sc)) != 0) { 520 device_printf(dev, "hardware not ready, error %d\n", error); 521 goto fail; 522 } 523 524 /* Allocate DMA memory for firmware transfers. */ 525 if ((error = iwn_alloc_fwmem(sc)) != 0) { 526 device_printf(dev, 527 "could not allocate memory for firmware, error %d\n", 528 error); 529 goto fail; 530 } 531 532 /* Allocate "Keep Warm" page. */ 533 if ((error = iwn_alloc_kw(sc)) != 0) { 534 device_printf(dev, 535 "could not allocate keep warm page, error %d\n", error); 536 goto fail; 537 } 538 539 /* Allocate ICT table for 5000 Series. */ 540 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 541 (error = iwn_alloc_ict(sc)) != 0) { 542 device_printf(dev, "could not allocate ICT table, error %d\n", 543 error); 544 goto fail; 545 } 546 547 /* Allocate TX scheduler "rings". */ 548 if ((error = iwn_alloc_sched(sc)) != 0) { 549 device_printf(dev, 550 "could not allocate TX scheduler rings, error %d\n", error); 551 goto fail; 552 } 553 554 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 555 for (i = 0; i < sc->ntxqs; i++) { 556 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 557 device_printf(dev, 558 "could not allocate TX ring %d, error %d\n", i, 559 error); 560 goto fail; 561 } 562 } 563 564 /* Allocate RX ring. */ 565 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 566 device_printf(dev, "could not allocate RX ring, error %d\n", 567 error); 568 goto fail; 569 } 570 571 /* Clear pending interrupts. */ 572 IWN_WRITE(sc, IWN_INT, 0xffffffff); 573 574 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 575 if (ifp == NULL) { 576 device_printf(dev, "can not allocate ifnet structure\n"); 577 goto fail; 578 } 579 580 ic = ifp->if_l2com; 581 ic->ic_ifp = ifp; 582 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 583 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 584 585 /* Set device capabilities. */ 586 ic->ic_caps = 587 IEEE80211_C_STA /* station mode supported */ 588 | IEEE80211_C_MONITOR /* monitor mode supported */ 589 | IEEE80211_C_BGSCAN /* background scanning */ 590 | IEEE80211_C_TXPMGT /* tx power management */ 591 | IEEE80211_C_SHSLOT /* short slot time supported */ 592 | IEEE80211_C_WPA 593 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 594 #if 0 595 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 596 #endif 597 | IEEE80211_C_WME /* WME */ 598 | IEEE80211_C_PMGT /* Station-side power mgmt */ 599 ; 600 601 /* Read MAC address, channels, etc from EEPROM. */ 602 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) { 603 device_printf(dev, "could not read EEPROM, error %d\n", 604 error); 605 goto fail; 606 } 607 608 /* Count the number of available chains. */ 609 sc->ntxchains = 610 ((sc->txchainmask >> 2) & 1) + 611 ((sc->txchainmask >> 1) & 1) + 612 ((sc->txchainmask >> 0) & 1); 613 sc->nrxchains = 614 ((sc->rxchainmask >> 2) & 1) + 615 ((sc->rxchainmask >> 1) & 1) + 616 ((sc->rxchainmask >> 0) & 1); 617 if (bootverbose) { 618 device_printf(dev, "MIMO %dT%dR, %.4s, address %s\n", 619 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 620 kether_ntoa(macaddr, ethstr)); 621 } 622 623 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 624 #ifdef notyet 625 ic->ic_rxstream = sc->nrxchains; 626 ic->ic_txstream = sc->ntxchains; 627 #endif 628 629 /* 630 * The NICs we currently support cap out at 2x2 support 631 * separate from the chains being used. 632 * 633 * This is a total hack to work around that until some 634 * per-device method is implemented to return the 635 * actual stream support. 636 * 637 * XXX Note: the 5350 is a 3x3 device; so we shouldn't 638 * cap this! But, anything that touches rates in the 639 * driver needs to be audited first before 3x3 is enabled. 640 */ 641 #ifdef notyet 642 if (ic->ic_rxstream > 2) 643 ic->ic_rxstream = 2; 644 if (ic->ic_txstream > 2) 645 ic->ic_txstream = 2; 646 #endif 647 648 ic->ic_htcaps = 649 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 650 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 651 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 652 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 653 #ifdef notyet 654 | IEEE80211_HTCAP_GREENFIELD 655 #if IWN_RBUF_SIZE == 8192 656 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 657 #else 658 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 659 #endif 660 #endif 661 /* s/w capabilities */ 662 | IEEE80211_HTC_HT /* HT operation */ 663 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 664 #ifdef notyet 665 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 666 #endif 667 ; 668 } 669 670 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 671 ifp->if_softc = sc; 672 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 673 ifp->if_init = iwn_init; 674 ifp->if_ioctl = iwn_ioctl; 675 ifp->if_start = iwn_start; 676 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 677 #ifdef notyet 678 ifq_set_ready(&ifp->if_snd); 679 #endif 680 681 ieee80211_ifattach(ic, macaddr); 682 ic->ic_vap_create = iwn_vap_create; 683 ic->ic_vap_delete = iwn_vap_delete; 684 ic->ic_raw_xmit = iwn_raw_xmit; 685 ic->ic_node_alloc = iwn_node_alloc; 686 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 687 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 688 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 689 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 690 sc->sc_addba_request = ic->ic_addba_request; 691 ic->ic_addba_request = iwn_addba_request; 692 sc->sc_addba_response = ic->ic_addba_response; 693 ic->ic_addba_response = iwn_addba_response; 694 sc->sc_addba_stop = ic->ic_addba_stop; 695 ic->ic_addba_stop = iwn_ampdu_tx_stop; 696 ic->ic_newassoc = iwn_newassoc; 697 ic->ic_wme.wme_update = iwn_updateedca; 698 ic->ic_update_mcast = iwn_update_mcast; 699 ic->ic_scan_start = iwn_scan_start; 700 ic->ic_scan_end = iwn_scan_end; 701 ic->ic_set_channel = iwn_set_channel; 702 ic->ic_scan_curchan = iwn_scan_curchan; 703 ic->ic_scan_mindwell = iwn_scan_mindwell; 704 ic->ic_setregdomain = iwn_setregdomain; 705 706 iwn_radiotap_attach(sc); 707 708 callout_init(&sc->calib_to); 709 callout_init(&sc->watchdog_to); 710 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset_task, sc); 711 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on_task, sc); 712 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off_task, sc); 713 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked_task, sc); 714 715 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK, 716 taskqueue_thread_enqueue, &sc->sc_tq); 717 error = taskqueue_start_threads(&sc->sc_tq, 1, TDPRI_KERN_DAEMON, -1, 718 "iwn_taskq"); 719 if (error != 0) { 720 device_printf(dev, "can't start threads, error %d\n", error); 721 goto fail; 722 } 723 724 iwn_sysctlattach(sc); 725 726 /* 727 * Hook our interrupt after all initialization is complete. 728 */ 729 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE, 730 iwn_intr, sc, &sc->sc_ih, 731 &wlan_global_serializer); 732 if (error != 0) { 733 device_printf(dev, "can't establish interrupt, error %d\n", 734 error); 735 goto fail; 736 } 737 738 #if 0 739 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n", 740 __func__, 741 sizeof(struct iwn_stats), 742 sizeof(struct iwn_stats_bt)); 743 #endif 744 745 if (bootverbose) 746 ieee80211_announce(ic); 747 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 748 wlan_serialize_exit(); 749 return 0; 750 fail: 751 wlan_serialize_exit(); 752 iwn_pci_detach(dev); 753 wlan_serialize_enter(); 754 fail2: 755 wlan_serialize_exit(); 756 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 757 return error; 758 } 759 760 /* 761 * Define specific configuration based on device id and subdevice id 762 * pid : PCI device id 763 */ 764 static int 765 iwn_config_specific(struct iwn_softc *sc, uint16_t pid) 766 { 767 768 switch (pid) { 769 /* 4965 series */ 770 case IWN_DID_4965_1: 771 case IWN_DID_4965_2: 772 case IWN_DID_4965_3: 773 case IWN_DID_4965_4: 774 sc->base_params = &iwn4965_base_params; 775 sc->limits = &iwn4965_sensitivity_limits; 776 sc->fwname = "iwn4965fw"; 777 /* Override chains masks, ROM is known to be broken. */ 778 sc->txchainmask = IWN_ANT_AB; 779 sc->rxchainmask = IWN_ANT_ABC; 780 /* Enable normal btcoex */ 781 sc->sc_flags |= IWN_FLAG_BTCOEX; 782 break; 783 /* 1000 Series */ 784 case IWN_DID_1000_1: 785 case IWN_DID_1000_2: 786 switch(sc->subdevice_id) { 787 case IWN_SDID_1000_1: 788 case IWN_SDID_1000_2: 789 case IWN_SDID_1000_3: 790 case IWN_SDID_1000_4: 791 case IWN_SDID_1000_5: 792 case IWN_SDID_1000_6: 793 case IWN_SDID_1000_7: 794 case IWN_SDID_1000_8: 795 case IWN_SDID_1000_9: 796 case IWN_SDID_1000_10: 797 case IWN_SDID_1000_11: 798 case IWN_SDID_1000_12: 799 sc->limits = &iwn1000_sensitivity_limits; 800 sc->base_params = &iwn1000_base_params; 801 sc->fwname = "iwn1000fw"; 802 break; 803 default: 804 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 805 "0x%04x rev %d not supported (subdevice)\n", pid, 806 sc->subdevice_id,sc->hw_type); 807 return ENOTSUP; 808 } 809 break; 810 /* 6x00 Series */ 811 case IWN_DID_6x00_2: 812 case IWN_DID_6x00_4: 813 case IWN_DID_6x00_1: 814 case IWN_DID_6x00_3: 815 sc->fwname = "iwn6000fw"; 816 sc->limits = &iwn6000_sensitivity_limits; 817 switch(sc->subdevice_id) { 818 case IWN_SDID_6x00_1: 819 case IWN_SDID_6x00_2: 820 case IWN_SDID_6x00_8: 821 //iwl6000_3agn_cfg 822 sc->base_params = &iwn_6000_base_params; 823 break; 824 case IWN_SDID_6x00_3: 825 case IWN_SDID_6x00_6: 826 case IWN_SDID_6x00_9: 827 ////iwl6000i_2agn 828 case IWN_SDID_6x00_4: 829 case IWN_SDID_6x00_7: 830 case IWN_SDID_6x00_10: 831 //iwl6000i_2abg_cfg 832 case IWN_SDID_6x00_5: 833 //iwl6000i_2bg_cfg 834 sc->base_params = &iwn_6000i_base_params; 835 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 836 sc->txchainmask = IWN_ANT_BC; 837 sc->rxchainmask = IWN_ANT_BC; 838 break; 839 default: 840 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 841 "0x%04x rev %d not supported (subdevice)\n", pid, 842 sc->subdevice_id,sc->hw_type); 843 return ENOTSUP; 844 } 845 break; 846 /* 6x05 Series */ 847 case IWN_DID_6x05_1: 848 case IWN_DID_6x05_2: 849 switch(sc->subdevice_id) { 850 case IWN_SDID_6x05_1: 851 case IWN_SDID_6x05_4: 852 case IWN_SDID_6x05_6: 853 //iwl6005_2agn_cfg 854 case IWN_SDID_6x05_2: 855 case IWN_SDID_6x05_5: 856 case IWN_SDID_6x05_7: 857 //iwl6005_2abg_cfg 858 case IWN_SDID_6x05_3: 859 //iwl6005_2bg_cfg 860 case IWN_SDID_6x05_8: 861 case IWN_SDID_6x05_9: 862 //iwl6005_2agn_sff_cfg 863 case IWN_SDID_6x05_10: 864 //iwl6005_2agn_d_cfg 865 case IWN_SDID_6x05_11: 866 //iwl6005_2agn_mow1_cfg 867 case IWN_SDID_6x05_12: 868 //iwl6005_2agn_mow2_cfg 869 sc->fwname = "iwn6000g2afw"; 870 sc->limits = &iwn6000_sensitivity_limits; 871 sc->base_params = &iwn_6000g2_base_params; 872 break; 873 default: 874 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 875 "0x%04x rev %d not supported (subdevice)\n", pid, 876 sc->subdevice_id,sc->hw_type); 877 return ENOTSUP; 878 } 879 break; 880 /* 6x35 Series */ 881 case IWN_DID_6035_1: 882 case IWN_DID_6035_2: 883 switch(sc->subdevice_id) { 884 case IWN_SDID_6035_1: 885 case IWN_SDID_6035_2: 886 case IWN_SDID_6035_3: 887 case IWN_SDID_6035_4: 888 sc->fwname = "iwn6000g2bfw"; 889 sc->limits = &iwn6235_sensitivity_limits; 890 sc->base_params = &iwn_6235_base_params; 891 break; 892 default: 893 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 894 "0x%04x rev %d not supported (subdevice)\n", pid, 895 sc->subdevice_id,sc->hw_type); 896 return ENOTSUP; 897 } 898 break; 899 /* 6x50 WiFi/WiMax Series */ 900 case IWN_DID_6050_1: 901 case IWN_DID_6050_2: 902 switch(sc->subdevice_id) { 903 case IWN_SDID_6050_1: 904 case IWN_SDID_6050_3: 905 case IWN_SDID_6050_5: 906 //iwl6050_2agn_cfg 907 case IWN_SDID_6050_2: 908 case IWN_SDID_6050_4: 909 case IWN_SDID_6050_6: 910 //iwl6050_2abg_cfg 911 sc->fwname = "iwn6050fw"; 912 sc->txchainmask = IWN_ANT_AB; 913 sc->rxchainmask = IWN_ANT_AB; 914 sc->limits = &iwn6000_sensitivity_limits; 915 sc->base_params = &iwn_6050_base_params; 916 break; 917 default: 918 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 919 "0x%04x rev %d not supported (subdevice)\n", pid, 920 sc->subdevice_id,sc->hw_type); 921 return ENOTSUP; 922 } 923 break; 924 /* 6150 WiFi/WiMax Series */ 925 case IWN_DID_6150_1: 926 case IWN_DID_6150_2: 927 switch(sc->subdevice_id) { 928 case IWN_SDID_6150_1: 929 case IWN_SDID_6150_3: 930 case IWN_SDID_6150_5: 931 // iwl6150_bgn_cfg 932 case IWN_SDID_6150_2: 933 case IWN_SDID_6150_4: 934 case IWN_SDID_6150_6: 935 //iwl6150_bg_cfg 936 sc->fwname = "iwn6050fw"; 937 sc->limits = &iwn6000_sensitivity_limits; 938 sc->base_params = &iwn_6150_base_params; 939 break; 940 default: 941 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 942 "0x%04x rev %d not supported (subdevice)\n", pid, 943 sc->subdevice_id,sc->hw_type); 944 return ENOTSUP; 945 } 946 break; 947 /* 6030 Series and 1030 Series */ 948 case IWN_DID_x030_1: 949 case IWN_DID_x030_2: 950 case IWN_DID_x030_3: 951 case IWN_DID_x030_4: 952 switch(sc->subdevice_id) { 953 case IWN_SDID_x030_1: 954 case IWN_SDID_x030_3: 955 case IWN_SDID_x030_5: 956 // iwl1030_bgn_cfg 957 case IWN_SDID_x030_2: 958 case IWN_SDID_x030_4: 959 case IWN_SDID_x030_6: 960 //iwl1030_bg_cfg 961 case IWN_SDID_x030_7: 962 case IWN_SDID_x030_10: 963 case IWN_SDID_x030_14: 964 //iwl6030_2agn_cfg 965 case IWN_SDID_x030_8: 966 case IWN_SDID_x030_11: 967 case IWN_SDID_x030_15: 968 // iwl6030_2bgn_cfg 969 case IWN_SDID_x030_9: 970 case IWN_SDID_x030_12: 971 case IWN_SDID_x030_16: 972 // iwl6030_2abg_cfg 973 case IWN_SDID_x030_13: 974 //iwl6030_2bg_cfg 975 sc->fwname = "iwn6000g2bfw"; 976 sc->limits = &iwn6000_sensitivity_limits; 977 sc->base_params = &iwn_6000g2b_base_params; 978 break; 979 default: 980 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 981 "0x%04x rev %d not supported (subdevice)\n", pid, 982 sc->subdevice_id,sc->hw_type); 983 return ENOTSUP; 984 } 985 break; 986 /* 130 Series WiFi */ 987 /* XXX: This series will need adjustment for rate. 988 * see rx_with_siso_diversity in linux kernel 989 */ 990 case IWN_DID_130_1: 991 case IWN_DID_130_2: 992 switch(sc->subdevice_id) { 993 case IWN_SDID_130_1: 994 case IWN_SDID_130_3: 995 case IWN_SDID_130_5: 996 //iwl130_bgn_cfg 997 case IWN_SDID_130_2: 998 case IWN_SDID_130_4: 999 case IWN_SDID_130_6: 1000 //iwl130_bg_cfg 1001 sc->fwname = "iwn6000g2bfw"; 1002 sc->limits = &iwn6000_sensitivity_limits; 1003 sc->base_params = &iwn_6000g2b_base_params; 1004 break; 1005 default: 1006 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1007 "0x%04x rev %d not supported (subdevice)\n", pid, 1008 sc->subdevice_id,sc->hw_type); 1009 return ENOTSUP; 1010 } 1011 break; 1012 /* 100 Series WiFi */ 1013 case IWN_DID_100_1: 1014 case IWN_DID_100_2: 1015 switch(sc->subdevice_id) { 1016 case IWN_SDID_100_1: 1017 case IWN_SDID_100_2: 1018 case IWN_SDID_100_3: 1019 case IWN_SDID_100_4: 1020 case IWN_SDID_100_5: 1021 case IWN_SDID_100_6: 1022 sc->limits = &iwn1000_sensitivity_limits; 1023 sc->base_params = &iwn1000_base_params; 1024 sc->fwname = "iwn100fw"; 1025 break; 1026 default: 1027 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1028 "0x%04x rev %d not supported (subdevice)\n", pid, 1029 sc->subdevice_id,sc->hw_type); 1030 return ENOTSUP; 1031 } 1032 break; 1033 1034 /* 105 Series */ 1035 /* XXX: This series will need adjustment for rate. 1036 * see rx_with_siso_diversity in linux kernel 1037 */ 1038 case IWN_DID_105_1: 1039 case IWN_DID_105_2: 1040 switch(sc->subdevice_id) { 1041 case IWN_SDID_105_1: 1042 case IWN_SDID_105_2: 1043 case IWN_SDID_105_3: 1044 //iwl105_bgn_cfg 1045 case IWN_SDID_105_4: 1046 //iwl105_bgn_d_cfg 1047 sc->limits = &iwn2030_sensitivity_limits; 1048 sc->base_params = &iwn2000_base_params; 1049 sc->fwname = "iwn105fw"; 1050 break; 1051 default: 1052 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1053 "0x%04x rev %d not supported (subdevice)\n", pid, 1054 sc->subdevice_id,sc->hw_type); 1055 return ENOTSUP; 1056 } 1057 break; 1058 1059 /* 135 Series */ 1060 /* XXX: This series will need adjustment for rate. 1061 * see rx_with_siso_diversity in linux kernel 1062 */ 1063 case IWN_DID_135_1: 1064 case IWN_DID_135_2: 1065 switch(sc->subdevice_id) { 1066 case IWN_SDID_135_1: 1067 case IWN_SDID_135_2: 1068 case IWN_SDID_135_3: 1069 sc->limits = &iwn2030_sensitivity_limits; 1070 sc->base_params = &iwn2030_base_params; 1071 sc->fwname = "iwn135fw"; 1072 break; 1073 default: 1074 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1075 "0x%04x rev %d not supported (subdevice)\n", pid, 1076 sc->subdevice_id,sc->hw_type); 1077 return ENOTSUP; 1078 } 1079 break; 1080 1081 /* 2x00 Series */ 1082 case IWN_DID_2x00_1: 1083 case IWN_DID_2x00_2: 1084 switch(sc->subdevice_id) { 1085 case IWN_SDID_2x00_1: 1086 case IWN_SDID_2x00_2: 1087 case IWN_SDID_2x00_3: 1088 //iwl2000_2bgn_cfg 1089 case IWN_SDID_2x00_4: 1090 //iwl2000_2bgn_d_cfg 1091 sc->limits = &iwn2030_sensitivity_limits; 1092 sc->base_params = &iwn2000_base_params; 1093 sc->fwname = "iwn2000fw"; 1094 break; 1095 default: 1096 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1097 "0x%04x rev %d not supported (subdevice) \n", 1098 pid, sc->subdevice_id, sc->hw_type); 1099 return ENOTSUP; 1100 } 1101 break; 1102 /* 2x30 Series */ 1103 case IWN_DID_2x30_1: 1104 case IWN_DID_2x30_2: 1105 switch(sc->subdevice_id) { 1106 case IWN_SDID_2x30_1: 1107 case IWN_SDID_2x30_3: 1108 case IWN_SDID_2x30_5: 1109 //iwl100_bgn_cfg 1110 case IWN_SDID_2x30_2: 1111 case IWN_SDID_2x30_4: 1112 case IWN_SDID_2x30_6: 1113 //iwl100_bg_cfg 1114 sc->limits = &iwn2030_sensitivity_limits; 1115 sc->base_params = &iwn2030_base_params; 1116 sc->fwname = "iwn2030fw"; 1117 break; 1118 default: 1119 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1120 "0x%04x rev %d not supported (subdevice)\n", pid, 1121 sc->subdevice_id,sc->hw_type); 1122 return ENOTSUP; 1123 } 1124 break; 1125 /* 5x00 Series */ 1126 case IWN_DID_5x00_1: 1127 case IWN_DID_5x00_2: 1128 case IWN_DID_5x00_3: 1129 case IWN_DID_5x00_4: 1130 sc->limits = &iwn5000_sensitivity_limits; 1131 sc->base_params = &iwn5000_base_params; 1132 sc->fwname = "iwn5000fw"; 1133 switch(sc->subdevice_id) { 1134 case IWN_SDID_5x00_1: 1135 case IWN_SDID_5x00_2: 1136 case IWN_SDID_5x00_3: 1137 case IWN_SDID_5x00_4: 1138 case IWN_SDID_5x00_9: 1139 case IWN_SDID_5x00_10: 1140 case IWN_SDID_5x00_11: 1141 case IWN_SDID_5x00_12: 1142 case IWN_SDID_5x00_17: 1143 case IWN_SDID_5x00_18: 1144 case IWN_SDID_5x00_19: 1145 case IWN_SDID_5x00_20: 1146 //iwl5100_agn_cfg 1147 sc->txchainmask = IWN_ANT_B; 1148 sc->rxchainmask = IWN_ANT_AB; 1149 break; 1150 case IWN_SDID_5x00_5: 1151 case IWN_SDID_5x00_6: 1152 case IWN_SDID_5x00_13: 1153 case IWN_SDID_5x00_14: 1154 case IWN_SDID_5x00_21: 1155 case IWN_SDID_5x00_22: 1156 //iwl5100_bgn_cfg 1157 sc->txchainmask = IWN_ANT_B; 1158 sc->rxchainmask = IWN_ANT_AB; 1159 break; 1160 case IWN_SDID_5x00_7: 1161 case IWN_SDID_5x00_8: 1162 case IWN_SDID_5x00_15: 1163 case IWN_SDID_5x00_16: 1164 case IWN_SDID_5x00_23: 1165 case IWN_SDID_5x00_24: 1166 //iwl5100_abg_cfg 1167 sc->txchainmask = IWN_ANT_B; 1168 sc->rxchainmask = IWN_ANT_AB; 1169 break; 1170 case IWN_SDID_5x00_25: 1171 case IWN_SDID_5x00_26: 1172 case IWN_SDID_5x00_27: 1173 case IWN_SDID_5x00_28: 1174 case IWN_SDID_5x00_29: 1175 case IWN_SDID_5x00_30: 1176 case IWN_SDID_5x00_31: 1177 case IWN_SDID_5x00_32: 1178 case IWN_SDID_5x00_33: 1179 case IWN_SDID_5x00_34: 1180 case IWN_SDID_5x00_35: 1181 case IWN_SDID_5x00_36: 1182 //iwl5300_agn_cfg 1183 sc->txchainmask = IWN_ANT_ABC; 1184 sc->rxchainmask = IWN_ANT_ABC; 1185 break; 1186 default: 1187 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1188 "0x%04x rev %d not supported (subdevice)\n", pid, 1189 sc->subdevice_id,sc->hw_type); 1190 return ENOTSUP; 1191 } 1192 break; 1193 /* 5x50 Series */ 1194 case IWN_DID_5x50_1: 1195 case IWN_DID_5x50_2: 1196 case IWN_DID_5x50_3: 1197 case IWN_DID_5x50_4: 1198 sc->limits = &iwn5000_sensitivity_limits; 1199 sc->base_params = &iwn5000_base_params; 1200 sc->fwname = "iwn5000fw"; 1201 switch(sc->subdevice_id) { 1202 case IWN_SDID_5x50_1: 1203 case IWN_SDID_5x50_2: 1204 case IWN_SDID_5x50_3: 1205 //iwl5350_agn_cfg 1206 sc->limits = &iwn5000_sensitivity_limits; 1207 sc->base_params = &iwn5000_base_params; 1208 sc->fwname = "iwn5000fw"; 1209 break; 1210 case IWN_SDID_5x50_4: 1211 case IWN_SDID_5x50_5: 1212 case IWN_SDID_5x50_8: 1213 case IWN_SDID_5x50_9: 1214 case IWN_SDID_5x50_10: 1215 case IWN_SDID_5x50_11: 1216 //iwl5150_agn_cfg 1217 case IWN_SDID_5x50_6: 1218 case IWN_SDID_5x50_7: 1219 case IWN_SDID_5x50_12: 1220 case IWN_SDID_5x50_13: 1221 //iwl5150_abg_cfg 1222 sc->limits = &iwn5000_sensitivity_limits; 1223 sc->fwname = "iwn5150fw"; 1224 sc->base_params = &iwn_5x50_base_params; 1225 break; 1226 default: 1227 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1228 "0x%04x rev %d not supported (subdevice)\n", pid, 1229 sc->subdevice_id,sc->hw_type); 1230 return ENOTSUP; 1231 } 1232 break; 1233 default: 1234 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x" 1235 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id, 1236 sc->hw_type); 1237 return ENOTSUP; 1238 } 1239 return 0; 1240 } 1241 1242 static int 1243 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 1244 { 1245 struct iwn_ops *ops = &sc->ops; 1246 1247 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1248 ops->load_firmware = iwn4965_load_firmware; 1249 ops->read_eeprom = iwn4965_read_eeprom; 1250 ops->post_alive = iwn4965_post_alive; 1251 ops->nic_config = iwn4965_nic_config; 1252 ops->update_sched = iwn4965_update_sched; 1253 ops->get_temperature = iwn4965_get_temperature; 1254 ops->get_rssi = iwn4965_get_rssi; 1255 ops->set_txpower = iwn4965_set_txpower; 1256 ops->init_gains = iwn4965_init_gains; 1257 ops->set_gains = iwn4965_set_gains; 1258 ops->add_node = iwn4965_add_node; 1259 ops->tx_done = iwn4965_tx_done; 1260 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 1261 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 1262 sc->ntxqs = IWN4965_NTXQUEUES; 1263 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 1264 sc->ndmachnls = IWN4965_NDMACHNLS; 1265 sc->broadcast_id = IWN4965_ID_BROADCAST; 1266 sc->rxonsz = IWN4965_RXONSZ; 1267 sc->schedsz = IWN4965_SCHEDSZ; 1268 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 1269 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 1270 sc->fwsz = IWN4965_FWSZ; 1271 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 1272 sc->limits = &iwn4965_sensitivity_limits; 1273 sc->fwname = "iwn4965fw"; 1274 /* Override chains masks, ROM is known to be broken. */ 1275 sc->txchainmask = IWN_ANT_AB; 1276 sc->rxchainmask = IWN_ANT_ABC; 1277 /* Enable normal btcoex */ 1278 sc->sc_flags |= IWN_FLAG_BTCOEX; 1279 1280 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1281 1282 return 0; 1283 } 1284 1285 static int 1286 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 1287 { 1288 struct iwn_ops *ops = &sc->ops; 1289 1290 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1291 1292 ops->load_firmware = iwn5000_load_firmware; 1293 ops->read_eeprom = iwn5000_read_eeprom; 1294 ops->post_alive = iwn5000_post_alive; 1295 ops->nic_config = iwn5000_nic_config; 1296 ops->update_sched = iwn5000_update_sched; 1297 ops->get_temperature = iwn5000_get_temperature; 1298 ops->get_rssi = iwn5000_get_rssi; 1299 ops->set_txpower = iwn5000_set_txpower; 1300 ops->init_gains = iwn5000_init_gains; 1301 ops->set_gains = iwn5000_set_gains; 1302 ops->add_node = iwn5000_add_node; 1303 ops->tx_done = iwn5000_tx_done; 1304 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 1305 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 1306 sc->ntxqs = IWN5000_NTXQUEUES; 1307 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 1308 sc->ndmachnls = IWN5000_NDMACHNLS; 1309 sc->broadcast_id = IWN5000_ID_BROADCAST; 1310 sc->rxonsz = IWN5000_RXONSZ; 1311 sc->schedsz = IWN5000_SCHEDSZ; 1312 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 1313 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 1314 sc->fwsz = IWN5000_FWSZ; 1315 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 1316 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 1317 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 1318 1319 return 0; 1320 } 1321 1322 /* 1323 * Attach the interface to 802.11 radiotap. 1324 */ 1325 static void 1326 iwn_radiotap_attach(struct iwn_softc *sc) 1327 { 1328 struct ifnet *ifp = sc->sc_ifp; 1329 struct ieee80211com *ic = ifp->if_l2com; 1330 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1331 ieee80211_radiotap_attach(ic, 1332 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 1333 IWN_TX_RADIOTAP_PRESENT, 1334 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 1335 IWN_RX_RADIOTAP_PRESENT); 1336 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1337 } 1338 1339 static void 1340 iwn_sysctlattach(struct iwn_softc *sc) 1341 { 1342 #ifdef IWN_DEBUG 1343 struct sysctl_ctx_list *ctx; 1344 struct sysctl_oid *tree; 1345 1346 ctx = &sc->sc_sysctl_ctx; 1347 tree = sc->sc_sysctl_tree; 1348 1349 if (tree) { 1350 device_printf(sc->sc_dev, "can't add sysctl node\n"); 1351 return; 1352 } 1353 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1354 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 1355 "control debugging printfs"); 1356 #endif 1357 } 1358 1359 static struct ieee80211vap * 1360 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1361 enum ieee80211_opmode opmode, int flags, 1362 const uint8_t bssid[IEEE80211_ADDR_LEN], 1363 const uint8_t mac[IEEE80211_ADDR_LEN]) 1364 { 1365 struct iwn_vap *ivp; 1366 struct ieee80211vap *vap; 1367 uint8_t mac1[IEEE80211_ADDR_LEN]; 1368 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1369 1370 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1371 return NULL; 1372 1373 IEEE80211_ADDR_COPY(mac1, mac); 1374 1375 ivp = kmalloc(sizeof(struct iwn_vap), M_80211_VAP, M_INTWAIT | M_ZERO); 1376 vap = &ivp->iv_vap; 1377 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac1); 1378 ivp->ctx = IWN_RXON_BSS_CTX; 1379 IEEE80211_ADDR_COPY(ivp->macaddr, mac1); 1380 vap->iv_bmissthreshold = 10; /* override default */ 1381 /* Override with driver methods. */ 1382 ivp->iv_newstate = vap->iv_newstate; 1383 vap->iv_newstate = iwn_newstate; 1384 sc->ivap[IWN_RXON_BSS_CTX] = vap; 1385 1386 ieee80211_ratectl_init(vap); 1387 /* Complete setup. */ 1388 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 1389 ic->ic_opmode = opmode; 1390 return vap; 1391 } 1392 1393 static void 1394 iwn_vap_delete(struct ieee80211vap *vap) 1395 { 1396 struct iwn_vap *ivp = IWN_VAP(vap); 1397 1398 ieee80211_ratectl_deinit(vap); 1399 ieee80211_vap_detach(vap); 1400 kfree(ivp, M_80211_VAP); 1401 } 1402 1403 static int 1404 iwn_pci_detach(device_t dev) 1405 { 1406 struct iwn_softc *sc = device_get_softc(dev); 1407 struct ifnet *ifp = sc->sc_ifp; 1408 struct ieee80211com *ic; 1409 int qid; 1410 1411 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1412 1413 wlan_serialize_enter(); 1414 1415 if (ifp != NULL) { 1416 ic = ifp->if_l2com; 1417 1418 ieee80211_draintask(ic, &sc->sc_reinit_task); 1419 ieee80211_draintask(ic, &sc->sc_radioon_task); 1420 ieee80211_draintask(ic, &sc->sc_radiooff_task); 1421 1422 iwn_stop_locked(sc); 1423 1424 #if 0 1425 // We don't need this for DragonFly as our taskqueue_free() 1426 // is running all remaining tasks before terminating. 1427 taskqueue_drain_all(sc->sc_tq); 1428 #endif 1429 taskqueue_free(sc->sc_tq); 1430 1431 callout_stop(&sc->watchdog_to); 1432 callout_stop(&sc->calib_to); 1433 ieee80211_ifdetach(ic); 1434 } 1435 1436 /* cleanup sysctl nodes */ 1437 sysctl_ctx_free(&sc->sc_sysctl_ctx); 1438 1439 /* Uninstall interrupt handler. */ 1440 if (sc->irq != NULL) { 1441 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 1442 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 1443 sc->irq); 1444 pci_release_msi(dev); 1445 sc->irq = NULL; 1446 } 1447 1448 /* Free DMA resources. */ 1449 iwn_free_rx_ring(sc, &sc->rxq); 1450 for (qid = 0; qid < sc->ntxqs; qid++) 1451 iwn_free_tx_ring(sc, &sc->txq[qid]); 1452 iwn_free_sched(sc); 1453 iwn_free_kw(sc); 1454 if (sc->ict != NULL) { 1455 iwn_free_ict(sc); 1456 sc->ict = NULL; 1457 } 1458 iwn_free_fwmem(sc); 1459 1460 if (sc->mem != NULL) { 1461 bus_release_resource(dev, SYS_RES_MEMORY, 1462 rman_get_rid(sc->mem), sc->mem); 1463 sc->mem = NULL; 1464 } 1465 1466 if (ifp != NULL) { 1467 if_free(ifp); 1468 sc->sc_ifp = NULL; 1469 } 1470 1471 bus_dma_tag_destroy(sc->sc_dmat); 1472 1473 wlan_serialize_exit(); 1474 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 1475 return 0; 1476 } 1477 1478 static int 1479 iwn_pci_shutdown(device_t dev) 1480 { 1481 struct iwn_softc *sc = device_get_softc(dev); 1482 1483 wlan_serialize_enter(); 1484 iwn_stop_locked(sc); 1485 wlan_serialize_exit(); 1486 1487 return 0; 1488 } 1489 1490 static int 1491 iwn_pci_suspend(device_t dev) 1492 { 1493 struct iwn_softc *sc = device_get_softc(dev); 1494 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1495 1496 ieee80211_suspend_all(ic); 1497 return 0; 1498 } 1499 1500 static int 1501 iwn_pci_resume(device_t dev) 1502 { 1503 struct iwn_softc *sc = device_get_softc(dev); 1504 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1505 1506 /* Clear device-specific "PCI retry timeout" register (41h). */ 1507 pci_write_config(dev, 0x41, 0, 1); 1508 1509 ieee80211_resume_all(ic); 1510 return 0; 1511 } 1512 1513 static int 1514 iwn_nic_lock(struct iwn_softc *sc) 1515 { 1516 int ntries; 1517 1518 /* Request exclusive access to NIC. */ 1519 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1520 1521 /* Spin until we actually get the lock. */ 1522 for (ntries = 0; ntries < 1000; ntries++) { 1523 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1524 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1525 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1526 return 0; 1527 DELAY(10); 1528 } 1529 return ETIMEDOUT; 1530 } 1531 1532 static __inline void 1533 iwn_nic_unlock(struct iwn_softc *sc) 1534 { 1535 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1536 } 1537 1538 static __inline uint32_t 1539 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1540 { 1541 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1542 IWN_BARRIER_READ_WRITE(sc); 1543 return IWN_READ(sc, IWN_PRPH_RDATA); 1544 } 1545 1546 static __inline void 1547 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1548 { 1549 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1550 IWN_BARRIER_WRITE(sc); 1551 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1552 } 1553 1554 static __inline void 1555 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1556 { 1557 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1558 } 1559 1560 static __inline void 1561 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1562 { 1563 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1564 } 1565 1566 static __inline void 1567 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1568 const uint32_t *data, int count) 1569 { 1570 for (; count > 0; count--, data++, addr += 4) 1571 iwn_prph_write(sc, addr, *data); 1572 } 1573 1574 static __inline uint32_t 1575 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1576 { 1577 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1578 IWN_BARRIER_READ_WRITE(sc); 1579 return IWN_READ(sc, IWN_MEM_RDATA); 1580 } 1581 1582 static __inline void 1583 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1584 { 1585 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1586 IWN_BARRIER_WRITE(sc); 1587 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1588 } 1589 1590 static __inline void 1591 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1592 { 1593 uint32_t tmp; 1594 1595 tmp = iwn_mem_read(sc, addr & ~3); 1596 if (addr & 3) 1597 tmp = (tmp & 0x0000ffff) | data << 16; 1598 else 1599 tmp = (tmp & 0xffff0000) | data; 1600 iwn_mem_write(sc, addr & ~3, tmp); 1601 } 1602 1603 static __inline void 1604 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1605 int count) 1606 { 1607 for (; count > 0; count--, addr += 4) 1608 *data++ = iwn_mem_read(sc, addr); 1609 } 1610 1611 static __inline void 1612 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1613 int count) 1614 { 1615 for (; count > 0; count--, addr += 4) 1616 iwn_mem_write(sc, addr, val); 1617 } 1618 1619 static int 1620 iwn_eeprom_lock(struct iwn_softc *sc) 1621 { 1622 int i, ntries; 1623 1624 for (i = 0; i < 100; i++) { 1625 /* Request exclusive access to EEPROM. */ 1626 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1627 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1628 1629 /* Spin until we actually get the lock. */ 1630 for (ntries = 0; ntries < 100; ntries++) { 1631 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1632 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1633 return 0; 1634 DELAY(10); 1635 } 1636 } 1637 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1638 return ETIMEDOUT; 1639 } 1640 1641 static __inline void 1642 iwn_eeprom_unlock(struct iwn_softc *sc) 1643 { 1644 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1645 } 1646 1647 /* 1648 * Initialize access by host to One Time Programmable ROM. 1649 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1650 */ 1651 static int 1652 iwn_init_otprom(struct iwn_softc *sc) 1653 { 1654 uint16_t prev, base, next; 1655 int count, error; 1656 1657 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1658 1659 /* Wait for clock stabilization before accessing prph. */ 1660 if ((error = iwn_clock_wait(sc)) != 0) 1661 return error; 1662 1663 if ((error = iwn_nic_lock(sc)) != 0) 1664 return error; 1665 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1666 DELAY(5); 1667 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1668 iwn_nic_unlock(sc); 1669 1670 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1671 if (sc->base_params->shadow_ram_support) { 1672 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1673 IWN_RESET_LINK_PWR_MGMT_DIS); 1674 } 1675 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1676 /* Clear ECC status. */ 1677 IWN_SETBITS(sc, IWN_OTP_GP, 1678 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1679 1680 /* 1681 * Find the block before last block (contains the EEPROM image) 1682 * for HW without OTP shadow RAM. 1683 */ 1684 if (! sc->base_params->shadow_ram_support) { 1685 /* Switch to absolute addressing mode. */ 1686 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1687 base = prev = 0; 1688 for (count = 0; count < sc->base_params->max_ll_items; 1689 count++) { 1690 error = iwn_read_prom_data(sc, base, &next, 2); 1691 if (error != 0) 1692 return error; 1693 if (next == 0) /* End of linked-list. */ 1694 break; 1695 prev = base; 1696 base = le16toh(next); 1697 } 1698 if (count == 0 || count == sc->base_params->max_ll_items) 1699 return EIO; 1700 /* Skip "next" word. */ 1701 sc->prom_base = prev + 1; 1702 } 1703 1704 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1705 1706 return 0; 1707 } 1708 1709 static int 1710 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1711 { 1712 uint8_t *out = data; 1713 uint32_t val, tmp; 1714 int ntries; 1715 1716 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1717 1718 addr += sc->prom_base; 1719 for (; count > 0; count -= 2, addr++) { 1720 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1721 for (ntries = 0; ntries < 10; ntries++) { 1722 val = IWN_READ(sc, IWN_EEPROM); 1723 if (val & IWN_EEPROM_READ_VALID) 1724 break; 1725 DELAY(5); 1726 } 1727 if (ntries == 10) { 1728 device_printf(sc->sc_dev, 1729 "timeout reading ROM at 0x%x\n", addr); 1730 return ETIMEDOUT; 1731 } 1732 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1733 /* OTPROM, check for ECC errors. */ 1734 tmp = IWN_READ(sc, IWN_OTP_GP); 1735 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1736 device_printf(sc->sc_dev, 1737 "OTPROM ECC error at 0x%x\n", addr); 1738 return EIO; 1739 } 1740 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1741 /* Correctable ECC error, clear bit. */ 1742 IWN_SETBITS(sc, IWN_OTP_GP, 1743 IWN_OTP_GP_ECC_CORR_STTS); 1744 } 1745 } 1746 *out++ = val >> 16; 1747 if (count > 1) 1748 *out++ = val >> 24; 1749 } 1750 1751 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1752 1753 return 0; 1754 } 1755 1756 static void 1757 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1758 { 1759 if (error != 0) 1760 return; 1761 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1762 *(bus_addr_t *)arg = segs[0].ds_addr; 1763 } 1764 1765 static int 1766 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1767 void **kvap, bus_size_t size, bus_size_t alignment) 1768 { 1769 int error; 1770 1771 dma->tag = NULL; 1772 dma->size = size; 1773 1774 error = bus_dma_tag_create(sc->sc_dmat, alignment, 1775 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1776 1, size, BUS_DMA_NOWAIT, &dma->tag); 1777 if (error != 0) 1778 goto fail; 1779 1780 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1781 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1782 if (error != 0) 1783 goto fail; 1784 1785 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1786 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1787 if (error != 0) 1788 goto fail; 1789 1790 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1791 1792 if (kvap != NULL) 1793 *kvap = dma->vaddr; 1794 1795 return 0; 1796 1797 fail: iwn_dma_contig_free(dma); 1798 return error; 1799 } 1800 1801 static void 1802 iwn_dma_contig_free(struct iwn_dma_info *dma) 1803 { 1804 if (dma->vaddr != NULL) { 1805 bus_dmamap_sync(dma->tag, dma->map, 1806 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1807 bus_dmamap_unload(dma->tag, dma->map); 1808 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1809 dma->vaddr = NULL; 1810 } 1811 if (dma->tag != NULL) { 1812 bus_dma_tag_destroy(dma->tag); 1813 dma->tag = NULL; 1814 } 1815 } 1816 1817 static int 1818 iwn_alloc_sched(struct iwn_softc *sc) 1819 { 1820 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1821 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1822 sc->schedsz, 1024); 1823 } 1824 1825 static void 1826 iwn_free_sched(struct iwn_softc *sc) 1827 { 1828 iwn_dma_contig_free(&sc->sched_dma); 1829 } 1830 1831 static int 1832 iwn_alloc_kw(struct iwn_softc *sc) 1833 { 1834 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1835 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1836 } 1837 1838 static void 1839 iwn_free_kw(struct iwn_softc *sc) 1840 { 1841 iwn_dma_contig_free(&sc->kw_dma); 1842 } 1843 1844 static int 1845 iwn_alloc_ict(struct iwn_softc *sc) 1846 { 1847 /* ICT table must be aligned on a 4KB boundary. */ 1848 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1849 IWN_ICT_SIZE, 4096); 1850 } 1851 1852 static void 1853 iwn_free_ict(struct iwn_softc *sc) 1854 { 1855 iwn_dma_contig_free(&sc->ict_dma); 1856 } 1857 1858 static int 1859 iwn_alloc_fwmem(struct iwn_softc *sc) 1860 { 1861 /* Must be aligned on a 16-byte boundary. */ 1862 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1863 } 1864 1865 static void 1866 iwn_free_fwmem(struct iwn_softc *sc) 1867 { 1868 iwn_dma_contig_free(&sc->fw_dma); 1869 } 1870 1871 static int 1872 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1873 { 1874 bus_size_t size; 1875 int i, error; 1876 1877 ring->cur = 0; 1878 1879 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1880 1881 /* Allocate RX descriptors (256-byte aligned). */ 1882 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1883 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1884 size, 256); 1885 if (error != 0) { 1886 device_printf(sc->sc_dev, 1887 "%s: could not allocate RX ring DMA memory, error %d\n", 1888 __func__, error); 1889 goto fail; 1890 } 1891 1892 /* Allocate RX status area (16-byte aligned). */ 1893 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1894 sizeof (struct iwn_rx_status), 16); 1895 if (error != 0) { 1896 device_printf(sc->sc_dev, 1897 "%s: could not allocate RX status DMA memory, error %d\n", 1898 __func__, error); 1899 goto fail; 1900 } 1901 1902 /* Create RX buffer DMA tag. */ 1903 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1904 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1905 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, &ring->data_dmat); 1906 if (error != 0) { 1907 device_printf(sc->sc_dev, 1908 "%s: could not create RX buf DMA tag, error %d\n", 1909 __func__, error); 1910 goto fail; 1911 } 1912 1913 /* 1914 * Allocate and map RX buffers. 1915 */ 1916 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1917 struct iwn_rx_data *data = &ring->data[i]; 1918 bus_addr_t paddr; 1919 1920 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1921 if (error != 0) { 1922 device_printf(sc->sc_dev, 1923 "%s: could not create RX buf DMA map, error %d\n", 1924 __func__, error); 1925 goto fail; 1926 } 1927 1928 data->m = m_getjcl(MB_DONTWAIT, MT_DATA, 1929 M_PKTHDR, IWN_RBUF_SIZE); 1930 if (data->m == NULL) { 1931 device_printf(sc->sc_dev, 1932 "%s: could not allocate RX mbuf\n", __func__); 1933 error = ENOBUFS; 1934 goto fail; 1935 } 1936 1937 error = bus_dmamap_load(ring->data_dmat, data->map, 1938 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1939 &paddr, BUS_DMA_NOWAIT); 1940 if (error != 0 && error != EFBIG) { 1941 device_printf(sc->sc_dev, 1942 "%s: can't not map mbuf, error %d\n", __func__, 1943 error); 1944 goto fail; 1945 } 1946 1947 /* Set physical address of RX buffer (256-byte aligned). */ 1948 ring->desc[i] = htole32(paddr >> 8); 1949 } 1950 1951 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1952 BUS_DMASYNC_PREWRITE); 1953 1954 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1955 1956 return 0; 1957 1958 fail: iwn_free_rx_ring(sc, ring); 1959 1960 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1961 1962 return error; 1963 } 1964 1965 static void 1966 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1967 { 1968 int ntries; 1969 1970 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 1971 1972 if (iwn_nic_lock(sc) == 0) { 1973 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1974 for (ntries = 0; ntries < 1000; ntries++) { 1975 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1976 IWN_FH_RX_STATUS_IDLE) 1977 break; 1978 DELAY(10); 1979 } 1980 iwn_nic_unlock(sc); 1981 } 1982 ring->cur = 0; 1983 sc->last_rx_valid = 0; 1984 } 1985 1986 static void 1987 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1988 { 1989 int i; 1990 1991 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1992 1993 iwn_dma_contig_free(&ring->desc_dma); 1994 iwn_dma_contig_free(&ring->stat_dma); 1995 1996 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1997 struct iwn_rx_data *data = &ring->data[i]; 1998 1999 if (data->m != NULL) { 2000 bus_dmamap_sync(ring->data_dmat, data->map, 2001 BUS_DMASYNC_POSTREAD); 2002 bus_dmamap_unload(ring->data_dmat, data->map); 2003 m_freem(data->m); 2004 data->m = NULL; 2005 } 2006 if (data->map != NULL) 2007 bus_dmamap_destroy(ring->data_dmat, data->map); 2008 } 2009 if (ring->data_dmat != NULL) { 2010 bus_dma_tag_destroy(ring->data_dmat); 2011 ring->data_dmat = NULL; 2012 } 2013 } 2014 2015 static int 2016 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 2017 { 2018 bus_addr_t paddr; 2019 bus_size_t size; 2020 int i, error; 2021 2022 ring->qid = qid; 2023 ring->queued = 0; 2024 ring->cur = 0; 2025 2026 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2027 2028 /* Allocate TX descriptors (256-byte aligned). */ 2029 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 2030 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 2031 size, 256); 2032 if (error != 0) { 2033 device_printf(sc->sc_dev, 2034 "%s: could not allocate TX ring DMA memory, error %d\n", 2035 __func__, error); 2036 goto fail; 2037 } 2038 2039 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 2040 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 2041 size, 4); 2042 if (error != 0) { 2043 device_printf(sc->sc_dev, 2044 "%s: could not allocate TX cmd DMA memory, error %d\n", 2045 __func__, error); 2046 goto fail; 2047 } 2048 2049 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 2050 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2051 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat); 2052 if (error != 0) { 2053 device_printf(sc->sc_dev, 2054 "%s: could not create TX buf DMA tag, error %d\n", 2055 __func__, error); 2056 goto fail; 2057 } 2058 2059 paddr = ring->cmd_dma.paddr; 2060 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2061 struct iwn_tx_data *data = &ring->data[i]; 2062 2063 data->cmd_paddr = paddr; 2064 data->scratch_paddr = paddr + 12; 2065 paddr += sizeof (struct iwn_tx_cmd); 2066 2067 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 2068 if (error != 0) { 2069 device_printf(sc->sc_dev, 2070 "%s: could not create TX buf DMA map, error %d\n", 2071 __func__, error); 2072 goto fail; 2073 } 2074 } 2075 2076 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2077 2078 return 0; 2079 2080 fail: iwn_free_tx_ring(sc, ring); 2081 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2082 return error; 2083 } 2084 2085 static void 2086 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2087 { 2088 int i; 2089 2090 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 2091 2092 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2093 struct iwn_tx_data *data = &ring->data[i]; 2094 2095 if (data->m != NULL) { 2096 bus_dmamap_sync(ring->data_dmat, data->map, 2097 BUS_DMASYNC_POSTWRITE); 2098 bus_dmamap_unload(ring->data_dmat, data->map); 2099 m_freem(data->m); 2100 data->m = NULL; 2101 } 2102 } 2103 /* Clear TX descriptors. */ 2104 memset(ring->desc, 0, ring->desc_dma.size); 2105 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2106 BUS_DMASYNC_PREWRITE); 2107 sc->qfullmsk &= ~(1 << ring->qid); 2108 ring->queued = 0; 2109 ring->cur = 0; 2110 } 2111 2112 static void 2113 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2114 { 2115 int i; 2116 2117 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2118 2119 iwn_dma_contig_free(&ring->desc_dma); 2120 iwn_dma_contig_free(&ring->cmd_dma); 2121 2122 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2123 struct iwn_tx_data *data = &ring->data[i]; 2124 2125 if (data->m != NULL) { 2126 bus_dmamap_sync(ring->data_dmat, data->map, 2127 BUS_DMASYNC_POSTWRITE); 2128 bus_dmamap_unload(ring->data_dmat, data->map); 2129 m_freem(data->m); 2130 } 2131 if (data->map != NULL) 2132 bus_dmamap_destroy(ring->data_dmat, data->map); 2133 } 2134 if (ring->data_dmat != NULL) { 2135 bus_dma_tag_destroy(ring->data_dmat); 2136 ring->data_dmat = NULL; 2137 } 2138 } 2139 2140 static void 2141 iwn5000_ict_reset(struct iwn_softc *sc) 2142 { 2143 /* Disable interrupts. */ 2144 IWN_WRITE(sc, IWN_INT_MASK, 0); 2145 2146 /* Reset ICT table. */ 2147 memset(sc->ict, 0, IWN_ICT_SIZE); 2148 sc->ict_cur = 0; 2149 2150 /* Set physical address of ICT table (4KB aligned). */ 2151 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 2152 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 2153 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 2154 2155 /* Enable periodic RX interrupt. */ 2156 sc->int_mask |= IWN_INT_RX_PERIODIC; 2157 /* Switch to ICT interrupt mode in driver. */ 2158 sc->sc_flags |= IWN_FLAG_USE_ICT; 2159 2160 /* Re-enable interrupts. */ 2161 IWN_WRITE(sc, IWN_INT, 0xffffffff); 2162 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2163 } 2164 2165 static int 2166 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2167 { 2168 struct iwn_ops *ops = &sc->ops; 2169 uint16_t val; 2170 int error; 2171 2172 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2173 2174 /* Check whether adapter has an EEPROM or an OTPROM. */ 2175 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 2176 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 2177 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 2178 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 2179 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 2180 2181 /* Adapter has to be powered on for EEPROM access to work. */ 2182 if ((error = iwn_apm_init(sc)) != 0) { 2183 device_printf(sc->sc_dev, 2184 "%s: could not power ON adapter, error %d\n", __func__, 2185 error); 2186 return error; 2187 } 2188 2189 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 2190 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 2191 return EIO; 2192 } 2193 if ((error = iwn_eeprom_lock(sc)) != 0) { 2194 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 2195 __func__, error); 2196 return error; 2197 } 2198 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 2199 if ((error = iwn_init_otprom(sc)) != 0) { 2200 device_printf(sc->sc_dev, 2201 "%s: could not initialize OTPROM, error %d\n", 2202 __func__, error); 2203 return error; 2204 } 2205 } 2206 2207 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 2208 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 2209 /* Check if HT support is bonded out. */ 2210 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 2211 sc->sc_flags |= IWN_FLAG_HAS_11N; 2212 2213 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 2214 sc->rfcfg = le16toh(val); 2215 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 2216 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 2217 if (sc->txchainmask == 0) 2218 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 2219 if (sc->rxchainmask == 0) 2220 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 2221 2222 /* Read MAC address. */ 2223 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 2224 2225 /* Read adapter-specific information from EEPROM. */ 2226 ops->read_eeprom(sc); 2227 2228 iwn_apm_stop(sc); /* Power OFF adapter. */ 2229 2230 iwn_eeprom_unlock(sc); 2231 2232 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2233 2234 return 0; 2235 } 2236 2237 static void 2238 iwn4965_read_eeprom(struct iwn_softc *sc) 2239 { 2240 uint32_t addr; 2241 uint16_t val; 2242 int i; 2243 2244 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2245 2246 /* Read regulatory domain (4 ASCII characters). */ 2247 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 2248 2249 /* Read the list of authorized channels (20MHz ones only). */ 2250 for (i = 0; i < IWN_NBANDS - 1; i++) { 2251 addr = iwn4965_regulatory_bands[i]; 2252 iwn_read_eeprom_channels(sc, i, addr); 2253 } 2254 2255 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 2256 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 2257 sc->maxpwr2GHz = val & 0xff; 2258 sc->maxpwr5GHz = val >> 8; 2259 /* Check that EEPROM values are within valid range. */ 2260 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 2261 sc->maxpwr5GHz = 38; 2262 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 2263 sc->maxpwr2GHz = 38; 2264 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 2265 sc->maxpwr2GHz, sc->maxpwr5GHz); 2266 2267 /* Read samples for each TX power group. */ 2268 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 2269 sizeof sc->bands); 2270 2271 /* Read voltage at which samples were taken. */ 2272 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 2273 sc->eeprom_voltage = (int16_t)le16toh(val); 2274 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 2275 sc->eeprom_voltage); 2276 2277 #ifdef IWN_DEBUG 2278 /* Print samples. */ 2279 if (sc->sc_debug & IWN_DEBUG_ANY) { 2280 for (i = 0; i < IWN_NBANDS - 1; i++) 2281 iwn4965_print_power_group(sc, i); 2282 } 2283 #endif 2284 2285 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2286 } 2287 2288 #ifdef IWN_DEBUG 2289 static void 2290 iwn4965_print_power_group(struct iwn_softc *sc, int i) 2291 { 2292 struct iwn4965_eeprom_band *band = &sc->bands[i]; 2293 struct iwn4965_eeprom_chan_samples *chans = band->chans; 2294 int j, c; 2295 2296 kprintf("===band %d===\n", i); 2297 kprintf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 2298 kprintf("chan1 num=%d\n", chans[0].num); 2299 for (c = 0; c < 2; c++) { 2300 for (j = 0; j < IWN_NSAMPLES; j++) { 2301 kprintf("chain %d, sample %d: temp=%d gain=%d " 2302 "power=%d pa_det=%d\n", c, j, 2303 chans[0].samples[c][j].temp, 2304 chans[0].samples[c][j].gain, 2305 chans[0].samples[c][j].power, 2306 chans[0].samples[c][j].pa_det); 2307 } 2308 } 2309 kprintf("chan2 num=%d\n", chans[1].num); 2310 for (c = 0; c < 2; c++) { 2311 for (j = 0; j < IWN_NSAMPLES; j++) { 2312 kprintf("chain %d, sample %d: temp=%d gain=%d " 2313 "power=%d pa_det=%d\n", c, j, 2314 chans[1].samples[c][j].temp, 2315 chans[1].samples[c][j].gain, 2316 chans[1].samples[c][j].power, 2317 chans[1].samples[c][j].pa_det); 2318 } 2319 } 2320 } 2321 #endif 2322 2323 static void 2324 iwn5000_read_eeprom(struct iwn_softc *sc) 2325 { 2326 struct iwn5000_eeprom_calib_hdr hdr; 2327 int32_t volt; 2328 uint32_t base, addr; 2329 uint16_t val; 2330 int i; 2331 2332 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2333 2334 /* Read regulatory domain (4 ASCII characters). */ 2335 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2336 base = le16toh(val); 2337 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 2338 sc->eeprom_domain, 4); 2339 2340 /* Read the list of authorized channels (20MHz ones only). */ 2341 for (i = 0; i < IWN_NBANDS - 1; i++) { 2342 addr = base + sc->base_params->regulatory_bands[i]; 2343 iwn_read_eeprom_channels(sc, i, addr); 2344 } 2345 2346 /* Read enhanced TX power information for 6000 Series. */ 2347 if (sc->base_params->enhanced_TX_power) 2348 iwn_read_eeprom_enhinfo(sc); 2349 2350 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 2351 base = le16toh(val); 2352 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 2353 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2354 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 2355 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 2356 sc->calib_ver = hdr.version; 2357 2358 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 2359 sc->eeprom_voltage = le16toh(hdr.volt); 2360 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2361 sc->eeprom_temp_high=le16toh(val); 2362 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2363 sc->eeprom_temp = le16toh(val); 2364 } 2365 2366 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 2367 /* Compute temperature offset. */ 2368 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2369 sc->eeprom_temp = le16toh(val); 2370 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2371 volt = le16toh(val); 2372 sc->temp_off = sc->eeprom_temp - (volt / -5); 2373 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 2374 sc->eeprom_temp, volt, sc->temp_off); 2375 } else { 2376 /* Read crystal calibration. */ 2377 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 2378 &sc->eeprom_crystal, sizeof (uint32_t)); 2379 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 2380 le32toh(sc->eeprom_crystal)); 2381 } 2382 2383 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2384 2385 } 2386 2387 /* 2388 * Translate EEPROM flags to net80211. 2389 */ 2390 static uint32_t 2391 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 2392 { 2393 uint32_t nflags; 2394 2395 nflags = 0; 2396 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 2397 nflags |= IEEE80211_CHAN_PASSIVE; 2398 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 2399 nflags |= IEEE80211_CHAN_NOADHOC; 2400 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 2401 nflags |= IEEE80211_CHAN_DFS; 2402 /* XXX apparently IBSS may still be marked */ 2403 nflags |= IEEE80211_CHAN_NOADHOC; 2404 } 2405 2406 return nflags; 2407 } 2408 2409 static void 2410 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 2411 { 2412 struct ifnet *ifp = sc->sc_ifp; 2413 struct ieee80211com *ic = ifp->if_l2com; 2414 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2415 const struct iwn_chan_band *band = &iwn_bands[n]; 2416 struct ieee80211_channel *c; 2417 uint8_t chan; 2418 int i, nflags; 2419 2420 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2421 2422 for (i = 0; i < band->nchan; i++) { 2423 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2424 DPRINTF(sc, IWN_DEBUG_RESET, 2425 "skip chan %d flags 0x%x maxpwr %d\n", 2426 band->chan[i], channels[i].flags, 2427 channels[i].maxpwr); 2428 continue; 2429 } 2430 chan = band->chan[i]; 2431 nflags = iwn_eeprom_channel_flags(&channels[i]); 2432 2433 c = &ic->ic_channels[ic->ic_nchans++]; 2434 c->ic_ieee = chan; 2435 c->ic_maxregpower = channels[i].maxpwr; 2436 c->ic_maxpower = 2*c->ic_maxregpower; 2437 2438 if (n == 0) { /* 2GHz band */ 2439 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G); 2440 /* G =>'s B is supported */ 2441 c->ic_flags = IEEE80211_CHAN_B | nflags; 2442 c = &ic->ic_channels[ic->ic_nchans++]; 2443 c[0] = c[-1]; 2444 c->ic_flags = IEEE80211_CHAN_G | nflags; 2445 } else { /* 5GHz band */ 2446 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A); 2447 c->ic_flags = IEEE80211_CHAN_A | nflags; 2448 } 2449 2450 /* Save maximum allowed TX power for this channel. */ 2451 sc->maxpwr[chan] = channels[i].maxpwr; 2452 2453 DPRINTF(sc, IWN_DEBUG_RESET, 2454 "add chan %d flags 0x%x maxpwr %d\n", chan, 2455 channels[i].flags, channels[i].maxpwr); 2456 2457 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 2458 /* add HT20, HT40 added separately */ 2459 c = &ic->ic_channels[ic->ic_nchans++]; 2460 c[0] = c[-1]; 2461 c->ic_flags |= IEEE80211_CHAN_HT20; 2462 } 2463 } 2464 2465 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2466 2467 } 2468 2469 static void 2470 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 2471 { 2472 struct ifnet *ifp = sc->sc_ifp; 2473 struct ieee80211com *ic = ifp->if_l2com; 2474 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2475 const struct iwn_chan_band *band = &iwn_bands[n]; 2476 struct ieee80211_channel *c, *cent, *extc; 2477 uint8_t chan; 2478 int i, nflags; 2479 2480 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2481 2482 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2483 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 2484 return; 2485 } 2486 2487 for (i = 0; i < band->nchan; i++) { 2488 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2489 DPRINTF(sc, IWN_DEBUG_RESET, 2490 "skip chan %d flags 0x%x maxpwr %d\n", 2491 band->chan[i], channels[i].flags, 2492 channels[i].maxpwr); 2493 continue; 2494 } 2495 chan = band->chan[i]; 2496 nflags = iwn_eeprom_channel_flags(&channels[i]); 2497 2498 /* 2499 * Each entry defines an HT40 channel pair; find the 2500 * center channel, then the extension channel above. 2501 */ 2502 cent = ieee80211_find_channel_byieee(ic, chan, 2503 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 2504 if (cent == NULL) { /* XXX shouldn't happen */ 2505 device_printf(sc->sc_dev, 2506 "%s: no entry for channel %d\n", __func__, chan); 2507 continue; 2508 } 2509 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 2510 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 2511 if (extc == NULL) { 2512 DPRINTF(sc, IWN_DEBUG_RESET, 2513 "%s: skip chan %d, extension channel not found\n", 2514 __func__, chan); 2515 continue; 2516 } 2517 2518 DPRINTF(sc, IWN_DEBUG_RESET, 2519 "add ht40 chan %d flags 0x%x maxpwr %d\n", 2520 chan, channels[i].flags, channels[i].maxpwr); 2521 2522 c = &ic->ic_channels[ic->ic_nchans++]; 2523 c[0] = cent[0]; 2524 c->ic_extieee = extc->ic_ieee; 2525 c->ic_flags &= ~IEEE80211_CHAN_HT; 2526 c->ic_flags |= IEEE80211_CHAN_HT40U | nflags; 2527 c = &ic->ic_channels[ic->ic_nchans++]; 2528 c[0] = extc[0]; 2529 c->ic_extieee = cent->ic_ieee; 2530 c->ic_flags &= ~IEEE80211_CHAN_HT; 2531 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags; 2532 } 2533 2534 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2535 2536 } 2537 2538 static void 2539 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 2540 { 2541 struct ifnet *ifp = sc->sc_ifp; 2542 struct ieee80211com *ic = ifp->if_l2com; 2543 2544 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 2545 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 2546 2547 if (n < 5) 2548 iwn_read_eeprom_band(sc, n); 2549 else 2550 iwn_read_eeprom_ht40(sc, n); 2551 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 2552 } 2553 2554 static struct iwn_eeprom_chan * 2555 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 2556 { 2557 int band, chan, i, j; 2558 2559 if (IEEE80211_IS_CHAN_HT40(c)) { 2560 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 2561 if (IEEE80211_IS_CHAN_HT40D(c)) 2562 chan = c->ic_extieee; 2563 else 2564 chan = c->ic_ieee; 2565 for (i = 0; i < iwn_bands[band].nchan; i++) { 2566 if (iwn_bands[band].chan[i] == chan) 2567 return &sc->eeprom_channels[band][i]; 2568 } 2569 } else { 2570 for (j = 0; j < 5; j++) { 2571 for (i = 0; i < iwn_bands[j].nchan; i++) { 2572 if (iwn_bands[j].chan[i] == c->ic_ieee) 2573 return &sc->eeprom_channels[j][i]; 2574 } 2575 } 2576 } 2577 return NULL; 2578 } 2579 2580 /* 2581 * Enforce flags read from EEPROM. 2582 */ 2583 static int 2584 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2585 int nchan, struct ieee80211_channel chans[]) 2586 { 2587 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2588 int i; 2589 2590 for (i = 0; i < nchan; i++) { 2591 struct ieee80211_channel *c = &chans[i]; 2592 struct iwn_eeprom_chan *channel; 2593 2594 channel = iwn_find_eeprom_channel(sc, c); 2595 if (channel == NULL) { 2596 if_printf(ic->ic_ifp, 2597 "%s: invalid channel %u freq %u/0x%x\n", 2598 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2599 return EINVAL; 2600 } 2601 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2602 } 2603 2604 return 0; 2605 } 2606 2607 static void 2608 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2609 { 2610 struct iwn_eeprom_enhinfo enhinfo[35]; 2611 struct ifnet *ifp = sc->sc_ifp; 2612 struct ieee80211com *ic = ifp->if_l2com; 2613 struct ieee80211_channel *c; 2614 uint16_t val, base; 2615 int8_t maxpwr; 2616 uint8_t flags; 2617 int i, j; 2618 2619 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2620 2621 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2622 base = le16toh(val); 2623 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2624 enhinfo, sizeof enhinfo); 2625 2626 for (i = 0; i < nitems(enhinfo); i++) { 2627 flags = enhinfo[i].flags; 2628 if (!(flags & IWN_ENHINFO_VALID)) 2629 continue; /* Skip invalid entries. */ 2630 2631 maxpwr = 0; 2632 if (sc->txchainmask & IWN_ANT_A) 2633 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2634 if (sc->txchainmask & IWN_ANT_B) 2635 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2636 if (sc->txchainmask & IWN_ANT_C) 2637 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2638 if (sc->ntxchains == 2) 2639 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2640 else if (sc->ntxchains == 3) 2641 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2642 2643 for (j = 0; j < ic->ic_nchans; j++) { 2644 c = &ic->ic_channels[j]; 2645 if ((flags & IWN_ENHINFO_5GHZ)) { 2646 if (!IEEE80211_IS_CHAN_A(c)) 2647 continue; 2648 } else if ((flags & IWN_ENHINFO_OFDM)) { 2649 if (!IEEE80211_IS_CHAN_G(c)) 2650 continue; 2651 } else if (!IEEE80211_IS_CHAN_B(c)) 2652 continue; 2653 if ((flags & IWN_ENHINFO_HT40)) { 2654 if (!IEEE80211_IS_CHAN_HT40(c)) 2655 continue; 2656 } else { 2657 if (IEEE80211_IS_CHAN_HT40(c)) 2658 continue; 2659 } 2660 if (enhinfo[i].chan != 0 && 2661 enhinfo[i].chan != c->ic_ieee) 2662 continue; 2663 2664 DPRINTF(sc, IWN_DEBUG_RESET, 2665 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2666 c->ic_flags, maxpwr / 2); 2667 c->ic_maxregpower = maxpwr / 2; 2668 c->ic_maxpower = maxpwr; 2669 } 2670 } 2671 2672 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2673 2674 } 2675 2676 static struct ieee80211_node * 2677 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2678 { 2679 return kmalloc(sizeof(struct iwn_node), M_80211_NODE, 2680 M_INTWAIT | M_ZERO); 2681 } 2682 2683 static __inline int 2684 rate2plcp(int rate) 2685 { 2686 switch (rate & 0xff) { 2687 case 12: return 0xd; 2688 case 18: return 0xf; 2689 case 24: return 0x5; 2690 case 36: return 0x7; 2691 case 48: return 0x9; 2692 case 72: return 0xb; 2693 case 96: return 0x1; 2694 case 108: return 0x3; 2695 case 2: return 10; 2696 case 4: return 20; 2697 case 11: return 55; 2698 case 22: return 110; 2699 } 2700 return 0; 2701 } 2702 2703 /* 2704 * Calculate the required PLCP value from the given rate, 2705 * to the given node. 2706 * 2707 * This will take the node configuration (eg 11n, rate table 2708 * setup, etc) into consideration. 2709 */ 2710 static uint32_t 2711 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2712 uint8_t rate) 2713 { 2714 #define RV(v) ((v) & IEEE80211_RATE_VAL) 2715 struct ieee80211com *ic = ni->ni_ic; 2716 uint8_t txant1, txant2; 2717 uint32_t plcp = 0; 2718 int ridx; 2719 2720 /* Use the first valid TX antenna. */ 2721 txant1 = IWN_LSB(sc->txchainmask); 2722 txant2 = IWN_LSB(sc->txchainmask & ~txant1); 2723 2724 /* 2725 * If it's an MCS rate, let's set the plcp correctly 2726 * and set the relevant flags based on the node config. 2727 */ 2728 if (rate & IEEE80211_RATE_MCS) { 2729 /* 2730 * Set the initial PLCP value to be between 0->31 for 2731 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2732 * flag. 2733 */ 2734 plcp = RV(rate) | IWN_RFLAG_MCS; 2735 2736 /* 2737 * XXX the following should only occur if both 2738 * the local configuration _and_ the remote node 2739 * advertise these capabilities. Thus this code 2740 * may need fixing! 2741 */ 2742 2743 /* 2744 * Set the channel width and guard interval. 2745 */ 2746 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2747 plcp |= IWN_RFLAG_HT40; 2748 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2749 plcp |= IWN_RFLAG_SGI; 2750 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) { 2751 plcp |= IWN_RFLAG_SGI; 2752 } 2753 2754 /* 2755 * If it's a two stream rate, enable TX on both 2756 * antennas. 2757 * 2758 * XXX three stream rates? 2759 */ 2760 if (rate > 0x87) 2761 plcp |= IWN_RFLAG_ANT(txant1 | txant2); 2762 else 2763 plcp |= IWN_RFLAG_ANT(txant1); 2764 } else { 2765 /* 2766 * Set the initial PLCP - fine for both 2767 * OFDM and CCK rates. 2768 */ 2769 plcp = rate2plcp(rate); 2770 2771 /* Set CCK flag if it's CCK */ 2772 2773 /* XXX It would be nice to have a method 2774 * to map the ridx -> phy table entry 2775 * so we could just query that, rather than 2776 * this hack to check against IWN_RIDX_OFDM6. 2777 */ 2778 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2779 rate & IEEE80211_RATE_VAL); 2780 if (ridx < IWN_RIDX_OFDM6 && 2781 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2782 plcp |= IWN_RFLAG_CCK; 2783 2784 /* Set antenna configuration */ 2785 plcp |= IWN_RFLAG_ANT(txant1); 2786 } 2787 2788 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2789 __func__, 2790 rate, 2791 plcp); 2792 2793 return (htole32(plcp)); 2794 #undef RV 2795 } 2796 2797 static void 2798 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2799 { 2800 /* Doesn't do anything at the moment */ 2801 } 2802 2803 static int 2804 iwn_media_change(struct ifnet *ifp) 2805 { 2806 int error; 2807 2808 error = ieee80211_media_change(ifp); 2809 /* NB: only the fixed rate can change and that doesn't need a reset */ 2810 return (error == ENETRESET ? 0 : error); 2811 } 2812 2813 static int 2814 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2815 { 2816 struct iwn_vap *ivp = IWN_VAP(vap); 2817 struct ieee80211com *ic = vap->iv_ic; 2818 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2819 int error = 0; 2820 2821 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2822 2823 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2824 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2825 2826 callout_stop(&sc->calib_to); 2827 2828 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2829 2830 switch (nstate) { 2831 case IEEE80211_S_ASSOC: 2832 if (vap->iv_state != IEEE80211_S_RUN) 2833 break; 2834 /* FALLTHROUGH */ 2835 case IEEE80211_S_AUTH: 2836 if (vap->iv_state == IEEE80211_S_AUTH) 2837 break; 2838 2839 /* 2840 * !AUTH -> AUTH transition requires state reset to handle 2841 * reassociations correctly. 2842 */ 2843 sc->rxon->associd = 0; 2844 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2845 sc->calib.state = IWN_CALIB_STATE_INIT; 2846 2847 if ((error = iwn_auth(sc, vap)) != 0) { 2848 device_printf(sc->sc_dev, 2849 "%s: could not move to auth state\n", __func__); 2850 } 2851 break; 2852 2853 case IEEE80211_S_RUN: 2854 /* 2855 * RUN -> RUN transition; Just restart the timers. 2856 */ 2857 if (vap->iv_state == IEEE80211_S_RUN) { 2858 sc->calib_cnt = 0; 2859 break; 2860 } 2861 2862 /* 2863 * !RUN -> RUN requires setting the association id 2864 * which is done with a firmware cmd. We also defer 2865 * starting the timers until that work is done. 2866 */ 2867 if ((error = iwn_run(sc, vap)) != 0) { 2868 device_printf(sc->sc_dev, 2869 "%s: could not move to run state\n", __func__); 2870 } 2871 break; 2872 2873 case IEEE80211_S_INIT: 2874 sc->calib.state = IWN_CALIB_STATE_INIT; 2875 break; 2876 2877 default: 2878 break; 2879 } 2880 if (error != 0){ 2881 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2882 return error; 2883 } 2884 2885 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2886 2887 return ivp->iv_newstate(vap, nstate, arg); 2888 } 2889 2890 static void 2891 iwn_calib_timeout(void *arg) 2892 { 2893 struct iwn_softc *sc = arg; 2894 2895 wlan_serialize_enter(); 2896 2897 /* Force automatic TX power calibration every 60 secs. */ 2898 if (++sc->calib_cnt >= 120) { 2899 uint32_t flags = 0; 2900 2901 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2902 "sending request for statistics"); 2903 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2904 sizeof flags, 1); 2905 sc->calib_cnt = 0; 2906 } 2907 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2908 sc); 2909 wlan_serialize_exit(); 2910 } 2911 2912 /* 2913 * Process an RX_PHY firmware notification. This is usually immediately 2914 * followed by an MPDU_RX_DONE notification. 2915 */ 2916 static void 2917 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2918 struct iwn_rx_data *data) 2919 { 2920 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2921 2922 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2923 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2924 2925 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2926 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2927 sc->last_rx_valid = 1; 2928 } 2929 2930 /* 2931 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2932 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2933 */ 2934 static void 2935 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2936 struct iwn_rx_data *data) 2937 { 2938 struct iwn_ops *ops = &sc->ops; 2939 struct ifnet *ifp = sc->sc_ifp; 2940 struct ieee80211com *ic = ifp->if_l2com; 2941 struct iwn_rx_ring *ring = &sc->rxq; 2942 struct ieee80211_frame *wh; 2943 struct ieee80211_node *ni; 2944 struct mbuf *m, *m1; 2945 struct iwn_rx_stat *stat; 2946 caddr_t head; 2947 bus_addr_t paddr; 2948 uint32_t flags; 2949 int error, len, rssi, nf; 2950 2951 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2952 2953 if (desc->type == IWN_MPDU_RX_DONE) { 2954 /* Check for prior RX_PHY notification. */ 2955 if (!sc->last_rx_valid) { 2956 DPRINTF(sc, IWN_DEBUG_ANY, 2957 "%s: missing RX_PHY\n", __func__); 2958 return; 2959 } 2960 stat = &sc->last_rx_stat; 2961 } else 2962 stat = (struct iwn_rx_stat *)(desc + 1); 2963 2964 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2965 2966 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2967 device_printf(sc->sc_dev, 2968 "%s: invalid RX statistic header, len %d\n", __func__, 2969 stat->cfg_phy_len); 2970 return; 2971 } 2972 if (desc->type == IWN_MPDU_RX_DONE) { 2973 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2974 head = (caddr_t)(mpdu + 1); 2975 len = le16toh(mpdu->len); 2976 } else { 2977 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2978 len = le16toh(stat->len); 2979 } 2980 2981 flags = le32toh(*(uint32_t *)(head + len)); 2982 2983 /* Discard frames with a bad FCS early. */ 2984 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2985 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 2986 __func__, flags); 2987 IFNET_STAT_INC(ifp, ierrors, 1); 2988 return; 2989 } 2990 /* Discard frames that are too short. */ 2991 if (len < sizeof (*wh)) { 2992 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2993 __func__, len); 2994 IFNET_STAT_INC(ifp, ierrors, 1); 2995 return; 2996 } 2997 2998 m1 = m_getjcl(MB_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 2999 if (m1 == NULL) { 3000 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 3001 __func__); 3002 IFNET_STAT_INC(ifp, ierrors, 1); 3003 return; 3004 } 3005 bus_dmamap_unload(ring->data_dmat, data->map); 3006 3007 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 3008 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3009 if (error != 0 && error != EFBIG) { 3010 device_printf(sc->sc_dev, 3011 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 3012 m_freem(m1); 3013 3014 /* Try to reload the old mbuf. */ 3015 error = bus_dmamap_load(ring->data_dmat, data->map, 3016 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 3017 &paddr, BUS_DMA_NOWAIT); 3018 if (error != 0 && error != EFBIG) { 3019 panic("%s: could not load old RX mbuf", __func__); 3020 } 3021 /* Physical address may have changed. */ 3022 ring->desc[ring->cur] = htole32(paddr >> 8); 3023 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map, 3024 BUS_DMASYNC_PREWRITE); 3025 IFNET_STAT_INC(ifp, ierrors, 1); 3026 return; 3027 } 3028 3029 m = data->m; 3030 data->m = m1; 3031 /* Update RX descriptor. */ 3032 ring->desc[ring->cur] = htole32(paddr >> 8); 3033 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3034 BUS_DMASYNC_PREWRITE); 3035 3036 /* Finalize mbuf. */ 3037 m->m_pkthdr.rcvif = ifp; 3038 m->m_data = head; 3039 m->m_pkthdr.len = m->m_len = len; 3040 3041 /* Grab a reference to the source node. */ 3042 wh = mtod(m, struct ieee80211_frame *); 3043 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3044 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 3045 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 3046 3047 rssi = ops->get_rssi(sc, stat); 3048 3049 if (ieee80211_radiotap_active(ic)) { 3050 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 3051 3052 tap->wr_flags = 0; 3053 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 3054 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3055 tap->wr_dbm_antsignal = (int8_t)rssi; 3056 tap->wr_dbm_antnoise = (int8_t)nf; 3057 tap->wr_tsft = stat->tstamp; 3058 switch (stat->rate) { 3059 /* CCK rates. */ 3060 case 10: tap->wr_rate = 2; break; 3061 case 20: tap->wr_rate = 4; break; 3062 case 55: tap->wr_rate = 11; break; 3063 case 110: tap->wr_rate = 22; break; 3064 /* OFDM rates. */ 3065 case 0xd: tap->wr_rate = 12; break; 3066 case 0xf: tap->wr_rate = 18; break; 3067 case 0x5: tap->wr_rate = 24; break; 3068 case 0x7: tap->wr_rate = 36; break; 3069 case 0x9: tap->wr_rate = 48; break; 3070 case 0xb: tap->wr_rate = 72; break; 3071 case 0x1: tap->wr_rate = 96; break; 3072 case 0x3: tap->wr_rate = 108; break; 3073 /* Unknown rate: should not happen. */ 3074 default: tap->wr_rate = 0; 3075 } 3076 } 3077 3078 /* Send the frame to the 802.11 layer. */ 3079 if (ni != NULL) { 3080 if (ni->ni_flags & IEEE80211_NODE_HT) 3081 m->m_flags |= M_AMPDU; 3082 (void)ieee80211_input(ni, m, rssi - nf, nf); 3083 /* Node is no longer needed. */ 3084 ieee80211_free_node(ni); 3085 } else { 3086 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 3087 } 3088 3089 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3090 3091 } 3092 3093 /* Process an incoming Compressed BlockAck. */ 3094 static void 3095 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3096 struct iwn_rx_data *data) 3097 { 3098 struct iwn_ops *ops = &sc->ops; 3099 struct ifnet *ifp = sc->sc_ifp; 3100 struct iwn_node *wn; 3101 struct ieee80211_node *ni; 3102 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 3103 struct iwn_tx_ring *txq; 3104 struct iwn_tx_data *txdata; 3105 struct ieee80211_tx_ampdu *tap; 3106 struct mbuf *m; 3107 uint64_t bitmap; 3108 uint16_t ssn; 3109 uint8_t tid; 3110 int ackfailcnt = 0, i, lastidx, qid, *res, shift; 3111 3112 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3113 3114 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3115 3116 qid = le16toh(ba->qid); 3117 txq = &sc->txq[ba->qid]; 3118 tap = sc->qid2tap[ba->qid]; 3119 tid = tap->txa_ac; 3120 wn = (void *)tap->txa_ni; 3121 3122 res = NULL; 3123 ssn = 0; 3124 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3125 res = tap->txa_private; 3126 ssn = tap->txa_start & 0xfff; 3127 } 3128 3129 for (lastidx = le16toh(ba->ssn) & 0xff; txq->read != lastidx;) { 3130 txdata = &txq->data[txq->read]; 3131 3132 /* Unmap and free mbuf. */ 3133 bus_dmamap_sync(txq->data_dmat, txdata->map, 3134 BUS_DMASYNC_POSTWRITE); 3135 bus_dmamap_unload(txq->data_dmat, txdata->map); 3136 m = txdata->m, txdata->m = NULL; 3137 ni = txdata->ni, txdata->ni = NULL; 3138 3139 KASSERT(ni != NULL, ("no node")); 3140 KASSERT(m != NULL, ("no mbuf")); 3141 3142 ieee80211_tx_complete(ni, m, 1); 3143 3144 txq->queued--; 3145 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 3146 } 3147 3148 if (txq->queued == 0 && res != NULL) { 3149 iwn_nic_lock(sc); 3150 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3151 iwn_nic_unlock(sc); 3152 sc->qid2tap[qid] = NULL; 3153 kfree(res, M_DEVBUF); 3154 return; 3155 } 3156 3157 if (wn->agg[tid].bitmap == 0) 3158 return; 3159 3160 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 3161 if (shift < 0) 3162 shift += 0x100; 3163 3164 if (wn->agg[tid].nframes > (64 - shift)) 3165 return; 3166 3167 ni = tap->txa_ni; 3168 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap; 3169 for (i = 0; bitmap; i++) { 3170 if ((bitmap & 1) == 0) { 3171 IFNET_STAT_INC(ifp, oerrors, 1); 3172 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3173 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 3174 } else { 3175 IFNET_STAT_INC(ifp, opackets, 1); 3176 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3177 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 3178 } 3179 bitmap >>= 1; 3180 } 3181 3182 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3183 3184 } 3185 3186 /* 3187 * Process a CALIBRATION_RESULT notification sent by the initialization 3188 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 3189 */ 3190 static void 3191 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3192 struct iwn_rx_data *data) 3193 { 3194 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 3195 int len, idx = -1; 3196 3197 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3198 3199 /* Runtime firmware should not send such a notification. */ 3200 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 3201 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received after clib done\n", 3202 __func__); 3203 return; 3204 } 3205 len = (le32toh(desc->len) & 0x3fff) - 4; 3206 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3207 3208 switch (calib->code) { 3209 case IWN5000_PHY_CALIB_DC: 3210 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC) 3211 idx = 0; 3212 break; 3213 case IWN5000_PHY_CALIB_LO: 3214 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO) 3215 idx = 1; 3216 break; 3217 case IWN5000_PHY_CALIB_TX_IQ: 3218 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ) 3219 idx = 2; 3220 break; 3221 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 3222 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC) 3223 idx = 3; 3224 break; 3225 case IWN5000_PHY_CALIB_BASE_BAND: 3226 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND) 3227 idx = 4; 3228 break; 3229 } 3230 if (idx == -1) /* Ignore other results. */ 3231 return; 3232 3233 /* Save calibration result. */ 3234 if (sc->calibcmd[idx].buf != NULL) 3235 kfree(sc->calibcmd[idx].buf, M_DEVBUF); 3236 sc->calibcmd[idx].buf = kmalloc(len, M_DEVBUF, M_INTWAIT); 3237 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3238 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len); 3239 sc->calibcmd[idx].len = len; 3240 memcpy(sc->calibcmd[idx].buf, calib, len); 3241 } 3242 3243 static void 3244 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib, 3245 struct iwn_stats *stats, int len) 3246 { 3247 struct iwn_stats_bt *stats_bt; 3248 struct iwn_stats *lstats; 3249 3250 /* 3251 * First - check whether the length is the bluetooth or normal. 3252 * 3253 * If it's normal - just copy it and bump out. 3254 * Otherwise we have to convert things. 3255 */ 3256 3257 if (len == sizeof(struct iwn_stats) + 4) { 3258 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3259 sc->last_stat_valid = 1; 3260 return; 3261 } 3262 3263 /* 3264 * If it's not the bluetooth size - log, then just copy. 3265 */ 3266 if (len != sizeof(struct iwn_stats_bt) + 4) { 3267 DPRINTF(sc, IWN_DEBUG_STATS, 3268 "%s: size of rx statistics (%d) not an expected size!\n", 3269 __func__, 3270 len); 3271 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3272 sc->last_stat_valid = 1; 3273 return; 3274 } 3275 3276 /* 3277 * Ok. Time to copy. 3278 */ 3279 stats_bt = (struct iwn_stats_bt *) stats; 3280 lstats = &sc->last_stat; 3281 3282 /* flags */ 3283 lstats->flags = stats_bt->flags; 3284 /* rx_bt */ 3285 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm, 3286 sizeof(struct iwn_rx_phy_stats)); 3287 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck, 3288 sizeof(struct iwn_rx_phy_stats)); 3289 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common, 3290 sizeof(struct iwn_rx_general_stats)); 3291 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht, 3292 sizeof(struct iwn_rx_ht_phy_stats)); 3293 /* tx */ 3294 memcpy(&lstats->tx, &stats_bt->tx, 3295 sizeof(struct iwn_tx_stats)); 3296 /* general */ 3297 memcpy(&lstats->general, &stats_bt->general, 3298 sizeof(struct iwn_general_stats)); 3299 3300 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */ 3301 sc->last_stat_valid = 1; 3302 } 3303 3304 /* 3305 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 3306 * The latter is sent by the firmware after each received beacon. 3307 */ 3308 static void 3309 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3310 struct iwn_rx_data *data) 3311 { 3312 struct iwn_ops *ops = &sc->ops; 3313 struct ifnet *ifp = sc->sc_ifp; 3314 struct ieee80211com *ic = ifp->if_l2com; 3315 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3316 struct iwn_calib_state *calib = &sc->calib; 3317 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 3318 struct iwn_stats *lstats; 3319 int temp; 3320 3321 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3322 3323 /* Ignore statistics received during a scan. */ 3324 if (vap->iv_state != IEEE80211_S_RUN || 3325 (ic->ic_flags & IEEE80211_F_SCAN)){ 3326 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 3327 __func__); 3328 return; 3329 } 3330 3331 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3332 3333 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS, 3334 "%s: received statistics, cmd %d, len %d\n", 3335 __func__, desc->type, le16toh(desc->len)); 3336 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 3337 3338 /* 3339 * Collect/track general statistics for reporting. 3340 * 3341 * This takes care of ensuring that the bluetooth sized message 3342 * will be correctly converted to the legacy sized message. 3343 */ 3344 iwn_stats_update(sc, calib, stats, le16toh(desc->len)); 3345 3346 /* 3347 * And now, let's take a reference of it to use! 3348 */ 3349 lstats = &sc->last_stat; 3350 3351 /* Test if temperature has changed. */ 3352 if (lstats->general.temp != sc->rawtemp) { 3353 /* Convert "raw" temperature to degC. */ 3354 sc->rawtemp = stats->general.temp; 3355 temp = ops->get_temperature(sc); 3356 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 3357 __func__, temp); 3358 3359 /* Update TX power if need be (4965AGN only). */ 3360 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3361 iwn4965_power_calibration(sc, temp); 3362 } 3363 3364 if (desc->type != IWN_BEACON_STATISTICS) 3365 return; /* Reply to a statistics request. */ 3366 3367 sc->noise = iwn_get_noise(&lstats->rx.general); 3368 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 3369 3370 /* Test that RSSI and noise are present in stats report. */ 3371 if (le32toh(lstats->rx.general.flags) != 1) { 3372 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 3373 "received statistics without RSSI"); 3374 return; 3375 } 3376 3377 if (calib->state == IWN_CALIB_STATE_ASSOC) 3378 iwn_collect_noise(sc, &lstats->rx.general); 3379 else if (calib->state == IWN_CALIB_STATE_RUN) { 3380 iwn_tune_sensitivity(sc, &lstats->rx); 3381 /* 3382 * XXX TODO: Only run the RX recovery if we're associated! 3383 */ 3384 iwn_check_rx_recovery(sc, lstats); 3385 iwn_save_stats_counters(sc, lstats); 3386 } 3387 3388 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3389 } 3390 3391 /* 3392 * Save the relevant statistic counters for the next calibration 3393 * pass. 3394 */ 3395 static void 3396 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs) 3397 { 3398 struct iwn_calib_state *calib = &sc->calib; 3399 3400 /* Save counters values for next call. */ 3401 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp); 3402 calib->fa_cck = le32toh(rs->rx.cck.fa); 3403 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp); 3404 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp); 3405 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa); 3406 3407 /* Last time we received these tick values */ 3408 sc->last_calib_ticks = ticks; 3409 } 3410 3411 /* 3412 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 3413 * and 5000 adapters have different incompatible TX status formats. 3414 */ 3415 static void 3416 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3417 struct iwn_rx_data *data) 3418 { 3419 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 3420 struct iwn_tx_ring *ring; 3421 int qid; 3422 3423 qid = desc->qid & 0xf; 3424 ring = &sc->txq[qid]; 3425 3426 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3427 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 3428 __func__, desc->qid, desc->idx, stat->ackfailcnt, 3429 stat->btkillcnt, stat->rate, le16toh(stat->duration), 3430 le32toh(stat->status)); 3431 3432 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3433 if (qid >= sc->firstaggqueue) { 3434 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3435 &stat->status); 3436 } else { 3437 iwn_tx_done(sc, desc, stat->ackfailcnt, 3438 le32toh(stat->status) & 0xff); 3439 } 3440 } 3441 3442 static void 3443 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3444 struct iwn_rx_data *data) 3445 { 3446 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 3447 struct iwn_tx_ring *ring; 3448 int qid; 3449 3450 qid = desc->qid & 0xf; 3451 ring = &sc->txq[qid]; 3452 3453 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3454 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 3455 __func__, desc->qid, desc->idx, stat->ackfailcnt, 3456 stat->btkillcnt, stat->rate, le16toh(stat->duration), 3457 le32toh(stat->status)); 3458 3459 #ifdef notyet 3460 /* Reset TX scheduler slot. */ 3461 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 3462 #endif 3463 3464 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3465 if (qid >= sc->firstaggqueue) { 3466 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3467 &stat->status); 3468 } else { 3469 iwn_tx_done(sc, desc, stat->ackfailcnt, 3470 le16toh(stat->status) & 0xff); 3471 } 3472 } 3473 3474 /* 3475 * Adapter-independent backend for TX_DONE firmware notifications. 3476 */ 3477 static void 3478 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 3479 uint8_t status) 3480 { 3481 struct ifnet *ifp = sc->sc_ifp; 3482 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 3483 struct iwn_tx_data *data = &ring->data[desc->idx]; 3484 struct mbuf *m; 3485 struct ieee80211_node *ni; 3486 struct ieee80211vap *vap; 3487 3488 KASSERT(data->ni != NULL, ("no node")); 3489 3490 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3491 3492 /* Unmap and free mbuf. */ 3493 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 3494 bus_dmamap_unload(ring->data_dmat, data->map); 3495 m = data->m, data->m = NULL; 3496 ni = data->ni, data->ni = NULL; 3497 vap = ni->ni_vap; 3498 3499 /* 3500 * Update rate control statistics for the node. 3501 */ 3502 if (status & IWN_TX_FAIL) { 3503 IFNET_STAT_INC(ifp, oerrors, 1); 3504 ieee80211_ratectl_tx_complete(vap, ni, 3505 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 3506 } else { 3507 IFNET_STAT_INC(ifp, opackets, 1); 3508 ieee80211_ratectl_tx_complete(vap, ni, 3509 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 3510 } 3511 3512 /* 3513 * Channels marked for "radar" require traffic to be received 3514 * to unlock before we can transmit. Until traffic is seen 3515 * any attempt to transmit is returned immediately with status 3516 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 3517 * happen on first authenticate after scanning. To workaround 3518 * this we ignore a failure of this sort in AUTH state so the 3519 * 802.11 layer will fall back to using a timeout to wait for 3520 * the AUTH reply. This allows the firmware time to see 3521 * traffic so a subsequent retry of AUTH succeeds. It's 3522 * unclear why the firmware does not maintain state for 3523 * channels recently visited as this would allow immediate 3524 * use of the channel after a scan (where we see traffic). 3525 */ 3526 if (status == IWN_TX_FAIL_TX_LOCKED && 3527 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 3528 ieee80211_tx_complete(ni, m, 0); 3529 else 3530 ieee80211_tx_complete(ni, m, 3531 (status & IWN_TX_FAIL) != 0); 3532 3533 sc->sc_tx_timer = 0; 3534 if (--ring->queued < IWN_TX_RING_LOMARK) { 3535 sc->qfullmsk &= ~(1 << ring->qid); 3536 if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) { 3537 ifq_clr_oactive(&ifp->if_snd); 3538 iwn_start_locked(ifp); 3539 } 3540 } 3541 3542 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3543 3544 } 3545 3546 /* 3547 * Process a "command done" firmware notification. This is where we wakeup 3548 * processes waiting for a synchronous command completion. 3549 */ 3550 static void 3551 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3552 { 3553 struct iwn_tx_ring *ring; 3554 struct iwn_tx_data *data; 3555 int cmd_queue_num; 3556 3557 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 3558 cmd_queue_num = IWN_PAN_CMD_QUEUE; 3559 else 3560 cmd_queue_num = IWN_CMD_QUEUE_NUM; 3561 3562 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num) 3563 return; /* Not a command ack. */ 3564 3565 ring = &sc->txq[cmd_queue_num]; 3566 data = &ring->data[desc->idx]; 3567 3568 /* If the command was mapped in an mbuf, free it. */ 3569 if (data->m != NULL) { 3570 bus_dmamap_sync(ring->data_dmat, data->map, 3571 BUS_DMASYNC_POSTWRITE); 3572 bus_dmamap_unload(ring->data_dmat, data->map); 3573 m_freem(data->m); 3574 data->m = NULL; 3575 } 3576 wakeup(&ring->desc[desc->idx]); 3577 } 3578 3579 static void 3580 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 3581 void *stat) 3582 { 3583 struct iwn_ops *ops = &sc->ops; 3584 struct ifnet *ifp = sc->sc_ifp; 3585 struct iwn_tx_ring *ring = &sc->txq[qid]; 3586 struct iwn_tx_data *data; 3587 struct mbuf *m; 3588 struct iwn_node *wn; 3589 struct ieee80211_node *ni; 3590 struct ieee80211_tx_ampdu *tap; 3591 uint64_t bitmap; 3592 uint32_t *status = stat; 3593 uint16_t *aggstatus = stat; 3594 uint16_t ssn; 3595 uint8_t tid; 3596 int bit, i, lastidx, *res, seqno, shift, start; 3597 3598 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3599 3600 if (nframes == 1) { 3601 if ((*status & 0xff) != 1 && (*status & 0xff) != 2) { 3602 #ifdef NOT_YET 3603 kprintf("ieee80211_send_bar()\n"); 3604 #endif 3605 /* 3606 * If we completely fail a transmit, make sure a 3607 * notification is pushed up to the rate control 3608 * layer. 3609 */ 3610 tap = sc->qid2tap[qid]; 3611 tid = tap->txa_ac; 3612 wn = (void *)tap->txa_ni; 3613 ni = tap->txa_ni; 3614 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3615 IEEE80211_RATECTL_TX_FAILURE, &nframes, NULL); 3616 } 3617 } 3618 3619 bitmap = 0; 3620 start = idx; 3621 for (i = 0; i < nframes; i++) { 3622 if (le16toh(aggstatus[i * 2]) & 0xc) 3623 continue; 3624 3625 idx = le16toh(aggstatus[2*i + 1]) & 0xff; 3626 bit = idx - start; 3627 shift = 0; 3628 if (bit >= 64) { 3629 shift = 0x100 - idx + start; 3630 bit = 0; 3631 start = idx; 3632 } else if (bit <= -64) 3633 bit = 0x100 - start + idx; 3634 else if (bit < 0) { 3635 shift = start - idx; 3636 start = idx; 3637 bit = 0; 3638 } 3639 bitmap = bitmap << shift; 3640 bitmap |= 1ULL << bit; 3641 } 3642 tap = sc->qid2tap[qid]; 3643 tid = tap->txa_ac; 3644 wn = (void *)tap->txa_ni; 3645 wn->agg[tid].bitmap = bitmap; 3646 wn->agg[tid].startidx = start; 3647 wn->agg[tid].nframes = nframes; 3648 3649 res = NULL; 3650 ssn = 0; 3651 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3652 res = tap->txa_private; 3653 ssn = tap->txa_start & 0xfff; 3654 } 3655 3656 seqno = le32toh(*(status + nframes)) & 0xfff; 3657 for (lastidx = (seqno & 0xff); ring->read != lastidx;) { 3658 data = &ring->data[ring->read]; 3659 3660 /* Unmap and free mbuf. */ 3661 bus_dmamap_sync(ring->data_dmat, data->map, 3662 BUS_DMASYNC_POSTWRITE); 3663 bus_dmamap_unload(ring->data_dmat, data->map); 3664 m = data->m, data->m = NULL; 3665 ni = data->ni, data->ni = NULL; 3666 3667 KASSERT(ni != NULL, ("no node")); 3668 KASSERT(m != NULL, ("no mbuf")); 3669 3670 ieee80211_tx_complete(ni, m, 1); 3671 3672 ring->queued--; 3673 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT; 3674 } 3675 3676 if (ring->queued == 0 && res != NULL) { 3677 iwn_nic_lock(sc); 3678 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3679 iwn_nic_unlock(sc); 3680 sc->qid2tap[qid] = NULL; 3681 kfree(res, M_DEVBUF); 3682 return; 3683 } 3684 3685 sc->sc_tx_timer = 0; 3686 if (ring->queued < IWN_TX_RING_LOMARK) { 3687 sc->qfullmsk &= ~(1 << ring->qid); 3688 if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) { 3689 ifq_clr_oactive(&ifp->if_snd); 3690 iwn_start_locked(ifp); 3691 } 3692 } 3693 3694 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3695 3696 } 3697 3698 /* 3699 * Process an INT_FH_RX or INT_SW_RX interrupt. 3700 */ 3701 static void 3702 iwn_notif_intr(struct iwn_softc *sc) 3703 { 3704 struct iwn_ops *ops = &sc->ops; 3705 struct ifnet *ifp = sc->sc_ifp; 3706 struct ieee80211com *ic = ifp->if_l2com; 3707 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3708 uint16_t hw; 3709 3710 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 3711 BUS_DMASYNC_POSTREAD); 3712 3713 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 3714 while (sc->rxq.cur != hw) { 3715 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 3716 struct iwn_rx_desc *desc; 3717 3718 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3719 BUS_DMASYNC_POSTREAD); 3720 desc = mtod(data->m, struct iwn_rx_desc *); 3721 3722 DPRINTF(sc, IWN_DEBUG_RECV, 3723 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n", 3724 __func__, sc->rxq.cur, desc->qid & 0xf, desc->idx, desc->flags, 3725 desc->type, iwn_intr_str(desc->type), 3726 le16toh(desc->len)); 3727 3728 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */ 3729 iwn_cmd_done(sc, desc); 3730 3731 switch (desc->type) { 3732 case IWN_RX_PHY: 3733 iwn_rx_phy(sc, desc, data); 3734 break; 3735 3736 case IWN_RX_DONE: /* 4965AGN only. */ 3737 case IWN_MPDU_RX_DONE: 3738 /* An 802.11 frame has been received. */ 3739 iwn_rx_done(sc, desc, data); 3740 break; 3741 3742 case IWN_RX_COMPRESSED_BA: 3743 /* A Compressed BlockAck has been received. */ 3744 iwn_rx_compressed_ba(sc, desc, data); 3745 break; 3746 3747 case IWN_TX_DONE: 3748 /* An 802.11 frame has been transmitted. */ 3749 ops->tx_done(sc, desc, data); 3750 break; 3751 3752 case IWN_RX_STATISTICS: 3753 case IWN_BEACON_STATISTICS: 3754 iwn_rx_statistics(sc, desc, data); 3755 break; 3756 3757 case IWN_BEACON_MISSED: 3758 { 3759 struct iwn_beacon_missed *miss = 3760 (struct iwn_beacon_missed *)(desc + 1); 3761 int misses; 3762 3763 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3764 BUS_DMASYNC_POSTREAD); 3765 misses = le32toh(miss->consecutive); 3766 3767 DPRINTF(sc, IWN_DEBUG_STATE, 3768 "%s: beacons missed %d/%d\n", __func__, 3769 misses, le32toh(miss->total)); 3770 /* 3771 * If more than 5 consecutive beacons are missed, 3772 * reinitialize the sensitivity state machine. 3773 */ 3774 if (vap->iv_state == IEEE80211_S_RUN && 3775 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 3776 if (misses > 5) 3777 (void)iwn_init_sensitivity(sc); 3778 if (misses >= vap->iv_bmissthreshold) { 3779 ieee80211_beacon_miss(ic); 3780 } 3781 } 3782 break; 3783 } 3784 case IWN_UC_READY: 3785 { 3786 struct iwn_ucode_info *uc = 3787 (struct iwn_ucode_info *)(desc + 1); 3788 3789 /* The microcontroller is ready. */ 3790 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3791 BUS_DMASYNC_POSTREAD); 3792 DPRINTF(sc, IWN_DEBUG_RESET, 3793 "microcode alive notification version=%d.%d " 3794 "subtype=%x alive=%x\n", uc->major, uc->minor, 3795 uc->subtype, le32toh(uc->valid)); 3796 3797 if (le32toh(uc->valid) != 1) { 3798 device_printf(sc->sc_dev, 3799 "microcontroller initialization failed"); 3800 break; 3801 } 3802 if (uc->subtype == IWN_UCODE_INIT) { 3803 /* Save microcontroller report. */ 3804 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 3805 } 3806 /* Save the address of the error log in SRAM. */ 3807 sc->errptr = le32toh(uc->errptr); 3808 break; 3809 } 3810 case IWN_STATE_CHANGED: 3811 { 3812 /* 3813 * State change allows hardware switch change to be 3814 * noted. However, we handle this in iwn_intr as we 3815 * get both the enable/disble intr. 3816 */ 3817 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3818 BUS_DMASYNC_POSTREAD); 3819 #ifdef IWN_DEBUG 3820 uint32_t *status = (uint32_t *)(desc + 1); 3821 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE, 3822 "state changed to %x\n", 3823 le32toh(*status)); 3824 #endif 3825 break; 3826 } 3827 case IWN_START_SCAN: 3828 { 3829 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3830 BUS_DMASYNC_POSTREAD); 3831 #ifdef IWN_DEBUG 3832 struct iwn_start_scan *scan = 3833 (struct iwn_start_scan *)(desc + 1); 3834 DPRINTF(sc, IWN_DEBUG_ANY, 3835 "%s: scanning channel %d status %x\n", 3836 __func__, scan->chan, le32toh(scan->status)); 3837 #endif 3838 break; 3839 } 3840 case IWN_STOP_SCAN: 3841 { 3842 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3843 BUS_DMASYNC_POSTREAD); 3844 #ifdef IWN_DEBUG 3845 struct iwn_stop_scan *scan = 3846 (struct iwn_stop_scan *)(desc + 1); 3847 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN, 3848 "scan finished nchan=%d status=%d chan=%d\n", 3849 scan->nchan, scan->status, scan->chan); 3850 #endif 3851 sc->sc_is_scanning = 0; 3852 ieee80211_scan_next(vap); 3853 break; 3854 } 3855 case IWN5000_CALIBRATION_RESULT: 3856 iwn5000_rx_calib_results(sc, desc, data); 3857 break; 3858 3859 case IWN5000_CALIBRATION_DONE: 3860 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3861 wakeup(sc); 3862 break; 3863 } 3864 3865 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3866 } 3867 3868 /* Tell the firmware what we have processed. */ 3869 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3870 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3871 } 3872 3873 /* 3874 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3875 * from power-down sleep mode. 3876 */ 3877 static void 3878 iwn_wakeup_intr(struct iwn_softc *sc) 3879 { 3880 int qid; 3881 3882 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 3883 __func__); 3884 3885 /* Wakeup RX and TX rings. */ 3886 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 3887 for (qid = 0; qid < sc->ntxqs; qid++) { 3888 struct iwn_tx_ring *ring = &sc->txq[qid]; 3889 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 3890 } 3891 } 3892 3893 static void 3894 iwn_rftoggle_intr(struct iwn_softc *sc) 3895 { 3896 struct ifnet *ifp = sc->sc_ifp; 3897 struct ieee80211com *ic = ifp->if_l2com; 3898 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 3899 3900 device_printf(sc->sc_dev, "RF switch: radio %s\n", 3901 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 3902 if (tmp & IWN_GP_CNTRL_RFKILL) 3903 ieee80211_runtask(ic, &sc->sc_radioon_task); 3904 else 3905 ieee80211_runtask(ic, &sc->sc_radiooff_task); 3906 } 3907 3908 /* 3909 * Dump the error log of the firmware when a firmware panic occurs. Although 3910 * we can't debug the firmware because it is neither open source nor free, it 3911 * can help us to identify certain classes of problems. 3912 */ 3913 static void 3914 iwn_fatal_intr(struct iwn_softc *sc) 3915 { 3916 struct iwn_fw_dump dump; 3917 int i; 3918 3919 /* Force a complete recalibration on next init. */ 3920 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 3921 3922 /* Check that the error log address is valid. */ 3923 if (sc->errptr < IWN_FW_DATA_BASE || 3924 sc->errptr + sizeof (dump) > 3925 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 3926 kprintf("%s: bad firmware error log address 0x%08x\n", __func__, 3927 sc->errptr); 3928 return; 3929 } 3930 if (iwn_nic_lock(sc) != 0) { 3931 kprintf("%s: could not read firmware error log\n", __func__); 3932 return; 3933 } 3934 /* Read firmware error log from SRAM. */ 3935 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 3936 sizeof (dump) / sizeof (uint32_t)); 3937 iwn_nic_unlock(sc); 3938 3939 if (dump.valid == 0) { 3940 kprintf("%s: firmware error log is empty\n", __func__); 3941 return; 3942 } 3943 kprintf("firmware error log:\n"); 3944 kprintf(" error type = \"%s\" (0x%08X)\n", 3945 (dump.id < nitems(iwn_fw_errmsg)) ? 3946 iwn_fw_errmsg[dump.id] : "UNKNOWN", 3947 dump.id); 3948 kprintf(" program counter = 0x%08X\n", dump.pc); 3949 kprintf(" source line = 0x%08X\n", dump.src_line); 3950 kprintf(" error data = 0x%08X%08X\n", 3951 dump.error_data[0], dump.error_data[1]); 3952 kprintf(" branch link = 0x%08X%08X\n", 3953 dump.branch_link[0], dump.branch_link[1]); 3954 kprintf(" interrupt link = 0x%08X%08X\n", 3955 dump.interrupt_link[0], dump.interrupt_link[1]); 3956 kprintf(" time = %u\n", dump.time[0]); 3957 3958 /* Dump driver status (TX and RX rings) while we're here. */ 3959 kprintf("driver status:\n"); 3960 for (i = 0; i < sc->ntxqs; i++) { 3961 struct iwn_tx_ring *ring = &sc->txq[i]; 3962 kprintf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 3963 i, ring->qid, ring->cur, ring->queued); 3964 } 3965 kprintf(" rx ring: cur=%d\n", sc->rxq.cur); 3966 } 3967 3968 static void 3969 iwn_intr(void *arg) 3970 { 3971 struct iwn_softc *sc = arg; 3972 struct ifnet *ifp = sc->sc_ifp; 3973 uint32_t r1, r2, tmp; 3974 3975 /* Disable interrupts. */ 3976 IWN_WRITE(sc, IWN_INT_MASK, 0); 3977 3978 /* Read interrupts from ICT (fast) or from registers (slow). */ 3979 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3980 tmp = 0; 3981 while (sc->ict[sc->ict_cur] != 0) { 3982 tmp |= sc->ict[sc->ict_cur]; 3983 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 3984 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 3985 } 3986 tmp = le32toh(tmp); 3987 if (tmp == 0xffffffff) /* Shouldn't happen. */ 3988 tmp = 0; 3989 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 3990 tmp |= 0x8000; 3991 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 3992 r2 = 0; /* Unused. */ 3993 } else { 3994 r1 = IWN_READ(sc, IWN_INT); 3995 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 3996 return; /* Hardware gone! */ 3997 r2 = IWN_READ(sc, IWN_FH_INT); 3998 } 3999 4000 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 4001 , r1, r2); 4002 4003 if (r1 == 0 && r2 == 0) 4004 goto done; /* Interrupt not for us. */ 4005 4006 /* Acknowledge interrupts. */ 4007 IWN_WRITE(sc, IWN_INT, r1); 4008 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 4009 IWN_WRITE(sc, IWN_FH_INT, r2); 4010 4011 if (r1 & IWN_INT_RF_TOGGLED) { 4012 iwn_rftoggle_intr(sc); 4013 goto done; 4014 } 4015 if (r1 & IWN_INT_CT_REACHED) { 4016 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 4017 __func__); 4018 } 4019 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 4020 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 4021 __func__); 4022 #ifdef IWN_DEBUG 4023 iwn_debug_register(sc); 4024 #endif 4025 /* Dump firmware error log and stop. */ 4026 iwn_fatal_intr(sc); 4027 4028 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task); 4029 goto done; 4030 } 4031 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 4032 (r2 & IWN_FH_INT_RX)) { 4033 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4034 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 4035 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 4036 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4037 IWN_INT_PERIODIC_DIS); 4038 iwn_notif_intr(sc); 4039 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 4040 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4041 IWN_INT_PERIODIC_ENA); 4042 } 4043 } else 4044 iwn_notif_intr(sc); 4045 } 4046 4047 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 4048 if (sc->sc_flags & IWN_FLAG_USE_ICT) 4049 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 4050 wakeup(sc); /* FH DMA transfer completed. */ 4051 } 4052 4053 if (r1 & IWN_INT_ALIVE) 4054 wakeup(sc); /* Firmware is alive. */ 4055 4056 if (r1 & IWN_INT_WAKEUP) 4057 iwn_wakeup_intr(sc); 4058 4059 done: 4060 /* Re-enable interrupts. */ 4061 if (ifp->if_flags & IFF_UP) 4062 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4063 } 4064 4065 /* 4066 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 4067 * 5000 adapters use a slightly different format). 4068 */ 4069 static void 4070 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4071 uint16_t len) 4072 { 4073 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 4074 4075 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4076 4077 *w = htole16(len + 8); 4078 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4079 BUS_DMASYNC_PREWRITE); 4080 if (idx < IWN_SCHED_WINSZ) { 4081 *(w + IWN_TX_RING_COUNT) = *w; 4082 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4083 BUS_DMASYNC_PREWRITE); 4084 } 4085 } 4086 4087 static void 4088 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4089 uint16_t len) 4090 { 4091 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4092 4093 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4094 4095 *w = htole16(id << 12 | (len + 8)); 4096 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4097 BUS_DMASYNC_PREWRITE); 4098 if (idx < IWN_SCHED_WINSZ) { 4099 *(w + IWN_TX_RING_COUNT) = *w; 4100 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4101 BUS_DMASYNC_PREWRITE); 4102 } 4103 } 4104 4105 #ifdef notyet 4106 static void 4107 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 4108 { 4109 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4110 4111 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4112 4113 *w = (*w & htole16(0xf000)) | htole16(1); 4114 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4115 BUS_DMASYNC_PREWRITE); 4116 if (idx < IWN_SCHED_WINSZ) { 4117 *(w + IWN_TX_RING_COUNT) = *w; 4118 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4119 BUS_DMASYNC_PREWRITE); 4120 } 4121 } 4122 #endif 4123 4124 /* 4125 * Check whether OFDM 11g protection will be enabled for the given rate. 4126 * 4127 * The original driver code only enabled protection for OFDM rates. 4128 * It didn't check to see whether it was operating in 11a or 11bg mode. 4129 */ 4130 static int 4131 iwn_check_rate_needs_protection(struct iwn_softc *sc, 4132 struct ieee80211vap *vap, uint8_t rate) 4133 { 4134 struct ieee80211com *ic = vap->iv_ic; 4135 4136 /* 4137 * Not in 2GHz mode? Then there's no need to enable OFDM 4138 * 11bg protection. 4139 */ 4140 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { 4141 return (0); 4142 } 4143 4144 /* 4145 * 11bg protection not enabled? Then don't use it. 4146 */ 4147 if ((ic->ic_flags & IEEE80211_F_USEPROT) == 0) 4148 return (0); 4149 4150 /* 4151 * If it's an 11n rate, then for now we enable 4152 * protection. 4153 */ 4154 if (rate & IEEE80211_RATE_MCS) { 4155 return (1); 4156 } 4157 4158 /* 4159 * Do a rate table lookup. If the PHY is CCK, 4160 * don't do protection. 4161 */ 4162 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK) 4163 return (0); 4164 4165 /* 4166 * Yup, enable protection. 4167 */ 4168 return (1); 4169 } 4170 4171 /* 4172 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into 4173 * the link quality table that reflects this particular entry. 4174 */ 4175 static int 4176 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni, 4177 uint8_t rate) 4178 { 4179 struct ieee80211_rateset *rs; 4180 int is_11n; 4181 int nr; 4182 int i; 4183 uint8_t cmp_rate; 4184 4185 /* 4186 * Figure out if we're using 11n or not here. 4187 */ 4188 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) 4189 is_11n = 1; 4190 else 4191 is_11n = 0; 4192 4193 /* 4194 * Use the correct rate table. 4195 */ 4196 if (is_11n) { 4197 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 4198 nr = ni->ni_htrates.rs_nrates; 4199 } else { 4200 rs = &ni->ni_rates; 4201 nr = rs->rs_nrates; 4202 } 4203 4204 /* 4205 * Find the relevant link quality entry in the table. 4206 */ 4207 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) { 4208 /* 4209 * The link quality table index starts at 0 == highest 4210 * rate, so we walk the rate table backwards. 4211 */ 4212 cmp_rate = rs->rs_rates[(nr - 1) - i]; 4213 if (rate & IEEE80211_RATE_MCS) 4214 cmp_rate |= IEEE80211_RATE_MCS; 4215 4216 #if 0 4217 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n", 4218 __func__, 4219 i, 4220 nr, 4221 rate, 4222 cmp_rate); 4223 #endif 4224 4225 if (cmp_rate == rate) 4226 return (i); 4227 } 4228 4229 /* Failed? Start at the end */ 4230 return (IWN_MAX_TX_RETRIES - 1); 4231 } 4232 4233 static int 4234 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 4235 { 4236 struct iwn_ops *ops = &sc->ops; 4237 const struct ieee80211_txparam *tp; 4238 struct ieee80211vap *vap = ni->ni_vap; 4239 struct ieee80211com *ic = ni->ni_ic; 4240 struct iwn_node *wn = (void *)ni; 4241 struct iwn_tx_ring *ring; 4242 struct iwn_tx_desc *desc; 4243 struct iwn_tx_data *data; 4244 struct iwn_tx_cmd *cmd; 4245 struct iwn_cmd_data *tx; 4246 struct ieee80211_frame *wh; 4247 struct ieee80211_key *k = NULL; 4248 struct mbuf *m1; 4249 uint32_t flags; 4250 uint16_t qos; 4251 u_int hdrlen; 4252 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4253 uint8_t tid, type; 4254 int ac, i, totlen, error, pad, nsegs = 0, rate; 4255 4256 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4257 4258 wh = mtod(m, struct ieee80211_frame *); 4259 hdrlen = ieee80211_anyhdrsize(wh); 4260 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4261 4262 /* Select EDCA Access Category and TX ring for this frame. */ 4263 if (IEEE80211_QOS_HAS_SEQ(wh)) { 4264 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 4265 tid = qos & IEEE80211_QOS_TID; 4266 } else { 4267 qos = 0; 4268 tid = 0; 4269 } 4270 ac = M_WME_GETAC(m); 4271 if (m->m_flags & M_AMPDU_MPDU) { 4272 uint16_t seqno; 4273 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 4274 4275 if (!IEEE80211_AMPDU_RUNNING(tap)) { 4276 m_freem(m); 4277 return EINVAL; 4278 } 4279 4280 /* 4281 * Queue this frame to the hardware ring that we've 4282 * negotiated AMPDU TX on. 4283 * 4284 * Note that the sequence number must match the TX slot 4285 * being used! 4286 */ 4287 ac = *(int *)tap->txa_private; 4288 seqno = ni->ni_txseqs[tid]; 4289 *(uint16_t *)wh->i_seq = 4290 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 4291 ring = &sc->txq[ac]; 4292 if ((seqno % 256) != ring->cur) { 4293 device_printf(sc->sc_dev, 4294 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n", 4295 __func__, 4296 m, 4297 seqno, 4298 seqno % 256, 4299 ring->cur); 4300 } 4301 ni->ni_txseqs[tid]++; 4302 } 4303 ring = &sc->txq[ac]; 4304 desc = &ring->desc[ring->cur]; 4305 data = &ring->data[ring->cur]; 4306 4307 /* Choose a TX rate index. */ 4308 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 4309 if (type == IEEE80211_FC0_TYPE_MGT) 4310 rate = tp->mgmtrate; 4311 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 4312 rate = tp->mcastrate; 4313 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 4314 rate = tp->ucastrate; 4315 else if (m->m_flags & M_EAPOL) 4316 rate = tp->mgmtrate; 4317 else { 4318 /* XXX pass pktlen */ 4319 (void) ieee80211_ratectl_rate(ni, NULL, 0); 4320 rate = ni->ni_txrate; 4321 } 4322 4323 /* Encrypt the frame if need be. */ 4324 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 4325 /* Retrieve key for TX. */ 4326 k = ieee80211_crypto_encap(ni, m); 4327 if (k == NULL) { 4328 m_freem(m); 4329 return ENOBUFS; 4330 } 4331 /* 802.11 header may have moved. */ 4332 wh = mtod(m, struct ieee80211_frame *); 4333 } 4334 totlen = m->m_pkthdr.len; 4335 4336 if (ieee80211_radiotap_active_vap(vap)) { 4337 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4338 4339 tap->wt_flags = 0; 4340 tap->wt_rate = rate; 4341 if (k != NULL) 4342 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4343 4344 ieee80211_radiotap_tx(vap, m); 4345 } 4346 4347 /* Prepare TX firmware command. */ 4348 cmd = &ring->cmd[ring->cur]; 4349 cmd->code = IWN_CMD_TX_DATA; 4350 cmd->flags = 0; 4351 cmd->qid = ring->qid; 4352 cmd->idx = ring->cur; 4353 4354 tx = (struct iwn_cmd_data *)cmd->data; 4355 /* NB: No need to clear tx, all fields are reinitialized here. */ 4356 tx->scratch = 0; /* clear "scratch" area */ 4357 4358 flags = 0; 4359 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4360 /* Unicast frame, check if an ACK is expected. */ 4361 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 4362 IEEE80211_QOS_ACKPOLICY_NOACK) 4363 flags |= IWN_TX_NEED_ACK; 4364 } 4365 if ((wh->i_fc[0] & 4366 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 4367 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 4368 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 4369 4370 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 4371 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 4372 4373 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 4374 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4375 /* NB: Group frames are sent using CCK in 802.11b/g. */ 4376 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 4377 flags |= IWN_TX_NEED_RTS; 4378 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) { 4379 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4380 flags |= IWN_TX_NEED_CTS; 4381 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4382 flags |= IWN_TX_NEED_RTS; 4383 } 4384 4385 /* XXX HT protection? */ 4386 4387 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 4388 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4389 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4390 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 4391 flags |= IWN_TX_NEED_PROTECTION; 4392 } else 4393 flags |= IWN_TX_FULL_TXOP; 4394 } 4395 } 4396 4397 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4398 type != IEEE80211_FC0_TYPE_DATA) 4399 tx->id = sc->broadcast_id; 4400 else 4401 tx->id = wn->id; 4402 4403 if (type == IEEE80211_FC0_TYPE_MGT) { 4404 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4405 4406 /* Tell HW to set timestamp in probe responses. */ 4407 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4408 flags |= IWN_TX_INSERT_TSTAMP; 4409 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4410 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4411 tx->timeout = htole16(3); 4412 else 4413 tx->timeout = htole16(2); 4414 } else 4415 tx->timeout = htole16(0); 4416 4417 if (hdrlen & 3) { 4418 /* First segment length must be a multiple of 4. */ 4419 flags |= IWN_TX_NEED_PADDING; 4420 pad = 4 - (hdrlen & 3); 4421 } else 4422 pad = 0; 4423 4424 tx->len = htole16(totlen); 4425 tx->tid = tid; 4426 tx->rts_ntries = 60; 4427 tx->data_ntries = 15; 4428 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4429 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4430 if (tx->id == sc->broadcast_id) { 4431 /* Group or management frame. */ 4432 tx->linkq = 0; 4433 } else { 4434 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate); 4435 flags |= IWN_TX_LINKQ; /* enable MRR */ 4436 } 4437 4438 /* Set physical address of "scratch area". */ 4439 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4440 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4441 4442 /* Copy 802.11 header in TX command. */ 4443 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4444 4445 /* Trim 802.11 header. */ 4446 m_adj(m, hdrlen); 4447 tx->security = 0; 4448 tx->flags = htole32(flags); 4449 4450 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map, 4451 m, segs, IWN_MAX_SCATTER - 1, 4452 &nsegs, BUS_DMA_NOWAIT); 4453 if (error != 0) { 4454 if (error != EFBIG) { 4455 device_printf(sc->sc_dev, 4456 "%s: can't map mbuf (error %d)\n", __func__, error); 4457 m_freem(m); 4458 return error; 4459 } 4460 /* Too many DMA segments, linearize mbuf. */ 4461 m1 = m_defrag(m, MB_DONTWAIT); 4462 if (m1 == NULL) { 4463 device_printf(sc->sc_dev, 4464 "%s: could not defrag mbuf\n", __func__); 4465 m_freem(m); 4466 return ENOBUFS; 4467 } 4468 m = m1; 4469 4470 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 4471 data->map, m, segs, 4472 IWN_MAX_SCATTER - 1, 4473 &nsegs, BUS_DMA_NOWAIT); 4474 if (error != 0) { 4475 device_printf(sc->sc_dev, 4476 "%s: can't map mbuf (error %d)\n", __func__, error); 4477 m_freem(m); 4478 return error; 4479 } 4480 } 4481 4482 data->m = m; 4483 data->ni = ni; 4484 4485 DPRINTF(sc, IWN_DEBUG_XMIT, 4486 "%s: qid %d idx %d len %d nsegs %d rate %04x plcp 0x%08x\n", 4487 __func__, 4488 ring->qid, 4489 ring->cur, 4490 m->m_pkthdr.len, 4491 nsegs, 4492 rate, 4493 tx->rate); 4494 4495 /* Fill TX descriptor. */ 4496 desc->nsegs = 1; 4497 if (m->m_len != 0) 4498 desc->nsegs += nsegs; 4499 /* First DMA segment is used by the TX command. */ 4500 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4501 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4502 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4503 /* Other DMA segments are for data payload. */ 4504 seg = &segs[0]; 4505 for (i = 1; i <= nsegs; i++) { 4506 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4507 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4508 seg->ds_len << 4); 4509 seg++; 4510 } 4511 4512 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4513 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4514 BUS_DMASYNC_PREWRITE); 4515 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4516 BUS_DMASYNC_PREWRITE); 4517 4518 /* Update TX scheduler. */ 4519 if (ring->qid >= sc->firstaggqueue) 4520 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4521 4522 /* Kick TX ring. */ 4523 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4524 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4525 4526 /* Mark TX ring as full if we reach a certain threshold. */ 4527 if (++ring->queued > IWN_TX_RING_HIMARK) 4528 sc->qfullmsk |= 1 << ring->qid; 4529 4530 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4531 4532 return 0; 4533 } 4534 4535 static int 4536 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 4537 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 4538 { 4539 struct iwn_ops *ops = &sc->ops; 4540 // struct ifnet *ifp = sc->sc_ifp; 4541 struct ieee80211vap *vap = ni->ni_vap; 4542 // struct ieee80211com *ic = ifp->if_l2com; 4543 struct iwn_tx_cmd *cmd; 4544 struct iwn_cmd_data *tx; 4545 struct ieee80211_frame *wh; 4546 struct iwn_tx_ring *ring; 4547 struct iwn_tx_desc *desc; 4548 struct iwn_tx_data *data; 4549 struct mbuf *m1; 4550 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4551 uint32_t flags; 4552 u_int hdrlen; 4553 int ac, totlen, error, pad, nsegs = 0, i, rate; 4554 uint8_t type; 4555 4556 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4557 4558 wh = mtod(m, struct ieee80211_frame *); 4559 hdrlen = ieee80211_anyhdrsize(wh); 4560 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4561 4562 ac = params->ibp_pri & 3; 4563 4564 ring = &sc->txq[ac]; 4565 desc = &ring->desc[ring->cur]; 4566 data = &ring->data[ring->cur]; 4567 4568 /* Choose a TX rate. */ 4569 rate = params->ibp_rate0; 4570 totlen = m->m_pkthdr.len; 4571 4572 /* Prepare TX firmware command. */ 4573 cmd = &ring->cmd[ring->cur]; 4574 cmd->code = IWN_CMD_TX_DATA; 4575 cmd->flags = 0; 4576 cmd->qid = ring->qid; 4577 cmd->idx = ring->cur; 4578 4579 tx = (struct iwn_cmd_data *)cmd->data; 4580 /* NB: No need to clear tx, all fields are reinitialized here. */ 4581 tx->scratch = 0; /* clear "scratch" area */ 4582 4583 flags = 0; 4584 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 4585 flags |= IWN_TX_NEED_ACK; 4586 if (params->ibp_flags & IEEE80211_BPF_RTS) { 4587 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4588 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4589 flags &= ~IWN_TX_NEED_RTS; 4590 flags |= IWN_TX_NEED_PROTECTION; 4591 } else 4592 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 4593 } 4594 if (params->ibp_flags & IEEE80211_BPF_CTS) { 4595 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4596 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4597 flags &= ~IWN_TX_NEED_CTS; 4598 flags |= IWN_TX_NEED_PROTECTION; 4599 } else 4600 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 4601 } 4602 if (type == IEEE80211_FC0_TYPE_MGT) { 4603 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4604 4605 /* Tell HW to set timestamp in probe responses. */ 4606 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4607 flags |= IWN_TX_INSERT_TSTAMP; 4608 4609 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4610 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4611 tx->timeout = htole16(3); 4612 else 4613 tx->timeout = htole16(2); 4614 } else 4615 tx->timeout = htole16(0); 4616 4617 if (hdrlen & 3) { 4618 /* First segment length must be a multiple of 4. */ 4619 flags |= IWN_TX_NEED_PADDING; 4620 pad = 4 - (hdrlen & 3); 4621 } else 4622 pad = 0; 4623 4624 if (ieee80211_radiotap_active_vap(vap)) { 4625 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4626 4627 tap->wt_flags = 0; 4628 tap->wt_rate = rate; 4629 4630 ieee80211_radiotap_tx(vap, m); 4631 } 4632 4633 tx->len = htole16(totlen); 4634 tx->tid = 0; 4635 tx->id = sc->broadcast_id; 4636 tx->rts_ntries = params->ibp_try1; 4637 tx->data_ntries = params->ibp_try0; 4638 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4639 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4640 4641 /* Group or management frame. */ 4642 tx->linkq = 0; 4643 4644 /* Set physical address of "scratch area". */ 4645 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4646 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4647 4648 /* Copy 802.11 header in TX command. */ 4649 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4650 4651 /* Trim 802.11 header. */ 4652 m_adj(m, hdrlen); 4653 tx->security = 0; 4654 tx->flags = htole32(flags); 4655 4656 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map, 4657 m, segs, 4658 IWN_MAX_SCATTER - 1, 4659 &nsegs, BUS_DMA_NOWAIT); 4660 if (error != 0) { 4661 if (error != EFBIG) { 4662 device_printf(sc->sc_dev, 4663 "%s: can't map mbuf (error %d)\n", __func__, error); 4664 m_freem(m); 4665 return error; 4666 } 4667 /* Too many DMA segments, linearize mbuf. */ 4668 m1 = m_defrag(m, M_NOWAIT); 4669 if (m1 == NULL) { 4670 device_printf(sc->sc_dev, 4671 "%s: could not defrag mbuf\n", __func__); 4672 m_freem(m); 4673 return ENOBUFS; 4674 } 4675 m = m1; 4676 4677 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 4678 data->map, m, segs, 4679 IWN_MAX_SCATTER - 1, 4680 &nsegs, BUS_DMA_NOWAIT); 4681 if (error != 0) { 4682 device_printf(sc->sc_dev, 4683 "%s: can't map mbuf (error %d)\n", __func__, error); 4684 m_freem(m); 4685 return error; 4686 } 4687 } 4688 4689 data->m = m; 4690 data->ni = ni; 4691 4692 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 4693 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 4694 4695 /* Fill TX descriptor. */ 4696 desc->nsegs = 1; 4697 if (m->m_len != 0) 4698 desc->nsegs += nsegs; 4699 /* First DMA segment is used by the TX command. */ 4700 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4701 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4702 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4703 /* Other DMA segments are for data payload. */ 4704 seg = &segs[0]; 4705 for (i = 1; i <= nsegs; i++) { 4706 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4707 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4708 seg->ds_len << 4); 4709 seg++; 4710 } 4711 4712 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4713 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4714 BUS_DMASYNC_PREWRITE); 4715 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4716 BUS_DMASYNC_PREWRITE); 4717 4718 /* Update TX scheduler. */ 4719 if (ring->qid >= sc->firstaggqueue) 4720 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4721 4722 /* Kick TX ring. */ 4723 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4724 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4725 4726 /* Mark TX ring as full if we reach a certain threshold. */ 4727 if (++ring->queued > IWN_TX_RING_HIMARK) 4728 sc->qfullmsk |= 1 << ring->qid; 4729 4730 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4731 4732 return 0; 4733 } 4734 4735 static int 4736 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4737 const struct ieee80211_bpf_params *params) 4738 { 4739 struct ieee80211com *ic = ni->ni_ic; 4740 struct ifnet *ifp = ic->ic_ifp; 4741 struct iwn_softc *sc = ifp->if_softc; 4742 int error = 0; 4743 4744 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4745 4746 if ((ifp->if_flags & IFF_RUNNING) == 0) { 4747 ieee80211_free_node(ni); 4748 m_freem(m); 4749 return ENETDOWN; 4750 } 4751 4752 if (params == NULL) { 4753 /* 4754 * Legacy path; interpret frame contents to decide 4755 * precisely how to send the frame. 4756 */ 4757 error = iwn_tx_data(sc, m, ni); 4758 } else { 4759 /* 4760 * Caller supplied explicit parameters to use in 4761 * sending the frame. 4762 */ 4763 error = iwn_tx_data_raw(sc, m, ni, params); 4764 } 4765 if (error != 0) { 4766 /* NB: m is reclaimed on tx failure */ 4767 ieee80211_free_node(ni); 4768 IFNET_STAT_INC(ifp, oerrors, 1); 4769 } 4770 sc->sc_tx_timer = 5; 4771 4772 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4773 4774 return error; 4775 } 4776 4777 static void 4778 iwn_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 4779 { 4780 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 4781 iwn_start_locked(ifp); 4782 } 4783 4784 static void 4785 iwn_start_locked(struct ifnet *ifp) 4786 { 4787 struct iwn_softc *sc = ifp->if_softc; 4788 struct ieee80211_node *ni; 4789 struct mbuf *m; 4790 4791 wlan_assert_serialized(); 4792 4793 if ((ifp->if_flags & IFF_RUNNING) == 0 || 4794 ifq_is_oactive(&ifp->if_snd)) 4795 return; 4796 4797 for (;;) { 4798 if (sc->qfullmsk != 0) { 4799 ifq_set_oactive(&ifp->if_snd); 4800 break; 4801 } 4802 m = ifq_dequeue(&ifp->if_snd); 4803 if (m == NULL) 4804 break; 4805 KKASSERT(M_TRAILINGSPACE(m) >= 0); 4806 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4807 if (iwn_tx_data(sc, m, ni) != 0) { 4808 ieee80211_free_node(ni); 4809 IFNET_STAT_INC(ifp, oerrors, 1); 4810 continue; 4811 } 4812 sc->sc_tx_timer = 5; 4813 } 4814 } 4815 4816 static void 4817 iwn_watchdog_timeout(void *arg) 4818 { 4819 struct iwn_softc *sc = arg; 4820 struct ifnet *ifp = sc->sc_ifp; 4821 struct ieee80211com *ic = ifp->if_l2com; 4822 4823 wlan_serialize_enter(); 4824 4825 KASSERT(ifp->if_flags & IFF_RUNNING, ("not running")); 4826 4827 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4828 4829 if (sc->sc_tx_timer > 0) { 4830 if (--sc->sc_tx_timer == 0) { 4831 if_printf(ifp, "device timeout\n"); 4832 ieee80211_runtask(ic, &sc->sc_reinit_task); 4833 wlan_serialize_exit(); 4834 return; 4835 } 4836 } 4837 callout_reset(&sc->watchdog_to, hz, iwn_watchdog_timeout, sc); 4838 wlan_serialize_exit(); 4839 } 4840 4841 static int 4842 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 4843 { 4844 struct iwn_softc *sc = ifp->if_softc; 4845 struct ieee80211com *ic = ifp->if_l2com; 4846 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4847 struct ifreq *ifr = (struct ifreq *) data; 4848 int error = 0, startall = 0, stop = 0; 4849 4850 wlan_assert_serialized(); 4851 4852 switch (cmd) { 4853 case SIOCGIFADDR: 4854 error = ether_ioctl(ifp, cmd, data); 4855 break; 4856 case SIOCSIFFLAGS: 4857 if (ifp->if_flags & IFF_UP) { 4858 if (!(ifp->if_flags & IFF_RUNNING)) { 4859 iwn_init_locked(sc); 4860 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 4861 startall = 1; 4862 else 4863 stop = 1; 4864 } 4865 } else { 4866 if (ifp->if_flags & IFF_RUNNING) 4867 iwn_stop_locked(sc); 4868 } 4869 if (startall) 4870 ieee80211_start_all(ic); 4871 else if (vap != NULL && stop) 4872 ieee80211_stop(vap); 4873 break; 4874 case SIOCGIFMEDIA: 4875 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 4876 break; 4877 case SIOCGIWNSTATS: 4878 IWN_LOCK(sc); 4879 /* XXX validate permissions/memory/etc? */ 4880 error = copyout(&sc->last_stat, ifr->ifr_data, 4881 sizeof(struct iwn_stats)); 4882 IWN_UNLOCK(sc); 4883 break; 4884 case SIOCZIWNSTATS: 4885 IWN_LOCK(sc); 4886 memset(&sc->last_stat, 0, sizeof(struct iwn_stats)); 4887 IWN_UNLOCK(sc); 4888 error = 0; 4889 break; 4890 default: 4891 error = EINVAL; 4892 break; 4893 } 4894 return error; 4895 } 4896 4897 /* 4898 * Send a command to the firmware. 4899 */ 4900 static int 4901 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 4902 { 4903 struct iwn_tx_ring *ring; 4904 struct iwn_tx_desc *desc; 4905 struct iwn_tx_data *data; 4906 struct iwn_tx_cmd *cmd; 4907 struct mbuf *m; 4908 bus_addr_t paddr; 4909 int totlen, error; 4910 int cmd_queue_num; 4911 4912 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4913 4914 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 4915 cmd_queue_num = IWN_PAN_CMD_QUEUE; 4916 else 4917 cmd_queue_num = IWN_CMD_QUEUE_NUM; 4918 4919 ring = &sc->txq[cmd_queue_num]; 4920 desc = &ring->desc[ring->cur]; 4921 data = &ring->data[ring->cur]; 4922 totlen = 4 + size; 4923 4924 if (size > sizeof cmd->data) { 4925 /* Command is too large to fit in a descriptor. */ 4926 if (totlen > MJUMPAGESIZE) 4927 return EINVAL; 4928 m = m_getjcl(MB_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 4929 if (m == NULL) 4930 return ENOMEM; 4931 cmd = mtod(m, struct iwn_tx_cmd *); 4932 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 4933 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 4934 if (error != 0) { 4935 m_freem(m); 4936 return error; 4937 } 4938 data->m = m; 4939 } else { 4940 cmd = &ring->cmd[ring->cur]; 4941 paddr = data->cmd_paddr; 4942 } 4943 4944 cmd->code = code; 4945 cmd->flags = 0; 4946 cmd->qid = ring->qid; 4947 cmd->idx = ring->cur; 4948 memcpy(cmd->data, buf, size); 4949 4950 desc->nsegs = 1; 4951 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 4952 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 4953 4954 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 4955 __func__, iwn_intr_str(cmd->code), cmd->code, 4956 cmd->flags, cmd->qid, cmd->idx); 4957 4958 if (size > sizeof cmd->data) { 4959 bus_dmamap_sync(ring->data_dmat, data->map, 4960 BUS_DMASYNC_PREWRITE); 4961 } else { 4962 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4963 BUS_DMASYNC_PREWRITE); 4964 } 4965 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4966 BUS_DMASYNC_PREWRITE); 4967 4968 /* Kick command ring. */ 4969 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4970 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4971 4972 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4973 4974 return async ? 0 : zsleep(desc, &wlan_global_serializer, 0, "iwncmd", hz); 4975 } 4976 4977 static int 4978 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 4979 { 4980 struct iwn4965_node_info hnode; 4981 caddr_t src, dst; 4982 4983 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4984 4985 /* 4986 * We use the node structure for 5000 Series internally (it is 4987 * a superset of the one for 4965AGN). We thus copy the common 4988 * fields before sending the command. 4989 */ 4990 src = (caddr_t)node; 4991 dst = (caddr_t)&hnode; 4992 memcpy(dst, src, 48); 4993 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 4994 memcpy(dst + 48, src + 72, 20); 4995 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 4996 } 4997 4998 static int 4999 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5000 { 5001 5002 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5003 5004 /* Direct mapping. */ 5005 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 5006 } 5007 5008 static int 5009 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 5010 { 5011 #define RV(v) ((v) & IEEE80211_RATE_VAL) 5012 struct iwn_node *wn = (void *)ni; 5013 struct ieee80211_rateset *rs; 5014 struct iwn_cmd_link_quality linkq; 5015 uint8_t txant; 5016 int i, rate, txrate; 5017 int is_11n; 5018 5019 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5020 5021 /* Use the first valid TX antenna. */ 5022 txant = IWN_LSB(sc->txchainmask); 5023 5024 memset(&linkq, 0, sizeof linkq); 5025 linkq.id = wn->id; 5026 linkq.antmsk_1stream = txant; 5027 5028 /* 5029 * The '2 stream' setup is a bit .. odd. 5030 * 5031 * For NICs that support only 1 antenna, default to IWN_ANT_AB or 5032 * the firmware panics (eg Intel 5100.) 5033 * 5034 * For NICs that support two antennas, we use ANT_AB. 5035 * 5036 * For NICs that support three antennas, we use the two that 5037 * wasn't the default one. 5038 * 5039 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict 5040 * this to only one antenna. 5041 */ 5042 5043 /* So - if there's no secondary antenna, assume IWN_ANT_AB */ 5044 5045 /* Default - transmit on the other antennas */ 5046 linkq.antmsk_2stream = (sc->txchainmask & ~IWN_LSB(sc->txchainmask)); 5047 5048 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */ 5049 if (linkq.antmsk_2stream == 0) 5050 linkq.antmsk_2stream = IWN_ANT_AB; 5051 5052 /* 5053 * If the NIC is a two-stream TX NIC, configure the TX mask to 5054 * the default chainmask 5055 */ 5056 else if (sc->ntxchains == 2) 5057 linkq.antmsk_2stream = sc->txchainmask; 5058 5059 linkq.ampdu_max = 32; /* XXX negotiated? */ 5060 linkq.ampdu_threshold = 3; 5061 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5062 5063 DPRINTF(sc, IWN_DEBUG_XMIT, 5064 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n", 5065 __func__, 5066 linkq.antmsk_1stream, 5067 linkq.antmsk_2stream, 5068 sc->ntxchains); 5069 5070 /* 5071 * Are we using 11n rates? Ensure the channel is 5072 * 11n _and_ we have some 11n rates, or don't 5073 * try. 5074 */ 5075 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) { 5076 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 5077 is_11n = 1; 5078 } else { 5079 rs = &ni->ni_rates; 5080 is_11n = 0; 5081 } 5082 5083 /* Start at highest available bit-rate. */ 5084 /* 5085 * XXX this is all very dirty! 5086 */ 5087 if (is_11n) 5088 txrate = ni->ni_htrates.rs_nrates - 1; 5089 else 5090 txrate = rs->rs_nrates - 1; 5091 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 5092 uint32_t plcp; 5093 5094 if (is_11n) 5095 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate]; 5096 else 5097 rate = RV(rs->rs_rates[txrate]); 5098 5099 DPRINTF(sc, IWN_DEBUG_XMIT, 5100 "%s: i=%d, txrate=%d, rate=0x%02x\n", 5101 __func__, 5102 i, 5103 txrate, 5104 rate); 5105 5106 /* Do rate -> PLCP config mapping */ 5107 plcp = iwn_rate_to_plcp(sc, ni, rate); 5108 linkq.retry[i] = plcp; 5109 5110 /* 5111 * The mimo field is an index into the table which 5112 * indicates the first index where it and subsequent entries 5113 * will not be using MIMO. 5114 * 5115 * Since we're filling linkq from 0..15 and we're filling 5116 * from the higest MCS rates to the lowest rates, if we 5117 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie, 5118 * the next entry.) That way if the next entry is a non-MIMO 5119 * entry, we're already pointing at it. 5120 */ 5121 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 5122 RV(le32toh(plcp)) > 7) 5123 linkq.mimo = i + 1; 5124 5125 /* Next retry at immediate lower bit-rate. */ 5126 if (txrate > 0) 5127 txrate--; 5128 } 5129 5130 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5131 5132 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 5133 #undef RV 5134 } 5135 5136 /* 5137 * Broadcast node is used to send group-addressed and management frames. 5138 */ 5139 static int 5140 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 5141 { 5142 struct iwn_ops *ops = &sc->ops; 5143 struct ifnet *ifp = sc->sc_ifp; 5144 struct ieee80211com *ic = ifp->if_l2com; 5145 struct iwn_node_info node; 5146 struct iwn_cmd_link_quality linkq; 5147 uint8_t txant; 5148 int i, error; 5149 5150 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5151 5152 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5153 5154 memset(&node, 0, sizeof node); 5155 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 5156 node.id = sc->broadcast_id; 5157 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 5158 if ((error = ops->add_node(sc, &node, async)) != 0) 5159 return error; 5160 5161 /* Use the first valid TX antenna. */ 5162 txant = IWN_LSB(sc->txchainmask); 5163 5164 memset(&linkq, 0, sizeof linkq); 5165 linkq.id = sc->broadcast_id; 5166 linkq.antmsk_1stream = txant; 5167 linkq.antmsk_2stream = IWN_ANT_AB; 5168 linkq.ampdu_max = 64; 5169 linkq.ampdu_threshold = 3; 5170 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5171 5172 /* Use lowest mandatory bit-rate. */ 5173 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 5174 linkq.retry[0] = htole32(0xd); 5175 else 5176 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 5177 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 5178 /* Use same bit-rate for all TX retries. */ 5179 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 5180 linkq.retry[i] = linkq.retry[0]; 5181 } 5182 5183 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5184 5185 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 5186 } 5187 5188 static int 5189 iwn_updateedca(struct ieee80211com *ic) 5190 { 5191 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 5192 struct iwn_softc *sc = ic->ic_ifp->if_softc; 5193 struct iwn_edca_params cmd; 5194 int aci; 5195 5196 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5197 5198 memset(&cmd, 0, sizeof cmd); 5199 cmd.flags = htole32(IWN_EDCA_UPDATE); 5200 for (aci = 0; aci < WME_NUM_AC; aci++) { 5201 const struct wmeParams *ac = 5202 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 5203 cmd.ac[aci].aifsn = ac->wmep_aifsn; 5204 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 5205 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 5206 cmd.ac[aci].txoplimit = 5207 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 5208 } 5209 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5210 5211 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5212 5213 return 0; 5214 #undef IWN_EXP2 5215 } 5216 5217 static void 5218 iwn_update_mcast(struct ifnet *ifp) 5219 { 5220 /* Ignore */ 5221 } 5222 5223 static void 5224 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 5225 { 5226 struct iwn_cmd_led led; 5227 5228 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5229 5230 #if 0 5231 /* XXX don't set LEDs during scan? */ 5232 if (sc->sc_is_scanning) 5233 return; 5234 #endif 5235 5236 /* Clear microcode LED ownership. */ 5237 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 5238 5239 led.which = which; 5240 led.unit = htole32(10000); /* on/off in unit of 100ms */ 5241 led.off = off; 5242 led.on = on; 5243 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 5244 } 5245 5246 /* 5247 * Set the critical temperature at which the firmware will stop the radio 5248 * and notify us. 5249 */ 5250 static int 5251 iwn_set_critical_temp(struct iwn_softc *sc) 5252 { 5253 struct iwn_critical_temp crit; 5254 int32_t temp; 5255 5256 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5257 5258 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 5259 5260 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 5261 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 5262 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 5263 temp = IWN_CTOK(110); 5264 else 5265 temp = 110; 5266 memset(&crit, 0, sizeof crit); 5267 crit.tempR = htole32(temp); 5268 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 5269 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 5270 } 5271 5272 static int 5273 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 5274 { 5275 struct iwn_cmd_timing cmd; 5276 uint64_t val, mod; 5277 5278 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5279 5280 memset(&cmd, 0, sizeof cmd); 5281 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 5282 cmd.bintval = htole16(ni->ni_intval); 5283 cmd.lintval = htole16(10); 5284 5285 /* Compute remaining time until next beacon. */ 5286 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 5287 mod = le64toh(cmd.tstamp) % val; 5288 cmd.binitval = htole32((uint32_t)(val - mod)); 5289 5290 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 5291 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 5292 5293 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 5294 } 5295 5296 static void 5297 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 5298 { 5299 struct ifnet *ifp = sc->sc_ifp; 5300 struct ieee80211com *ic = ifp->if_l2com; 5301 5302 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5303 5304 /* Adjust TX power if need be (delta >= 3 degC). */ 5305 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 5306 __func__, sc->temp, temp); 5307 if (abs(temp - sc->temp) >= 3) { 5308 /* Record temperature of last calibration. */ 5309 sc->temp = temp; 5310 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 5311 } 5312 } 5313 5314 /* 5315 * Set TX power for current channel (each rate has its own power settings). 5316 * This function takes into account the regulatory information from EEPROM, 5317 * the current temperature and the current voltage. 5318 */ 5319 static int 5320 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 5321 int async) 5322 { 5323 /* Fixed-point arithmetic division using a n-bit fractional part. */ 5324 #define fdivround(a, b, n) \ 5325 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 5326 /* Linear interpolation. */ 5327 #define interpolate(x, x1, y1, x2, y2, n) \ 5328 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 5329 5330 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 5331 struct iwn_ucode_info *uc = &sc->ucode_info; 5332 struct iwn4965_cmd_txpower cmd; 5333 struct iwn4965_eeprom_chan_samples *chans; 5334 const uint8_t *rf_gain, *dsp_gain; 5335 int32_t vdiff, tdiff; 5336 int i, c, grp, maxpwr; 5337 uint8_t chan; 5338 5339 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5340 /* Retrieve current channel from last RXON. */ 5341 chan = sc->rxon->chan; 5342 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 5343 chan); 5344 5345 memset(&cmd, 0, sizeof cmd); 5346 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 5347 cmd.chan = chan; 5348 5349 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 5350 maxpwr = sc->maxpwr5GHz; 5351 rf_gain = iwn4965_rf_gain_5ghz; 5352 dsp_gain = iwn4965_dsp_gain_5ghz; 5353 } else { 5354 maxpwr = sc->maxpwr2GHz; 5355 rf_gain = iwn4965_rf_gain_2ghz; 5356 dsp_gain = iwn4965_dsp_gain_2ghz; 5357 } 5358 5359 /* Compute voltage compensation. */ 5360 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 5361 if (vdiff > 0) 5362 vdiff *= 2; 5363 if (abs(vdiff) > 2) 5364 vdiff = 0; 5365 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5366 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 5367 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 5368 5369 /* Get channel attenuation group. */ 5370 if (chan <= 20) /* 1-20 */ 5371 grp = 4; 5372 else if (chan <= 43) /* 34-43 */ 5373 grp = 0; 5374 else if (chan <= 70) /* 44-70 */ 5375 grp = 1; 5376 else if (chan <= 124) /* 71-124 */ 5377 grp = 2; 5378 else /* 125-200 */ 5379 grp = 3; 5380 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5381 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 5382 5383 /* Get channel sub-band. */ 5384 for (i = 0; i < IWN_NBANDS; i++) 5385 if (sc->bands[i].lo != 0 && 5386 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 5387 break; 5388 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 5389 return EINVAL; 5390 chans = sc->bands[i].chans; 5391 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5392 "%s: chan %d sub-band=%d\n", __func__, chan, i); 5393 5394 for (c = 0; c < 2; c++) { 5395 uint8_t power, gain, temp; 5396 int maxchpwr, pwr, ridx, idx; 5397 5398 power = interpolate(chan, 5399 chans[0].num, chans[0].samples[c][1].power, 5400 chans[1].num, chans[1].samples[c][1].power, 1); 5401 gain = interpolate(chan, 5402 chans[0].num, chans[0].samples[c][1].gain, 5403 chans[1].num, chans[1].samples[c][1].gain, 1); 5404 temp = interpolate(chan, 5405 chans[0].num, chans[0].samples[c][1].temp, 5406 chans[1].num, chans[1].samples[c][1].temp, 1); 5407 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5408 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 5409 __func__, c, power, gain, temp); 5410 5411 /* Compute temperature compensation. */ 5412 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 5413 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5414 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 5415 __func__, tdiff, sc->temp, temp); 5416 5417 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 5418 /* Convert dBm to half-dBm. */ 5419 maxchpwr = sc->maxpwr[chan] * 2; 5420 if ((ridx / 8) & 1) 5421 maxchpwr -= 6; /* MIMO 2T: -3dB */ 5422 5423 pwr = maxpwr; 5424 5425 /* Adjust TX power based on rate. */ 5426 if ((ridx % 8) == 5) 5427 pwr -= 15; /* OFDM48: -7.5dB */ 5428 else if ((ridx % 8) == 6) 5429 pwr -= 17; /* OFDM54: -8.5dB */ 5430 else if ((ridx % 8) == 7) 5431 pwr -= 20; /* OFDM60: -10dB */ 5432 else 5433 pwr -= 10; /* Others: -5dB */ 5434 5435 /* Do not exceed channel max TX power. */ 5436 if (pwr > maxchpwr) 5437 pwr = maxchpwr; 5438 5439 idx = gain - (pwr - power) - tdiff - vdiff; 5440 if ((ridx / 8) & 1) /* MIMO */ 5441 idx += (int32_t)le32toh(uc->atten[grp][c]); 5442 5443 if (cmd.band == 0) 5444 idx += 9; /* 5GHz */ 5445 if (ridx == IWN_RIDX_MAX) 5446 idx += 5; /* CCK */ 5447 5448 /* Make sure idx stays in a valid range. */ 5449 if (idx < 0) 5450 idx = 0; 5451 else if (idx > IWN4965_MAX_PWR_INDEX) 5452 idx = IWN4965_MAX_PWR_INDEX; 5453 5454 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5455 "%s: Tx chain %d, rate idx %d: power=%d\n", 5456 __func__, c, ridx, idx); 5457 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 5458 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 5459 } 5460 } 5461 5462 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5463 "%s: set tx power for chan %d\n", __func__, chan); 5464 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 5465 5466 #undef interpolate 5467 #undef fdivround 5468 } 5469 5470 static int 5471 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 5472 int async) 5473 { 5474 struct iwn5000_cmd_txpower cmd; 5475 5476 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5477 5478 /* 5479 * TX power calibration is handled automatically by the firmware 5480 * for 5000 Series. 5481 */ 5482 memset(&cmd, 0, sizeof cmd); 5483 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 5484 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 5485 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 5486 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 5487 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 5488 } 5489 5490 /* 5491 * Retrieve the maximum RSSI (in dBm) among receivers. 5492 */ 5493 static int 5494 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5495 { 5496 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 5497 uint8_t mask, agc; 5498 int rssi; 5499 5500 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5501 5502 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5503 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5504 5505 rssi = 0; 5506 if (mask & IWN_ANT_A) 5507 rssi = MAX(rssi, phy->rssi[0]); 5508 if (mask & IWN_ANT_B) 5509 rssi = MAX(rssi, phy->rssi[2]); 5510 if (mask & IWN_ANT_C) 5511 rssi = MAX(rssi, phy->rssi[4]); 5512 5513 DPRINTF(sc, IWN_DEBUG_RECV, 5514 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 5515 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 5516 rssi - agc - IWN_RSSI_TO_DBM); 5517 return rssi - agc - IWN_RSSI_TO_DBM; 5518 } 5519 5520 static int 5521 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5522 { 5523 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 5524 uint8_t agc; 5525 int rssi; 5526 5527 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5528 5529 agc = (le32toh(phy->agc) >> 9) & 0x7f; 5530 5531 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 5532 le16toh(phy->rssi[1]) & 0xff); 5533 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 5534 5535 DPRINTF(sc, IWN_DEBUG_RECV, 5536 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 5537 phy->rssi[0], phy->rssi[1], phy->rssi[2], 5538 rssi - agc - IWN_RSSI_TO_DBM); 5539 return rssi - agc - IWN_RSSI_TO_DBM; 5540 } 5541 5542 /* 5543 * Retrieve the average noise (in dBm) among receivers. 5544 */ 5545 static int 5546 iwn_get_noise(const struct iwn_rx_general_stats *stats) 5547 { 5548 int i, total, nbant, noise; 5549 5550 total = nbant = 0; 5551 for (i = 0; i < 3; i++) { 5552 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 5553 continue; 5554 total += noise; 5555 nbant++; 5556 } 5557 /* There should be at least one antenna but check anyway. */ 5558 return (nbant == 0) ? -127 : (total / nbant) - 107; 5559 } 5560 5561 /* 5562 * Compute temperature (in degC) from last received statistics. 5563 */ 5564 static int 5565 iwn4965_get_temperature(struct iwn_softc *sc) 5566 { 5567 struct iwn_ucode_info *uc = &sc->ucode_info; 5568 int32_t r1, r2, r3, r4, temp; 5569 5570 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5571 5572 r1 = le32toh(uc->temp[0].chan20MHz); 5573 r2 = le32toh(uc->temp[1].chan20MHz); 5574 r3 = le32toh(uc->temp[2].chan20MHz); 5575 r4 = le32toh(sc->rawtemp); 5576 5577 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 5578 return 0; 5579 5580 /* Sign-extend 23-bit R4 value to 32-bit. */ 5581 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 5582 /* Compute temperature in Kelvin. */ 5583 temp = (259 * (r4 - r2)) / (r3 - r1); 5584 temp = (temp * 97) / 100 + 8; 5585 5586 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 5587 IWN_KTOC(temp)); 5588 return IWN_KTOC(temp); 5589 } 5590 5591 static int 5592 iwn5000_get_temperature(struct iwn_softc *sc) 5593 { 5594 int32_t temp; 5595 5596 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5597 5598 /* 5599 * Temperature is not used by the driver for 5000 Series because 5600 * TX power calibration is handled by firmware. 5601 */ 5602 temp = le32toh(sc->rawtemp); 5603 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 5604 temp = (temp / -5) + sc->temp_off; 5605 temp = IWN_KTOC(temp); 5606 } 5607 return temp; 5608 } 5609 5610 /* 5611 * Initialize sensitivity calibration state machine. 5612 */ 5613 static int 5614 iwn_init_sensitivity(struct iwn_softc *sc) 5615 { 5616 struct iwn_ops *ops = &sc->ops; 5617 struct iwn_calib_state *calib = &sc->calib; 5618 uint32_t flags; 5619 int error; 5620 5621 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5622 5623 /* Reset calibration state machine. */ 5624 memset(calib, 0, sizeof (*calib)); 5625 calib->state = IWN_CALIB_STATE_INIT; 5626 calib->cck_state = IWN_CCK_STATE_HIFA; 5627 /* Set initial correlation values. */ 5628 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 5629 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 5630 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 5631 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 5632 calib->cck_x4 = 125; 5633 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 5634 calib->energy_cck = sc->limits->energy_cck; 5635 5636 /* Write initial sensitivity. */ 5637 if ((error = iwn_send_sensitivity(sc)) != 0) 5638 return error; 5639 5640 /* Write initial gains. */ 5641 if ((error = ops->init_gains(sc)) != 0) 5642 return error; 5643 5644 /* Request statistics at each beacon interval. */ 5645 flags = 0; 5646 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 5647 __func__); 5648 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 5649 } 5650 5651 /* 5652 * Collect noise and RSSI statistics for the first 20 beacons received 5653 * after association and use them to determine connected antennas and 5654 * to set differential gains. 5655 */ 5656 static void 5657 iwn_collect_noise(struct iwn_softc *sc, 5658 const struct iwn_rx_general_stats *stats) 5659 { 5660 struct iwn_ops *ops = &sc->ops; 5661 struct iwn_calib_state *calib = &sc->calib; 5662 struct ifnet *ifp = sc->sc_ifp; 5663 struct ieee80211com *ic = ifp->if_l2com; 5664 uint32_t val; 5665 int i; 5666 5667 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5668 5669 /* Accumulate RSSI and noise for all 3 antennas. */ 5670 for (i = 0; i < 3; i++) { 5671 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 5672 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 5673 } 5674 /* NB: We update differential gains only once after 20 beacons. */ 5675 if (++calib->nbeacons < 20) 5676 return; 5677 5678 /* Determine highest average RSSI. */ 5679 val = MAX(calib->rssi[0], calib->rssi[1]); 5680 val = MAX(calib->rssi[2], val); 5681 5682 /* Determine which antennas are connected. */ 5683 sc->chainmask = sc->rxchainmask; 5684 for (i = 0; i < 3; i++) 5685 if (val - calib->rssi[i] > 15 * 20) 5686 sc->chainmask &= ~(1 << i); 5687 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5688 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 5689 __func__, sc->rxchainmask, sc->chainmask); 5690 5691 /* If none of the TX antennas are connected, keep at least one. */ 5692 if ((sc->chainmask & sc->txchainmask) == 0) 5693 sc->chainmask |= IWN_LSB(sc->txchainmask); 5694 5695 (void)ops->set_gains(sc); 5696 calib->state = IWN_CALIB_STATE_RUN; 5697 5698 #ifdef notyet 5699 /* XXX Disable RX chains with no antennas connected. */ 5700 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 5701 if (sc->sc_is_scanning) 5702 device_printf(sc->sc_dev, 5703 "%s: is_scanning set, before RXON\n", 5704 __func__); 5705 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 5706 #endif 5707 5708 /* Enable power-saving mode if requested by user. */ 5709 if (ic->ic_flags & IEEE80211_F_PMGTON) 5710 (void)iwn_set_pslevel(sc, 0, 3, 1); 5711 5712 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5713 5714 } 5715 5716 static int 5717 iwn4965_init_gains(struct iwn_softc *sc) 5718 { 5719 struct iwn_phy_calib_gain cmd; 5720 5721 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5722 5723 memset(&cmd, 0, sizeof cmd); 5724 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 5725 /* Differential gains initially set to 0 for all 3 antennas. */ 5726 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5727 "%s: setting initial differential gains\n", __func__); 5728 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5729 } 5730 5731 static int 5732 iwn5000_init_gains(struct iwn_softc *sc) 5733 { 5734 struct iwn_phy_calib cmd; 5735 5736 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5737 5738 memset(&cmd, 0, sizeof cmd); 5739 cmd.code = sc->reset_noise_gain; 5740 cmd.ngroups = 1; 5741 cmd.isvalid = 1; 5742 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5743 "%s: setting initial differential gains\n", __func__); 5744 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5745 } 5746 5747 static int 5748 iwn4965_set_gains(struct iwn_softc *sc) 5749 { 5750 struct iwn_calib_state *calib = &sc->calib; 5751 struct iwn_phy_calib_gain cmd; 5752 int i, delta, noise; 5753 5754 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5755 5756 /* Get minimal noise among connected antennas. */ 5757 noise = INT_MAX; /* NB: There's at least one antenna. */ 5758 for (i = 0; i < 3; i++) 5759 if (sc->chainmask & (1 << i)) 5760 noise = MIN(calib->noise[i], noise); 5761 5762 memset(&cmd, 0, sizeof cmd); 5763 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 5764 /* Set differential gains for connected antennas. */ 5765 for (i = 0; i < 3; i++) { 5766 if (sc->chainmask & (1 << i)) { 5767 /* Compute attenuation (in unit of 1.5dB). */ 5768 delta = (noise - (int32_t)calib->noise[i]) / 30; 5769 /* NB: delta <= 0 */ 5770 /* Limit to [-4.5dB,0]. */ 5771 cmd.gain[i] = MIN(abs(delta), 3); 5772 if (delta < 0) 5773 cmd.gain[i] |= 1 << 2; /* sign bit */ 5774 } 5775 } 5776 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5777 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 5778 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 5779 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5780 } 5781 5782 static int 5783 iwn5000_set_gains(struct iwn_softc *sc) 5784 { 5785 struct iwn_calib_state *calib = &sc->calib; 5786 struct iwn_phy_calib_gain cmd; 5787 int i, ant, div, delta; 5788 5789 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5790 5791 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 5792 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 5793 5794 memset(&cmd, 0, sizeof cmd); 5795 cmd.code = sc->noise_gain; 5796 cmd.ngroups = 1; 5797 cmd.isvalid = 1; 5798 /* Get first available RX antenna as referential. */ 5799 ant = IWN_LSB(sc->rxchainmask); 5800 /* Set differential gains for other antennas. */ 5801 for (i = ant + 1; i < 3; i++) { 5802 if (sc->chainmask & (1 << i)) { 5803 /* The delta is relative to antenna "ant". */ 5804 delta = ((int32_t)calib->noise[ant] - 5805 (int32_t)calib->noise[i]) / div; 5806 /* Limit to [-4.5dB,+4.5dB]. */ 5807 cmd.gain[i - 1] = MIN(abs(delta), 3); 5808 if (delta < 0) 5809 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 5810 } 5811 } 5812 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5813 "setting differential gains Ant B/C: %x/%x (%x)\n", 5814 cmd.gain[0], cmd.gain[1], sc->chainmask); 5815 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5816 } 5817 5818 /* 5819 * Tune RF RX sensitivity based on the number of false alarms detected 5820 * during the last beacon period. 5821 */ 5822 static void 5823 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 5824 { 5825 #define inc(val, inc, max) \ 5826 if ((val) < (max)) { \ 5827 if ((val) < (max) - (inc)) \ 5828 (val) += (inc); \ 5829 else \ 5830 (val) = (max); \ 5831 needs_update = 1; \ 5832 } 5833 #define dec(val, dec, min) \ 5834 if ((val) > (min)) { \ 5835 if ((val) > (min) + (dec)) \ 5836 (val) -= (dec); \ 5837 else \ 5838 (val) = (min); \ 5839 needs_update = 1; \ 5840 } 5841 5842 const struct iwn_sensitivity_limits *limits = sc->limits; 5843 struct iwn_calib_state *calib = &sc->calib; 5844 uint32_t val, rxena, fa; 5845 uint32_t energy[3], energy_min; 5846 uint8_t noise[3], noise_ref; 5847 int i, needs_update = 0; 5848 5849 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5850 5851 /* Check that we've been enabled long enough. */ 5852 if ((rxena = le32toh(stats->general.load)) == 0){ 5853 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 5854 return; 5855 } 5856 5857 /* Compute number of false alarms since last call for OFDM. */ 5858 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 5859 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 5860 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 5861 5862 if (fa > 50 * rxena) { 5863 /* High false alarm count, decrease sensitivity. */ 5864 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5865 "%s: OFDM high false alarm count: %u\n", __func__, fa); 5866 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 5867 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 5868 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 5869 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 5870 5871 } else if (fa < 5 * rxena) { 5872 /* Low false alarm count, increase sensitivity. */ 5873 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5874 "%s: OFDM low false alarm count: %u\n", __func__, fa); 5875 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 5876 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 5877 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 5878 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 5879 } 5880 5881 /* Compute maximum noise among 3 receivers. */ 5882 for (i = 0; i < 3; i++) 5883 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 5884 val = MAX(noise[0], noise[1]); 5885 val = MAX(noise[2], val); 5886 /* Insert it into our samples table. */ 5887 calib->noise_samples[calib->cur_noise_sample] = val; 5888 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 5889 5890 /* Compute maximum noise among last 20 samples. */ 5891 noise_ref = calib->noise_samples[0]; 5892 for (i = 1; i < 20; i++) 5893 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 5894 5895 /* Compute maximum energy among 3 receivers. */ 5896 for (i = 0; i < 3; i++) 5897 energy[i] = le32toh(stats->general.energy[i]); 5898 val = MIN(energy[0], energy[1]); 5899 val = MIN(energy[2], val); 5900 /* Insert it into our samples table. */ 5901 calib->energy_samples[calib->cur_energy_sample] = val; 5902 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 5903 5904 /* Compute minimum energy among last 10 samples. */ 5905 energy_min = calib->energy_samples[0]; 5906 for (i = 1; i < 10; i++) 5907 energy_min = MAX(energy_min, calib->energy_samples[i]); 5908 energy_min += 6; 5909 5910 /* Compute number of false alarms since last call for CCK. */ 5911 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 5912 fa += le32toh(stats->cck.fa) - calib->fa_cck; 5913 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 5914 5915 if (fa > 50 * rxena) { 5916 /* High false alarm count, decrease sensitivity. */ 5917 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5918 "%s: CCK high false alarm count: %u\n", __func__, fa); 5919 calib->cck_state = IWN_CCK_STATE_HIFA; 5920 calib->low_fa = 0; 5921 5922 if (calib->cck_x4 > 160) { 5923 calib->noise_ref = noise_ref; 5924 if (calib->energy_cck > 2) 5925 dec(calib->energy_cck, 2, energy_min); 5926 } 5927 if (calib->cck_x4 < 160) { 5928 calib->cck_x4 = 161; 5929 needs_update = 1; 5930 } else 5931 inc(calib->cck_x4, 3, limits->max_cck_x4); 5932 5933 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 5934 5935 } else if (fa < 5 * rxena) { 5936 /* Low false alarm count, increase sensitivity. */ 5937 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5938 "%s: CCK low false alarm count: %u\n", __func__, fa); 5939 calib->cck_state = IWN_CCK_STATE_LOFA; 5940 calib->low_fa++; 5941 5942 if (calib->cck_state != IWN_CCK_STATE_INIT && 5943 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 5944 calib->low_fa > 100)) { 5945 inc(calib->energy_cck, 2, limits->min_energy_cck); 5946 dec(calib->cck_x4, 3, limits->min_cck_x4); 5947 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 5948 } 5949 } else { 5950 /* Not worth to increase or decrease sensitivity. */ 5951 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5952 "%s: CCK normal false alarm count: %u\n", __func__, fa); 5953 calib->low_fa = 0; 5954 calib->noise_ref = noise_ref; 5955 5956 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 5957 /* Previous interval had many false alarms. */ 5958 dec(calib->energy_cck, 8, energy_min); 5959 } 5960 calib->cck_state = IWN_CCK_STATE_INIT; 5961 } 5962 5963 if (needs_update) 5964 (void)iwn_send_sensitivity(sc); 5965 5966 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5967 5968 #undef dec 5969 #undef inc 5970 } 5971 5972 static int 5973 iwn_send_sensitivity(struct iwn_softc *sc) 5974 { 5975 struct iwn_calib_state *calib = &sc->calib; 5976 struct iwn_enhanced_sensitivity_cmd cmd; 5977 int len; 5978 5979 memset(&cmd, 0, sizeof cmd); 5980 len = sizeof (struct iwn_sensitivity_cmd); 5981 cmd.which = IWN_SENSITIVITY_WORKTBL; 5982 /* OFDM modulation. */ 5983 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 5984 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 5985 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 5986 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 5987 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 5988 cmd.energy_ofdm_th = htole16(62); 5989 /* CCK modulation. */ 5990 cmd.corr_cck_x4 = htole16(calib->cck_x4); 5991 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 5992 cmd.energy_cck = htole16(calib->energy_cck); 5993 /* Barker modulation: use default values. */ 5994 cmd.corr_barker = htole16(190); 5995 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 5996 5997 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5998 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 5999 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 6000 calib->ofdm_mrc_x4, calib->cck_x4, 6001 calib->cck_mrc_x4, calib->energy_cck); 6002 6003 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 6004 goto send; 6005 /* Enhanced sensitivity settings. */ 6006 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 6007 cmd.ofdm_det_slope_mrc = htole16(668); 6008 cmd.ofdm_det_icept_mrc = htole16(4); 6009 cmd.ofdm_det_slope = htole16(486); 6010 cmd.ofdm_det_icept = htole16(37); 6011 cmd.cck_det_slope_mrc = htole16(853); 6012 cmd.cck_det_icept_mrc = htole16(4); 6013 cmd.cck_det_slope = htole16(476); 6014 cmd.cck_det_icept = htole16(99); 6015 send: 6016 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 6017 } 6018 6019 /* 6020 * Look at the increase of PLCP errors over time; if it exceeds 6021 * a programmed threshold then trigger an RF retune. 6022 */ 6023 static void 6024 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs) 6025 { 6026 int32_t delta_ofdm, delta_ht, delta_cck; 6027 struct iwn_calib_state *calib = &sc->calib; 6028 int delta_ticks, cur_ticks; 6029 int delta_msec; 6030 int thresh; 6031 6032 /* 6033 * Calculate the difference between the current and 6034 * previous statistics. 6035 */ 6036 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck; 6037 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6038 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht; 6039 6040 /* 6041 * Calculate the delta in time between successive statistics 6042 * messages. Yes, it can roll over; so we make sure that 6043 * this doesn't happen. 6044 * 6045 * XXX go figure out what to do about rollover 6046 * XXX go figure out what to do if ticks rolls over to -ve instead! 6047 * XXX go stab signed integer overflow undefined-ness in the face. 6048 */ 6049 cur_ticks = ticks; 6050 delta_ticks = cur_ticks - sc->last_calib_ticks; 6051 6052 /* 6053 * If any are negative, then the firmware likely reset; so just 6054 * bail. We'll pick this up next time. 6055 */ 6056 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0) 6057 return; 6058 6059 /* 6060 * delta_ticks is in ticks; we need to convert it up to milliseconds 6061 * so we can do some useful math with it. 6062 */ 6063 delta_msec = ticks_to_msecs(delta_ticks); 6064 6065 /* 6066 * Calculate what our threshold is given the current delta_msec. 6067 */ 6068 thresh = sc->base_params->plcp_err_threshold * delta_msec; 6069 6070 DPRINTF(sc, IWN_DEBUG_STATE, 6071 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n", 6072 __func__, 6073 delta_msec, 6074 delta_cck, 6075 delta_ofdm, 6076 delta_ht, 6077 (delta_msec + delta_cck + delta_ofdm + delta_ht), 6078 thresh); 6079 6080 /* 6081 * If we need a retune, then schedule a single channel scan 6082 * to a channel that isn't the currently active one! 6083 * 6084 * The math from linux iwlwifi: 6085 * 6086 * if ((delta * 100 / msecs) > threshold) 6087 */ 6088 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) { 6089 DPRINTF(sc, IWN_DEBUG_ANY, 6090 "%s: PLCP error threshold raw (%d) comparison (%d) " 6091 "over limit (%d); retune!\n", 6092 __func__, 6093 (delta_cck + delta_ofdm + delta_ht), 6094 (delta_cck + delta_ofdm + delta_ht) * 100, 6095 thresh); 6096 } 6097 } 6098 6099 /* 6100 * Set STA mode power saving level (between 0 and 5). 6101 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 6102 */ 6103 static int 6104 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 6105 { 6106 struct iwn_pmgt_cmd cmd; 6107 const struct iwn_pmgt *pmgt; 6108 uint32_t max, skip_dtim; 6109 uint32_t reg; 6110 int i; 6111 6112 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 6113 "%s: dtim=%d, level=%d, async=%d\n", 6114 __func__, 6115 dtim, 6116 level, 6117 async); 6118 6119 /* Select which PS parameters to use. */ 6120 if (dtim <= 2) 6121 pmgt = &iwn_pmgt[0][level]; 6122 else if (dtim <= 10) 6123 pmgt = &iwn_pmgt[1][level]; 6124 else 6125 pmgt = &iwn_pmgt[2][level]; 6126 6127 memset(&cmd, 0, sizeof cmd); 6128 if (level != 0) /* not CAM */ 6129 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 6130 if (level == 5) 6131 cmd.flags |= htole16(IWN_PS_FAST_PD); 6132 /* Retrieve PCIe Active State Power Management (ASPM). */ 6133 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 6134 if (!(reg & 0x1)) /* L0s Entry disabled. */ 6135 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6136 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 6137 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 6138 6139 if (dtim == 0) { 6140 dtim = 1; 6141 skip_dtim = 0; 6142 } else 6143 skip_dtim = pmgt->skip_dtim; 6144 if (skip_dtim != 0) { 6145 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 6146 max = pmgt->intval[4]; 6147 if (max == (uint32_t)-1) 6148 max = dtim * (skip_dtim + 1); 6149 else if (max > dtim) 6150 max = (max / dtim) * dtim; 6151 } else 6152 max = dtim; 6153 for (i = 0; i < 5; i++) 6154 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 6155 6156 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 6157 level); 6158 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 6159 } 6160 6161 static int 6162 iwn_send_btcoex(struct iwn_softc *sc) 6163 { 6164 struct iwn_bluetooth cmd; 6165 6166 memset(&cmd, 0, sizeof cmd); 6167 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 6168 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 6169 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 6170 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 6171 __func__); 6172 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 6173 } 6174 6175 static int 6176 iwn_send_advanced_btcoex(struct iwn_softc *sc) 6177 { 6178 static const uint32_t btcoex_3wire[12] = { 6179 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 6180 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 6181 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 6182 }; 6183 struct iwn6000_btcoex_config btconfig; 6184 struct iwn2000_btcoex_config btconfig2k; 6185 struct iwn_btcoex_priotable btprio; 6186 struct iwn_btcoex_prot btprot; 6187 int error, i; 6188 uint8_t flags; 6189 6190 memset(&btconfig, 0, sizeof btconfig); 6191 memset(&btconfig2k, 0, sizeof btconfig2k); 6192 6193 flags = IWN_BT_FLAG_COEX6000_MODE_3W << 6194 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2 6195 6196 if (sc->base_params->bt_sco_disable) 6197 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6198 else 6199 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6200 6201 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION; 6202 6203 /* Default flags result is 145 as old value */ 6204 6205 /* 6206 * Flags value has to be review. Values must change if we 6207 * which to disable it 6208 */ 6209 if (sc->base_params->bt_session_2) { 6210 btconfig2k.flags = flags; 6211 btconfig2k.max_kill = 5; 6212 btconfig2k.bt3_t7_timer = 1; 6213 btconfig2k.kill_ack = htole32(0xffff0000); 6214 btconfig2k.kill_cts = htole32(0xffff0000); 6215 btconfig2k.sample_time = 2; 6216 btconfig2k.bt3_t2_timer = 0xc; 6217 6218 for (i = 0; i < 12; i++) 6219 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]); 6220 btconfig2k.valid = htole16(0xff); 6221 btconfig2k.prio_boost = htole32(0xf0); 6222 DPRINTF(sc, IWN_DEBUG_RESET, 6223 "%s: configuring advanced bluetooth coexistence" 6224 " session 2, flags : 0x%x\n", 6225 __func__, 6226 flags); 6227 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k, 6228 sizeof(btconfig2k), 1); 6229 } else { 6230 btconfig.flags = flags; 6231 btconfig.max_kill = 5; 6232 btconfig.bt3_t7_timer = 1; 6233 btconfig.kill_ack = htole32(0xffff0000); 6234 btconfig.kill_cts = htole32(0xffff0000); 6235 btconfig.sample_time = 2; 6236 btconfig.bt3_t2_timer = 0xc; 6237 6238 for (i = 0; i < 12; i++) 6239 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 6240 btconfig.valid = htole16(0xff); 6241 btconfig.prio_boost = 0xf0; 6242 DPRINTF(sc, IWN_DEBUG_RESET, 6243 "%s: configuring advanced bluetooth coexistence," 6244 " flags : 0x%x\n", 6245 __func__, 6246 flags); 6247 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 6248 sizeof(btconfig), 1); 6249 } 6250 6251 if (error != 0) 6252 return error; 6253 6254 memset(&btprio, 0, sizeof btprio); 6255 btprio.calib_init1 = 0x6; 6256 btprio.calib_init2 = 0x7; 6257 btprio.calib_periodic_low1 = 0x2; 6258 btprio.calib_periodic_low2 = 0x3; 6259 btprio.calib_periodic_high1 = 0x4; 6260 btprio.calib_periodic_high2 = 0x5; 6261 btprio.dtim = 0x6; 6262 btprio.scan52 = 0x8; 6263 btprio.scan24 = 0xa; 6264 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 6265 1); 6266 if (error != 0) 6267 return error; 6268 6269 /* Force BT state machine change. */ 6270 memset(&btprot, 0, sizeof btprot); 6271 btprot.open = 1; 6272 btprot.type = 1; 6273 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6274 if (error != 0) 6275 return error; 6276 btprot.open = 0; 6277 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6278 } 6279 6280 static int 6281 iwn5000_runtime_calib(struct iwn_softc *sc) 6282 { 6283 struct iwn5000_calib_config cmd; 6284 6285 memset(&cmd, 0, sizeof cmd); 6286 cmd.ucode.once.enable = 0xffffffff; 6287 cmd.ucode.once.start = IWN5000_CALIB_DC; 6288 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6289 "%s: configuring runtime calibration\n", __func__); 6290 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 6291 } 6292 6293 static int 6294 iwn_config(struct iwn_softc *sc) 6295 { 6296 struct iwn_ops *ops = &sc->ops; 6297 struct ifnet *ifp = sc->sc_ifp; 6298 struct ieee80211com *ic = ifp->if_l2com; 6299 uint32_t txmask; 6300 uint16_t rxchain; 6301 int error; 6302 6303 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6304 6305 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) 6306 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) { 6307 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are" 6308 " exclusive each together. Review NIC config file. Conf" 6309 " : 0x%08x Flags : 0x%08x \n", __func__, 6310 sc->base_params->calib_need, 6311 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET | 6312 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)); 6313 return (EINVAL); 6314 } 6315 6316 /* Compute temperature calib if needed. Will be send by send calib */ 6317 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) { 6318 error = iwn5000_temp_offset_calib(sc); 6319 if (error != 0) { 6320 device_printf(sc->sc_dev, 6321 "%s: could not set temperature offset\n", __func__); 6322 return (error); 6323 } 6324 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 6325 error = iwn5000_temp_offset_calibv2(sc); 6326 if (error != 0) { 6327 device_printf(sc->sc_dev, 6328 "%s: could not compute temperature offset v2\n", 6329 __func__); 6330 return (error); 6331 } 6332 } 6333 6334 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6335 /* Configure runtime DC calibration. */ 6336 error = iwn5000_runtime_calib(sc); 6337 if (error != 0) { 6338 device_printf(sc->sc_dev, 6339 "%s: could not configure runtime calibration\n", 6340 __func__); 6341 return error; 6342 } 6343 } 6344 6345 /* Configure valid TX chains for >=5000 Series. */ 6346 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 6347 txmask = htole32(sc->txchainmask); 6348 DPRINTF(sc, IWN_DEBUG_RESET, 6349 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 6350 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 6351 sizeof txmask, 0); 6352 if (error != 0) { 6353 device_printf(sc->sc_dev, 6354 "%s: could not configure valid TX chains, " 6355 "error %d\n", __func__, error); 6356 return error; 6357 } 6358 } 6359 6360 /* Configure bluetooth coexistence. */ 6361 error = 0; 6362 6363 /* Configure bluetooth coexistence if needed. */ 6364 if (sc->base_params->bt_mode == IWN_BT_ADVANCED) 6365 error = iwn_send_advanced_btcoex(sc); 6366 if (sc->base_params->bt_mode == IWN_BT_SIMPLE) 6367 error = iwn_send_btcoex(sc); 6368 6369 if (error != 0) { 6370 device_printf(sc->sc_dev, 6371 "%s: could not configure bluetooth coexistence, error %d\n", 6372 __func__, error); 6373 return error; 6374 } 6375 6376 /* Set mode, channel, RX filter and enable RX. */ 6377 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6378 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 6379 IEEE80211_ADDR_COPY(sc->rxon->myaddr, IF_LLADDR(ifp)); 6380 IEEE80211_ADDR_COPY(sc->rxon->wlap, IF_LLADDR(ifp)); 6381 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 6382 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6383 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 6384 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6385 switch (ic->ic_opmode) { 6386 case IEEE80211_M_STA: 6387 sc->rxon->mode = IWN_MODE_STA; 6388 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 6389 break; 6390 case IEEE80211_M_MONITOR: 6391 sc->rxon->mode = IWN_MODE_MONITOR; 6392 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST | 6393 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 6394 break; 6395 default: 6396 /* Should not get there. */ 6397 break; 6398 } 6399 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 6400 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 6401 sc->rxon->ht_single_mask = 0xff; 6402 sc->rxon->ht_dual_mask = 0xff; 6403 sc->rxon->ht_triple_mask = 0xff; 6404 rxchain = 6405 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6406 IWN_RXCHAIN_MIMO_COUNT(2) | 6407 IWN_RXCHAIN_IDLE_COUNT(2); 6408 sc->rxon->rxchain = htole16(rxchain); 6409 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 6410 if (sc->sc_is_scanning) 6411 device_printf(sc->sc_dev, 6412 "%s: is_scanning set, before RXON\n", 6413 __func__); 6414 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 0); 6415 if (error != 0) { 6416 device_printf(sc->sc_dev, "%s: RXON command failed\n", 6417 __func__); 6418 return error; 6419 } 6420 6421 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 6422 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 6423 __func__); 6424 return error; 6425 } 6426 6427 /* Configuration has changed, set TX power accordingly. */ 6428 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) { 6429 device_printf(sc->sc_dev, "%s: could not set TX power\n", 6430 __func__); 6431 return error; 6432 } 6433 6434 if ((error = iwn_set_critical_temp(sc)) != 0) { 6435 device_printf(sc->sc_dev, 6436 "%s: could not set critical temperature\n", __func__); 6437 return error; 6438 } 6439 6440 /* Set power saving level to CAM during initialization. */ 6441 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 6442 device_printf(sc->sc_dev, 6443 "%s: could not set power saving level\n", __func__); 6444 return error; 6445 } 6446 6447 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6448 6449 return 0; 6450 } 6451 6452 /* 6453 * Add an ssid element to a frame. 6454 */ 6455 static uint8_t * 6456 ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len) 6457 { 6458 *frm++ = IEEE80211_ELEMID_SSID; 6459 *frm++ = len; 6460 memcpy(frm, ssid, len); 6461 return frm + len; 6462 } 6463 6464 static uint16_t 6465 iwn_get_active_dwell_time(struct iwn_softc *sc, 6466 struct ieee80211_channel *c, uint8_t n_probes) 6467 { 6468 /* No channel? Default to 2GHz settings */ 6469 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6470 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 6471 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 6472 } 6473 6474 /* 5GHz dwell time */ 6475 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 6476 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 6477 } 6478 6479 /* 6480 * Limit the total dwell time to 85% of the beacon interval. 6481 * 6482 * Returns the dwell time in milliseconds. 6483 */ 6484 static uint16_t 6485 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 6486 { 6487 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 6488 struct ieee80211vap *vap = NULL; 6489 int bintval = 0; 6490 6491 /* bintval is in TU (1.024mS) */ 6492 if (! TAILQ_EMPTY(&ic->ic_vaps)) { 6493 vap = TAILQ_FIRST(&ic->ic_vaps); 6494 bintval = vap->iv_bss->ni_intval; 6495 } 6496 6497 /* 6498 * If it's non-zero, we should calculate the minimum of 6499 * it and the DWELL_BASE. 6500 * 6501 * XXX Yes, the math should take into account that bintval 6502 * is 1.024mS, not 1mS.. 6503 */ 6504 if (bintval > 0) { 6505 DPRINTF(sc, IWN_DEBUG_SCAN, 6506 "%s: bintval=%d\n", 6507 __func__, 6508 bintval); 6509 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 6510 } 6511 6512 /* No association context? Default */ 6513 return (IWN_PASSIVE_DWELL_BASE); 6514 } 6515 6516 static uint16_t 6517 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c) 6518 { 6519 uint16_t passive; 6520 6521 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6522 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 6523 } else { 6524 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 6525 } 6526 6527 /* Clamp to the beacon interval if we're associated */ 6528 return (iwn_limit_dwell(sc, passive)); 6529 } 6530 6531 static int 6532 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap, 6533 struct ieee80211_scan_state *ss, struct ieee80211_channel *c) 6534 { 6535 struct ifnet *ifp = sc->sc_ifp; 6536 struct ieee80211com *ic = ifp->if_l2com; 6537 struct ieee80211_node *ni = vap->iv_bss; 6538 struct iwn_scan_hdr *hdr; 6539 struct iwn_cmd_data *tx; 6540 struct iwn_scan_essid *essid; 6541 struct iwn_scan_chan *chan; 6542 struct ieee80211_frame *wh; 6543 struct ieee80211_rateset *rs; 6544 uint8_t *buf, *frm; 6545 uint16_t rxchain; 6546 uint8_t txant; 6547 int buflen, error; 6548 int is_active; 6549 uint16_t dwell_active, dwell_passive; 6550 uint32_t extra, scan_service_time; 6551 6552 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6553 6554 /* 6555 * We are absolutely not allowed to send a scan command when another 6556 * scan command is pending. 6557 */ 6558 if (sc->sc_is_scanning) { 6559 device_printf(sc->sc_dev, "%s: called whilst scanning!\n", 6560 __func__); 6561 return (EAGAIN); 6562 } 6563 6564 /* Assign the scan channel */ 6565 c = ic->ic_curchan; 6566 6567 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6568 buf = kmalloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_INTWAIT | M_ZERO); 6569 hdr = (struct iwn_scan_hdr *)buf; 6570 /* 6571 * Move to the next channel if no frames are received within 10ms 6572 * after sending the probe request. 6573 */ 6574 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 6575 hdr->quiet_threshold = htole16(1); /* min # of packets */ 6576 /* 6577 * Max needs to be greater than active and passive and quiet! 6578 * It's also in microseconds! 6579 */ 6580 hdr->max_svc = htole32(250 * 1024); 6581 6582 /* 6583 * Reset scan: interval=100 6584 * Normal scan: interval=becaon interval 6585 * suspend_time: 100 (TU) 6586 * 6587 */ 6588 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22; 6589 //scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024); 6590 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */ 6591 hdr->pause_svc = htole32(scan_service_time); 6592 6593 /* Select antennas for scanning. */ 6594 rxchain = 6595 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6596 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 6597 IWN_RXCHAIN_DRIVER_FORCE; 6598 if (IEEE80211_IS_CHAN_A(c) && 6599 sc->hw_type == IWN_HW_REV_TYPE_4965) { 6600 /* Ant A must be avoided in 5GHz because of an HW bug. */ 6601 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 6602 } else /* Use all available RX antennas. */ 6603 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 6604 hdr->rxchain = htole16(rxchain); 6605 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 6606 6607 tx = (struct iwn_cmd_data *)(hdr + 1); 6608 tx->flags = htole32(IWN_TX_AUTO_SEQ); 6609 tx->id = sc->broadcast_id; 6610 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 6611 6612 if (IEEE80211_IS_CHAN_5GHZ(c)) { 6613 /* Send probe requests at 6Mbps. */ 6614 tx->rate = htole32(0xd); 6615 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 6616 } else { 6617 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 6618 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 6619 sc->rxon->associd && sc->rxon->chan > 14) 6620 tx->rate = htole32(0xd); 6621 else { 6622 /* Send probe requests at 1Mbps. */ 6623 tx->rate = htole32(10 | IWN_RFLAG_CCK); 6624 } 6625 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 6626 } 6627 /* Use the first valid TX antenna. */ 6628 txant = IWN_LSB(sc->txchainmask); 6629 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 6630 6631 /* 6632 * Only do active scanning if we're announcing a probe request 6633 * for a given SSID (or more, if we ever add it to the driver.) 6634 */ 6635 is_active = 0; 6636 6637 /* 6638 * If we're scanning for a specific SSID, add it to the command. 6639 * 6640 * XXX maybe look at adding support for scanning multiple SSIDs? 6641 */ 6642 essid = (struct iwn_scan_essid *)(tx + 1); 6643 if (ss != NULL) { 6644 if (ss->ss_ssid[0].len != 0) { 6645 essid[0].id = IEEE80211_ELEMID_SSID; 6646 essid[0].len = ss->ss_ssid[0].len; 6647 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 6648 } 6649 6650 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n", 6651 __func__, 6652 ss->ss_ssid[0].len, 6653 ss->ss_ssid[0].len, 6654 ss->ss_ssid[0].ssid); 6655 6656 if (ss->ss_nssid > 0) 6657 is_active = 1; 6658 } 6659 6660 /* 6661 * Build a probe request frame. Most of the following code is a 6662 * copy & paste of what is done in net80211. 6663 */ 6664 wh = (struct ieee80211_frame *)(essid + 20); 6665 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 6666 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 6667 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 6668 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 6669 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 6670 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 6671 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 6672 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 6673 6674 frm = (uint8_t *)(wh + 1); 6675 frm = ieee80211_add_ssid(frm, NULL, 0); 6676 frm = ieee80211_add_rates(frm, rs); 6677 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 6678 frm = ieee80211_add_xrates(frm, rs); 6679 if (ic->ic_htcaps & IEEE80211_HTC_HT) 6680 frm = ieee80211_add_htcap(frm, ni); 6681 6682 /* Set length of probe request. */ 6683 tx->len = htole16(frm - (uint8_t *)wh); 6684 6685 /* 6686 * If active scanning is requested but a certain channel is 6687 * marked passive, we can do active scanning if we detect 6688 * transmissions. 6689 * 6690 * There is an issue with some firmware versions that triggers 6691 * a sysassert on a "good CRC threshold" of zero (== disabled), 6692 * on a radar channel even though this means that we should NOT 6693 * send probes. 6694 * 6695 * The "good CRC threshold" is the number of frames that we 6696 * need to receive during our dwell time on a channel before 6697 * sending out probes -- setting this to a huge value will 6698 * mean we never reach it, but at the same time work around 6699 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 6700 * here instead of IWL_GOOD_CRC_TH_DISABLED. 6701 * 6702 * This was fixed in later versions along with some other 6703 * scan changes, and the threshold behaves as a flag in those 6704 * versions. 6705 */ 6706 6707 /* 6708 * If we're doing active scanning, set the crc_threshold 6709 * to a suitable value. This is different to active veruss 6710 * passive scanning depending upon the channel flags; the 6711 * firmware will obey that particular check for us. 6712 */ 6713 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 6714 hdr->crc_threshold = is_active ? 6715 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 6716 else 6717 hdr->crc_threshold = is_active ? 6718 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 6719 6720 chan = (struct iwn_scan_chan *)frm; 6721 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 6722 chan->flags = 0; 6723 if (ss->ss_nssid > 0) 6724 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 6725 chan->dsp_gain = 0x6e; 6726 6727 /* 6728 * Set the passive/active flag depending upon the channel mode. 6729 * XXX TODO: take the is_active flag into account as well? 6730 */ 6731 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 6732 chan->flags |= htole32(IWN_CHAN_PASSIVE); 6733 else 6734 chan->flags |= htole32(IWN_CHAN_ACTIVE); 6735 6736 /* 6737 * Calculate the active/passive dwell times. 6738 */ 6739 6740 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid); 6741 dwell_passive = iwn_get_passive_dwell_time(sc, c); 6742 6743 /* Make sure they're valid */ 6744 if (dwell_passive <= dwell_active) 6745 dwell_passive = dwell_active + 1; 6746 6747 chan->active = htole16(dwell_active); 6748 chan->passive = htole16(dwell_passive); 6749 6750 if (IEEE80211_IS_CHAN_5GHZ(c) && 6751 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 6752 chan->rf_gain = 0x3b; 6753 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 6754 chan->rf_gain = 0x3b; 6755 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 6756 chan->rf_gain = 0x28; 6757 } else { 6758 chan->rf_gain = 0x28; 6759 } 6760 6761 DPRINTF(sc, IWN_DEBUG_STATE, 6762 "%s: chan %u flags 0x%x rf_gain 0x%x " 6763 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x " 6764 "isactive=%d numssid=%d\n", __func__, 6765 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 6766 dwell_active, dwell_passive, scan_service_time, 6767 hdr->crc_threshold, is_active, ss->ss_nssid); 6768 6769 hdr->nchan++; 6770 chan++; 6771 buflen = (uint8_t *)chan - buf; 6772 hdr->len = htole16(buflen); 6773 6774 if (sc->sc_is_scanning) { 6775 device_printf(sc->sc_dev, 6776 "%s: called with is_scanning set!\n", 6777 __func__); 6778 } 6779 sc->sc_is_scanning = 1; 6780 6781 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 6782 hdr->nchan); 6783 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 6784 kfree(buf, M_DEVBUF); 6785 6786 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6787 6788 return error; 6789 } 6790 6791 static int 6792 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 6793 { 6794 struct iwn_ops *ops = &sc->ops; 6795 struct ifnet *ifp = sc->sc_ifp; 6796 struct ieee80211com *ic = ifp->if_l2com; 6797 struct ieee80211_node *ni = vap->iv_bss; 6798 int error; 6799 6800 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6801 6802 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6803 /* Update adapter configuration. */ 6804 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 6805 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 6806 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6807 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 6808 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6809 if (ic->ic_flags & IEEE80211_F_SHSLOT) 6810 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 6811 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 6812 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 6813 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 6814 sc->rxon->cck_mask = 0; 6815 sc->rxon->ofdm_mask = 0x15; 6816 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 6817 sc->rxon->cck_mask = 0x03; 6818 sc->rxon->ofdm_mask = 0; 6819 } else { 6820 /* Assume 802.11b/g. */ 6821 sc->rxon->cck_mask = 0x03; 6822 sc->rxon->ofdm_mask = 0x15; 6823 } 6824 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 6825 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 6826 sc->rxon->ofdm_mask); 6827 if (sc->sc_is_scanning) 6828 device_printf(sc->sc_dev, 6829 "%s: is_scanning set, before RXON\n", 6830 __func__); 6831 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 6832 if (error != 0) { 6833 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 6834 __func__, error); 6835 return error; 6836 } 6837 6838 /* Configuration has changed, set TX power accordingly. */ 6839 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 6840 device_printf(sc->sc_dev, 6841 "%s: could not set TX power, error %d\n", __func__, error); 6842 return error; 6843 } 6844 /* 6845 * Reconfiguring RXON clears the firmware nodes table so we must 6846 * add the broadcast node again. 6847 */ 6848 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 6849 device_printf(sc->sc_dev, 6850 "%s: could not add broadcast node, error %d\n", __func__, 6851 error); 6852 return error; 6853 } 6854 6855 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6856 6857 return 0; 6858 } 6859 6860 static int 6861 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 6862 { 6863 struct iwn_ops *ops = &sc->ops; 6864 struct ifnet *ifp = sc->sc_ifp; 6865 struct ieee80211com *ic = ifp->if_l2com; 6866 struct ieee80211_node *ni = vap->iv_bss; 6867 struct iwn_node_info node; 6868 uint32_t htflags = 0; 6869 int error; 6870 6871 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6872 6873 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6874 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 6875 /* Link LED blinks while monitoring. */ 6876 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 6877 return 0; 6878 } 6879 if ((error = iwn_set_timing(sc, ni)) != 0) { 6880 device_printf(sc->sc_dev, 6881 "%s: could not set timing, error %d\n", __func__, error); 6882 return error; 6883 } 6884 6885 /* Update adapter configuration. */ 6886 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 6887 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 6888 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 6889 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6890 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 6891 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6892 if (ic->ic_flags & IEEE80211_F_SHSLOT) 6893 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 6894 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 6895 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 6896 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 6897 sc->rxon->cck_mask = 0; 6898 sc->rxon->ofdm_mask = 0x15; 6899 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 6900 sc->rxon->cck_mask = 0x03; 6901 sc->rxon->ofdm_mask = 0; 6902 } else { 6903 /* Assume 802.11b/g. */ 6904 sc->rxon->cck_mask = 0x0f; 6905 sc->rxon->ofdm_mask = 0x15; 6906 } 6907 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 6908 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 6909 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 6910 switch (ic->ic_curhtprotmode) { 6911 case IEEE80211_HTINFO_OPMODE_HT20PR: 6912 htflags |= IWN_RXON_HT_MODEPURE40; 6913 break; 6914 default: 6915 htflags |= IWN_RXON_HT_MODEMIXED; 6916 break; 6917 } 6918 } 6919 if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 6920 htflags |= IWN_RXON_HT_HT40MINUS; 6921 } 6922 sc->rxon->flags |= htole32(htflags); 6923 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 6924 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n", 6925 sc->rxon->chan, sc->rxon->flags); 6926 if (sc->sc_is_scanning) 6927 device_printf(sc->sc_dev, 6928 "%s: is_scanning set, before RXON\n", 6929 __func__); 6930 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 6931 if (error != 0) { 6932 device_printf(sc->sc_dev, 6933 "%s: could not update configuration, error %d\n", __func__, 6934 error); 6935 return error; 6936 } 6937 6938 /* Configuration has changed, set TX power accordingly. */ 6939 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 6940 device_printf(sc->sc_dev, 6941 "%s: could not set TX power, error %d\n", __func__, error); 6942 return error; 6943 } 6944 6945 /* Fake a join to initialize the TX rate. */ 6946 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 6947 iwn_newassoc(ni, 1); 6948 6949 /* Add BSS node. */ 6950 memset(&node, 0, sizeof node); 6951 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 6952 node.id = IWN_ID_BSS; 6953 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 6954 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 6955 case IEEE80211_HTCAP_SMPS_ENA: 6956 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 6957 break; 6958 case IEEE80211_HTCAP_SMPS_DYNAMIC: 6959 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 6960 break; 6961 } 6962 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 6963 IWN_AMDPU_DENSITY(5)); /* 4us */ 6964 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 6965 node.htflags |= htole32(IWN_NODE_HT40); 6966 } 6967 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 6968 error = ops->add_node(sc, &node, 1); 6969 if (error != 0) { 6970 device_printf(sc->sc_dev, 6971 "%s: could not add BSS node, error %d\n", __func__, error); 6972 return error; 6973 } 6974 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 6975 __func__, node.id); 6976 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 6977 device_printf(sc->sc_dev, 6978 "%s: could not setup link quality for node %d, error %d\n", 6979 __func__, node.id, error); 6980 return error; 6981 } 6982 6983 if ((error = iwn_init_sensitivity(sc)) != 0) { 6984 device_printf(sc->sc_dev, 6985 "%s: could not set sensitivity, error %d\n", __func__, 6986 error); 6987 return error; 6988 } 6989 /* Start periodic calibration timer. */ 6990 sc->calib.state = IWN_CALIB_STATE_ASSOC; 6991 sc->calib_cnt = 0; 6992 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 6993 sc); 6994 6995 /* Link LED always on while associated. */ 6996 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6997 6998 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6999 7000 return 0; 7001 } 7002 7003 /* 7004 * This function is called by upper layer when an ADDBA request is received 7005 * from another STA and before the ADDBA response is sent. 7006 */ 7007 static int 7008 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 7009 int baparamset, int batimeout, int baseqctl) 7010 { 7011 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 7012 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7013 struct iwn_ops *ops = &sc->ops; 7014 struct iwn_node *wn = (void *)ni; 7015 struct iwn_node_info node; 7016 uint16_t ssn; 7017 uint8_t tid; 7018 int error; 7019 7020 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7021 7022 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 7023 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 7024 7025 memset(&node, 0, sizeof node); 7026 node.id = wn->id; 7027 node.control = IWN_NODE_UPDATE; 7028 node.flags = IWN_FLAG_SET_ADDBA; 7029 node.addba_tid = tid; 7030 node.addba_ssn = htole16(ssn); 7031 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 7032 wn->id, tid, ssn); 7033 error = ops->add_node(sc, &node, 1); 7034 if (error != 0) 7035 return error; 7036 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 7037 #undef MS 7038 } 7039 7040 /* 7041 * This function is called by upper layer on teardown of an HT-immediate 7042 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 7043 */ 7044 static void 7045 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 7046 { 7047 struct ieee80211com *ic = ni->ni_ic; 7048 struct iwn_softc *sc = ic->ic_ifp->if_softc; 7049 struct iwn_ops *ops = &sc->ops; 7050 struct iwn_node *wn = (void *)ni; 7051 struct iwn_node_info node; 7052 uint8_t tid; 7053 7054 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7055 7056 /* XXX: tid as an argument */ 7057 for (tid = 0; tid < WME_NUM_TID; tid++) { 7058 if (&ni->ni_rx_ampdu[tid] == rap) 7059 break; 7060 } 7061 7062 memset(&node, 0, sizeof node); 7063 node.id = wn->id; 7064 node.control = IWN_NODE_UPDATE; 7065 node.flags = IWN_FLAG_SET_DELBA; 7066 node.delba_tid = tid; 7067 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 7068 (void)ops->add_node(sc, &node, 1); 7069 sc->sc_ampdu_rx_stop(ni, rap); 7070 } 7071 7072 static int 7073 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7074 int dialogtoken, int baparamset, int batimeout) 7075 { 7076 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7077 int qid; 7078 7079 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7080 7081 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 7082 if (sc->qid2tap[qid] == NULL) 7083 break; 7084 } 7085 if (qid == sc->ntxqs) { 7086 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 7087 __func__); 7088 return 0; 7089 } 7090 tap->txa_private = kmalloc(sizeof(int), M_DEVBUF, M_INTWAIT); 7091 sc->qid2tap[qid] = tap; 7092 *(int *)tap->txa_private = qid; 7093 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 7094 batimeout); 7095 } 7096 7097 static int 7098 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7099 int code, int baparamset, int batimeout) 7100 { 7101 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7102 int qid = *(int *)tap->txa_private; 7103 uint8_t tid = tap->txa_ac; 7104 int ret; 7105 7106 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7107 7108 if (code == IEEE80211_STATUS_SUCCESS) { 7109 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 7110 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 7111 if (ret != 1) 7112 return ret; 7113 } else { 7114 sc->qid2tap[qid] = NULL; 7115 kfree(tap->txa_private, M_DEVBUF); 7116 tap->txa_private = NULL; 7117 } 7118 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 7119 } 7120 7121 /* 7122 * This function is called by upper layer when an ADDBA response is received 7123 * from another STA. 7124 */ 7125 static int 7126 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 7127 uint8_t tid) 7128 { 7129 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 7130 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7131 struct iwn_ops *ops = &sc->ops; 7132 struct iwn_node *wn = (void *)ni; 7133 struct iwn_node_info node; 7134 int error, qid; 7135 7136 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7137 7138 /* Enable TX for the specified RA/TID. */ 7139 wn->disable_tid &= ~(1 << tid); 7140 memset(&node, 0, sizeof node); 7141 node.id = wn->id; 7142 node.control = IWN_NODE_UPDATE; 7143 node.flags = IWN_FLAG_SET_DISABLE_TID; 7144 node.disable_tid = htole16(wn->disable_tid); 7145 error = ops->add_node(sc, &node, 1); 7146 if (error != 0) 7147 return 0; 7148 7149 if ((error = iwn_nic_lock(sc)) != 0) 7150 return 0; 7151 qid = *(int *)tap->txa_private; 7152 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 7153 __func__, wn->id, tid, tap->txa_start, qid); 7154 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 7155 iwn_nic_unlock(sc); 7156 7157 iwn_set_link_quality(sc, ni); 7158 return 1; 7159 } 7160 7161 static void 7162 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 7163 { 7164 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7165 struct iwn_ops *ops = &sc->ops; 7166 uint8_t tid = tap->txa_ac; 7167 int qid; 7168 7169 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7170 7171 sc->sc_addba_stop(ni, tap); 7172 7173 if (tap->txa_private == NULL) 7174 return; 7175 7176 qid = *(int *)tap->txa_private; 7177 if (sc->txq[qid].queued != 0) 7178 return; 7179 if (iwn_nic_lock(sc) != 0) 7180 return; 7181 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 7182 iwn_nic_unlock(sc); 7183 sc->qid2tap[qid] = NULL; 7184 kfree(tap->txa_private, M_DEVBUF); 7185 tap->txa_private = NULL; 7186 } 7187 7188 static void 7189 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7190 int qid, uint8_t tid, uint16_t ssn) 7191 { 7192 struct iwn_node *wn = (void *)ni; 7193 7194 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7195 7196 /* Stop TX scheduler while we're changing its configuration. */ 7197 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7198 IWN4965_TXQ_STATUS_CHGACT); 7199 7200 /* Assign RA/TID translation to the queue. */ 7201 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 7202 wn->id << 4 | tid); 7203 7204 /* Enable chain-building mode for the queue. */ 7205 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 7206 7207 /* Set starting sequence number from the ADDBA request. */ 7208 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7209 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7210 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7211 7212 /* Set scheduler window size. */ 7213 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 7214 IWN_SCHED_WINSZ); 7215 /* Set scheduler frame limit. */ 7216 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7217 IWN_SCHED_LIMIT << 16); 7218 7219 /* Enable interrupts for the queue. */ 7220 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7221 7222 /* Mark the queue as active. */ 7223 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7224 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 7225 iwn_tid2fifo[tid] << 1); 7226 } 7227 7228 static void 7229 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7230 { 7231 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7232 7233 /* Stop TX scheduler while we're changing its configuration. */ 7234 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7235 IWN4965_TXQ_STATUS_CHGACT); 7236 7237 /* Set starting sequence number from the ADDBA request. */ 7238 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7239 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7240 7241 /* Disable interrupts for the queue. */ 7242 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7243 7244 /* Mark the queue as inactive. */ 7245 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7246 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 7247 } 7248 7249 static void 7250 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7251 int qid, uint8_t tid, uint16_t ssn) 7252 { 7253 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7254 7255 struct iwn_node *wn = (void *)ni; 7256 7257 /* Stop TX scheduler while we're changing its configuration. */ 7258 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7259 IWN5000_TXQ_STATUS_CHGACT); 7260 7261 /* Assign RA/TID translation to the queue. */ 7262 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 7263 wn->id << 4 | tid); 7264 7265 /* Enable chain-building mode for the queue. */ 7266 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 7267 7268 /* Enable aggregation for the queue. */ 7269 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7270 7271 /* Set starting sequence number from the ADDBA request. */ 7272 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7273 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7274 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7275 7276 /* Set scheduler window size and frame limit. */ 7277 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7278 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7279 7280 /* Enable interrupts for the queue. */ 7281 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7282 7283 /* Mark the queue as active. */ 7284 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7285 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 7286 } 7287 7288 static void 7289 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7290 { 7291 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7292 7293 /* Stop TX scheduler while we're changing its configuration. */ 7294 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7295 IWN5000_TXQ_STATUS_CHGACT); 7296 7297 /* Disable aggregation for the queue. */ 7298 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7299 7300 /* Set starting sequence number from the ADDBA request. */ 7301 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7302 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7303 7304 /* Disable interrupts for the queue. */ 7305 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7306 7307 /* Mark the queue as inactive. */ 7308 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7309 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 7310 } 7311 7312 /* 7313 * Query calibration tables from the initialization firmware. We do this 7314 * only once at first boot. Called from a process context. 7315 */ 7316 static int 7317 iwn5000_query_calibration(struct iwn_softc *sc) 7318 { 7319 struct iwn5000_calib_config cmd; 7320 int error; 7321 7322 memset(&cmd, 0, sizeof cmd); 7323 cmd.ucode.once.enable = htole32(0xffffffff); 7324 cmd.ucode.once.start = htole32(0xffffffff); 7325 cmd.ucode.once.send = htole32(0xffffffff); 7326 cmd.ucode.flags = htole32(0xffffffff); 7327 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 7328 __func__); 7329 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 7330 if (error != 0) 7331 return error; 7332 7333 /* Wait at most two seconds for calibration to complete. */ 7334 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 7335 error = zsleep(sc, &wlan_global_serializer, 0, "iwncal", 2 * hz); 7336 return error; 7337 } 7338 7339 /* 7340 * Send calibration results to the runtime firmware. These results were 7341 * obtained on first boot from the initialization firmware. 7342 */ 7343 static int 7344 iwn5000_send_calibration(struct iwn_softc *sc) 7345 { 7346 int idx, error; 7347 7348 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) { 7349 if (!(sc->base_params->calib_need & (1<<idx))) { 7350 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7351 "No need of calib %d\n", 7352 idx); 7353 continue; /* no need for this calib */ 7354 } 7355 if (sc->calibcmd[idx].buf == NULL) { 7356 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7357 "Need calib idx : %d but no available data\n", 7358 idx); 7359 continue; 7360 } 7361 7362 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7363 "send calibration result idx=%d len=%d\n", idx, 7364 sc->calibcmd[idx].len); 7365 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 7366 sc->calibcmd[idx].len, 0); 7367 if (error != 0) { 7368 device_printf(sc->sc_dev, 7369 "%s: could not send calibration result, error %d\n", 7370 __func__, error); 7371 return error; 7372 } 7373 } 7374 return 0; 7375 } 7376 7377 static int 7378 iwn5000_send_wimax_coex(struct iwn_softc *sc) 7379 { 7380 struct iwn5000_wimax_coex wimax; 7381 7382 #if 0 7383 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 7384 /* Enable WiMAX coexistence for combo adapters. */ 7385 wimax.flags = 7386 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 7387 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 7388 IWN_WIMAX_COEX_STA_TABLE_VALID | 7389 IWN_WIMAX_COEX_ENABLE; 7390 memcpy(wimax.events, iwn6050_wimax_events, 7391 sizeof iwn6050_wimax_events); 7392 } else 7393 #endif 7394 { 7395 /* Disable WiMAX coexistence. */ 7396 wimax.flags = 0; 7397 memset(wimax.events, 0, sizeof wimax.events); 7398 } 7399 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 7400 __func__); 7401 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 7402 } 7403 7404 static int 7405 iwn5000_crystal_calib(struct iwn_softc *sc) 7406 { 7407 struct iwn5000_phy_calib_crystal cmd; 7408 7409 memset(&cmd, 0, sizeof cmd); 7410 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 7411 cmd.ngroups = 1; 7412 cmd.isvalid = 1; 7413 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 7414 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 7415 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 7416 cmd.cap_pin[0], cmd.cap_pin[1]); 7417 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7418 } 7419 7420 static int 7421 iwn5000_temp_offset_calib(struct iwn_softc *sc) 7422 { 7423 struct iwn5000_phy_calib_temp_offset cmd; 7424 7425 memset(&cmd, 0, sizeof cmd); 7426 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7427 cmd.ngroups = 1; 7428 cmd.isvalid = 1; 7429 if (sc->eeprom_temp != 0) 7430 cmd.offset = htole16(sc->eeprom_temp); 7431 else 7432 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 7433 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 7434 le16toh(cmd.offset)); 7435 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7436 } 7437 7438 static int 7439 iwn5000_temp_offset_calibv2(struct iwn_softc *sc) 7440 { 7441 struct iwn5000_phy_calib_temp_offsetv2 cmd; 7442 7443 memset(&cmd, 0, sizeof cmd); 7444 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7445 cmd.ngroups = 1; 7446 cmd.isvalid = 1; 7447 if (sc->eeprom_temp != 0) { 7448 cmd.offset_low = htole16(sc->eeprom_temp); 7449 cmd.offset_high = htole16(sc->eeprom_temp_high); 7450 } else { 7451 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 7452 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 7453 } 7454 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 7455 7456 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7457 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n", 7458 le16toh(cmd.offset_low), 7459 le16toh(cmd.offset_high), 7460 le16toh(cmd.burnt_voltage_ref)); 7461 7462 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7463 } 7464 7465 /* 7466 * This function is called after the runtime firmware notifies us of its 7467 * readiness (called in a process context). 7468 */ 7469 static int 7470 iwn4965_post_alive(struct iwn_softc *sc) 7471 { 7472 int error, qid; 7473 7474 if ((error = iwn_nic_lock(sc)) != 0) 7475 return error; 7476 7477 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7478 7479 /* Clear TX scheduler state in SRAM. */ 7480 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7481 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 7482 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 7483 7484 /* Set physical address of TX scheduler rings (1KB aligned). */ 7485 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7486 7487 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7488 7489 /* Disable chain mode for all our 16 queues. */ 7490 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 7491 7492 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 7493 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 7494 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7495 7496 /* Set scheduler window size. */ 7497 iwn_mem_write(sc, sc->sched_base + 7498 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 7499 /* Set scheduler frame limit. */ 7500 iwn_mem_write(sc, sc->sched_base + 7501 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7502 IWN_SCHED_LIMIT << 16); 7503 } 7504 7505 /* Enable interrupts for all our 16 queues. */ 7506 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 7507 /* Identify TX FIFO rings (0-7). */ 7508 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 7509 7510 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7511 for (qid = 0; qid < 7; qid++) { 7512 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 7513 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7514 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 7515 } 7516 iwn_nic_unlock(sc); 7517 return 0; 7518 } 7519 7520 /* 7521 * This function is called after the initialization or runtime firmware 7522 * notifies us of its readiness (called in a process context). 7523 */ 7524 static int 7525 iwn5000_post_alive(struct iwn_softc *sc) 7526 { 7527 int error, qid; 7528 7529 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7530 7531 /* Switch to using ICT interrupt mode. */ 7532 iwn5000_ict_reset(sc); 7533 7534 if ((error = iwn_nic_lock(sc)) != 0){ 7535 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 7536 return error; 7537 } 7538 7539 /* Clear TX scheduler state in SRAM. */ 7540 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7541 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 7542 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 7543 7544 /* Set physical address of TX scheduler rings (1KB aligned). */ 7545 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7546 7547 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7548 7549 /* Enable chain mode for all queues, except command queue. */ 7550 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 7551 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf); 7552 else 7553 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 7554 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 7555 7556 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 7557 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 7558 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7559 7560 iwn_mem_write(sc, sc->sched_base + 7561 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 7562 /* Set scheduler window size and frame limit. */ 7563 iwn_mem_write(sc, sc->sched_base + 7564 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7565 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7566 } 7567 7568 /* Enable interrupts for all our 20 queues. */ 7569 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 7570 /* Identify TX FIFO rings (0-7). */ 7571 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 7572 7573 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7574 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) { 7575 /* Mark TX rings as active. */ 7576 for (qid = 0; qid < 11; qid++) { 7577 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 }; 7578 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7579 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7580 } 7581 } else { 7582 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7583 for (qid = 0; qid < 7; qid++) { 7584 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 7585 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7586 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7587 } 7588 } 7589 iwn_nic_unlock(sc); 7590 7591 /* Configure WiMAX coexistence for combo adapters. */ 7592 error = iwn5000_send_wimax_coex(sc); 7593 if (error != 0) { 7594 device_printf(sc->sc_dev, 7595 "%s: could not configure WiMAX coexistence, error %d\n", 7596 __func__, error); 7597 return error; 7598 } 7599 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 7600 /* Perform crystal calibration. */ 7601 error = iwn5000_crystal_calib(sc); 7602 if (error != 0) { 7603 device_printf(sc->sc_dev, 7604 "%s: crystal calibration failed, error %d\n", 7605 __func__, error); 7606 return error; 7607 } 7608 } 7609 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 7610 /* Query calibration from the initialization firmware. */ 7611 if ((error = iwn5000_query_calibration(sc)) != 0) { 7612 device_printf(sc->sc_dev, 7613 "%s: could not query calibration, error %d\n", 7614 __func__, error); 7615 return error; 7616 } 7617 /* 7618 * We have the calibration results now, reboot with the 7619 * runtime firmware (call ourselves recursively!) 7620 */ 7621 iwn_hw_stop(sc); 7622 error = iwn_hw_init(sc); 7623 } else { 7624 /* Send calibration results to runtime firmware. */ 7625 error = iwn5000_send_calibration(sc); 7626 } 7627 7628 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7629 7630 return error; 7631 } 7632 7633 /* 7634 * The firmware boot code is small and is intended to be copied directly into 7635 * the NIC internal memory (no DMA transfer). 7636 */ 7637 static int 7638 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 7639 { 7640 int error, ntries; 7641 7642 size /= sizeof (uint32_t); 7643 7644 if ((error = iwn_nic_lock(sc)) != 0) 7645 return error; 7646 7647 /* Copy microcode image into NIC memory. */ 7648 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 7649 (const uint32_t *)ucode, size); 7650 7651 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 7652 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 7653 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 7654 7655 /* Start boot load now. */ 7656 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 7657 7658 /* Wait for transfer to complete. */ 7659 for (ntries = 0; ntries < 1000; ntries++) { 7660 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 7661 IWN_BSM_WR_CTRL_START)) 7662 break; 7663 DELAY(10); 7664 } 7665 if (ntries == 1000) { 7666 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 7667 __func__); 7668 iwn_nic_unlock(sc); 7669 return ETIMEDOUT; 7670 } 7671 7672 /* Enable boot after power up. */ 7673 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 7674 7675 iwn_nic_unlock(sc); 7676 return 0; 7677 } 7678 7679 static int 7680 iwn4965_load_firmware(struct iwn_softc *sc) 7681 { 7682 struct iwn_fw_info *fw = &sc->fw; 7683 struct iwn_dma_info *dma = &sc->fw_dma; 7684 int error; 7685 7686 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 7687 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 7688 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7689 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 7690 fw->init.text, fw->init.textsz); 7691 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7692 7693 /* Tell adapter where to find initialization sections. */ 7694 if ((error = iwn_nic_lock(sc)) != 0) 7695 return error; 7696 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 7697 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 7698 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 7699 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 7700 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 7701 iwn_nic_unlock(sc); 7702 7703 /* Load firmware boot code. */ 7704 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 7705 if (error != 0) { 7706 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 7707 __func__); 7708 return error; 7709 } 7710 /* Now press "execute". */ 7711 IWN_WRITE(sc, IWN_RESET, 0); 7712 7713 /* Wait at most one second for first alive notification. */ 7714 if ((error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz)) != 0) { 7715 device_printf(sc->sc_dev, 7716 "%s: timeout waiting for adapter to initialize, error %d\n", 7717 __func__, error); 7718 return error; 7719 } 7720 7721 /* Retrieve current temperature for initial TX power calibration. */ 7722 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 7723 sc->temp = iwn4965_get_temperature(sc); 7724 7725 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 7726 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 7727 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7728 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 7729 fw->main.text, fw->main.textsz); 7730 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7731 7732 /* Tell adapter where to find runtime sections. */ 7733 if ((error = iwn_nic_lock(sc)) != 0) 7734 return error; 7735 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 7736 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 7737 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 7738 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 7739 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 7740 IWN_FW_UPDATED | fw->main.textsz); 7741 iwn_nic_unlock(sc); 7742 7743 return 0; 7744 } 7745 7746 static int 7747 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 7748 const uint8_t *section, int size) 7749 { 7750 struct iwn_dma_info *dma = &sc->fw_dma; 7751 int error; 7752 7753 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7754 7755 /* Copy firmware section into pre-allocated DMA-safe memory. */ 7756 memcpy(dma->vaddr, section, size); 7757 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7758 7759 if ((error = iwn_nic_lock(sc)) != 0) 7760 return error; 7761 7762 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 7763 IWN_FH_TX_CONFIG_DMA_PAUSE); 7764 7765 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 7766 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 7767 IWN_LOADDR(dma->paddr)); 7768 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 7769 IWN_HIADDR(dma->paddr) << 28 | size); 7770 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 7771 IWN_FH_TXBUF_STATUS_TBNUM(1) | 7772 IWN_FH_TXBUF_STATUS_TBIDX(1) | 7773 IWN_FH_TXBUF_STATUS_TFBD_VALID); 7774 7775 /* Kick Flow Handler to start DMA transfer. */ 7776 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 7777 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 7778 7779 iwn_nic_unlock(sc); 7780 7781 /* Wait at most five seconds for FH DMA transfer to complete. */ 7782 return zsleep(sc, &wlan_global_serializer, 0, "iwninit", 5 * hz); 7783 } 7784 7785 static int 7786 iwn5000_load_firmware(struct iwn_softc *sc) 7787 { 7788 struct iwn_fw_part *fw; 7789 int error; 7790 7791 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7792 7793 /* Load the initialization firmware on first boot only. */ 7794 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 7795 &sc->fw.main : &sc->fw.init; 7796 7797 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 7798 fw->text, fw->textsz); 7799 if (error != 0) { 7800 device_printf(sc->sc_dev, 7801 "%s: could not load firmware %s section, error %d\n", 7802 __func__, ".text", error); 7803 return error; 7804 } 7805 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 7806 fw->data, fw->datasz); 7807 if (error != 0) { 7808 device_printf(sc->sc_dev, 7809 "%s: could not load firmware %s section, error %d\n", 7810 __func__, ".data", error); 7811 return error; 7812 } 7813 7814 /* Now press "execute". */ 7815 IWN_WRITE(sc, IWN_RESET, 0); 7816 return 0; 7817 } 7818 7819 /* 7820 * Extract text and data sections from a legacy firmware image. 7821 */ 7822 static int 7823 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 7824 { 7825 const uint32_t *ptr; 7826 size_t hdrlen = 24; 7827 uint32_t rev; 7828 7829 ptr = (const uint32_t *)fw->data; 7830 rev = le32toh(*ptr++); 7831 7832 /* Check firmware API version. */ 7833 if (IWN_FW_API(rev) <= 1) { 7834 device_printf(sc->sc_dev, 7835 "%s: bad firmware, need API version >=2\n", __func__); 7836 return EINVAL; 7837 } 7838 if (IWN_FW_API(rev) >= 3) { 7839 /* Skip build number (version 2 header). */ 7840 hdrlen += 4; 7841 ptr++; 7842 } 7843 if (fw->size < hdrlen) { 7844 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 7845 __func__, fw->size); 7846 return EINVAL; 7847 } 7848 fw->main.textsz = le32toh(*ptr++); 7849 fw->main.datasz = le32toh(*ptr++); 7850 fw->init.textsz = le32toh(*ptr++); 7851 fw->init.datasz = le32toh(*ptr++); 7852 fw->boot.textsz = le32toh(*ptr++); 7853 7854 /* Check that all firmware sections fit. */ 7855 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 7856 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 7857 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 7858 __func__, fw->size); 7859 return EINVAL; 7860 } 7861 7862 /* Get pointers to firmware sections. */ 7863 fw->main.text = (const uint8_t *)ptr; 7864 fw->main.data = fw->main.text + fw->main.textsz; 7865 fw->init.text = fw->main.data + fw->main.datasz; 7866 fw->init.data = fw->init.text + fw->init.textsz; 7867 fw->boot.text = fw->init.data + fw->init.datasz; 7868 return 0; 7869 } 7870 7871 /* 7872 * Extract text and data sections from a TLV firmware image. 7873 */ 7874 static int 7875 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 7876 uint16_t alt) 7877 { 7878 const struct iwn_fw_tlv_hdr *hdr; 7879 const struct iwn_fw_tlv *tlv; 7880 const uint8_t *ptr, *end; 7881 uint64_t altmask; 7882 uint32_t len, tmp; 7883 7884 if (fw->size < sizeof (*hdr)) { 7885 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 7886 __func__, fw->size); 7887 return EINVAL; 7888 } 7889 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 7890 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 7891 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 7892 __func__, le32toh(hdr->signature)); 7893 return EINVAL; 7894 } 7895 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 7896 le32toh(hdr->build)); 7897 7898 /* 7899 * Select the closest supported alternative that is less than 7900 * or equal to the specified one. 7901 */ 7902 altmask = le64toh(hdr->altmask); 7903 while (alt > 0 && !(altmask & (1ULL << alt))) 7904 alt--; /* Downgrade. */ 7905 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 7906 7907 ptr = (const uint8_t *)(hdr + 1); 7908 end = (const uint8_t *)(fw->data + fw->size); 7909 7910 /* Parse type-length-value fields. */ 7911 while (ptr + sizeof (*tlv) <= end) { 7912 tlv = (const struct iwn_fw_tlv *)ptr; 7913 len = le32toh(tlv->len); 7914 7915 ptr += sizeof (*tlv); 7916 if (ptr + len > end) { 7917 device_printf(sc->sc_dev, 7918 "%s: firmware too short: %zu bytes\n", __func__, 7919 fw->size); 7920 return EINVAL; 7921 } 7922 /* Skip other alternatives. */ 7923 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 7924 goto next; 7925 7926 switch (le16toh(tlv->type)) { 7927 case IWN_FW_TLV_MAIN_TEXT: 7928 fw->main.text = ptr; 7929 fw->main.textsz = len; 7930 break; 7931 case IWN_FW_TLV_MAIN_DATA: 7932 fw->main.data = ptr; 7933 fw->main.datasz = len; 7934 break; 7935 case IWN_FW_TLV_INIT_TEXT: 7936 fw->init.text = ptr; 7937 fw->init.textsz = len; 7938 break; 7939 case IWN_FW_TLV_INIT_DATA: 7940 fw->init.data = ptr; 7941 fw->init.datasz = len; 7942 break; 7943 case IWN_FW_TLV_BOOT_TEXT: 7944 fw->boot.text = ptr; 7945 fw->boot.textsz = len; 7946 break; 7947 case IWN_FW_TLV_ENH_SENS: 7948 if (!len) 7949 sc->sc_flags |= IWN_FLAG_ENH_SENS; 7950 break; 7951 case IWN_FW_TLV_PHY_CALIB: 7952 tmp = le32toh(*ptr); 7953 if (tmp < 253) { 7954 sc->reset_noise_gain = tmp; 7955 sc->noise_gain = tmp + 1; 7956 } 7957 break; 7958 case IWN_FW_TLV_PAN: 7959 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 7960 DPRINTF(sc, IWN_DEBUG_RESET, 7961 "PAN Support found: %d\n", 1); 7962 break; 7963 case IWN_FW_TLV_FLAGS: 7964 if (len < sizeof(uint32_t)) 7965 break; 7966 if (len % sizeof(uint32_t)) 7967 break; 7968 sc->tlv_feature_flags = le32toh(*ptr); 7969 DPRINTF(sc, IWN_DEBUG_RESET, 7970 "%s: feature: 0x%08x\n", 7971 __func__, 7972 sc->tlv_feature_flags); 7973 break; 7974 case IWN_FW_TLV_PBREQ_MAXLEN: 7975 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 7976 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 7977 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 7978 case IWN_FW_TLV_INIT_EVTLOG_PTR: 7979 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 7980 case IWN_FW_TLV_INIT_ERRLOG_PTR: 7981 case IWN_FW_TLV_WOWLAN_INST: 7982 case IWN_FW_TLV_WOWLAN_DATA: 7983 DPRINTF(sc, IWN_DEBUG_RESET, 7984 "TLV type %d recognized but not handled\n", 7985 le16toh(tlv->type)); 7986 break; 7987 default: 7988 DPRINTF(sc, IWN_DEBUG_RESET, 7989 "TLV type %d not handled\n", le16toh(tlv->type)); 7990 break; 7991 } 7992 next: /* TLV fields are 32-bit aligned. */ 7993 ptr += (len + 3) & ~3; 7994 } 7995 return 0; 7996 } 7997 7998 static int 7999 iwn_read_firmware(struct iwn_softc *sc) 8000 { 8001 struct iwn_fw_info *fw = &sc->fw; 8002 int error; 8003 8004 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8005 8006 wlan_assert_serialized(); 8007 memset(fw, 0, sizeof (*fw)); 8008 8009 /* 8010 * Read firmware image from filesystem. The firmware can block 8011 * in a taskq and deadlock against our serializer so unlock 8012 * while we do tihs. 8013 */ 8014 wlan_serialize_exit(); 8015 sc->fw_fp = firmware_get(sc->fwname); 8016 wlan_serialize_enter(); 8017 if (sc->fw_fp == NULL) { 8018 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 8019 __func__, sc->fwname); 8020 return EINVAL; 8021 } 8022 8023 fw->size = sc->fw_fp->datasize; 8024 fw->data = (const uint8_t *)sc->fw_fp->data; 8025 if (fw->size < sizeof (uint32_t)) { 8026 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8027 __func__, fw->size); 8028 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8029 sc->fw_fp = NULL; 8030 return EINVAL; 8031 } 8032 8033 /* Retrieve text and data sections. */ 8034 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 8035 error = iwn_read_firmware_leg(sc, fw); 8036 else 8037 error = iwn_read_firmware_tlv(sc, fw, 1); 8038 if (error != 0) { 8039 device_printf(sc->sc_dev, 8040 "%s: could not read firmware sections, error %d\n", 8041 __func__, error); 8042 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8043 sc->fw_fp = NULL; 8044 return error; 8045 } 8046 8047 /* Make sure text and data sections fit in hardware memory. */ 8048 if (fw->main.textsz > sc->fw_text_maxsz || 8049 fw->main.datasz > sc->fw_data_maxsz || 8050 fw->init.textsz > sc->fw_text_maxsz || 8051 fw->init.datasz > sc->fw_data_maxsz || 8052 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 8053 (fw->boot.textsz & 3) != 0) { 8054 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 8055 __func__); 8056 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8057 sc->fw_fp = NULL; 8058 return EINVAL; 8059 } 8060 8061 /* We can proceed with loading the firmware. */ 8062 return 0; 8063 } 8064 8065 static int 8066 iwn_clock_wait(struct iwn_softc *sc) 8067 { 8068 int ntries; 8069 8070 /* Set "initialization complete" bit. */ 8071 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8072 8073 /* Wait for clock stabilization. */ 8074 for (ntries = 0; ntries < 2500; ntries++) { 8075 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 8076 return 0; 8077 DELAY(10); 8078 } 8079 device_printf(sc->sc_dev, 8080 "%s: timeout waiting for clock stabilization\n", __func__); 8081 return ETIMEDOUT; 8082 } 8083 8084 static int 8085 iwn_apm_init(struct iwn_softc *sc) 8086 { 8087 uint32_t reg; 8088 int error; 8089 8090 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8091 8092 /* Disable L0s exit timer (NMI bug workaround). */ 8093 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 8094 /* Don't wait for ICH L0s (ICH bug workaround). */ 8095 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 8096 8097 /* Set FH wait threshold to max (HW bug under stress workaround). */ 8098 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 8099 8100 /* Enable HAP INTA to move adapter from L1a to L0s. */ 8101 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 8102 8103 /* Retrieve PCIe Active State Power Management (ASPM). */ 8104 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 8105 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8106 if (reg & 0x02) /* L1 Entry enabled. */ 8107 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8108 else 8109 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8110 8111 if (sc->base_params->pll_cfg_val) 8112 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val); 8113 8114 /* Wait for clock stabilization before accessing prph. */ 8115 if ((error = iwn_clock_wait(sc)) != 0) 8116 return error; 8117 8118 if ((error = iwn_nic_lock(sc)) != 0) 8119 return error; 8120 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 8121 /* Enable DMA and BSM (Bootstrap State Machine). */ 8122 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8123 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 8124 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 8125 } else { 8126 /* Enable DMA. */ 8127 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8128 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8129 } 8130 DELAY(20); 8131 /* Disable L1-Active. */ 8132 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 8133 iwn_nic_unlock(sc); 8134 8135 return 0; 8136 } 8137 8138 static void 8139 iwn_apm_stop_master(struct iwn_softc *sc) 8140 { 8141 int ntries; 8142 8143 /* Stop busmaster DMA activity. */ 8144 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 8145 for (ntries = 0; ntries < 100; ntries++) { 8146 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 8147 return; 8148 DELAY(10); 8149 } 8150 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 8151 } 8152 8153 static void 8154 iwn_apm_stop(struct iwn_softc *sc) 8155 { 8156 iwn_apm_stop_master(sc); 8157 8158 /* Reset the entire device. */ 8159 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 8160 DELAY(10); 8161 /* Clear "initialization complete" bit. */ 8162 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8163 } 8164 8165 static int 8166 iwn4965_nic_config(struct iwn_softc *sc) 8167 { 8168 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8169 8170 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 8171 /* 8172 * I don't believe this to be correct but this is what the 8173 * vendor driver is doing. Probably the bits should not be 8174 * shifted in IWN_RFCFG_*. 8175 */ 8176 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8177 IWN_RFCFG_TYPE(sc->rfcfg) | 8178 IWN_RFCFG_STEP(sc->rfcfg) | 8179 IWN_RFCFG_DASH(sc->rfcfg)); 8180 } 8181 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8182 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8183 return 0; 8184 } 8185 8186 static int 8187 iwn5000_nic_config(struct iwn_softc *sc) 8188 { 8189 uint32_t tmp; 8190 int error; 8191 8192 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8193 8194 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 8195 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8196 IWN_RFCFG_TYPE(sc->rfcfg) | 8197 IWN_RFCFG_STEP(sc->rfcfg) | 8198 IWN_RFCFG_DASH(sc->rfcfg)); 8199 } 8200 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8201 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8202 8203 if ((error = iwn_nic_lock(sc)) != 0) 8204 return error; 8205 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 8206 8207 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 8208 /* 8209 * Select first Switching Voltage Regulator (1.32V) to 8210 * solve a stability issue related to noisy DC2DC line 8211 * in the silicon of 1000 Series. 8212 */ 8213 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 8214 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 8215 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 8216 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 8217 } 8218 iwn_nic_unlock(sc); 8219 8220 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 8221 /* Use internal power amplifier only. */ 8222 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 8223 } 8224 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) { 8225 /* Indicate that ROM calibration version is >=6. */ 8226 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 8227 } 8228 if (sc->base_params->additional_gp_drv_bit) 8229 IWN_SETBITS(sc, IWN_GP_DRIVER, 8230 sc->base_params->additional_gp_drv_bit); 8231 return 0; 8232 } 8233 8234 /* 8235 * Take NIC ownership over Intel Active Management Technology (AMT). 8236 */ 8237 static int 8238 iwn_hw_prepare(struct iwn_softc *sc) 8239 { 8240 int ntries; 8241 8242 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8243 8244 /* Check if hardware is ready. */ 8245 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8246 for (ntries = 0; ntries < 5; ntries++) { 8247 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8248 IWN_HW_IF_CONFIG_NIC_READY) 8249 return 0; 8250 DELAY(10); 8251 } 8252 8253 /* Hardware not ready, force into ready state. */ 8254 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 8255 for (ntries = 0; ntries < 15000; ntries++) { 8256 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 8257 IWN_HW_IF_CONFIG_PREPARE_DONE)) 8258 break; 8259 DELAY(10); 8260 } 8261 if (ntries == 15000) 8262 return ETIMEDOUT; 8263 8264 /* Hardware should be ready now. */ 8265 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8266 for (ntries = 0; ntries < 5; ntries++) { 8267 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8268 IWN_HW_IF_CONFIG_NIC_READY) 8269 return 0; 8270 DELAY(10); 8271 } 8272 return ETIMEDOUT; 8273 } 8274 8275 static int 8276 iwn_hw_init(struct iwn_softc *sc) 8277 { 8278 struct iwn_ops *ops = &sc->ops; 8279 int error, chnl, qid; 8280 8281 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8282 8283 /* Clear pending interrupts. */ 8284 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8285 8286 if ((error = iwn_apm_init(sc)) != 0) { 8287 device_printf(sc->sc_dev, 8288 "%s: could not power ON adapter, error %d\n", __func__, 8289 error); 8290 return error; 8291 } 8292 8293 /* Select VMAIN power source. */ 8294 if ((error = iwn_nic_lock(sc)) != 0) 8295 return error; 8296 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 8297 iwn_nic_unlock(sc); 8298 8299 /* Perform adapter-specific initialization. */ 8300 if ((error = ops->nic_config(sc)) != 0) 8301 return error; 8302 8303 /* Initialize RX ring. */ 8304 if ((error = iwn_nic_lock(sc)) != 0) 8305 return error; 8306 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 8307 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 8308 /* Set physical address of RX ring (256-byte aligned). */ 8309 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 8310 /* Set physical address of RX status (16-byte aligned). */ 8311 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 8312 /* Enable RX. */ 8313 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 8314 IWN_FH_RX_CONFIG_ENA | 8315 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 8316 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 8317 IWN_FH_RX_CONFIG_SINGLE_FRAME | 8318 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 8319 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 8320 iwn_nic_unlock(sc); 8321 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 8322 8323 if ((error = iwn_nic_lock(sc)) != 0) 8324 return error; 8325 8326 /* Initialize TX scheduler. */ 8327 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8328 8329 /* Set physical address of "keep warm" page (16-byte aligned). */ 8330 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 8331 8332 /* Initialize TX rings. */ 8333 for (qid = 0; qid < sc->ntxqs; qid++) { 8334 struct iwn_tx_ring *txq = &sc->txq[qid]; 8335 8336 /* Set physical address of TX ring (256-byte aligned). */ 8337 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 8338 txq->desc_dma.paddr >> 8); 8339 } 8340 iwn_nic_unlock(sc); 8341 8342 /* Enable DMA channels. */ 8343 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8344 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 8345 IWN_FH_TX_CONFIG_DMA_ENA | 8346 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 8347 } 8348 8349 /* Clear "radio off" and "commands blocked" bits. */ 8350 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8351 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 8352 8353 /* Clear pending interrupts. */ 8354 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8355 /* Enable interrupt coalescing. */ 8356 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 8357 /* Enable interrupts. */ 8358 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8359 8360 /* _Really_ make sure "radio off" bit is cleared! */ 8361 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8362 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8363 8364 /* Enable shadow registers. */ 8365 if (sc->base_params->shadow_reg_enable) 8366 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 8367 8368 if ((error = ops->load_firmware(sc)) != 0) { 8369 device_printf(sc->sc_dev, 8370 "%s: could not load firmware, error %d\n", __func__, 8371 error); 8372 return error; 8373 } 8374 /* Wait at most one second for firmware alive notification. */ 8375 if ((error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz)) != 0) { 8376 device_printf(sc->sc_dev, 8377 "%s: timeout waiting for adapter to initialize, error %d\n", 8378 __func__, error); 8379 return error; 8380 } 8381 /* Do post-firmware initialization. */ 8382 8383 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8384 8385 return ops->post_alive(sc); 8386 } 8387 8388 static void 8389 iwn_hw_stop(struct iwn_softc *sc) 8390 { 8391 int chnl, qid, ntries; 8392 8393 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8394 8395 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 8396 8397 /* Disable interrupts. */ 8398 IWN_WRITE(sc, IWN_INT_MASK, 0); 8399 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8400 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 8401 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8402 8403 /* Make sure we no longer hold the NIC lock. */ 8404 iwn_nic_unlock(sc); 8405 8406 /* Stop TX scheduler. */ 8407 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8408 8409 /* Stop all DMA channels. */ 8410 if (iwn_nic_lock(sc) == 0) { 8411 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8412 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 8413 for (ntries = 0; ntries < 200; ntries++) { 8414 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 8415 IWN_FH_TX_STATUS_IDLE(chnl)) 8416 break; 8417 DELAY(10); 8418 } 8419 } 8420 iwn_nic_unlock(sc); 8421 } 8422 8423 /* Stop RX ring. */ 8424 iwn_reset_rx_ring(sc, &sc->rxq); 8425 8426 /* Reset all TX rings. */ 8427 for (qid = 0; qid < sc->ntxqs; qid++) 8428 iwn_reset_tx_ring(sc, &sc->txq[qid]); 8429 8430 if (iwn_nic_lock(sc) == 0) { 8431 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 8432 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8433 iwn_nic_unlock(sc); 8434 } 8435 DELAY(5); 8436 /* Power OFF adapter. */ 8437 iwn_apm_stop(sc); 8438 } 8439 8440 static void 8441 iwn_radio_on_task(void *arg0, int pending) 8442 { 8443 struct iwn_softc *sc = arg0; 8444 struct ifnet *ifp; 8445 struct ieee80211com *ic; 8446 struct ieee80211vap *vap; 8447 8448 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8449 8450 wlan_serialize_enter(); 8451 ifp = sc->sc_ifp; 8452 ic = ifp->if_l2com; 8453 vap = TAILQ_FIRST(&ic->ic_vaps); 8454 if (vap != NULL) { 8455 iwn_init_locked(sc); 8456 ieee80211_init(vap); 8457 } 8458 wlan_serialize_exit(); 8459 } 8460 8461 static void 8462 iwn_radio_off_task(void *arg0, int pending) 8463 { 8464 struct iwn_softc *sc = arg0; 8465 struct ifnet *ifp; 8466 struct ieee80211com *ic; 8467 struct ieee80211vap *vap; 8468 8469 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8470 8471 wlan_serialize_enter(); 8472 ifp = sc->sc_ifp; 8473 ic = ifp->if_l2com; 8474 vap = TAILQ_FIRST(&ic->ic_vaps); 8475 iwn_stop_locked(sc); 8476 if (vap != NULL) 8477 ieee80211_stop(vap); 8478 8479 /* Enable interrupts to get RF toggle notification. */ 8480 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8481 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8482 wlan_serialize_exit(); 8483 } 8484 8485 static void 8486 iwn_panicked_task(void *arg0, int pending) 8487 { 8488 struct iwn_softc *sc = arg0; 8489 struct ifnet *ifp = sc->sc_ifp; 8490 struct ieee80211com *ic = ifp->if_l2com; 8491 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8492 int error; 8493 8494 if (vap == NULL) { 8495 kprintf("%s: null vap\n", __func__); 8496 return; 8497 } 8498 8499 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 8500 "resetting...\n", __func__, vap->iv_state); 8501 8502 wlan_serialize_enter(); 8503 8504 iwn_stop_locked(sc); 8505 iwn_init_locked(sc); 8506 if (vap->iv_state >= IEEE80211_S_AUTH && 8507 (error = iwn_auth(sc, vap)) != 0) { 8508 device_printf(sc->sc_dev, 8509 "%s: could not move to auth state\n", __func__); 8510 } 8511 if (vap->iv_state >= IEEE80211_S_RUN && 8512 (error = iwn_run(sc, vap)) != 0) { 8513 device_printf(sc->sc_dev, 8514 "%s: could not move to run state\n", __func__); 8515 } 8516 8517 /* Only run start once the NIC is in a useful state, like associated */ 8518 iwn_start_locked(sc->sc_ifp); 8519 8520 wlan_serialize_exit(); 8521 } 8522 8523 static void 8524 iwn_init_locked(struct iwn_softc *sc) 8525 { 8526 struct ifnet *ifp = sc->sc_ifp; 8527 int error; 8528 8529 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8530 8531 /* 8532 * Make sure we hold the serializer or we will have timing issues 8533 * with the wlan subsystem. 8534 */ 8535 wlan_assert_serialized(); 8536 if ((error = iwn_hw_prepare(sc)) != 0) { 8537 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 8538 __func__, error); 8539 goto fail; 8540 } 8541 8542 /* Initialize interrupt mask to default value. */ 8543 sc->int_mask = IWN_INT_MASK_DEF; 8544 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8545 8546 /* Check that the radio is not disabled by hardware switch. */ 8547 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 8548 device_printf(sc->sc_dev, 8549 "radio is disabled by hardware switch\n"); 8550 /* Enable interrupts to get RF toggle notifications. */ 8551 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8552 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8553 return; 8554 } 8555 8556 /* Read firmware images from the filesystem. */ 8557 if ((error = iwn_read_firmware(sc)) != 0) { 8558 device_printf(sc->sc_dev, 8559 "%s: could not read firmware, error %d\n", __func__, 8560 error); 8561 goto fail; 8562 } 8563 8564 /* Initialize hardware and upload firmware. */ 8565 error = iwn_hw_init(sc); 8566 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8567 sc->fw_fp = NULL; 8568 if (error != 0) { 8569 device_printf(sc->sc_dev, 8570 "%s: could not initialize hardware, error %d\n", __func__, 8571 error); 8572 goto fail; 8573 } 8574 8575 /* Configure adapter now that it is ready. */ 8576 if ((error = iwn_config(sc)) != 0) { 8577 device_printf(sc->sc_dev, 8578 "%s: could not configure device, error %d\n", __func__, 8579 error); 8580 goto fail; 8581 } 8582 8583 ifq_clr_oactive(&ifp->if_snd); 8584 ifp->if_flags |= IFF_RUNNING; 8585 8586 callout_reset(&sc->watchdog_to, hz, iwn_watchdog_timeout, sc); 8587 8588 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8589 8590 return; 8591 8592 fail: iwn_stop_locked(sc); 8593 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 8594 } 8595 8596 static void 8597 iwn_init(void *arg) 8598 { 8599 struct iwn_softc *sc = arg; 8600 struct ifnet *ifp = sc->sc_ifp; 8601 struct ieee80211com *ic = ifp->if_l2com; 8602 8603 wlan_assert_serialized(); 8604 iwn_init_locked(sc); 8605 8606 if (ifp->if_flags & IFF_RUNNING) 8607 ieee80211_start_all(ic); 8608 } 8609 8610 static void 8611 iwn_stop_locked(struct iwn_softc *sc) 8612 { 8613 struct ifnet *ifp = sc->sc_ifp; 8614 8615 sc->sc_is_scanning = 0; 8616 sc->sc_tx_timer = 0; 8617 callout_stop(&sc->watchdog_to); 8618 callout_stop(&sc->calib_to); 8619 ifp->if_flags &= ~IFF_RUNNING; 8620 ifq_clr_oactive(&ifp->if_snd); 8621 8622 /* Power OFF hardware. */ 8623 iwn_hw_stop(sc); 8624 } 8625 8626 /* 8627 * Callback from net80211 to start a scan. 8628 */ 8629 static void 8630 iwn_scan_start(struct ieee80211com *ic) 8631 { 8632 struct ifnet *ifp = ic->ic_ifp; 8633 struct iwn_softc *sc = ifp->if_softc; 8634 8635 /* make the link LED blink while we're scanning */ 8636 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 8637 } 8638 8639 /* 8640 * Callback from net80211 to terminate a scan. 8641 */ 8642 static void 8643 iwn_scan_end(struct ieee80211com *ic) 8644 { 8645 struct ifnet *ifp = ic->ic_ifp; 8646 struct iwn_softc *sc = ifp->if_softc; 8647 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8648 8649 if (vap->iv_state == IEEE80211_S_RUN) { 8650 /* Set link LED to ON status if we are associated */ 8651 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 8652 } 8653 } 8654 8655 /* 8656 * Callback from net80211 to force a channel change. 8657 */ 8658 static void 8659 iwn_set_channel(struct ieee80211com *ic) 8660 { 8661 const struct ieee80211_channel *c = ic->ic_curchan; 8662 struct ifnet *ifp = ic->ic_ifp; 8663 struct iwn_softc *sc = ifp->if_softc; 8664 int error; 8665 8666 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8667 8668 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 8669 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 8670 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 8671 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 8672 8673 /* 8674 * Only need to set the channel in Monitor mode. AP scanning and auth 8675 * are already taken care of by their respective firmware commands. 8676 */ 8677 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 8678 error = iwn_config(sc); 8679 if (error != 0) 8680 device_printf(sc->sc_dev, 8681 "%s: error %d settting channel\n", __func__, error); 8682 } 8683 } 8684 8685 /* 8686 * Callback from net80211 to start scanning of the current channel. 8687 */ 8688 static void 8689 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 8690 { 8691 struct ieee80211vap *vap = ss->ss_vap; 8692 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 8693 struct ieee80211com *ic = vap->iv_ic; 8694 int error; 8695 8696 error = iwn_scan(sc, vap, ss, ic->ic_curchan); 8697 if (error != 0) 8698 ieee80211_cancel_scan(vap); 8699 } 8700 8701 /* 8702 * Callback from net80211 to handle the minimum dwell time being met. 8703 * The intent is to terminate the scan but we just let the firmware 8704 * notify us when it's finished as we have no safe way to abort it. 8705 */ 8706 static void 8707 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 8708 { 8709 /* NB: don't try to abort scan; wait for firmware to finish */ 8710 } 8711 8712 static void 8713 iwn_hw_reset_task(void *arg0, int pending) 8714 { 8715 struct iwn_softc *sc = arg0; 8716 struct ifnet *ifp; 8717 struct ieee80211com *ic; 8718 8719 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8720 8721 wlan_serialize_enter(); 8722 ifp = sc->sc_ifp; 8723 ic = ifp->if_l2com; 8724 iwn_stop_locked(sc); 8725 iwn_init_locked(sc); 8726 ieee80211_notify_radio(ic, 1); 8727 wlan_serialize_exit(); 8728 } 8729 #ifdef IWN_DEBUG 8730 #define IWN_DESC(x) case x: return #x 8731 #define COUNTOF(array) (sizeof(array) / sizeof(array[0])) 8732 8733 /* 8734 * Translate CSR code to string 8735 */ 8736 static char *iwn_get_csr_string(int csr) 8737 { 8738 switch (csr) { 8739 IWN_DESC(IWN_HW_IF_CONFIG); 8740 IWN_DESC(IWN_INT_COALESCING); 8741 IWN_DESC(IWN_INT); 8742 IWN_DESC(IWN_INT_MASK); 8743 IWN_DESC(IWN_FH_INT); 8744 IWN_DESC(IWN_GPIO_IN); 8745 IWN_DESC(IWN_RESET); 8746 IWN_DESC(IWN_GP_CNTRL); 8747 IWN_DESC(IWN_HW_REV); 8748 IWN_DESC(IWN_EEPROM); 8749 IWN_DESC(IWN_EEPROM_GP); 8750 IWN_DESC(IWN_OTP_GP); 8751 IWN_DESC(IWN_GIO); 8752 IWN_DESC(IWN_GP_UCODE); 8753 IWN_DESC(IWN_GP_DRIVER); 8754 IWN_DESC(IWN_UCODE_GP1); 8755 IWN_DESC(IWN_UCODE_GP2); 8756 IWN_DESC(IWN_LED); 8757 IWN_DESC(IWN_DRAM_INT_TBL); 8758 IWN_DESC(IWN_GIO_CHICKEN); 8759 IWN_DESC(IWN_ANA_PLL); 8760 IWN_DESC(IWN_HW_REV_WA); 8761 IWN_DESC(IWN_DBG_HPET_MEM); 8762 default: 8763 return "UNKNOWN CSR"; 8764 } 8765 } 8766 8767 /* 8768 * This function print firmware register 8769 */ 8770 static void 8771 iwn_debug_register(struct iwn_softc *sc) 8772 { 8773 int i; 8774 static const uint32_t csr_tbl[] = { 8775 IWN_HW_IF_CONFIG, 8776 IWN_INT_COALESCING, 8777 IWN_INT, 8778 IWN_INT_MASK, 8779 IWN_FH_INT, 8780 IWN_GPIO_IN, 8781 IWN_RESET, 8782 IWN_GP_CNTRL, 8783 IWN_HW_REV, 8784 IWN_EEPROM, 8785 IWN_EEPROM_GP, 8786 IWN_OTP_GP, 8787 IWN_GIO, 8788 IWN_GP_UCODE, 8789 IWN_GP_DRIVER, 8790 IWN_UCODE_GP1, 8791 IWN_UCODE_GP2, 8792 IWN_LED, 8793 IWN_DRAM_INT_TBL, 8794 IWN_GIO_CHICKEN, 8795 IWN_ANA_PLL, 8796 IWN_HW_REV_WA, 8797 IWN_DBG_HPET_MEM, 8798 }; 8799 DPRINTF(sc, IWN_DEBUG_REGISTER, 8800 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 8801 "\n"); 8802 for (i = 0; i < COUNTOF(csr_tbl); i++){ 8803 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 8804 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 8805 if ((i+1) % 3 == 0) 8806 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 8807 } 8808 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 8809 } 8810 #endif 8811