1 /*- 2 * Copyright (c) 2007-2009 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2008 Benjamin Close <benjsc@FreeBSD.org> 4 * Copyright (c) 2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2011 Intel Corporation 6 * Copyright (c) 2013 Cedric GROSS <c.gross@kreiz-it.fr> 7 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 * $FreeBSD: head/sys/dev/iwn/if_iwn.c 258118 2013-11-14 07:27:00Z adrian $ 22 */ 23 24 /* 25 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 26 * adapters. 27 */ 28 29 #include "opt_wlan.h" 30 #include "opt_iwn.h" 31 32 #include <sys/param.h> 33 #include <sys/sockio.h> 34 #include <sys/sysctl.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/stdbool.h> 41 #include <sys/bus.h> 42 #include <sys/rman.h> 43 #include <sys/endian.h> 44 #include <sys/firmware.h> 45 #include <sys/limits.h> 46 #include <sys/module.h> 47 #include <sys/queue.h> 48 #include <sys/taskqueue.h> 49 #include <sys/libkern.h> 50 51 #include <sys/resource.h> 52 #include <machine/clock.h> 53 54 #include <bus/pci/pcireg.h> 55 #include <bus/pci/pcivar.h> 56 57 #include <net/bpf.h> 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_arp.h> 61 #include <net/ifq_var.h> 62 #include <net/ethernet.h> 63 #include <net/if_dl.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 73 #include <netproto/802_11/ieee80211_var.h> 74 #include <netproto/802_11/ieee80211_radiotap.h> 75 #include <netproto/802_11/ieee80211_regdomain.h> 76 #include <netproto/802_11/ieee80211_ratectl.h> 77 78 #include "if_iwnreg.h" 79 #include "if_iwnvar.h" 80 #include "if_iwn_devid.h" 81 #include "if_iwn_chip_cfg.h" 82 #include "if_iwn_debug.h" 83 #include "if_iwn_ioctl.h" 84 85 #define nitems(ary) (sizeof(ary) / sizeof((ary)[0])) 86 87 #define IWN_LOCK(sc) 88 #define IWN_UNLOCK(sc) 89 90 struct iwn_ident { 91 uint16_t vendor; 92 uint16_t device; 93 const char *name; 94 }; 95 96 static const struct iwn_ident iwn_ident_table[] = { 97 { 0x8086, IWN_DID_6x05_1, "Intel Centrino Advanced-N 6205" }, 98 { 0x8086, IWN_DID_1000_1, "Intel Centrino Wireless-N 1000" }, 99 { 0x8086, IWN_DID_1000_2, "Intel Centrino Wireless-N 1000" }, 100 { 0x8086, IWN_DID_6x05_2, "Intel Centrino Advanced-N 6205" }, 101 { 0x8086, IWN_DID_6050_1, "Intel Centrino Advanced-N + WiMAX 6250" }, 102 { 0x8086, IWN_DID_6050_2, "Intel Centrino Advanced-N + WiMAX 6250" }, 103 { 0x8086, IWN_DID_x030_1, "Intel Centrino Wireless-N 1030" }, 104 { 0x8086, IWN_DID_x030_2, "Intel Centrino Wireless-N 1030" }, 105 { 0x8086, IWN_DID_x030_3, "Intel Centrino Advanced-N 6230" }, 106 { 0x8086, IWN_DID_x030_4, "Intel Centrino Advanced-N 6230" }, 107 { 0x8086, IWN_DID_6150_1, "Intel Centrino Wireless-N + WiMAX 6150" }, 108 { 0x8086, IWN_DID_6150_2, "Intel Centrino Wireless-N + WiMAX 6150" }, 109 { 0x8086, IWN_DID_2x00_1, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 110 { 0x8086, IWN_DID_2x00_2, "Intel(R) Centrino(R) Wireless-N 2200 BGN" }, 111 /* XXX 2200D is IWN_SDID_2x00_4; there's no way to express this here! */ 112 { 0x8086, IWN_DID_2x30_1, "Intel Centrino Wireless-N 2230" }, 113 { 0x8086, IWN_DID_2x30_2, "Intel Centrino Wireless-N 2230" }, 114 { 0x8086, IWN_DID_130_1, "Intel Centrino Wireless-N 130" }, 115 { 0x8086, IWN_DID_130_2, "Intel Centrino Wireless-N 130" }, 116 { 0x8086, IWN_DID_100_1, "Intel Centrino Wireless-N 100" }, 117 { 0x8086, IWN_DID_100_2, "Intel Centrino Wireless-N 100" }, 118 { 0x8086, IWN_DID_105_1, "Intel Centrino Wireless-N 105" }, 119 { 0x8086, IWN_DID_105_2, "Intel Centrino Wireless-N 105" }, 120 { 0x8086, IWN_DID_135_1, "Intel Centrino Wireless-N 135" }, 121 { 0x8086, IWN_DID_135_2, "Intel Centrino Wireless-N 135" }, 122 { 0x8086, IWN_DID_4965_1, "Intel Wireless WiFi Link 4965" }, 123 { 0x8086, IWN_DID_6x00_1, "Intel Centrino Ultimate-N 6300" }, 124 { 0x8086, IWN_DID_6x00_2, "Intel Centrino Advanced-N 6200" }, 125 { 0x8086, IWN_DID_4965_2, "Intel Wireless WiFi Link 4965" }, 126 { 0x8086, IWN_DID_4965_3, "Intel Wireless WiFi Link 4965" }, 127 { 0x8086, IWN_DID_5x00_1, "Intel WiFi Link 5100" }, 128 { 0x8086, IWN_DID_4965_4, "Intel Wireless WiFi Link 4965" }, 129 { 0x8086, IWN_DID_5x00_3, "Intel Ultimate N WiFi Link 5300" }, 130 { 0x8086, IWN_DID_5x00_4, "Intel Ultimate N WiFi Link 5300" }, 131 { 0x8086, IWN_DID_5x00_2, "Intel WiFi Link 5100" }, 132 { 0x8086, IWN_DID_6x00_3, "Intel Centrino Ultimate-N 6300" }, 133 { 0x8086, IWN_DID_6x00_4, "Intel Centrino Advanced-N 6200" }, 134 { 0x8086, IWN_DID_5x50_1, "Intel WiMAX/WiFi Link 5350" }, 135 { 0x8086, IWN_DID_5x50_2, "Intel WiMAX/WiFi Link 5350" }, 136 { 0x8086, IWN_DID_5x50_3, "Intel WiMAX/WiFi Link 5150" }, 137 { 0x8086, IWN_DID_5x50_4, "Intel WiMAX/WiFi Link 5150" }, 138 { 0x8086, IWN_DID_6035_1, "Intel Centrino Advanced 6235" }, 139 { 0x8086, IWN_DID_6035_2, "Intel Centrino Advanced 6235" }, 140 { 0, 0, NULL } 141 }; 142 143 static int iwn_pci_probe(device_t); 144 static int iwn_pci_attach(device_t); 145 static int iwn4965_attach(struct iwn_softc *, uint16_t); 146 static int iwn5000_attach(struct iwn_softc *, uint16_t); 147 static int iwn_config_specific(struct iwn_softc *, uint16_t); 148 static void iwn_radiotap_attach(struct iwn_softc *); 149 static void iwn_sysctlattach(struct iwn_softc *); 150 static struct ieee80211vap *iwn_vap_create(struct ieee80211com *, 151 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 152 const uint8_t [IEEE80211_ADDR_LEN], 153 const uint8_t [IEEE80211_ADDR_LEN]); 154 static void iwn_vap_delete(struct ieee80211vap *); 155 static int iwn_pci_detach(device_t); 156 static int iwn_pci_shutdown(device_t); 157 static int iwn_pci_suspend(device_t); 158 static int iwn_pci_resume(device_t); 159 static int iwn_nic_lock(struct iwn_softc *); 160 static int iwn_eeprom_lock(struct iwn_softc *); 161 static int iwn_init_otprom(struct iwn_softc *); 162 static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 163 static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 164 static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *, 165 void **, bus_size_t, bus_size_t); 166 static void iwn_dma_contig_free(struct iwn_dma_info *); 167 static int iwn_alloc_sched(struct iwn_softc *); 168 static void iwn_free_sched(struct iwn_softc *); 169 static int iwn_alloc_kw(struct iwn_softc *); 170 static void iwn_free_kw(struct iwn_softc *); 171 static int iwn_alloc_ict(struct iwn_softc *); 172 static void iwn_free_ict(struct iwn_softc *); 173 static int iwn_alloc_fwmem(struct iwn_softc *); 174 static void iwn_free_fwmem(struct iwn_softc *); 175 static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 176 static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 177 static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 178 static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 179 int); 180 static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 181 static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 182 static void iwn5000_ict_reset(struct iwn_softc *); 183 static int iwn_read_eeprom(struct iwn_softc *, 184 uint8_t macaddr[IEEE80211_ADDR_LEN]); 185 static void iwn4965_read_eeprom(struct iwn_softc *); 186 #ifdef IWN_DEBUG 187 static void iwn4965_print_power_group(struct iwn_softc *, int); 188 #endif 189 static void iwn5000_read_eeprom(struct iwn_softc *); 190 static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *); 191 static void iwn_read_eeprom_band(struct iwn_softc *, int); 192 static void iwn_read_eeprom_ht40(struct iwn_softc *, int); 193 static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 194 static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *, 195 struct ieee80211_channel *); 196 static int iwn_setregdomain(struct ieee80211com *, 197 struct ieee80211_regdomain *, int, 198 struct ieee80211_channel[]); 199 static void iwn_read_eeprom_enhinfo(struct iwn_softc *); 200 static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *, 201 const uint8_t mac[IEEE80211_ADDR_LEN]); 202 static void iwn_newassoc(struct ieee80211_node *, int); 203 static int iwn_media_change(struct ifnet *); 204 static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 205 static void iwn_calib_timeout(void *); 206 static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 207 struct iwn_rx_data *); 208 static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 209 struct iwn_rx_data *); 210 static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 211 struct iwn_rx_data *); 212 static void iwn5000_rx_calib_results(struct iwn_softc *, 213 struct iwn_rx_desc *, struct iwn_rx_data *); 214 static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 215 struct iwn_rx_data *); 216 static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 217 struct iwn_rx_data *); 218 static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 219 struct iwn_rx_data *); 220 static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int, 221 uint8_t); 222 static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *); 223 static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 224 static void iwn_notif_intr(struct iwn_softc *); 225 static void iwn_wakeup_intr(struct iwn_softc *); 226 static void iwn_rftoggle_intr(struct iwn_softc *); 227 static void iwn_fatal_intr(struct iwn_softc *); 228 static void iwn_intr(void *); 229 static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 230 uint16_t); 231 static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 232 uint16_t); 233 #ifdef notyet 234 static void iwn5000_reset_sched(struct iwn_softc *, int, int); 235 #endif 236 static int iwn_tx_data(struct iwn_softc *, struct mbuf *, 237 struct ieee80211_node *); 238 static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *, 239 struct ieee80211_node *, 240 const struct ieee80211_bpf_params *params); 241 static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 242 const struct ieee80211_bpf_params *); 243 static void iwn_start(struct ifnet *, struct ifaltq_subque *); 244 static void iwn_start_locked(struct ifnet *); 245 static void iwn_watchdog_timeout(void *); 246 static int iwn_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 247 static int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 248 static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 249 int); 250 static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 251 int); 252 static int iwn_set_link_quality(struct iwn_softc *, 253 struct ieee80211_node *); 254 static int iwn_add_broadcast_node(struct iwn_softc *, int); 255 static int iwn_updateedca(struct ieee80211com *); 256 static void iwn_update_mcast(struct ifnet *); 257 static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 258 static int iwn_set_critical_temp(struct iwn_softc *); 259 static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 260 static void iwn4965_power_calibration(struct iwn_softc *, int); 261 static int iwn4965_set_txpower(struct iwn_softc *, 262 struct ieee80211_channel *, int); 263 static int iwn5000_set_txpower(struct iwn_softc *, 264 struct ieee80211_channel *, int); 265 static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 266 static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *); 267 static int iwn_get_noise(const struct iwn_rx_general_stats *); 268 static int iwn4965_get_temperature(struct iwn_softc *); 269 static int iwn5000_get_temperature(struct iwn_softc *); 270 static int iwn_init_sensitivity(struct iwn_softc *); 271 static void iwn_collect_noise(struct iwn_softc *, 272 const struct iwn_rx_general_stats *); 273 static int iwn4965_init_gains(struct iwn_softc *); 274 static int iwn5000_init_gains(struct iwn_softc *); 275 static int iwn4965_set_gains(struct iwn_softc *); 276 static int iwn5000_set_gains(struct iwn_softc *); 277 static void iwn_tune_sensitivity(struct iwn_softc *, 278 const struct iwn_rx_stats *); 279 static void iwn_save_stats_counters(struct iwn_softc *, 280 const struct iwn_stats *); 281 static int iwn_send_sensitivity(struct iwn_softc *); 282 static void iwn_check_rx_recovery(struct iwn_softc *, struct iwn_stats *); 283 static int iwn_set_pslevel(struct iwn_softc *, int, int, int); 284 static int iwn_send_btcoex(struct iwn_softc *); 285 static int iwn_send_advanced_btcoex(struct iwn_softc *); 286 static int iwn5000_runtime_calib(struct iwn_softc *); 287 static int iwn_config(struct iwn_softc *); 288 static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int); 289 static int iwn_scan(struct iwn_softc *, struct ieee80211vap *, 290 struct ieee80211_scan_state *, struct ieee80211_channel *); 291 static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap); 292 static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap); 293 static int iwn_ampdu_rx_start(struct ieee80211_node *, 294 struct ieee80211_rx_ampdu *, int, int, int); 295 static void iwn_ampdu_rx_stop(struct ieee80211_node *, 296 struct ieee80211_rx_ampdu *); 297 static int iwn_addba_request(struct ieee80211_node *, 298 struct ieee80211_tx_ampdu *, int, int, int); 299 static int iwn_addba_response(struct ieee80211_node *, 300 struct ieee80211_tx_ampdu *, int, int, int); 301 static int iwn_ampdu_tx_start(struct ieee80211com *, 302 struct ieee80211_node *, uint8_t); 303 static void iwn_ampdu_tx_stop(struct ieee80211_node *, 304 struct ieee80211_tx_ampdu *); 305 static void iwn4965_ampdu_tx_start(struct iwn_softc *, 306 struct ieee80211_node *, int, uint8_t, uint16_t); 307 static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int, 308 uint8_t, uint16_t); 309 static void iwn5000_ampdu_tx_start(struct iwn_softc *, 310 struct ieee80211_node *, int, uint8_t, uint16_t); 311 static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int, 312 uint8_t, uint16_t); 313 static int iwn5000_query_calibration(struct iwn_softc *); 314 static int iwn5000_send_calibration(struct iwn_softc *); 315 static int iwn5000_send_wimax_coex(struct iwn_softc *); 316 static int iwn5000_crystal_calib(struct iwn_softc *); 317 static int iwn5000_temp_offset_calib(struct iwn_softc *); 318 static int iwn5000_temp_offset_calibv2(struct iwn_softc *); 319 static int iwn4965_post_alive(struct iwn_softc *); 320 static int iwn5000_post_alive(struct iwn_softc *); 321 static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 322 int); 323 static int iwn4965_load_firmware(struct iwn_softc *); 324 static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 325 const uint8_t *, int); 326 static int iwn5000_load_firmware(struct iwn_softc *); 327 static int iwn_read_firmware_leg(struct iwn_softc *, 328 struct iwn_fw_info *); 329 static int iwn_read_firmware_tlv(struct iwn_softc *, 330 struct iwn_fw_info *, uint16_t); 331 static int iwn_read_firmware(struct iwn_softc *); 332 static int iwn_clock_wait(struct iwn_softc *); 333 static int iwn_apm_init(struct iwn_softc *); 334 static void iwn_apm_stop_master(struct iwn_softc *); 335 static void iwn_apm_stop(struct iwn_softc *); 336 static int iwn4965_nic_config(struct iwn_softc *); 337 static int iwn5000_nic_config(struct iwn_softc *); 338 static int iwn_hw_prepare(struct iwn_softc *); 339 static int iwn_hw_init(struct iwn_softc *); 340 static void iwn_hw_stop(struct iwn_softc *); 341 static void iwn_radio_on_task(void *, int); 342 static void iwn_radio_off_task(void *, int); 343 static void iwn_panicked_task(void *, int); 344 static void iwn_init_locked(struct iwn_softc *); 345 static void iwn_init(void *); 346 static void iwn_stop_locked(struct iwn_softc *); 347 static void iwn_scan_start(struct ieee80211com *); 348 static void iwn_scan_end(struct ieee80211com *); 349 static void iwn_set_channel(struct ieee80211com *); 350 static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long); 351 static void iwn_scan_mindwell(struct ieee80211_scan_state *); 352 static void iwn_hw_reset_task(void *, int); 353 #ifdef IWN_DEBUG 354 static char *iwn_get_csr_string(int); 355 static void iwn_debug_register(struct iwn_softc *); 356 #endif 357 358 static device_method_t iwn_methods[] = { 359 /* Device interface */ 360 DEVMETHOD(device_probe, iwn_pci_probe), 361 DEVMETHOD(device_attach, iwn_pci_attach), 362 DEVMETHOD(device_detach, iwn_pci_detach), 363 DEVMETHOD(device_shutdown, iwn_pci_shutdown), 364 DEVMETHOD(device_suspend, iwn_pci_suspend), 365 DEVMETHOD(device_resume, iwn_pci_resume), 366 367 DEVMETHOD_END 368 }; 369 370 static driver_t iwn_driver = { 371 "iwn", 372 iwn_methods, 373 sizeof(struct iwn_softc) 374 }; 375 static devclass_t iwn_devclass; 376 377 DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, NULL, NULL); 378 379 MODULE_VERSION(iwn, 1); 380 381 MODULE_DEPEND(iwn, firmware, 1, 1, 1); 382 MODULE_DEPEND(iwn, pci, 1, 1, 1); 383 MODULE_DEPEND(iwn, wlan, 1, 1, 1); 384 MODULE_DEPEND(iwn, wlan_amrr, 1, 1, 1); 385 386 static int 387 iwn_pci_probe(device_t dev) 388 { 389 const struct iwn_ident *ident; 390 391 /* no wlan serializer needed */ 392 for (ident = iwn_ident_table; ident->name != NULL; ident++) { 393 if (pci_get_vendor(dev) == ident->vendor && 394 pci_get_device(dev) == ident->device) { 395 device_set_desc(dev, ident->name); 396 return (BUS_PROBE_DEFAULT); 397 } 398 } 399 return ENXIO; 400 } 401 402 static int 403 iwn_pci_attach(device_t dev) 404 { 405 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev); 406 struct ieee80211com *ic; 407 struct ifnet *ifp; 408 int i, error, rid; 409 uint8_t macaddr[IEEE80211_ADDR_LEN]; 410 char ethstr[ETHER_ADDRSTRLEN + 1]; 411 412 wlan_serialize_enter(); 413 414 sc->sc_dev = dev; 415 sc->sc_dmat = NULL; 416 417 if (bus_dma_tag_create(sc->sc_dmat, 418 1, 0, 419 BUS_SPACE_MAXADDR_32BIT, 420 BUS_SPACE_MAXADDR, 421 NULL, NULL, 422 BUS_SPACE_MAXSIZE, 423 IWN_MAX_SCATTER, 424 BUS_SPACE_MAXSIZE, 425 BUS_DMA_ALLOCNOW, 426 &sc->sc_dmat)) { 427 device_printf(dev, "cannot allocate DMA tag\n"); 428 error = ENOMEM; 429 goto fail; 430 } 431 432 /* prepare sysctl tree for use in sub modules */ 433 sysctl_ctx_init(&sc->sc_sysctl_ctx); 434 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx, 435 SYSCTL_STATIC_CHILDREN(_hw), 436 OID_AUTO, 437 device_get_nameunit(sc->sc_dev), 438 CTLFLAG_RD, 0, ""); 439 440 #ifdef IWN_DEBUG 441 error = resource_int_value(device_get_name(sc->sc_dev), 442 device_get_unit(sc->sc_dev), "debug", &(sc->sc_debug)); 443 if (error != 0) 444 sc->sc_debug = 0; 445 #else 446 sc->sc_debug = 0; 447 #endif 448 449 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: begin\n",__func__); 450 451 /* 452 * Get the offset of the PCI Express Capability Structure in PCI 453 * Configuration Space. 454 */ 455 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 456 if (error != 0) { 457 device_printf(dev, "PCIe capability structure not found!\n"); 458 goto fail2; 459 } 460 461 /* Clear device-specific "PCI retry timeout" register (41h). */ 462 pci_write_config(dev, 0x41, 0, 1); 463 464 /* Enable bus-mastering. */ 465 pci_enable_busmaster(dev); 466 467 rid = PCIR_BAR(0); 468 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 469 RF_ACTIVE); 470 if (sc->mem == NULL) { 471 device_printf(dev, "can't map mem space\n"); 472 error = ENOMEM; 473 goto fail2; 474 } 475 sc->sc_st = rman_get_bustag(sc->mem); 476 sc->sc_sh = rman_get_bushandle(sc->mem); 477 478 rid = 0; 479 #ifdef OLD_MSI 480 i = 1; 481 if (pci_alloc_msi(dev, &i) == 0) 482 rid = 1; 483 #endif 484 /* Install interrupt handler. */ 485 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 486 (rid != 0 ? 0 : RF_SHAREABLE)); 487 if (sc->irq == NULL) { 488 device_printf(dev, "can't map interrupt\n"); 489 error = ENOMEM; 490 goto fail; 491 } 492 493 /* Read hardware revision and attach. */ 494 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> IWN_HW_REV_TYPE_SHIFT) 495 & IWN_HW_REV_TYPE_MASK; 496 sc->subdevice_id = pci_get_subdevice(dev); 497 /* 498 * 4965 versus 5000 and later have different methods. 499 * Let's set those up first. 500 */ 501 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 502 error = iwn4965_attach(sc, pci_get_device(dev)); 503 else 504 error = iwn5000_attach(sc, pci_get_device(dev)); 505 if (error != 0) { 506 device_printf(dev, "could not attach device, error %d\n", 507 error); 508 goto fail; 509 } 510 511 /* 512 * Next, let's setup the various parameters of each NIC. 513 */ 514 error = iwn_config_specific(sc, pci_get_device(dev)); 515 if (error != 0) { 516 device_printf(dev, "could not attach device, error %d\n", 517 error); 518 goto fail; 519 } 520 521 if ((error = iwn_hw_prepare(sc)) != 0) { 522 device_printf(dev, "hardware not ready, error %d\n", error); 523 goto fail; 524 } 525 526 /* Allocate DMA memory for firmware transfers. */ 527 if ((error = iwn_alloc_fwmem(sc)) != 0) { 528 device_printf(dev, 529 "could not allocate memory for firmware, error %d\n", 530 error); 531 goto fail; 532 } 533 534 /* Allocate "Keep Warm" page. */ 535 if ((error = iwn_alloc_kw(sc)) != 0) { 536 device_printf(dev, 537 "could not allocate keep warm page, error %d\n", error); 538 goto fail; 539 } 540 541 /* Allocate ICT table for 5000 Series. */ 542 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 543 (error = iwn_alloc_ict(sc)) != 0) { 544 device_printf(dev, "could not allocate ICT table, error %d\n", 545 error); 546 goto fail; 547 } 548 549 /* Allocate TX scheduler "rings". */ 550 if ((error = iwn_alloc_sched(sc)) != 0) { 551 device_printf(dev, 552 "could not allocate TX scheduler rings, error %d\n", error); 553 goto fail; 554 } 555 556 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 557 for (i = 0; i < sc->ntxqs; i++) { 558 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 559 device_printf(dev, 560 "could not allocate TX ring %d, error %d\n", i, 561 error); 562 goto fail; 563 } 564 } 565 566 /* Allocate RX ring. */ 567 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 568 device_printf(dev, "could not allocate RX ring, error %d\n", 569 error); 570 goto fail; 571 } 572 573 /* Clear pending interrupts. */ 574 IWN_WRITE(sc, IWN_INT, 0xffffffff); 575 576 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 577 if (ifp == NULL) { 578 device_printf(dev, "can not allocate ifnet structure\n"); 579 goto fail; 580 } 581 582 ic = ifp->if_l2com; 583 ic->ic_ifp = ifp; 584 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 585 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 586 587 /* Set device capabilities. */ 588 ic->ic_caps = 589 IEEE80211_C_STA /* station mode supported */ 590 | IEEE80211_C_MONITOR /* monitor mode supported */ 591 | IEEE80211_C_BGSCAN /* background scanning */ 592 | IEEE80211_C_TXPMGT /* tx power management */ 593 | IEEE80211_C_SHSLOT /* short slot time supported */ 594 | IEEE80211_C_WPA 595 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 596 #if 0 597 | IEEE80211_C_IBSS /* ibss/adhoc mode */ 598 #endif 599 | IEEE80211_C_WME /* WME */ 600 | IEEE80211_C_PMGT /* Station-side power mgmt */ 601 ; 602 603 /* Read MAC address, channels, etc from EEPROM. */ 604 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) { 605 device_printf(dev, "could not read EEPROM, error %d\n", 606 error); 607 goto fail; 608 } 609 610 /* Count the number of available chains. */ 611 sc->ntxchains = 612 ((sc->txchainmask >> 2) & 1) + 613 ((sc->txchainmask >> 1) & 1) + 614 ((sc->txchainmask >> 0) & 1); 615 sc->nrxchains = 616 ((sc->rxchainmask >> 2) & 1) + 617 ((sc->rxchainmask >> 1) & 1) + 618 ((sc->rxchainmask >> 0) & 1); 619 if (bootverbose) { 620 device_printf(dev, "MIMO %dT%dR, %.4s, address %s\n", 621 sc->ntxchains, sc->nrxchains, sc->eeprom_domain, 622 kether_ntoa(macaddr, ethstr)); 623 } 624 625 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 626 #ifdef notyet 627 ic->ic_rxstream = sc->nrxchains; 628 ic->ic_txstream = sc->ntxchains; 629 #endif 630 631 /* 632 * The NICs we currently support cap out at 2x2 support 633 * separate from the chains being used. 634 * 635 * This is a total hack to work around that until some 636 * per-device method is implemented to return the 637 * actual stream support. 638 * 639 * XXX Note: the 5350 is a 3x3 device; so we shouldn't 640 * cap this! But, anything that touches rates in the 641 * driver needs to be audited first before 3x3 is enabled. 642 */ 643 #ifdef notyet 644 if (ic->ic_rxstream > 2) 645 ic->ic_rxstream = 2; 646 if (ic->ic_txstream > 2) 647 ic->ic_txstream = 2; 648 #endif 649 650 ic->ic_htcaps = 651 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */ 652 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */ 653 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/ 654 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */ 655 #ifdef notyet 656 | IEEE80211_HTCAP_GREENFIELD 657 #if IWN_RBUF_SIZE == 8192 658 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */ 659 #else 660 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */ 661 #endif 662 #endif 663 /* s/w capabilities */ 664 | IEEE80211_HTC_HT /* HT operation */ 665 | IEEE80211_HTC_AMPDU /* tx A-MPDU */ 666 #ifdef notyet 667 | IEEE80211_HTC_AMSDU /* tx A-MSDU */ 668 #endif 669 ; 670 } 671 672 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 673 ifp->if_softc = sc; 674 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 675 ifp->if_init = iwn_init; 676 ifp->if_ioctl = iwn_ioctl; 677 ifp->if_start = iwn_start; 678 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 679 #ifdef notyet 680 ifq_set_ready(&ifp->if_snd); 681 #endif 682 683 ieee80211_ifattach(ic, macaddr); 684 ic->ic_vap_create = iwn_vap_create; 685 ic->ic_vap_delete = iwn_vap_delete; 686 ic->ic_raw_xmit = iwn_raw_xmit; 687 ic->ic_node_alloc = iwn_node_alloc; 688 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start; 689 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 690 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop; 691 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 692 sc->sc_addba_request = ic->ic_addba_request; 693 ic->ic_addba_request = iwn_addba_request; 694 sc->sc_addba_response = ic->ic_addba_response; 695 ic->ic_addba_response = iwn_addba_response; 696 sc->sc_addba_stop = ic->ic_addba_stop; 697 ic->ic_addba_stop = iwn_ampdu_tx_stop; 698 ic->ic_newassoc = iwn_newassoc; 699 ic->ic_wme.wme_update = iwn_updateedca; 700 ic->ic_update_mcast = iwn_update_mcast; 701 ic->ic_scan_start = iwn_scan_start; 702 ic->ic_scan_end = iwn_scan_end; 703 ic->ic_set_channel = iwn_set_channel; 704 ic->ic_scan_curchan = iwn_scan_curchan; 705 ic->ic_scan_mindwell = iwn_scan_mindwell; 706 ic->ic_setregdomain = iwn_setregdomain; 707 708 iwn_radiotap_attach(sc); 709 710 callout_init(&sc->calib_to); 711 callout_init(&sc->watchdog_to); 712 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset_task, sc); 713 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on_task, sc); 714 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off_task, sc); 715 TASK_INIT(&sc->sc_panic_task, 0, iwn_panicked_task, sc); 716 717 sc->sc_tq = taskqueue_create("iwn_taskq", M_WAITOK, 718 taskqueue_thread_enqueue, &sc->sc_tq); 719 error = taskqueue_start_threads(&sc->sc_tq, 1, TDPRI_KERN_DAEMON, -1, 720 "iwn_taskq"); 721 if (error != 0) { 722 device_printf(dev, "can't start threads, error %d\n", error); 723 goto fail; 724 } 725 726 iwn_sysctlattach(sc); 727 728 /* 729 * Hook our interrupt after all initialization is complete. 730 */ 731 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE, 732 iwn_intr, sc, &sc->sc_ih, 733 &wlan_global_serializer); 734 if (error != 0) { 735 device_printf(dev, "can't establish interrupt, error %d\n", 736 error); 737 goto fail; 738 } 739 740 #if 0 741 device_printf(sc->sc_dev, "%s: rx_stats=%d, rx_stats_bt=%d\n", 742 __func__, 743 sizeof(struct iwn_stats), 744 sizeof(struct iwn_stats_bt)); 745 #endif 746 747 if (bootverbose) 748 ieee80211_announce(ic); 749 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 750 wlan_serialize_exit(); 751 return 0; 752 fail: 753 wlan_serialize_exit(); 754 iwn_pci_detach(dev); 755 wlan_serialize_enter(); 756 fail2: 757 wlan_serialize_exit(); 758 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 759 return error; 760 } 761 762 /* 763 * Define specific configuration based on device id and subdevice id 764 * pid : PCI device id 765 */ 766 static int 767 iwn_config_specific(struct iwn_softc *sc, uint16_t pid) 768 { 769 770 switch (pid) { 771 /* 4965 series */ 772 case IWN_DID_4965_1: 773 case IWN_DID_4965_2: 774 case IWN_DID_4965_3: 775 case IWN_DID_4965_4: 776 sc->base_params = &iwn4965_base_params; 777 sc->limits = &iwn4965_sensitivity_limits; 778 sc->fwname = "iwn4965fw"; 779 /* Override chains masks, ROM is known to be broken. */ 780 sc->txchainmask = IWN_ANT_AB; 781 sc->rxchainmask = IWN_ANT_ABC; 782 /* Enable normal btcoex */ 783 sc->sc_flags |= IWN_FLAG_BTCOEX; 784 break; 785 /* 1000 Series */ 786 case IWN_DID_1000_1: 787 case IWN_DID_1000_2: 788 switch(sc->subdevice_id) { 789 case IWN_SDID_1000_1: 790 case IWN_SDID_1000_2: 791 case IWN_SDID_1000_3: 792 case IWN_SDID_1000_4: 793 case IWN_SDID_1000_5: 794 case IWN_SDID_1000_6: 795 case IWN_SDID_1000_7: 796 case IWN_SDID_1000_8: 797 case IWN_SDID_1000_9: 798 case IWN_SDID_1000_10: 799 case IWN_SDID_1000_11: 800 case IWN_SDID_1000_12: 801 sc->limits = &iwn1000_sensitivity_limits; 802 sc->base_params = &iwn1000_base_params; 803 sc->fwname = "iwn1000fw"; 804 break; 805 default: 806 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 807 "0x%04x rev %d not supported (subdevice)\n", pid, 808 sc->subdevice_id,sc->hw_type); 809 return ENOTSUP; 810 } 811 break; 812 /* 6x00 Series */ 813 case IWN_DID_6x00_2: 814 case IWN_DID_6x00_4: 815 case IWN_DID_6x00_1: 816 case IWN_DID_6x00_3: 817 sc->fwname = "iwn6000fw"; 818 sc->limits = &iwn6000_sensitivity_limits; 819 switch(sc->subdevice_id) { 820 case IWN_SDID_6x00_1: 821 case IWN_SDID_6x00_2: 822 case IWN_SDID_6x00_8: 823 //iwl6000_3agn_cfg 824 sc->base_params = &iwn_6000_base_params; 825 break; 826 case IWN_SDID_6x00_3: 827 case IWN_SDID_6x00_6: 828 case IWN_SDID_6x00_9: 829 ////iwl6000i_2agn 830 case IWN_SDID_6x00_4: 831 case IWN_SDID_6x00_7: 832 case IWN_SDID_6x00_10: 833 //iwl6000i_2abg_cfg 834 case IWN_SDID_6x00_5: 835 //iwl6000i_2bg_cfg 836 sc->base_params = &iwn_6000i_base_params; 837 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 838 sc->txchainmask = IWN_ANT_BC; 839 sc->rxchainmask = IWN_ANT_BC; 840 break; 841 default: 842 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 843 "0x%04x rev %d not supported (subdevice)\n", pid, 844 sc->subdevice_id,sc->hw_type); 845 return ENOTSUP; 846 } 847 break; 848 /* 6x05 Series */ 849 case IWN_DID_6x05_1: 850 case IWN_DID_6x05_2: 851 switch(sc->subdevice_id) { 852 case IWN_SDID_6x05_1: 853 case IWN_SDID_6x05_4: 854 case IWN_SDID_6x05_6: 855 //iwl6005_2agn_cfg 856 case IWN_SDID_6x05_2: 857 case IWN_SDID_6x05_5: 858 case IWN_SDID_6x05_7: 859 //iwl6005_2abg_cfg 860 case IWN_SDID_6x05_3: 861 //iwl6005_2bg_cfg 862 case IWN_SDID_6x05_8: 863 case IWN_SDID_6x05_9: 864 //iwl6005_2agn_sff_cfg 865 case IWN_SDID_6x05_10: 866 //iwl6005_2agn_d_cfg 867 case IWN_SDID_6x05_11: 868 //iwl6005_2agn_mow1_cfg 869 case IWN_SDID_6x05_12: 870 //iwl6005_2agn_mow2_cfg 871 sc->fwname = "iwn6000g2afw"; 872 sc->limits = &iwn6000_sensitivity_limits; 873 sc->base_params = &iwn_6000g2_base_params; 874 break; 875 default: 876 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 877 "0x%04x rev %d not supported (subdevice)\n", pid, 878 sc->subdevice_id,sc->hw_type); 879 return ENOTSUP; 880 } 881 break; 882 /* 6x35 Series */ 883 case IWN_DID_6035_1: 884 case IWN_DID_6035_2: 885 switch(sc->subdevice_id) { 886 case IWN_SDID_6035_1: 887 case IWN_SDID_6035_2: 888 case IWN_SDID_6035_3: 889 case IWN_SDID_6035_4: 890 sc->fwname = "iwn6000g2bfw"; 891 sc->limits = &iwn6235_sensitivity_limits; 892 sc->base_params = &iwn_6235_base_params; 893 break; 894 default: 895 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 896 "0x%04x rev %d not supported (subdevice)\n", pid, 897 sc->subdevice_id,sc->hw_type); 898 return ENOTSUP; 899 } 900 break; 901 /* 6x50 WiFi/WiMax Series */ 902 case IWN_DID_6050_1: 903 case IWN_DID_6050_2: 904 switch(sc->subdevice_id) { 905 case IWN_SDID_6050_1: 906 case IWN_SDID_6050_3: 907 case IWN_SDID_6050_5: 908 //iwl6050_2agn_cfg 909 case IWN_SDID_6050_2: 910 case IWN_SDID_6050_4: 911 case IWN_SDID_6050_6: 912 //iwl6050_2abg_cfg 913 sc->fwname = "iwn6050fw"; 914 sc->txchainmask = IWN_ANT_AB; 915 sc->rxchainmask = IWN_ANT_AB; 916 sc->limits = &iwn6000_sensitivity_limits; 917 sc->base_params = &iwn_6050_base_params; 918 break; 919 default: 920 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 921 "0x%04x rev %d not supported (subdevice)\n", pid, 922 sc->subdevice_id,sc->hw_type); 923 return ENOTSUP; 924 } 925 break; 926 /* 6150 WiFi/WiMax Series */ 927 case IWN_DID_6150_1: 928 case IWN_DID_6150_2: 929 switch(sc->subdevice_id) { 930 case IWN_SDID_6150_1: 931 case IWN_SDID_6150_3: 932 case IWN_SDID_6150_5: 933 // iwl6150_bgn_cfg 934 case IWN_SDID_6150_2: 935 case IWN_SDID_6150_4: 936 case IWN_SDID_6150_6: 937 //iwl6150_bg_cfg 938 sc->fwname = "iwn6050fw"; 939 sc->limits = &iwn6000_sensitivity_limits; 940 sc->base_params = &iwn_6150_base_params; 941 break; 942 default: 943 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 944 "0x%04x rev %d not supported (subdevice)\n", pid, 945 sc->subdevice_id,sc->hw_type); 946 return ENOTSUP; 947 } 948 break; 949 /* 6030 Series and 1030 Series */ 950 case IWN_DID_x030_1: 951 case IWN_DID_x030_2: 952 case IWN_DID_x030_3: 953 case IWN_DID_x030_4: 954 switch(sc->subdevice_id) { 955 case IWN_SDID_x030_1: 956 case IWN_SDID_x030_3: 957 case IWN_SDID_x030_5: 958 // iwl1030_bgn_cfg 959 case IWN_SDID_x030_2: 960 case IWN_SDID_x030_4: 961 case IWN_SDID_x030_6: 962 //iwl1030_bg_cfg 963 case IWN_SDID_x030_7: 964 case IWN_SDID_x030_10: 965 case IWN_SDID_x030_14: 966 //iwl6030_2agn_cfg 967 case IWN_SDID_x030_8: 968 case IWN_SDID_x030_11: 969 case IWN_SDID_x030_15: 970 // iwl6030_2bgn_cfg 971 case IWN_SDID_x030_9: 972 case IWN_SDID_x030_12: 973 case IWN_SDID_x030_16: 974 // iwl6030_2abg_cfg 975 case IWN_SDID_x030_13: 976 //iwl6030_2bg_cfg 977 sc->fwname = "iwn6000g2bfw"; 978 sc->limits = &iwn6000_sensitivity_limits; 979 sc->base_params = &iwn_6000g2b_base_params; 980 break; 981 default: 982 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 983 "0x%04x rev %d not supported (subdevice)\n", pid, 984 sc->subdevice_id,sc->hw_type); 985 return ENOTSUP; 986 } 987 break; 988 /* 130 Series WiFi */ 989 /* XXX: This series will need adjustment for rate. 990 * see rx_with_siso_diversity in linux kernel 991 */ 992 case IWN_DID_130_1: 993 case IWN_DID_130_2: 994 switch(sc->subdevice_id) { 995 case IWN_SDID_130_1: 996 case IWN_SDID_130_3: 997 case IWN_SDID_130_5: 998 //iwl130_bgn_cfg 999 case IWN_SDID_130_2: 1000 case IWN_SDID_130_4: 1001 case IWN_SDID_130_6: 1002 //iwl130_bg_cfg 1003 sc->fwname = "iwn6000g2bfw"; 1004 sc->limits = &iwn6000_sensitivity_limits; 1005 sc->base_params = &iwn_6000g2b_base_params; 1006 break; 1007 default: 1008 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1009 "0x%04x rev %d not supported (subdevice)\n", pid, 1010 sc->subdevice_id,sc->hw_type); 1011 return ENOTSUP; 1012 } 1013 break; 1014 /* 100 Series WiFi */ 1015 case IWN_DID_100_1: 1016 case IWN_DID_100_2: 1017 switch(sc->subdevice_id) { 1018 case IWN_SDID_100_1: 1019 case IWN_SDID_100_2: 1020 case IWN_SDID_100_3: 1021 case IWN_SDID_100_4: 1022 case IWN_SDID_100_5: 1023 case IWN_SDID_100_6: 1024 sc->limits = &iwn1000_sensitivity_limits; 1025 sc->base_params = &iwn1000_base_params; 1026 sc->fwname = "iwn100fw"; 1027 break; 1028 default: 1029 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1030 "0x%04x rev %d not supported (subdevice)\n", pid, 1031 sc->subdevice_id,sc->hw_type); 1032 return ENOTSUP; 1033 } 1034 break; 1035 1036 /* 105 Series */ 1037 /* XXX: This series will need adjustment for rate. 1038 * see rx_with_siso_diversity in linux kernel 1039 */ 1040 case IWN_DID_105_1: 1041 case IWN_DID_105_2: 1042 switch(sc->subdevice_id) { 1043 case IWN_SDID_105_1: 1044 case IWN_SDID_105_2: 1045 case IWN_SDID_105_3: 1046 //iwl105_bgn_cfg 1047 case IWN_SDID_105_4: 1048 //iwl105_bgn_d_cfg 1049 sc->limits = &iwn2030_sensitivity_limits; 1050 sc->base_params = &iwn2000_base_params; 1051 sc->fwname = "iwn105fw"; 1052 break; 1053 default: 1054 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1055 "0x%04x rev %d not supported (subdevice)\n", pid, 1056 sc->subdevice_id,sc->hw_type); 1057 return ENOTSUP; 1058 } 1059 break; 1060 1061 /* 135 Series */ 1062 /* XXX: This series will need adjustment for rate. 1063 * see rx_with_siso_diversity in linux kernel 1064 */ 1065 case IWN_DID_135_1: 1066 case IWN_DID_135_2: 1067 switch(sc->subdevice_id) { 1068 case IWN_SDID_135_1: 1069 case IWN_SDID_135_2: 1070 case IWN_SDID_135_3: 1071 sc->limits = &iwn2030_sensitivity_limits; 1072 sc->base_params = &iwn2030_base_params; 1073 sc->fwname = "iwn135fw"; 1074 break; 1075 default: 1076 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1077 "0x%04x rev %d not supported (subdevice)\n", pid, 1078 sc->subdevice_id,sc->hw_type); 1079 return ENOTSUP; 1080 } 1081 break; 1082 1083 /* 2x00 Series */ 1084 case IWN_DID_2x00_1: 1085 case IWN_DID_2x00_2: 1086 switch(sc->subdevice_id) { 1087 case IWN_SDID_2x00_1: 1088 case IWN_SDID_2x00_2: 1089 case IWN_SDID_2x00_3: 1090 //iwl2000_2bgn_cfg 1091 case IWN_SDID_2x00_4: 1092 //iwl2000_2bgn_d_cfg 1093 sc->limits = &iwn2030_sensitivity_limits; 1094 sc->base_params = &iwn2000_base_params; 1095 sc->fwname = "iwn2000fw"; 1096 break; 1097 default: 1098 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1099 "0x%04x rev %d not supported (subdevice) \n", 1100 pid, sc->subdevice_id, sc->hw_type); 1101 return ENOTSUP; 1102 } 1103 break; 1104 /* 2x30 Series */ 1105 case IWN_DID_2x30_1: 1106 case IWN_DID_2x30_2: 1107 switch(sc->subdevice_id) { 1108 case IWN_SDID_2x30_1: 1109 case IWN_SDID_2x30_3: 1110 case IWN_SDID_2x30_5: 1111 //iwl100_bgn_cfg 1112 case IWN_SDID_2x30_2: 1113 case IWN_SDID_2x30_4: 1114 case IWN_SDID_2x30_6: 1115 //iwl100_bg_cfg 1116 sc->limits = &iwn2030_sensitivity_limits; 1117 sc->base_params = &iwn2030_base_params; 1118 sc->fwname = "iwn2030fw"; 1119 break; 1120 default: 1121 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1122 "0x%04x rev %d not supported (subdevice)\n", pid, 1123 sc->subdevice_id,sc->hw_type); 1124 return ENOTSUP; 1125 } 1126 break; 1127 /* 5x00 Series */ 1128 case IWN_DID_5x00_1: 1129 case IWN_DID_5x00_2: 1130 case IWN_DID_5x00_3: 1131 case IWN_DID_5x00_4: 1132 sc->limits = &iwn5000_sensitivity_limits; 1133 sc->base_params = &iwn5000_base_params; 1134 sc->fwname = "iwn5000fw"; 1135 switch(sc->subdevice_id) { 1136 case IWN_SDID_5x00_1: 1137 case IWN_SDID_5x00_2: 1138 case IWN_SDID_5x00_3: 1139 case IWN_SDID_5x00_4: 1140 case IWN_SDID_5x00_9: 1141 case IWN_SDID_5x00_10: 1142 case IWN_SDID_5x00_11: 1143 case IWN_SDID_5x00_12: 1144 case IWN_SDID_5x00_17: 1145 case IWN_SDID_5x00_18: 1146 case IWN_SDID_5x00_19: 1147 case IWN_SDID_5x00_20: 1148 //iwl5100_agn_cfg 1149 sc->txchainmask = IWN_ANT_B; 1150 sc->rxchainmask = IWN_ANT_AB; 1151 break; 1152 case IWN_SDID_5x00_5: 1153 case IWN_SDID_5x00_6: 1154 case IWN_SDID_5x00_13: 1155 case IWN_SDID_5x00_14: 1156 case IWN_SDID_5x00_21: 1157 case IWN_SDID_5x00_22: 1158 //iwl5100_bgn_cfg 1159 sc->txchainmask = IWN_ANT_B; 1160 sc->rxchainmask = IWN_ANT_AB; 1161 break; 1162 case IWN_SDID_5x00_7: 1163 case IWN_SDID_5x00_8: 1164 case IWN_SDID_5x00_15: 1165 case IWN_SDID_5x00_16: 1166 case IWN_SDID_5x00_23: 1167 case IWN_SDID_5x00_24: 1168 //iwl5100_abg_cfg 1169 sc->txchainmask = IWN_ANT_B; 1170 sc->rxchainmask = IWN_ANT_AB; 1171 break; 1172 case IWN_SDID_5x00_25: 1173 case IWN_SDID_5x00_26: 1174 case IWN_SDID_5x00_27: 1175 case IWN_SDID_5x00_28: 1176 case IWN_SDID_5x00_29: 1177 case IWN_SDID_5x00_30: 1178 case IWN_SDID_5x00_31: 1179 case IWN_SDID_5x00_32: 1180 case IWN_SDID_5x00_33: 1181 case IWN_SDID_5x00_34: 1182 case IWN_SDID_5x00_35: 1183 case IWN_SDID_5x00_36: 1184 //iwl5300_agn_cfg 1185 sc->txchainmask = IWN_ANT_ABC; 1186 sc->rxchainmask = IWN_ANT_ABC; 1187 break; 1188 default: 1189 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1190 "0x%04x rev %d not supported (subdevice)\n", pid, 1191 sc->subdevice_id,sc->hw_type); 1192 return ENOTSUP; 1193 } 1194 break; 1195 /* 5x50 Series */ 1196 case IWN_DID_5x50_1: 1197 case IWN_DID_5x50_2: 1198 case IWN_DID_5x50_3: 1199 case IWN_DID_5x50_4: 1200 sc->limits = &iwn5000_sensitivity_limits; 1201 sc->base_params = &iwn5000_base_params; 1202 sc->fwname = "iwn5000fw"; 1203 switch(sc->subdevice_id) { 1204 case IWN_SDID_5x50_1: 1205 case IWN_SDID_5x50_2: 1206 case IWN_SDID_5x50_3: 1207 //iwl5350_agn_cfg 1208 sc->limits = &iwn5000_sensitivity_limits; 1209 sc->base_params = &iwn5000_base_params; 1210 sc->fwname = "iwn5000fw"; 1211 break; 1212 case IWN_SDID_5x50_4: 1213 case IWN_SDID_5x50_5: 1214 case IWN_SDID_5x50_8: 1215 case IWN_SDID_5x50_9: 1216 case IWN_SDID_5x50_10: 1217 case IWN_SDID_5x50_11: 1218 //iwl5150_agn_cfg 1219 case IWN_SDID_5x50_6: 1220 case IWN_SDID_5x50_7: 1221 case IWN_SDID_5x50_12: 1222 case IWN_SDID_5x50_13: 1223 //iwl5150_abg_cfg 1224 sc->limits = &iwn5000_sensitivity_limits; 1225 sc->fwname = "iwn5150fw"; 1226 sc->base_params = &iwn_5x50_base_params; 1227 break; 1228 default: 1229 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id :" 1230 "0x%04x rev %d not supported (subdevice)\n", pid, 1231 sc->subdevice_id,sc->hw_type); 1232 return ENOTSUP; 1233 } 1234 break; 1235 default: 1236 device_printf(sc->sc_dev, "adapter type id : 0x%04x sub id : 0x%04x" 1237 "rev 0x%08x not supported (device)\n", pid, sc->subdevice_id, 1238 sc->hw_type); 1239 return ENOTSUP; 1240 } 1241 return 0; 1242 } 1243 1244 static int 1245 iwn4965_attach(struct iwn_softc *sc, uint16_t pid) 1246 { 1247 struct iwn_ops *ops = &sc->ops; 1248 1249 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1250 ops->load_firmware = iwn4965_load_firmware; 1251 ops->read_eeprom = iwn4965_read_eeprom; 1252 ops->post_alive = iwn4965_post_alive; 1253 ops->nic_config = iwn4965_nic_config; 1254 ops->update_sched = iwn4965_update_sched; 1255 ops->get_temperature = iwn4965_get_temperature; 1256 ops->get_rssi = iwn4965_get_rssi; 1257 ops->set_txpower = iwn4965_set_txpower; 1258 ops->init_gains = iwn4965_init_gains; 1259 ops->set_gains = iwn4965_set_gains; 1260 ops->add_node = iwn4965_add_node; 1261 ops->tx_done = iwn4965_tx_done; 1262 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 1263 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 1264 sc->ntxqs = IWN4965_NTXQUEUES; 1265 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE; 1266 sc->ndmachnls = IWN4965_NDMACHNLS; 1267 sc->broadcast_id = IWN4965_ID_BROADCAST; 1268 sc->rxonsz = IWN4965_RXONSZ; 1269 sc->schedsz = IWN4965_SCHEDSZ; 1270 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 1271 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 1272 sc->fwsz = IWN4965_FWSZ; 1273 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 1274 sc->limits = &iwn4965_sensitivity_limits; 1275 sc->fwname = "iwn4965fw"; 1276 /* Override chains masks, ROM is known to be broken. */ 1277 sc->txchainmask = IWN_ANT_AB; 1278 sc->rxchainmask = IWN_ANT_ABC; 1279 /* Enable normal btcoex */ 1280 sc->sc_flags |= IWN_FLAG_BTCOEX; 1281 1282 DPRINTF(sc, IWN_DEBUG_TRACE, "%s: end\n",__func__); 1283 1284 return 0; 1285 } 1286 1287 static int 1288 iwn5000_attach(struct iwn_softc *sc, uint16_t pid) 1289 { 1290 struct iwn_ops *ops = &sc->ops; 1291 1292 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1293 1294 ops->load_firmware = iwn5000_load_firmware; 1295 ops->read_eeprom = iwn5000_read_eeprom; 1296 ops->post_alive = iwn5000_post_alive; 1297 ops->nic_config = iwn5000_nic_config; 1298 ops->update_sched = iwn5000_update_sched; 1299 ops->get_temperature = iwn5000_get_temperature; 1300 ops->get_rssi = iwn5000_get_rssi; 1301 ops->set_txpower = iwn5000_set_txpower; 1302 ops->init_gains = iwn5000_init_gains; 1303 ops->set_gains = iwn5000_set_gains; 1304 ops->add_node = iwn5000_add_node; 1305 ops->tx_done = iwn5000_tx_done; 1306 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 1307 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 1308 sc->ntxqs = IWN5000_NTXQUEUES; 1309 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE; 1310 sc->ndmachnls = IWN5000_NDMACHNLS; 1311 sc->broadcast_id = IWN5000_ID_BROADCAST; 1312 sc->rxonsz = IWN5000_RXONSZ; 1313 sc->schedsz = IWN5000_SCHEDSZ; 1314 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 1315 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 1316 sc->fwsz = IWN5000_FWSZ; 1317 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 1318 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 1319 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 1320 1321 return 0; 1322 } 1323 1324 /* 1325 * Attach the interface to 802.11 radiotap. 1326 */ 1327 static void 1328 iwn_radiotap_attach(struct iwn_softc *sc) 1329 { 1330 struct ifnet *ifp = sc->sc_ifp; 1331 struct ieee80211com *ic = ifp->if_l2com; 1332 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1333 ieee80211_radiotap_attach(ic, 1334 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 1335 IWN_TX_RADIOTAP_PRESENT, 1336 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 1337 IWN_RX_RADIOTAP_PRESENT); 1338 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1339 } 1340 1341 static void 1342 iwn_sysctlattach(struct iwn_softc *sc) 1343 { 1344 #ifdef IWN_DEBUG 1345 struct sysctl_ctx_list *ctx; 1346 struct sysctl_oid *tree; 1347 1348 ctx = &sc->sc_sysctl_ctx; 1349 tree = sc->sc_sysctl_tree; 1350 1351 if (tree) { 1352 device_printf(sc->sc_dev, "can't add sysctl node\n"); 1353 return; 1354 } 1355 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1356 "debug", CTLFLAG_RW, &sc->sc_debug, sc->sc_debug, 1357 "control debugging printfs"); 1358 #endif 1359 } 1360 1361 static struct ieee80211vap * 1362 iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1363 enum ieee80211_opmode opmode, int flags, 1364 const uint8_t bssid[IEEE80211_ADDR_LEN], 1365 const uint8_t mac[IEEE80211_ADDR_LEN]) 1366 { 1367 struct iwn_vap *ivp; 1368 struct ieee80211vap *vap; 1369 uint8_t mac1[IEEE80211_ADDR_LEN]; 1370 struct iwn_softc *sc = ic->ic_ifp->if_softc; 1371 1372 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1373 return NULL; 1374 1375 IEEE80211_ADDR_COPY(mac1, mac); 1376 1377 ivp = kmalloc(sizeof(struct iwn_vap), M_80211_VAP, M_INTWAIT | M_ZERO); 1378 vap = &ivp->iv_vap; 1379 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac1); 1380 ivp->ctx = IWN_RXON_BSS_CTX; 1381 IEEE80211_ADDR_COPY(ivp->macaddr, mac1); 1382 vap->iv_bmissthreshold = 10; /* override default */ 1383 /* Override with driver methods. */ 1384 ivp->iv_newstate = vap->iv_newstate; 1385 vap->iv_newstate = iwn_newstate; 1386 sc->ivap[IWN_RXON_BSS_CTX] = vap; 1387 1388 ieee80211_ratectl_init(vap); 1389 /* Complete setup. */ 1390 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status); 1391 ic->ic_opmode = opmode; 1392 return vap; 1393 } 1394 1395 static void 1396 iwn_vap_delete(struct ieee80211vap *vap) 1397 { 1398 struct iwn_vap *ivp = IWN_VAP(vap); 1399 1400 ieee80211_ratectl_deinit(vap); 1401 ieee80211_vap_detach(vap); 1402 kfree(ivp, M_80211_VAP); 1403 } 1404 1405 static int 1406 iwn_pci_detach(device_t dev) 1407 { 1408 struct iwn_softc *sc = device_get_softc(dev); 1409 struct ifnet *ifp = sc->sc_ifp; 1410 struct ieee80211com *ic; 1411 int qid; 1412 1413 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1414 1415 wlan_serialize_enter(); 1416 1417 if (ifp != NULL) { 1418 ic = ifp->if_l2com; 1419 1420 ieee80211_draintask(ic, &sc->sc_reinit_task); 1421 ieee80211_draintask(ic, &sc->sc_radioon_task); 1422 ieee80211_draintask(ic, &sc->sc_radiooff_task); 1423 1424 iwn_stop_locked(sc); 1425 1426 #if 0 1427 // We don't need this for DragonFly as our taskqueue_free() 1428 // is running all remaining tasks before terminating. 1429 taskqueue_drain_all(sc->sc_tq); 1430 #endif 1431 taskqueue_free(sc->sc_tq); 1432 1433 callout_stop(&sc->watchdog_to); 1434 callout_stop(&sc->calib_to); 1435 ieee80211_ifdetach(ic); 1436 } 1437 1438 /* cleanup sysctl nodes */ 1439 sysctl_ctx_free(&sc->sc_sysctl_ctx); 1440 1441 /* Uninstall interrupt handler. */ 1442 if (sc->irq != NULL) { 1443 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 1444 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 1445 sc->irq); 1446 pci_release_msi(dev); 1447 sc->irq = NULL; 1448 } 1449 1450 /* Free DMA resources. */ 1451 iwn_free_rx_ring(sc, &sc->rxq); 1452 for (qid = 0; qid < sc->ntxqs; qid++) 1453 iwn_free_tx_ring(sc, &sc->txq[qid]); 1454 iwn_free_sched(sc); 1455 iwn_free_kw(sc); 1456 if (sc->ict != NULL) { 1457 iwn_free_ict(sc); 1458 sc->ict = NULL; 1459 } 1460 iwn_free_fwmem(sc); 1461 1462 if (sc->mem != NULL) { 1463 bus_release_resource(dev, SYS_RES_MEMORY, 1464 rman_get_rid(sc->mem), sc->mem); 1465 sc->mem = NULL; 1466 } 1467 1468 if (ifp != NULL) { 1469 if_free(ifp); 1470 sc->sc_ifp = NULL; 1471 } 1472 1473 bus_dma_tag_destroy(sc->sc_dmat); 1474 1475 wlan_serialize_exit(); 1476 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n", __func__); 1477 return 0; 1478 } 1479 1480 static int 1481 iwn_pci_shutdown(device_t dev) 1482 { 1483 struct iwn_softc *sc = device_get_softc(dev); 1484 1485 wlan_serialize_enter(); 1486 iwn_stop_locked(sc); 1487 wlan_serialize_exit(); 1488 1489 return 0; 1490 } 1491 1492 static int 1493 iwn_pci_suspend(device_t dev) 1494 { 1495 struct iwn_softc *sc = device_get_softc(dev); 1496 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1497 1498 ieee80211_suspend_all(ic); 1499 return 0; 1500 } 1501 1502 static int 1503 iwn_pci_resume(device_t dev) 1504 { 1505 struct iwn_softc *sc = device_get_softc(dev); 1506 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1507 1508 /* Clear device-specific "PCI retry timeout" register (41h). */ 1509 pci_write_config(dev, 0x41, 0, 1); 1510 1511 ieee80211_resume_all(ic); 1512 return 0; 1513 } 1514 1515 static int 1516 iwn_nic_lock(struct iwn_softc *sc) 1517 { 1518 int ntries; 1519 1520 /* Request exclusive access to NIC. */ 1521 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1522 1523 /* Spin until we actually get the lock. */ 1524 for (ntries = 0; ntries < 1000; ntries++) { 1525 if ((IWN_READ(sc, IWN_GP_CNTRL) & 1526 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 1527 IWN_GP_CNTRL_MAC_ACCESS_ENA) 1528 return 0; 1529 DELAY(10); 1530 } 1531 return ETIMEDOUT; 1532 } 1533 1534 static __inline void 1535 iwn_nic_unlock(struct iwn_softc *sc) 1536 { 1537 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 1538 } 1539 1540 static __inline uint32_t 1541 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 1542 { 1543 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 1544 IWN_BARRIER_READ_WRITE(sc); 1545 return IWN_READ(sc, IWN_PRPH_RDATA); 1546 } 1547 1548 static __inline void 1549 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1550 { 1551 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 1552 IWN_BARRIER_WRITE(sc); 1553 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 1554 } 1555 1556 static __inline void 1557 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1558 { 1559 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 1560 } 1561 1562 static __inline void 1563 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 1564 { 1565 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 1566 } 1567 1568 static __inline void 1569 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 1570 const uint32_t *data, int count) 1571 { 1572 for (; count > 0; count--, data++, addr += 4) 1573 iwn_prph_write(sc, addr, *data); 1574 } 1575 1576 static __inline uint32_t 1577 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 1578 { 1579 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 1580 IWN_BARRIER_READ_WRITE(sc); 1581 return IWN_READ(sc, IWN_MEM_RDATA); 1582 } 1583 1584 static __inline void 1585 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 1586 { 1587 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 1588 IWN_BARRIER_WRITE(sc); 1589 IWN_WRITE(sc, IWN_MEM_WDATA, data); 1590 } 1591 1592 static __inline void 1593 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 1594 { 1595 uint32_t tmp; 1596 1597 tmp = iwn_mem_read(sc, addr & ~3); 1598 if (addr & 3) 1599 tmp = (tmp & 0x0000ffff) | data << 16; 1600 else 1601 tmp = (tmp & 0xffff0000) | data; 1602 iwn_mem_write(sc, addr & ~3, tmp); 1603 } 1604 1605 static __inline void 1606 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 1607 int count) 1608 { 1609 for (; count > 0; count--, addr += 4) 1610 *data++ = iwn_mem_read(sc, addr); 1611 } 1612 1613 static __inline void 1614 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 1615 int count) 1616 { 1617 for (; count > 0; count--, addr += 4) 1618 iwn_mem_write(sc, addr, val); 1619 } 1620 1621 static int 1622 iwn_eeprom_lock(struct iwn_softc *sc) 1623 { 1624 int i, ntries; 1625 1626 for (i = 0; i < 100; i++) { 1627 /* Request exclusive access to EEPROM. */ 1628 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 1629 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1630 1631 /* Spin until we actually get the lock. */ 1632 for (ntries = 0; ntries < 100; ntries++) { 1633 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 1634 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 1635 return 0; 1636 DELAY(10); 1637 } 1638 } 1639 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end timeout\n", __func__); 1640 return ETIMEDOUT; 1641 } 1642 1643 static __inline void 1644 iwn_eeprom_unlock(struct iwn_softc *sc) 1645 { 1646 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 1647 } 1648 1649 /* 1650 * Initialize access by host to One Time Programmable ROM. 1651 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 1652 */ 1653 static int 1654 iwn_init_otprom(struct iwn_softc *sc) 1655 { 1656 uint16_t prev, base, next; 1657 int count, error; 1658 1659 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1660 1661 /* Wait for clock stabilization before accessing prph. */ 1662 if ((error = iwn_clock_wait(sc)) != 0) 1663 return error; 1664 1665 if ((error = iwn_nic_lock(sc)) != 0) 1666 return error; 1667 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1668 DELAY(5); 1669 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 1670 iwn_nic_unlock(sc); 1671 1672 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 1673 if (sc->base_params->shadow_ram_support) { 1674 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 1675 IWN_RESET_LINK_PWR_MGMT_DIS); 1676 } 1677 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 1678 /* Clear ECC status. */ 1679 IWN_SETBITS(sc, IWN_OTP_GP, 1680 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 1681 1682 /* 1683 * Find the block before last block (contains the EEPROM image) 1684 * for HW without OTP shadow RAM. 1685 */ 1686 if (! sc->base_params->shadow_ram_support) { 1687 /* Switch to absolute addressing mode. */ 1688 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 1689 base = prev = 0; 1690 for (count = 0; count < sc->base_params->max_ll_items; 1691 count++) { 1692 error = iwn_read_prom_data(sc, base, &next, 2); 1693 if (error != 0) 1694 return error; 1695 if (next == 0) /* End of linked-list. */ 1696 break; 1697 prev = base; 1698 base = le16toh(next); 1699 } 1700 if (count == 0 || count == sc->base_params->max_ll_items) 1701 return EIO; 1702 /* Skip "next" word. */ 1703 sc->prom_base = prev + 1; 1704 } 1705 1706 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1707 1708 return 0; 1709 } 1710 1711 static int 1712 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1713 { 1714 uint8_t *out = data; 1715 uint32_t val, tmp; 1716 int ntries; 1717 1718 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1719 1720 addr += sc->prom_base; 1721 for (; count > 0; count -= 2, addr++) { 1722 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1723 for (ntries = 0; ntries < 10; ntries++) { 1724 val = IWN_READ(sc, IWN_EEPROM); 1725 if (val & IWN_EEPROM_READ_VALID) 1726 break; 1727 DELAY(5); 1728 } 1729 if (ntries == 10) { 1730 device_printf(sc->sc_dev, 1731 "timeout reading ROM at 0x%x\n", addr); 1732 return ETIMEDOUT; 1733 } 1734 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1735 /* OTPROM, check for ECC errors. */ 1736 tmp = IWN_READ(sc, IWN_OTP_GP); 1737 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1738 device_printf(sc->sc_dev, 1739 "OTPROM ECC error at 0x%x\n", addr); 1740 return EIO; 1741 } 1742 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1743 /* Correctable ECC error, clear bit. */ 1744 IWN_SETBITS(sc, IWN_OTP_GP, 1745 IWN_OTP_GP_ECC_CORR_STTS); 1746 } 1747 } 1748 *out++ = val >> 16; 1749 if (count > 1) 1750 *out++ = val >> 24; 1751 } 1752 1753 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 1754 1755 return 0; 1756 } 1757 1758 static void 1759 iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1760 { 1761 if (error != 0) 1762 return; 1763 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 1764 *(bus_addr_t *)arg = segs[0].ds_addr; 1765 } 1766 1767 static int 1768 iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, 1769 void **kvap, bus_size_t size, bus_size_t alignment) 1770 { 1771 int error; 1772 1773 dma->tag = NULL; 1774 dma->size = size; 1775 1776 error = bus_dma_tag_create(sc->sc_dmat, alignment, 1777 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, 1778 1, size, BUS_DMA_NOWAIT, &dma->tag); 1779 if (error != 0) 1780 goto fail; 1781 1782 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr, 1783 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map); 1784 if (error != 0) 1785 goto fail; 1786 1787 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size, 1788 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT); 1789 if (error != 0) 1790 goto fail; 1791 1792 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 1793 1794 if (kvap != NULL) 1795 *kvap = dma->vaddr; 1796 1797 return 0; 1798 1799 fail: iwn_dma_contig_free(dma); 1800 return error; 1801 } 1802 1803 static void 1804 iwn_dma_contig_free(struct iwn_dma_info *dma) 1805 { 1806 if (dma->vaddr != NULL) { 1807 bus_dmamap_sync(dma->tag, dma->map, 1808 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1809 bus_dmamap_unload(dma->tag, dma->map); 1810 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1811 dma->vaddr = NULL; 1812 } 1813 if (dma->tag != NULL) { 1814 bus_dma_tag_destroy(dma->tag); 1815 dma->tag = NULL; 1816 } 1817 } 1818 1819 static int 1820 iwn_alloc_sched(struct iwn_softc *sc) 1821 { 1822 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1823 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched, 1824 sc->schedsz, 1024); 1825 } 1826 1827 static void 1828 iwn_free_sched(struct iwn_softc *sc) 1829 { 1830 iwn_dma_contig_free(&sc->sched_dma); 1831 } 1832 1833 static int 1834 iwn_alloc_kw(struct iwn_softc *sc) 1835 { 1836 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1837 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096); 1838 } 1839 1840 static void 1841 iwn_free_kw(struct iwn_softc *sc) 1842 { 1843 iwn_dma_contig_free(&sc->kw_dma); 1844 } 1845 1846 static int 1847 iwn_alloc_ict(struct iwn_softc *sc) 1848 { 1849 /* ICT table must be aligned on a 4KB boundary. */ 1850 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict, 1851 IWN_ICT_SIZE, 4096); 1852 } 1853 1854 static void 1855 iwn_free_ict(struct iwn_softc *sc) 1856 { 1857 iwn_dma_contig_free(&sc->ict_dma); 1858 } 1859 1860 static int 1861 iwn_alloc_fwmem(struct iwn_softc *sc) 1862 { 1863 /* Must be aligned on a 16-byte boundary. */ 1864 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16); 1865 } 1866 1867 static void 1868 iwn_free_fwmem(struct iwn_softc *sc) 1869 { 1870 iwn_dma_contig_free(&sc->fw_dma); 1871 } 1872 1873 static int 1874 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1875 { 1876 bus_size_t size; 1877 int i, error; 1878 1879 ring->cur = 0; 1880 1881 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 1882 1883 /* Allocate RX descriptors (256-byte aligned). */ 1884 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1885 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 1886 size, 256); 1887 if (error != 0) { 1888 device_printf(sc->sc_dev, 1889 "%s: could not allocate RX ring DMA memory, error %d\n", 1890 __func__, error); 1891 goto fail; 1892 } 1893 1894 /* Allocate RX status area (16-byte aligned). */ 1895 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat, 1896 sizeof (struct iwn_rx_status), 16); 1897 if (error != 0) { 1898 device_printf(sc->sc_dev, 1899 "%s: could not allocate RX status DMA memory, error %d\n", 1900 __func__, error); 1901 goto fail; 1902 } 1903 1904 /* Create RX buffer DMA tag. */ 1905 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 1906 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1907 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, &ring->data_dmat); 1908 if (error != 0) { 1909 device_printf(sc->sc_dev, 1910 "%s: could not create RX buf DMA tag, error %d\n", 1911 __func__, error); 1912 goto fail; 1913 } 1914 1915 /* 1916 * Allocate and map RX buffers. 1917 */ 1918 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1919 struct iwn_rx_data *data = &ring->data[i]; 1920 bus_addr_t paddr; 1921 1922 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 1923 if (error != 0) { 1924 device_printf(sc->sc_dev, 1925 "%s: could not create RX buf DMA map, error %d\n", 1926 __func__, error); 1927 goto fail; 1928 } 1929 1930 data->m = m_getjcl(MB_DONTWAIT, MT_DATA, 1931 M_PKTHDR, IWN_RBUF_SIZE); 1932 if (data->m == NULL) { 1933 device_printf(sc->sc_dev, 1934 "%s: could not allocate RX mbuf\n", __func__); 1935 error = ENOBUFS; 1936 goto fail; 1937 } 1938 1939 error = bus_dmamap_load(ring->data_dmat, data->map, 1940 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 1941 &paddr, BUS_DMA_NOWAIT); 1942 if (error != 0 && error != EFBIG) { 1943 device_printf(sc->sc_dev, 1944 "%s: can't not map mbuf, error %d\n", __func__, 1945 error); 1946 goto fail; 1947 } 1948 1949 /* Set physical address of RX buffer (256-byte aligned). */ 1950 ring->desc[i] = htole32(paddr >> 8); 1951 } 1952 1953 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 1954 BUS_DMASYNC_PREWRITE); 1955 1956 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 1957 1958 return 0; 1959 1960 fail: iwn_free_rx_ring(sc, ring); 1961 1962 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 1963 1964 return error; 1965 } 1966 1967 static void 1968 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1969 { 1970 int ntries; 1971 1972 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 1973 1974 if (iwn_nic_lock(sc) == 0) { 1975 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1976 for (ntries = 0; ntries < 1000; ntries++) { 1977 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1978 IWN_FH_RX_STATUS_IDLE) 1979 break; 1980 DELAY(10); 1981 } 1982 iwn_nic_unlock(sc); 1983 } 1984 ring->cur = 0; 1985 sc->last_rx_valid = 0; 1986 } 1987 1988 static void 1989 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1990 { 1991 int i; 1992 1993 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 1994 1995 iwn_dma_contig_free(&ring->desc_dma); 1996 iwn_dma_contig_free(&ring->stat_dma); 1997 1998 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1999 struct iwn_rx_data *data = &ring->data[i]; 2000 2001 if (data->m != NULL) { 2002 bus_dmamap_sync(ring->data_dmat, data->map, 2003 BUS_DMASYNC_POSTREAD); 2004 bus_dmamap_unload(ring->data_dmat, data->map); 2005 m_freem(data->m); 2006 data->m = NULL; 2007 } 2008 if (data->map != NULL) 2009 bus_dmamap_destroy(ring->data_dmat, data->map); 2010 } 2011 if (ring->data_dmat != NULL) { 2012 bus_dma_tag_destroy(ring->data_dmat); 2013 ring->data_dmat = NULL; 2014 } 2015 } 2016 2017 static int 2018 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 2019 { 2020 bus_addr_t paddr; 2021 bus_size_t size; 2022 int i, error; 2023 2024 ring->qid = qid; 2025 ring->queued = 0; 2026 ring->cur = 0; 2027 2028 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2029 2030 /* Allocate TX descriptors (256-byte aligned). */ 2031 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 2032 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc, 2033 size, 256); 2034 if (error != 0) { 2035 device_printf(sc->sc_dev, 2036 "%s: could not allocate TX ring DMA memory, error %d\n", 2037 __func__, error); 2038 goto fail; 2039 } 2040 2041 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 2042 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd, 2043 size, 4); 2044 if (error != 0) { 2045 device_printf(sc->sc_dev, 2046 "%s: could not allocate TX cmd DMA memory, error %d\n", 2047 __func__, error); 2048 goto fail; 2049 } 2050 2051 error = bus_dma_tag_create(sc->sc_dmat, 1, 0, 2052 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 2053 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat); 2054 if (error != 0) { 2055 device_printf(sc->sc_dev, 2056 "%s: could not create TX buf DMA tag, error %d\n", 2057 __func__, error); 2058 goto fail; 2059 } 2060 2061 paddr = ring->cmd_dma.paddr; 2062 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2063 struct iwn_tx_data *data = &ring->data[i]; 2064 2065 data->cmd_paddr = paddr; 2066 data->scratch_paddr = paddr + 12; 2067 paddr += sizeof (struct iwn_tx_cmd); 2068 2069 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 2070 if (error != 0) { 2071 device_printf(sc->sc_dev, 2072 "%s: could not create TX buf DMA map, error %d\n", 2073 __func__, error); 2074 goto fail; 2075 } 2076 } 2077 2078 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2079 2080 return 0; 2081 2082 fail: iwn_free_tx_ring(sc, ring); 2083 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2084 return error; 2085 } 2086 2087 static void 2088 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2089 { 2090 int i; 2091 2092 DPRINTF(sc, IWN_DEBUG_TRACE, "->doing %s \n", __func__); 2093 2094 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2095 struct iwn_tx_data *data = &ring->data[i]; 2096 2097 if (data->m != NULL) { 2098 bus_dmamap_sync(ring->data_dmat, data->map, 2099 BUS_DMASYNC_POSTWRITE); 2100 bus_dmamap_unload(ring->data_dmat, data->map); 2101 m_freem(data->m); 2102 data->m = NULL; 2103 } 2104 } 2105 /* Clear TX descriptors. */ 2106 memset(ring->desc, 0, ring->desc_dma.size); 2107 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 2108 BUS_DMASYNC_PREWRITE); 2109 sc->qfullmsk &= ~(1 << ring->qid); 2110 ring->queued = 0; 2111 ring->cur = 0; 2112 } 2113 2114 static void 2115 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2116 { 2117 int i; 2118 2119 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s \n", __func__); 2120 2121 iwn_dma_contig_free(&ring->desc_dma); 2122 iwn_dma_contig_free(&ring->cmd_dma); 2123 2124 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 2125 struct iwn_tx_data *data = &ring->data[i]; 2126 2127 if (data->m != NULL) { 2128 bus_dmamap_sync(ring->data_dmat, data->map, 2129 BUS_DMASYNC_POSTWRITE); 2130 bus_dmamap_unload(ring->data_dmat, data->map); 2131 m_freem(data->m); 2132 } 2133 if (data->map != NULL) 2134 bus_dmamap_destroy(ring->data_dmat, data->map); 2135 } 2136 if (ring->data_dmat != NULL) { 2137 bus_dma_tag_destroy(ring->data_dmat); 2138 ring->data_dmat = NULL; 2139 } 2140 } 2141 2142 static void 2143 iwn5000_ict_reset(struct iwn_softc *sc) 2144 { 2145 /* Disable interrupts. */ 2146 IWN_WRITE(sc, IWN_INT_MASK, 0); 2147 2148 /* Reset ICT table. */ 2149 memset(sc->ict, 0, IWN_ICT_SIZE); 2150 sc->ict_cur = 0; 2151 2152 /* Set physical address of ICT table (4KB aligned). */ 2153 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__); 2154 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 2155 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 2156 2157 /* Enable periodic RX interrupt. */ 2158 sc->int_mask |= IWN_INT_RX_PERIODIC; 2159 /* Switch to ICT interrupt mode in driver. */ 2160 sc->sc_flags |= IWN_FLAG_USE_ICT; 2161 2162 /* Re-enable interrupts. */ 2163 IWN_WRITE(sc, IWN_INT, 0xffffffff); 2164 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 2165 } 2166 2167 static int 2168 iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2169 { 2170 struct iwn_ops *ops = &sc->ops; 2171 uint16_t val; 2172 int error; 2173 2174 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2175 2176 /* Check whether adapter has an EEPROM or an OTPROM. */ 2177 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 2178 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 2179 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 2180 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n", 2181 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM"); 2182 2183 /* Adapter has to be powered on for EEPROM access to work. */ 2184 if ((error = iwn_apm_init(sc)) != 0) { 2185 device_printf(sc->sc_dev, 2186 "%s: could not power ON adapter, error %d\n", __func__, 2187 error); 2188 return error; 2189 } 2190 2191 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 2192 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__); 2193 return EIO; 2194 } 2195 if ((error = iwn_eeprom_lock(sc)) != 0) { 2196 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n", 2197 __func__, error); 2198 return error; 2199 } 2200 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 2201 if ((error = iwn_init_otprom(sc)) != 0) { 2202 device_printf(sc->sc_dev, 2203 "%s: could not initialize OTPROM, error %d\n", 2204 __func__, error); 2205 return error; 2206 } 2207 } 2208 2209 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 2210 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val)); 2211 /* Check if HT support is bonded out. */ 2212 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 2213 sc->sc_flags |= IWN_FLAG_HAS_11N; 2214 2215 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 2216 sc->rfcfg = le16toh(val); 2217 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg); 2218 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 2219 if (sc->txchainmask == 0) 2220 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 2221 if (sc->rxchainmask == 0) 2222 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 2223 2224 /* Read MAC address. */ 2225 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6); 2226 2227 /* Read adapter-specific information from EEPROM. */ 2228 ops->read_eeprom(sc); 2229 2230 iwn_apm_stop(sc); /* Power OFF adapter. */ 2231 2232 iwn_eeprom_unlock(sc); 2233 2234 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2235 2236 return 0; 2237 } 2238 2239 static void 2240 iwn4965_read_eeprom(struct iwn_softc *sc) 2241 { 2242 uint32_t addr; 2243 uint16_t val; 2244 int i; 2245 2246 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2247 2248 /* Read regulatory domain (4 ASCII characters). */ 2249 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 2250 2251 /* Read the list of authorized channels (20MHz ones only). */ 2252 for (i = 0; i < IWN_NBANDS - 1; i++) { 2253 addr = iwn4965_regulatory_bands[i]; 2254 iwn_read_eeprom_channels(sc, i, addr); 2255 } 2256 2257 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 2258 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 2259 sc->maxpwr2GHz = val & 0xff; 2260 sc->maxpwr5GHz = val >> 8; 2261 /* Check that EEPROM values are within valid range. */ 2262 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 2263 sc->maxpwr5GHz = 38; 2264 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 2265 sc->maxpwr2GHz = 38; 2266 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n", 2267 sc->maxpwr2GHz, sc->maxpwr5GHz); 2268 2269 /* Read samples for each TX power group. */ 2270 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 2271 sizeof sc->bands); 2272 2273 /* Read voltage at which samples were taken. */ 2274 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 2275 sc->eeprom_voltage = (int16_t)le16toh(val); 2276 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n", 2277 sc->eeprom_voltage); 2278 2279 #ifdef IWN_DEBUG 2280 /* Print samples. */ 2281 if (sc->sc_debug & IWN_DEBUG_ANY) { 2282 for (i = 0; i < IWN_NBANDS - 1; i++) 2283 iwn4965_print_power_group(sc, i); 2284 } 2285 #endif 2286 2287 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2288 } 2289 2290 #ifdef IWN_DEBUG 2291 static void 2292 iwn4965_print_power_group(struct iwn_softc *sc, int i) 2293 { 2294 struct iwn4965_eeprom_band *band = &sc->bands[i]; 2295 struct iwn4965_eeprom_chan_samples *chans = band->chans; 2296 int j, c; 2297 2298 kprintf("===band %d===\n", i); 2299 kprintf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 2300 kprintf("chan1 num=%d\n", chans[0].num); 2301 for (c = 0; c < 2; c++) { 2302 for (j = 0; j < IWN_NSAMPLES; j++) { 2303 kprintf("chain %d, sample %d: temp=%d gain=%d " 2304 "power=%d pa_det=%d\n", c, j, 2305 chans[0].samples[c][j].temp, 2306 chans[0].samples[c][j].gain, 2307 chans[0].samples[c][j].power, 2308 chans[0].samples[c][j].pa_det); 2309 } 2310 } 2311 kprintf("chan2 num=%d\n", chans[1].num); 2312 for (c = 0; c < 2; c++) { 2313 for (j = 0; j < IWN_NSAMPLES; j++) { 2314 kprintf("chain %d, sample %d: temp=%d gain=%d " 2315 "power=%d pa_det=%d\n", c, j, 2316 chans[1].samples[c][j].temp, 2317 chans[1].samples[c][j].gain, 2318 chans[1].samples[c][j].power, 2319 chans[1].samples[c][j].pa_det); 2320 } 2321 } 2322 } 2323 #endif 2324 2325 static void 2326 iwn5000_read_eeprom(struct iwn_softc *sc) 2327 { 2328 struct iwn5000_eeprom_calib_hdr hdr; 2329 int32_t volt; 2330 uint32_t base, addr; 2331 uint16_t val; 2332 int i; 2333 2334 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2335 2336 /* Read regulatory domain (4 ASCII characters). */ 2337 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2338 base = le16toh(val); 2339 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 2340 sc->eeprom_domain, 4); 2341 2342 /* Read the list of authorized channels (20MHz ones only). */ 2343 for (i = 0; i < IWN_NBANDS - 1; i++) { 2344 addr = base + sc->base_params->regulatory_bands[i]; 2345 iwn_read_eeprom_channels(sc, i, addr); 2346 } 2347 2348 /* Read enhanced TX power information for 6000 Series. */ 2349 if (sc->base_params->enhanced_TX_power) 2350 iwn_read_eeprom_enhinfo(sc); 2351 2352 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 2353 base = le16toh(val); 2354 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 2355 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 2356 "%s: calib version=%u pa type=%u voltage=%u\n", __func__, 2357 hdr.version, hdr.pa_type, le16toh(hdr.volt)); 2358 sc->calib_ver = hdr.version; 2359 2360 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 2361 sc->eeprom_voltage = le16toh(hdr.volt); 2362 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2363 sc->eeprom_temp_high=le16toh(val); 2364 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2365 sc->eeprom_temp = le16toh(val); 2366 } 2367 2368 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 2369 /* Compute temperature offset. */ 2370 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 2371 sc->eeprom_temp = le16toh(val); 2372 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 2373 volt = le16toh(val); 2374 sc->temp_off = sc->eeprom_temp - (volt / -5); 2375 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n", 2376 sc->eeprom_temp, volt, sc->temp_off); 2377 } else { 2378 /* Read crystal calibration. */ 2379 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 2380 &sc->eeprom_crystal, sizeof (uint32_t)); 2381 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n", 2382 le32toh(sc->eeprom_crystal)); 2383 } 2384 2385 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2386 2387 } 2388 2389 /* 2390 * Translate EEPROM flags to net80211. 2391 */ 2392 static uint32_t 2393 iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel) 2394 { 2395 uint32_t nflags; 2396 2397 nflags = 0; 2398 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0) 2399 nflags |= IEEE80211_CHAN_PASSIVE; 2400 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0) 2401 nflags |= IEEE80211_CHAN_NOADHOC; 2402 if (channel->flags & IWN_EEPROM_CHAN_RADAR) { 2403 nflags |= IEEE80211_CHAN_DFS; 2404 /* XXX apparently IBSS may still be marked */ 2405 nflags |= IEEE80211_CHAN_NOADHOC; 2406 } 2407 2408 return nflags; 2409 } 2410 2411 static void 2412 iwn_read_eeprom_band(struct iwn_softc *sc, int n) 2413 { 2414 struct ifnet *ifp = sc->sc_ifp; 2415 struct ieee80211com *ic = ifp->if_l2com; 2416 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2417 const struct iwn_chan_band *band = &iwn_bands[n]; 2418 struct ieee80211_channel *c; 2419 uint8_t chan; 2420 int i, nflags; 2421 2422 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2423 2424 for (i = 0; i < band->nchan; i++) { 2425 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2426 DPRINTF(sc, IWN_DEBUG_RESET, 2427 "skip chan %d flags 0x%x maxpwr %d\n", 2428 band->chan[i], channels[i].flags, 2429 channels[i].maxpwr); 2430 continue; 2431 } 2432 chan = band->chan[i]; 2433 nflags = iwn_eeprom_channel_flags(&channels[i]); 2434 2435 c = &ic->ic_channels[ic->ic_nchans++]; 2436 c->ic_ieee = chan; 2437 c->ic_maxregpower = channels[i].maxpwr; 2438 c->ic_maxpower = 2*c->ic_maxregpower; 2439 2440 if (n == 0) { /* 2GHz band */ 2441 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G); 2442 /* G =>'s B is supported */ 2443 c->ic_flags = IEEE80211_CHAN_B | nflags; 2444 c = &ic->ic_channels[ic->ic_nchans++]; 2445 c[0] = c[-1]; 2446 c->ic_flags = IEEE80211_CHAN_G | nflags; 2447 } else { /* 5GHz band */ 2448 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A); 2449 c->ic_flags = IEEE80211_CHAN_A | nflags; 2450 } 2451 2452 /* Save maximum allowed TX power for this channel. */ 2453 sc->maxpwr[chan] = channels[i].maxpwr; 2454 2455 DPRINTF(sc, IWN_DEBUG_RESET, 2456 "add chan %d flags 0x%x maxpwr %d\n", chan, 2457 channels[i].flags, channels[i].maxpwr); 2458 2459 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 2460 /* add HT20, HT40 added separately */ 2461 c = &ic->ic_channels[ic->ic_nchans++]; 2462 c[0] = c[-1]; 2463 c->ic_flags |= IEEE80211_CHAN_HT20; 2464 } 2465 } 2466 2467 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2468 2469 } 2470 2471 static void 2472 iwn_read_eeprom_ht40(struct iwn_softc *sc, int n) 2473 { 2474 struct ifnet *ifp = sc->sc_ifp; 2475 struct ieee80211com *ic = ifp->if_l2com; 2476 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n]; 2477 const struct iwn_chan_band *band = &iwn_bands[n]; 2478 struct ieee80211_channel *c, *cent, *extc; 2479 uint8_t chan; 2480 int i, nflags; 2481 2482 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s start\n", __func__); 2483 2484 if (!(sc->sc_flags & IWN_FLAG_HAS_11N)) { 2485 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end no 11n\n", __func__); 2486 return; 2487 } 2488 2489 for (i = 0; i < band->nchan; i++) { 2490 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) { 2491 DPRINTF(sc, IWN_DEBUG_RESET, 2492 "skip chan %d flags 0x%x maxpwr %d\n", 2493 band->chan[i], channels[i].flags, 2494 channels[i].maxpwr); 2495 continue; 2496 } 2497 chan = band->chan[i]; 2498 nflags = iwn_eeprom_channel_flags(&channels[i]); 2499 2500 /* 2501 * Each entry defines an HT40 channel pair; find the 2502 * center channel, then the extension channel above. 2503 */ 2504 cent = ieee80211_find_channel_byieee(ic, chan, 2505 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 2506 if (cent == NULL) { /* XXX shouldn't happen */ 2507 device_printf(sc->sc_dev, 2508 "%s: no entry for channel %d\n", __func__, chan); 2509 continue; 2510 } 2511 extc = ieee80211_find_channel(ic, cent->ic_freq+20, 2512 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A)); 2513 if (extc == NULL) { 2514 DPRINTF(sc, IWN_DEBUG_RESET, 2515 "%s: skip chan %d, extension channel not found\n", 2516 __func__, chan); 2517 continue; 2518 } 2519 2520 DPRINTF(sc, IWN_DEBUG_RESET, 2521 "add ht40 chan %d flags 0x%x maxpwr %d\n", 2522 chan, channels[i].flags, channels[i].maxpwr); 2523 2524 c = &ic->ic_channels[ic->ic_nchans++]; 2525 c[0] = cent[0]; 2526 c->ic_extieee = extc->ic_ieee; 2527 c->ic_flags &= ~IEEE80211_CHAN_HT; 2528 c->ic_flags |= IEEE80211_CHAN_HT40U | nflags; 2529 c = &ic->ic_channels[ic->ic_nchans++]; 2530 c[0] = extc[0]; 2531 c->ic_extieee = cent->ic_ieee; 2532 c->ic_flags &= ~IEEE80211_CHAN_HT; 2533 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags; 2534 } 2535 2536 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2537 2538 } 2539 2540 static void 2541 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 2542 { 2543 struct ifnet *ifp = sc->sc_ifp; 2544 struct ieee80211com *ic = ifp->if_l2com; 2545 2546 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n], 2547 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan)); 2548 2549 if (n < 5) 2550 iwn_read_eeprom_band(sc, n); 2551 else 2552 iwn_read_eeprom_ht40(sc, n); 2553 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans); 2554 } 2555 2556 static struct iwn_eeprom_chan * 2557 iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c) 2558 { 2559 int band, chan, i, j; 2560 2561 if (IEEE80211_IS_CHAN_HT40(c)) { 2562 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5; 2563 if (IEEE80211_IS_CHAN_HT40D(c)) 2564 chan = c->ic_extieee; 2565 else 2566 chan = c->ic_ieee; 2567 for (i = 0; i < iwn_bands[band].nchan; i++) { 2568 if (iwn_bands[band].chan[i] == chan) 2569 return &sc->eeprom_channels[band][i]; 2570 } 2571 } else { 2572 for (j = 0; j < 5; j++) { 2573 for (i = 0; i < iwn_bands[j].nchan; i++) { 2574 if (iwn_bands[j].chan[i] == c->ic_ieee) 2575 return &sc->eeprom_channels[j][i]; 2576 } 2577 } 2578 } 2579 return NULL; 2580 } 2581 2582 /* 2583 * Enforce flags read from EEPROM. 2584 */ 2585 static int 2586 iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd, 2587 int nchan, struct ieee80211_channel chans[]) 2588 { 2589 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2590 int i; 2591 2592 for (i = 0; i < nchan; i++) { 2593 struct ieee80211_channel *c = &chans[i]; 2594 struct iwn_eeprom_chan *channel; 2595 2596 channel = iwn_find_eeprom_channel(sc, c); 2597 if (channel == NULL) { 2598 if_printf(ic->ic_ifp, 2599 "%s: invalid channel %u freq %u/0x%x\n", 2600 __func__, c->ic_ieee, c->ic_freq, c->ic_flags); 2601 return EINVAL; 2602 } 2603 c->ic_flags |= iwn_eeprom_channel_flags(channel); 2604 } 2605 2606 return 0; 2607 } 2608 2609 static void 2610 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 2611 { 2612 struct iwn_eeprom_enhinfo enhinfo[35]; 2613 struct ifnet *ifp = sc->sc_ifp; 2614 struct ieee80211com *ic = ifp->if_l2com; 2615 struct ieee80211_channel *c; 2616 uint16_t val, base; 2617 int8_t maxpwr; 2618 uint8_t flags; 2619 int i, j; 2620 2621 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2622 2623 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 2624 base = le16toh(val); 2625 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 2626 enhinfo, sizeof enhinfo); 2627 2628 for (i = 0; i < nitems(enhinfo); i++) { 2629 flags = enhinfo[i].flags; 2630 if (!(flags & IWN_ENHINFO_VALID)) 2631 continue; /* Skip invalid entries. */ 2632 2633 maxpwr = 0; 2634 if (sc->txchainmask & IWN_ANT_A) 2635 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 2636 if (sc->txchainmask & IWN_ANT_B) 2637 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 2638 if (sc->txchainmask & IWN_ANT_C) 2639 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 2640 if (sc->ntxchains == 2) 2641 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 2642 else if (sc->ntxchains == 3) 2643 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 2644 2645 for (j = 0; j < ic->ic_nchans; j++) { 2646 c = &ic->ic_channels[j]; 2647 if ((flags & IWN_ENHINFO_5GHZ)) { 2648 if (!IEEE80211_IS_CHAN_A(c)) 2649 continue; 2650 } else if ((flags & IWN_ENHINFO_OFDM)) { 2651 if (!IEEE80211_IS_CHAN_G(c)) 2652 continue; 2653 } else if (!IEEE80211_IS_CHAN_B(c)) 2654 continue; 2655 if ((flags & IWN_ENHINFO_HT40)) { 2656 if (!IEEE80211_IS_CHAN_HT40(c)) 2657 continue; 2658 } else { 2659 if (IEEE80211_IS_CHAN_HT40(c)) 2660 continue; 2661 } 2662 if (enhinfo[i].chan != 0 && 2663 enhinfo[i].chan != c->ic_ieee) 2664 continue; 2665 2666 DPRINTF(sc, IWN_DEBUG_RESET, 2667 "channel %d(%x), maxpwr %d\n", c->ic_ieee, 2668 c->ic_flags, maxpwr / 2); 2669 c->ic_maxregpower = maxpwr / 2; 2670 c->ic_maxpower = maxpwr; 2671 } 2672 } 2673 2674 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end\n", __func__); 2675 2676 } 2677 2678 static struct ieee80211_node * 2679 iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 2680 { 2681 return kmalloc(sizeof(struct iwn_node), M_80211_NODE, 2682 M_INTWAIT | M_ZERO); 2683 } 2684 2685 static __inline int 2686 rate2plcp(int rate) 2687 { 2688 switch (rate & 0xff) { 2689 case 12: return 0xd; 2690 case 18: return 0xf; 2691 case 24: return 0x5; 2692 case 36: return 0x7; 2693 case 48: return 0x9; 2694 case 72: return 0xb; 2695 case 96: return 0x1; 2696 case 108: return 0x3; 2697 case 2: return 10; 2698 case 4: return 20; 2699 case 11: return 55; 2700 case 22: return 110; 2701 } 2702 return 0; 2703 } 2704 2705 /* 2706 * Calculate the required PLCP value from the given rate, 2707 * to the given node. 2708 * 2709 * This will take the node configuration (eg 11n, rate table 2710 * setup, etc) into consideration. 2711 */ 2712 static uint32_t 2713 iwn_rate_to_plcp(struct iwn_softc *sc, struct ieee80211_node *ni, 2714 uint8_t rate) 2715 { 2716 #define RV(v) ((v) & IEEE80211_RATE_VAL) 2717 struct ieee80211com *ic = ni->ni_ic; 2718 uint8_t txant1, txant2; 2719 uint32_t plcp = 0; 2720 int ridx; 2721 2722 /* Use the first valid TX antenna. */ 2723 txant1 = IWN_LSB(sc->txchainmask); 2724 txant2 = IWN_LSB(sc->txchainmask & ~txant1); 2725 2726 /* 2727 * If it's an MCS rate, let's set the plcp correctly 2728 * and set the relevant flags based on the node config. 2729 */ 2730 if (rate & IEEE80211_RATE_MCS) { 2731 /* 2732 * Set the initial PLCP value to be between 0->31 for 2733 * MCS 0 -> MCS 31, then set the "I'm an MCS rate!" 2734 * flag. 2735 */ 2736 plcp = RV(rate) | IWN_RFLAG_MCS; 2737 2738 /* 2739 * XXX the following should only occur if both 2740 * the local configuration _and_ the remote node 2741 * advertise these capabilities. Thus this code 2742 * may need fixing! 2743 */ 2744 2745 /* 2746 * Set the channel width and guard interval. 2747 */ 2748 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 2749 plcp |= IWN_RFLAG_HT40; 2750 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40) 2751 plcp |= IWN_RFLAG_SGI; 2752 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20) { 2753 plcp |= IWN_RFLAG_SGI; 2754 } 2755 2756 /* 2757 * If it's a two stream rate, enable TX on both 2758 * antennas. 2759 * 2760 * XXX three stream rates? 2761 */ 2762 if (rate > 0x87) 2763 plcp |= IWN_RFLAG_ANT(txant1 | txant2); 2764 else 2765 plcp |= IWN_RFLAG_ANT(txant1); 2766 } else { 2767 /* 2768 * Set the initial PLCP - fine for both 2769 * OFDM and CCK rates. 2770 */ 2771 plcp = rate2plcp(rate); 2772 2773 /* Set CCK flag if it's CCK */ 2774 2775 /* XXX It would be nice to have a method 2776 * to map the ridx -> phy table entry 2777 * so we could just query that, rather than 2778 * this hack to check against IWN_RIDX_OFDM6. 2779 */ 2780 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 2781 rate & IEEE80211_RATE_VAL); 2782 if (ridx < IWN_RIDX_OFDM6 && 2783 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 2784 plcp |= IWN_RFLAG_CCK; 2785 2786 /* Set antenna configuration */ 2787 plcp |= IWN_RFLAG_ANT(txant1); 2788 } 2789 2790 DPRINTF(sc, IWN_DEBUG_TXRATE, "%s: rate=0x%02x, plcp=0x%08x\n", 2791 __func__, 2792 rate, 2793 plcp); 2794 2795 return (htole32(plcp)); 2796 #undef RV 2797 } 2798 2799 static void 2800 iwn_newassoc(struct ieee80211_node *ni, int isnew) 2801 { 2802 /* Doesn't do anything at the moment */ 2803 } 2804 2805 static int 2806 iwn_media_change(struct ifnet *ifp) 2807 { 2808 int error; 2809 2810 error = ieee80211_media_change(ifp); 2811 /* NB: only the fixed rate can change and that doesn't need a reset */ 2812 return (error == ENETRESET ? 0 : error); 2813 } 2814 2815 static int 2816 iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2817 { 2818 struct iwn_vap *ivp = IWN_VAP(vap); 2819 struct ieee80211com *ic = vap->iv_ic; 2820 struct iwn_softc *sc = ic->ic_ifp->if_softc; 2821 int error = 0; 2822 2823 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2824 2825 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 2826 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); 2827 2828 callout_stop(&sc->calib_to); 2829 2830 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 2831 2832 switch (nstate) { 2833 case IEEE80211_S_ASSOC: 2834 if (vap->iv_state != IEEE80211_S_RUN) 2835 break; 2836 /* FALLTHROUGH */ 2837 case IEEE80211_S_AUTH: 2838 if (vap->iv_state == IEEE80211_S_AUTH) 2839 break; 2840 2841 /* 2842 * !AUTH -> AUTH transition requires state reset to handle 2843 * reassociations correctly. 2844 */ 2845 sc->rxon->associd = 0; 2846 sc->rxon->filter &= ~htole32(IWN_FILTER_BSS); 2847 sc->calib.state = IWN_CALIB_STATE_INIT; 2848 2849 if ((error = iwn_auth(sc, vap)) != 0) { 2850 device_printf(sc->sc_dev, 2851 "%s: could not move to auth state\n", __func__); 2852 } 2853 break; 2854 2855 case IEEE80211_S_RUN: 2856 /* 2857 * RUN -> RUN transition; Just restart the timers. 2858 */ 2859 if (vap->iv_state == IEEE80211_S_RUN) { 2860 sc->calib_cnt = 0; 2861 break; 2862 } 2863 2864 /* 2865 * !RUN -> RUN requires setting the association id 2866 * which is done with a firmware cmd. We also defer 2867 * starting the timers until that work is done. 2868 */ 2869 if ((error = iwn_run(sc, vap)) != 0) { 2870 device_printf(sc->sc_dev, 2871 "%s: could not move to run state\n", __func__); 2872 } 2873 break; 2874 2875 case IEEE80211_S_INIT: 2876 sc->calib.state = IWN_CALIB_STATE_INIT; 2877 break; 2878 2879 default: 2880 break; 2881 } 2882 if (error != 0){ 2883 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 2884 return error; 2885 } 2886 2887 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 2888 2889 return ivp->iv_newstate(vap, nstate, arg); 2890 } 2891 2892 static void 2893 iwn_calib_timeout(void *arg) 2894 { 2895 struct iwn_softc *sc = arg; 2896 2897 wlan_serialize_enter(); 2898 2899 /* Force automatic TX power calibration every 60 secs. */ 2900 if (++sc->calib_cnt >= 120) { 2901 uint32_t flags = 0; 2902 2903 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n", 2904 "sending request for statistics"); 2905 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 2906 sizeof flags, 1); 2907 sc->calib_cnt = 0; 2908 } 2909 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 2910 sc); 2911 wlan_serialize_exit(); 2912 } 2913 2914 /* 2915 * Process an RX_PHY firmware notification. This is usually immediately 2916 * followed by an MPDU_RX_DONE notification. 2917 */ 2918 static void 2919 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2920 struct iwn_rx_data *data) 2921 { 2922 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 2923 2924 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__); 2925 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2926 2927 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 2928 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 2929 sc->last_rx_valid = 1; 2930 } 2931 2932 /* 2933 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 2934 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 2935 */ 2936 static void 2937 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2938 struct iwn_rx_data *data) 2939 { 2940 struct iwn_ops *ops = &sc->ops; 2941 struct ifnet *ifp = sc->sc_ifp; 2942 struct ieee80211com *ic = ifp->if_l2com; 2943 struct iwn_rx_ring *ring = &sc->rxq; 2944 struct ieee80211_frame *wh; 2945 struct ieee80211_node *ni; 2946 struct mbuf *m, *m1; 2947 struct iwn_rx_stat *stat; 2948 caddr_t head; 2949 bus_addr_t paddr; 2950 uint32_t flags; 2951 int error, len, rssi, nf; 2952 2953 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 2954 2955 if (desc->type == IWN_MPDU_RX_DONE) { 2956 /* Check for prior RX_PHY notification. */ 2957 if (!sc->last_rx_valid) { 2958 DPRINTF(sc, IWN_DEBUG_ANY, 2959 "%s: missing RX_PHY\n", __func__); 2960 return; 2961 } 2962 stat = &sc->last_rx_stat; 2963 } else 2964 stat = (struct iwn_rx_stat *)(desc + 1); 2965 2966 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 2967 2968 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2969 device_printf(sc->sc_dev, 2970 "%s: invalid RX statistic header, len %d\n", __func__, 2971 stat->cfg_phy_len); 2972 return; 2973 } 2974 if (desc->type == IWN_MPDU_RX_DONE) { 2975 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2976 head = (caddr_t)(mpdu + 1); 2977 len = le16toh(mpdu->len); 2978 } else { 2979 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2980 len = le16toh(stat->len); 2981 } 2982 2983 flags = le32toh(*(uint32_t *)(head + len)); 2984 2985 /* Discard frames with a bad FCS early. */ 2986 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2987 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n", 2988 __func__, flags); 2989 IFNET_STAT_INC(ifp, ierrors, 1); 2990 return; 2991 } 2992 /* Discard frames that are too short. */ 2993 if (len < sizeof (*wh)) { 2994 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n", 2995 __func__, len); 2996 IFNET_STAT_INC(ifp, ierrors, 1); 2997 return; 2998 } 2999 3000 m1 = m_getjcl(MB_DONTWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE); 3001 if (m1 == NULL) { 3002 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n", 3003 __func__); 3004 IFNET_STAT_INC(ifp, ierrors, 1); 3005 return; 3006 } 3007 bus_dmamap_unload(ring->data_dmat, data->map); 3008 3009 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *), 3010 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 3011 if (error != 0 && error != EFBIG) { 3012 device_printf(sc->sc_dev, 3013 "%s: bus_dmamap_load failed, error %d\n", __func__, error); 3014 m_freem(m1); 3015 3016 /* Try to reload the old mbuf. */ 3017 error = bus_dmamap_load(ring->data_dmat, data->map, 3018 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr, 3019 &paddr, BUS_DMA_NOWAIT); 3020 if (error != 0 && error != EFBIG) { 3021 panic("%s: could not load old RX mbuf", __func__); 3022 } 3023 /* Physical address may have changed. */ 3024 ring->desc[ring->cur] = htole32(paddr >> 8); 3025 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map, 3026 BUS_DMASYNC_PREWRITE); 3027 IFNET_STAT_INC(ifp, ierrors, 1); 3028 return; 3029 } 3030 3031 m = data->m; 3032 data->m = m1; 3033 /* Update RX descriptor. */ 3034 ring->desc[ring->cur] = htole32(paddr >> 8); 3035 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 3036 BUS_DMASYNC_PREWRITE); 3037 3038 /* Finalize mbuf. */ 3039 m->m_pkthdr.rcvif = ifp; 3040 m->m_data = head; 3041 m->m_pkthdr.len = m->m_len = len; 3042 3043 /* Grab a reference to the source node. */ 3044 wh = mtod(m, struct ieee80211_frame *); 3045 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh); 3046 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN && 3047 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95; 3048 3049 rssi = ops->get_rssi(sc, stat); 3050 3051 if (ieee80211_radiotap_active(ic)) { 3052 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 3053 3054 tap->wr_flags = 0; 3055 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 3056 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3057 tap->wr_dbm_antsignal = (int8_t)rssi; 3058 tap->wr_dbm_antnoise = (int8_t)nf; 3059 tap->wr_tsft = stat->tstamp; 3060 switch (stat->rate) { 3061 /* CCK rates. */ 3062 case 10: tap->wr_rate = 2; break; 3063 case 20: tap->wr_rate = 4; break; 3064 case 55: tap->wr_rate = 11; break; 3065 case 110: tap->wr_rate = 22; break; 3066 /* OFDM rates. */ 3067 case 0xd: tap->wr_rate = 12; break; 3068 case 0xf: tap->wr_rate = 18; break; 3069 case 0x5: tap->wr_rate = 24; break; 3070 case 0x7: tap->wr_rate = 36; break; 3071 case 0x9: tap->wr_rate = 48; break; 3072 case 0xb: tap->wr_rate = 72; break; 3073 case 0x1: tap->wr_rate = 96; break; 3074 case 0x3: tap->wr_rate = 108; break; 3075 /* Unknown rate: should not happen. */ 3076 default: tap->wr_rate = 0; 3077 } 3078 } 3079 3080 /* Send the frame to the 802.11 layer. */ 3081 if (ni != NULL) { 3082 if (ni->ni_flags & IEEE80211_NODE_HT) 3083 m->m_flags |= M_AMPDU; 3084 (void)ieee80211_input(ni, m, rssi - nf, nf); 3085 /* Node is no longer needed. */ 3086 ieee80211_free_node(ni); 3087 } else { 3088 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 3089 } 3090 3091 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3092 3093 } 3094 3095 /* Process an incoming Compressed BlockAck. */ 3096 static void 3097 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3098 struct iwn_rx_data *data) 3099 { 3100 struct iwn_ops *ops = &sc->ops; 3101 struct ifnet *ifp = sc->sc_ifp; 3102 struct iwn_node *wn; 3103 struct ieee80211_node *ni; 3104 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1); 3105 struct iwn_tx_ring *txq; 3106 struct iwn_tx_data *txdata; 3107 struct ieee80211_tx_ampdu *tap; 3108 struct mbuf *m; 3109 uint64_t bitmap; 3110 uint16_t ssn; 3111 uint8_t tid; 3112 int ackfailcnt = 0, i, lastidx, qid, *res, shift; 3113 3114 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3115 3116 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3117 3118 qid = le16toh(ba->qid); 3119 txq = &sc->txq[ba->qid]; 3120 tap = sc->qid2tap[ba->qid]; 3121 tid = tap->txa_ac; 3122 wn = (void *)tap->txa_ni; 3123 3124 res = NULL; 3125 ssn = 0; 3126 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3127 res = tap->txa_private; 3128 ssn = tap->txa_start & 0xfff; 3129 } 3130 3131 for (lastidx = le16toh(ba->ssn) & 0xff; txq->read != lastidx;) { 3132 txdata = &txq->data[txq->read]; 3133 3134 /* Unmap and free mbuf. */ 3135 bus_dmamap_sync(txq->data_dmat, txdata->map, 3136 BUS_DMASYNC_POSTWRITE); 3137 bus_dmamap_unload(txq->data_dmat, txdata->map); 3138 m = txdata->m, txdata->m = NULL; 3139 ni = txdata->ni, txdata->ni = NULL; 3140 3141 KASSERT(ni != NULL, ("no node")); 3142 KASSERT(m != NULL, ("no mbuf")); 3143 3144 ieee80211_tx_complete(ni, m, 1); 3145 3146 txq->queued--; 3147 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 3148 } 3149 3150 if (txq->queued == 0 && res != NULL) { 3151 iwn_nic_lock(sc); 3152 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3153 iwn_nic_unlock(sc); 3154 sc->qid2tap[qid] = NULL; 3155 kfree(res, M_DEVBUF); 3156 return; 3157 } 3158 3159 if (wn->agg[tid].bitmap == 0) 3160 return; 3161 3162 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff); 3163 if (shift < 0) 3164 shift += 0x100; 3165 3166 if (wn->agg[tid].nframes > (64 - shift)) 3167 return; 3168 3169 ni = tap->txa_ni; 3170 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap; 3171 for (i = 0; bitmap; i++) { 3172 if ((bitmap & 1) == 0) { 3173 IFNET_STAT_INC(ifp, oerrors, 1); 3174 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3175 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 3176 } else { 3177 IFNET_STAT_INC(ifp, opackets, 1); 3178 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3179 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 3180 } 3181 bitmap >>= 1; 3182 } 3183 3184 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3185 3186 } 3187 3188 /* 3189 * Process a CALIBRATION_RESULT notification sent by the initialization 3190 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 3191 */ 3192 static void 3193 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3194 struct iwn_rx_data *data) 3195 { 3196 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 3197 int len, idx = -1; 3198 3199 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3200 3201 /* Runtime firmware should not send such a notification. */ 3202 if (sc->sc_flags & IWN_FLAG_CALIB_DONE){ 3203 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received after clib done\n", 3204 __func__); 3205 return; 3206 } 3207 len = (le32toh(desc->len) & 0x3fff) - 4; 3208 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3209 3210 switch (calib->code) { 3211 case IWN5000_PHY_CALIB_DC: 3212 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_DC) 3213 idx = 0; 3214 break; 3215 case IWN5000_PHY_CALIB_LO: 3216 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_LO) 3217 idx = 1; 3218 break; 3219 case IWN5000_PHY_CALIB_TX_IQ: 3220 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ) 3221 idx = 2; 3222 break; 3223 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 3224 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TX_IQ_PERIODIC) 3225 idx = 3; 3226 break; 3227 case IWN5000_PHY_CALIB_BASE_BAND: 3228 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_BASE_BAND) 3229 idx = 4; 3230 break; 3231 } 3232 if (idx == -1) /* Ignore other results. */ 3233 return; 3234 3235 /* Save calibration result. */ 3236 if (sc->calibcmd[idx].buf != NULL) 3237 kfree(sc->calibcmd[idx].buf, M_DEVBUF); 3238 sc->calibcmd[idx].buf = kmalloc(len, M_DEVBUF, M_INTWAIT); 3239 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 3240 "saving calibration result idx=%d, code=%d len=%d\n", idx, calib->code, len); 3241 sc->calibcmd[idx].len = len; 3242 memcpy(sc->calibcmd[idx].buf, calib, len); 3243 } 3244 3245 static void 3246 iwn_stats_update(struct iwn_softc *sc, struct iwn_calib_state *calib, 3247 struct iwn_stats *stats, int len) 3248 { 3249 struct iwn_stats_bt *stats_bt; 3250 struct iwn_stats *lstats; 3251 3252 /* 3253 * First - check whether the length is the bluetooth or normal. 3254 * 3255 * If it's normal - just copy it and bump out. 3256 * Otherwise we have to convert things. 3257 */ 3258 3259 if (len == sizeof(struct iwn_stats) + 4) { 3260 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3261 sc->last_stat_valid = 1; 3262 return; 3263 } 3264 3265 /* 3266 * If it's not the bluetooth size - log, then just copy. 3267 */ 3268 if (len != sizeof(struct iwn_stats_bt) + 4) { 3269 DPRINTF(sc, IWN_DEBUG_STATS, 3270 "%s: size of rx statistics (%d) not an expected size!\n", 3271 __func__, 3272 len); 3273 memcpy(&sc->last_stat, stats, sizeof(struct iwn_stats)); 3274 sc->last_stat_valid = 1; 3275 return; 3276 } 3277 3278 /* 3279 * Ok. Time to copy. 3280 */ 3281 stats_bt = (struct iwn_stats_bt *) stats; 3282 lstats = &sc->last_stat; 3283 3284 /* flags */ 3285 lstats->flags = stats_bt->flags; 3286 /* rx_bt */ 3287 memcpy(&lstats->rx.ofdm, &stats_bt->rx_bt.ofdm, 3288 sizeof(struct iwn_rx_phy_stats)); 3289 memcpy(&lstats->rx.cck, &stats_bt->rx_bt.cck, 3290 sizeof(struct iwn_rx_phy_stats)); 3291 memcpy(&lstats->rx.general, &stats_bt->rx_bt.general_bt.common, 3292 sizeof(struct iwn_rx_general_stats)); 3293 memcpy(&lstats->rx.ht, &stats_bt->rx_bt.ht, 3294 sizeof(struct iwn_rx_ht_phy_stats)); 3295 /* tx */ 3296 memcpy(&lstats->tx, &stats_bt->tx, 3297 sizeof(struct iwn_tx_stats)); 3298 /* general */ 3299 memcpy(&lstats->general, &stats_bt->general, 3300 sizeof(struct iwn_general_stats)); 3301 3302 /* XXX TODO: Squirrel away the extra bluetooth stats somewhere */ 3303 sc->last_stat_valid = 1; 3304 } 3305 3306 /* 3307 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 3308 * The latter is sent by the firmware after each received beacon. 3309 */ 3310 static void 3311 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3312 struct iwn_rx_data *data) 3313 { 3314 struct iwn_ops *ops = &sc->ops; 3315 struct ifnet *ifp = sc->sc_ifp; 3316 struct ieee80211com *ic = ifp->if_l2com; 3317 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3318 struct iwn_calib_state *calib = &sc->calib; 3319 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 3320 struct iwn_stats *lstats; 3321 int temp; 3322 3323 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3324 3325 /* Ignore statistics received during a scan. */ 3326 if (vap->iv_state != IEEE80211_S_RUN || 3327 (ic->ic_flags & IEEE80211_F_SCAN)){ 3328 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s received during calib\n", 3329 __func__); 3330 return; 3331 } 3332 3333 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3334 3335 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_STATS, 3336 "%s: received statistics, cmd %d, len %d\n", 3337 __func__, desc->type, le16toh(desc->len)); 3338 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 3339 3340 /* 3341 * Collect/track general statistics for reporting. 3342 * 3343 * This takes care of ensuring that the bluetooth sized message 3344 * will be correctly converted to the legacy sized message. 3345 */ 3346 iwn_stats_update(sc, calib, stats, le16toh(desc->len)); 3347 3348 /* 3349 * And now, let's take a reference of it to use! 3350 */ 3351 lstats = &sc->last_stat; 3352 3353 /* Test if temperature has changed. */ 3354 if (lstats->general.temp != sc->rawtemp) { 3355 /* Convert "raw" temperature to degC. */ 3356 sc->rawtemp = stats->general.temp; 3357 temp = ops->get_temperature(sc); 3358 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n", 3359 __func__, temp); 3360 3361 /* Update TX power if need be (4965AGN only). */ 3362 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 3363 iwn4965_power_calibration(sc, temp); 3364 } 3365 3366 if (desc->type != IWN_BEACON_STATISTICS) 3367 return; /* Reply to a statistics request. */ 3368 3369 sc->noise = iwn_get_noise(&lstats->rx.general); 3370 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise); 3371 3372 /* Test that RSSI and noise are present in stats report. */ 3373 if (le32toh(lstats->rx.general.flags) != 1) { 3374 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n", 3375 "received statistics without RSSI"); 3376 return; 3377 } 3378 3379 if (calib->state == IWN_CALIB_STATE_ASSOC) 3380 iwn_collect_noise(sc, &lstats->rx.general); 3381 else if (calib->state == IWN_CALIB_STATE_RUN) { 3382 iwn_tune_sensitivity(sc, &lstats->rx); 3383 /* 3384 * XXX TODO: Only run the RX recovery if we're associated! 3385 */ 3386 iwn_check_rx_recovery(sc, lstats); 3387 iwn_save_stats_counters(sc, lstats); 3388 } 3389 3390 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3391 } 3392 3393 /* 3394 * Save the relevant statistic counters for the next calibration 3395 * pass. 3396 */ 3397 static void 3398 iwn_save_stats_counters(struct iwn_softc *sc, const struct iwn_stats *rs) 3399 { 3400 struct iwn_calib_state *calib = &sc->calib; 3401 3402 /* Save counters values for next call. */ 3403 calib->bad_plcp_cck = le32toh(rs->rx.cck.bad_plcp); 3404 calib->fa_cck = le32toh(rs->rx.cck.fa); 3405 calib->bad_plcp_ht = le32toh(rs->rx.ht.bad_plcp); 3406 calib->bad_plcp_ofdm = le32toh(rs->rx.ofdm.bad_plcp); 3407 calib->fa_ofdm = le32toh(rs->rx.ofdm.fa); 3408 3409 /* Last time we received these tick values */ 3410 sc->last_calib_ticks = ticks; 3411 } 3412 3413 /* 3414 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 3415 * and 5000 adapters have different incompatible TX status formats. 3416 */ 3417 static void 3418 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3419 struct iwn_rx_data *data) 3420 { 3421 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 3422 struct iwn_tx_ring *ring; 3423 int qid; 3424 3425 qid = desc->qid & 0xf; 3426 ring = &sc->txq[qid]; 3427 3428 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3429 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 3430 __func__, desc->qid, desc->idx, stat->ackfailcnt, 3431 stat->btkillcnt, stat->rate, le16toh(stat->duration), 3432 le32toh(stat->status)); 3433 3434 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3435 if (qid >= sc->firstaggqueue) { 3436 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3437 &stat->status); 3438 } else { 3439 iwn_tx_done(sc, desc, stat->ackfailcnt, 3440 le32toh(stat->status) & 0xff); 3441 } 3442 } 3443 3444 static void 3445 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 3446 struct iwn_rx_data *data) 3447 { 3448 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 3449 struct iwn_tx_ring *ring; 3450 int qid; 3451 3452 qid = desc->qid & 0xf; 3453 ring = &sc->txq[qid]; 3454 3455 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: " 3456 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n", 3457 __func__, desc->qid, desc->idx, stat->ackfailcnt, 3458 stat->btkillcnt, stat->rate, le16toh(stat->duration), 3459 le32toh(stat->status)); 3460 3461 #ifdef notyet 3462 /* Reset TX scheduler slot. */ 3463 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx); 3464 #endif 3465 3466 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD); 3467 if (qid >= sc->firstaggqueue) { 3468 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes, 3469 &stat->status); 3470 } else { 3471 iwn_tx_done(sc, desc, stat->ackfailcnt, 3472 le16toh(stat->status) & 0xff); 3473 } 3474 } 3475 3476 /* 3477 * Adapter-independent backend for TX_DONE firmware notifications. 3478 */ 3479 static void 3480 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt, 3481 uint8_t status) 3482 { 3483 struct ifnet *ifp = sc->sc_ifp; 3484 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf]; 3485 struct iwn_tx_data *data = &ring->data[desc->idx]; 3486 struct mbuf *m; 3487 struct ieee80211_node *ni; 3488 struct ieee80211vap *vap; 3489 3490 KASSERT(data->ni != NULL, ("no node")); 3491 3492 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3493 3494 /* Unmap and free mbuf. */ 3495 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 3496 bus_dmamap_unload(ring->data_dmat, data->map); 3497 m = data->m, data->m = NULL; 3498 ni = data->ni, data->ni = NULL; 3499 vap = ni->ni_vap; 3500 3501 /* 3502 * Update rate control statistics for the node. 3503 */ 3504 if (status & IWN_TX_FAIL) { 3505 IFNET_STAT_INC(ifp, oerrors, 1); 3506 ieee80211_ratectl_tx_complete(vap, ni, 3507 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL); 3508 } else { 3509 IFNET_STAT_INC(ifp, opackets, 1); 3510 ieee80211_ratectl_tx_complete(vap, ni, 3511 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL); 3512 } 3513 3514 /* 3515 * Channels marked for "radar" require traffic to be received 3516 * to unlock before we can transmit. Until traffic is seen 3517 * any attempt to transmit is returned immediately with status 3518 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily 3519 * happen on first authenticate after scanning. To workaround 3520 * this we ignore a failure of this sort in AUTH state so the 3521 * 802.11 layer will fall back to using a timeout to wait for 3522 * the AUTH reply. This allows the firmware time to see 3523 * traffic so a subsequent retry of AUTH succeeds. It's 3524 * unclear why the firmware does not maintain state for 3525 * channels recently visited as this would allow immediate 3526 * use of the channel after a scan (where we see traffic). 3527 */ 3528 if (status == IWN_TX_FAIL_TX_LOCKED && 3529 ni->ni_vap->iv_state == IEEE80211_S_AUTH) 3530 ieee80211_tx_complete(ni, m, 0); 3531 else 3532 ieee80211_tx_complete(ni, m, 3533 (status & IWN_TX_FAIL) != 0); 3534 3535 sc->sc_tx_timer = 0; 3536 if (--ring->queued < IWN_TX_RING_LOMARK) { 3537 sc->qfullmsk &= ~(1 << ring->qid); 3538 if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) { 3539 ifq_clr_oactive(&ifp->if_snd); 3540 iwn_start_locked(ifp); 3541 } 3542 } 3543 3544 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3545 3546 } 3547 3548 /* 3549 * Process a "command done" firmware notification. This is where we wakeup 3550 * processes waiting for a synchronous command completion. 3551 */ 3552 static void 3553 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 3554 { 3555 struct iwn_tx_ring *ring; 3556 struct iwn_tx_data *data; 3557 int cmd_queue_num; 3558 3559 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 3560 cmd_queue_num = IWN_PAN_CMD_QUEUE; 3561 else 3562 cmd_queue_num = IWN_CMD_QUEUE_NUM; 3563 3564 if ((desc->qid & IWN_RX_DESC_QID_MSK) != cmd_queue_num) 3565 return; /* Not a command ack. */ 3566 3567 ring = &sc->txq[cmd_queue_num]; 3568 data = &ring->data[desc->idx]; 3569 3570 /* If the command was mapped in an mbuf, free it. */ 3571 if (data->m != NULL) { 3572 bus_dmamap_sync(ring->data_dmat, data->map, 3573 BUS_DMASYNC_POSTWRITE); 3574 bus_dmamap_unload(ring->data_dmat, data->map); 3575 m_freem(data->m); 3576 data->m = NULL; 3577 } 3578 wakeup(&ring->desc[desc->idx]); 3579 } 3580 3581 static void 3582 iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes, 3583 void *stat) 3584 { 3585 struct iwn_ops *ops = &sc->ops; 3586 struct ifnet *ifp = sc->sc_ifp; 3587 struct iwn_tx_ring *ring = &sc->txq[qid]; 3588 struct iwn_tx_data *data; 3589 struct mbuf *m; 3590 struct iwn_node *wn; 3591 struct ieee80211_node *ni; 3592 struct ieee80211_tx_ampdu *tap; 3593 uint64_t bitmap; 3594 uint32_t *status = stat; 3595 uint16_t *aggstatus = stat; 3596 uint16_t ssn; 3597 uint8_t tid; 3598 int bit, i, lastidx, *res, seqno, shift, start; 3599 3600 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 3601 3602 if (nframes == 1) { 3603 if ((*status & 0xff) != 1 && (*status & 0xff) != 2) { 3604 #ifdef NOT_YET 3605 kprintf("ieee80211_send_bar()\n"); 3606 #endif 3607 /* 3608 * If we completely fail a transmit, make sure a 3609 * notification is pushed up to the rate control 3610 * layer. 3611 */ 3612 tap = sc->qid2tap[qid]; 3613 tid = tap->txa_ac; 3614 wn = (void *)tap->txa_ni; 3615 ni = tap->txa_ni; 3616 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 3617 IEEE80211_RATECTL_TX_FAILURE, &nframes, NULL); 3618 } 3619 } 3620 3621 bitmap = 0; 3622 start = idx; 3623 for (i = 0; i < nframes; i++) { 3624 if (le16toh(aggstatus[i * 2]) & 0xc) 3625 continue; 3626 3627 idx = le16toh(aggstatus[2*i + 1]) & 0xff; 3628 bit = idx - start; 3629 shift = 0; 3630 if (bit >= 64) { 3631 shift = 0x100 - idx + start; 3632 bit = 0; 3633 start = idx; 3634 } else if (bit <= -64) 3635 bit = 0x100 - start + idx; 3636 else if (bit < 0) { 3637 shift = start - idx; 3638 start = idx; 3639 bit = 0; 3640 } 3641 bitmap = bitmap << shift; 3642 bitmap |= 1ULL << bit; 3643 } 3644 tap = sc->qid2tap[qid]; 3645 tid = tap->txa_ac; 3646 wn = (void *)tap->txa_ni; 3647 wn->agg[tid].bitmap = bitmap; 3648 wn->agg[tid].startidx = start; 3649 wn->agg[tid].nframes = nframes; 3650 3651 res = NULL; 3652 ssn = 0; 3653 if (!IEEE80211_AMPDU_RUNNING(tap)) { 3654 res = tap->txa_private; 3655 ssn = tap->txa_start & 0xfff; 3656 } 3657 3658 seqno = le32toh(*(status + nframes)) & 0xfff; 3659 for (lastidx = (seqno & 0xff); ring->read != lastidx;) { 3660 data = &ring->data[ring->read]; 3661 3662 /* Unmap and free mbuf. */ 3663 bus_dmamap_sync(ring->data_dmat, data->map, 3664 BUS_DMASYNC_POSTWRITE); 3665 bus_dmamap_unload(ring->data_dmat, data->map); 3666 m = data->m, data->m = NULL; 3667 ni = data->ni, data->ni = NULL; 3668 3669 KASSERT(ni != NULL, ("no node")); 3670 KASSERT(m != NULL, ("no mbuf")); 3671 3672 ieee80211_tx_complete(ni, m, 1); 3673 3674 ring->queued--; 3675 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT; 3676 } 3677 3678 if (ring->queued == 0 && res != NULL) { 3679 iwn_nic_lock(sc); 3680 ops->ampdu_tx_stop(sc, qid, tid, ssn); 3681 iwn_nic_unlock(sc); 3682 sc->qid2tap[qid] = NULL; 3683 kfree(res, M_DEVBUF); 3684 return; 3685 } 3686 3687 sc->sc_tx_timer = 0; 3688 if (ring->queued < IWN_TX_RING_LOMARK) { 3689 sc->qfullmsk &= ~(1 << ring->qid); 3690 if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) { 3691 ifq_clr_oactive(&ifp->if_snd); 3692 iwn_start_locked(ifp); 3693 } 3694 } 3695 3696 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 3697 3698 } 3699 3700 /* 3701 * Process an INT_FH_RX or INT_SW_RX interrupt. 3702 */ 3703 static void 3704 iwn_notif_intr(struct iwn_softc *sc) 3705 { 3706 struct iwn_ops *ops = &sc->ops; 3707 struct ifnet *ifp = sc->sc_ifp; 3708 struct ieee80211com *ic = ifp->if_l2com; 3709 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3710 uint16_t hw; 3711 3712 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map, 3713 BUS_DMASYNC_POSTREAD); 3714 3715 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff; 3716 while (sc->rxq.cur != hw) { 3717 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 3718 struct iwn_rx_desc *desc; 3719 3720 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3721 BUS_DMASYNC_POSTREAD); 3722 desc = mtod(data->m, struct iwn_rx_desc *); 3723 3724 DPRINTF(sc, IWN_DEBUG_RECV, 3725 "%s: cur=%d; qid %x idx %d flags %x type %d(%s) len %d\n", 3726 __func__, sc->rxq.cur, desc->qid & 0xf, desc->idx, desc->flags, 3727 desc->type, iwn_intr_str(desc->type), 3728 le16toh(desc->len)); 3729 3730 if (!(desc->qid & IWN_UNSOLICITED_RX_NOTIF)) /* Reply to a command. */ 3731 iwn_cmd_done(sc, desc); 3732 3733 switch (desc->type) { 3734 case IWN_RX_PHY: 3735 iwn_rx_phy(sc, desc, data); 3736 break; 3737 3738 case IWN_RX_DONE: /* 4965AGN only. */ 3739 case IWN_MPDU_RX_DONE: 3740 /* An 802.11 frame has been received. */ 3741 iwn_rx_done(sc, desc, data); 3742 break; 3743 3744 case IWN_RX_COMPRESSED_BA: 3745 /* A Compressed BlockAck has been received. */ 3746 iwn_rx_compressed_ba(sc, desc, data); 3747 break; 3748 3749 case IWN_TX_DONE: 3750 /* An 802.11 frame has been transmitted. */ 3751 ops->tx_done(sc, desc, data); 3752 break; 3753 3754 case IWN_RX_STATISTICS: 3755 case IWN_BEACON_STATISTICS: 3756 iwn_rx_statistics(sc, desc, data); 3757 break; 3758 3759 case IWN_BEACON_MISSED: 3760 { 3761 struct iwn_beacon_missed *miss = 3762 (struct iwn_beacon_missed *)(desc + 1); 3763 int misses; 3764 3765 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3766 BUS_DMASYNC_POSTREAD); 3767 misses = le32toh(miss->consecutive); 3768 3769 DPRINTF(sc, IWN_DEBUG_STATE, 3770 "%s: beacons missed %d/%d\n", __func__, 3771 misses, le32toh(miss->total)); 3772 /* 3773 * If more than 5 consecutive beacons are missed, 3774 * reinitialize the sensitivity state machine. 3775 */ 3776 if (vap->iv_state == IEEE80211_S_RUN && 3777 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 3778 if (misses > 5) 3779 (void)iwn_init_sensitivity(sc); 3780 if (misses >= vap->iv_bmissthreshold) { 3781 ieee80211_beacon_miss(ic); 3782 } 3783 } 3784 break; 3785 } 3786 case IWN_UC_READY: 3787 { 3788 struct iwn_ucode_info *uc = 3789 (struct iwn_ucode_info *)(desc + 1); 3790 3791 /* The microcontroller is ready. */ 3792 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3793 BUS_DMASYNC_POSTREAD); 3794 DPRINTF(sc, IWN_DEBUG_RESET, 3795 "microcode alive notification version=%d.%d " 3796 "subtype=%x alive=%x\n", uc->major, uc->minor, 3797 uc->subtype, le32toh(uc->valid)); 3798 3799 if (le32toh(uc->valid) != 1) { 3800 device_printf(sc->sc_dev, 3801 "microcontroller initialization failed"); 3802 break; 3803 } 3804 if (uc->subtype == IWN_UCODE_INIT) { 3805 /* Save microcontroller report. */ 3806 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 3807 } 3808 /* Save the address of the error log in SRAM. */ 3809 sc->errptr = le32toh(uc->errptr); 3810 break; 3811 } 3812 case IWN_STATE_CHANGED: 3813 { 3814 /* 3815 * State change allows hardware switch change to be 3816 * noted. However, we handle this in iwn_intr as we 3817 * get both the enable/disble intr. 3818 */ 3819 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3820 BUS_DMASYNC_POSTREAD); 3821 #ifdef IWN_DEBUG 3822 uint32_t *status = (uint32_t *)(desc + 1); 3823 DPRINTF(sc, IWN_DEBUG_INTR | IWN_DEBUG_STATE, 3824 "state changed to %x\n", 3825 le32toh(*status)); 3826 #endif 3827 break; 3828 } 3829 case IWN_START_SCAN: 3830 { 3831 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3832 BUS_DMASYNC_POSTREAD); 3833 #ifdef IWN_DEBUG 3834 struct iwn_start_scan *scan = 3835 (struct iwn_start_scan *)(desc + 1); 3836 DPRINTF(sc, IWN_DEBUG_ANY, 3837 "%s: scanning channel %d status %x\n", 3838 __func__, scan->chan, le32toh(scan->status)); 3839 #endif 3840 break; 3841 } 3842 case IWN_STOP_SCAN: 3843 { 3844 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 3845 BUS_DMASYNC_POSTREAD); 3846 #ifdef IWN_DEBUG 3847 struct iwn_stop_scan *scan = 3848 (struct iwn_stop_scan *)(desc + 1); 3849 DPRINTF(sc, IWN_DEBUG_STATE | IWN_DEBUG_SCAN, 3850 "scan finished nchan=%d status=%d chan=%d\n", 3851 scan->nchan, scan->status, scan->chan); 3852 #endif 3853 sc->sc_is_scanning = 0; 3854 ieee80211_scan_next(vap); 3855 break; 3856 } 3857 case IWN5000_CALIBRATION_RESULT: 3858 iwn5000_rx_calib_results(sc, desc, data); 3859 break; 3860 3861 case IWN5000_CALIBRATION_DONE: 3862 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3863 wakeup(sc); 3864 break; 3865 } 3866 3867 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3868 } 3869 3870 /* Tell the firmware what we have processed. */ 3871 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3872 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3873 } 3874 3875 /* 3876 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3877 * from power-down sleep mode. 3878 */ 3879 static void 3880 iwn_wakeup_intr(struct iwn_softc *sc) 3881 { 3882 int qid; 3883 3884 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n", 3885 __func__); 3886 3887 /* Wakeup RX and TX rings. */ 3888 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 3889 for (qid = 0; qid < sc->ntxqs; qid++) { 3890 struct iwn_tx_ring *ring = &sc->txq[qid]; 3891 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 3892 } 3893 } 3894 3895 static void 3896 iwn_rftoggle_intr(struct iwn_softc *sc) 3897 { 3898 struct ifnet *ifp = sc->sc_ifp; 3899 struct ieee80211com *ic = ifp->if_l2com; 3900 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL); 3901 3902 device_printf(sc->sc_dev, "RF switch: radio %s\n", 3903 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled"); 3904 if (tmp & IWN_GP_CNTRL_RFKILL) 3905 ieee80211_runtask(ic, &sc->sc_radioon_task); 3906 else 3907 ieee80211_runtask(ic, &sc->sc_radiooff_task); 3908 } 3909 3910 /* 3911 * Dump the error log of the firmware when a firmware panic occurs. Although 3912 * we can't debug the firmware because it is neither open source nor free, it 3913 * can help us to identify certain classes of problems. 3914 */ 3915 static void 3916 iwn_fatal_intr(struct iwn_softc *sc) 3917 { 3918 struct iwn_fw_dump dump; 3919 int i; 3920 3921 /* Force a complete recalibration on next init. */ 3922 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 3923 3924 /* Check that the error log address is valid. */ 3925 if (sc->errptr < IWN_FW_DATA_BASE || 3926 sc->errptr + sizeof (dump) > 3927 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 3928 kprintf("%s: bad firmware error log address 0x%08x\n", __func__, 3929 sc->errptr); 3930 return; 3931 } 3932 if (iwn_nic_lock(sc) != 0) { 3933 kprintf("%s: could not read firmware error log\n", __func__); 3934 return; 3935 } 3936 /* Read firmware error log from SRAM. */ 3937 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 3938 sizeof (dump) / sizeof (uint32_t)); 3939 iwn_nic_unlock(sc); 3940 3941 if (dump.valid == 0) { 3942 kprintf("%s: firmware error log is empty\n", __func__); 3943 return; 3944 } 3945 kprintf("firmware error log:\n"); 3946 kprintf(" error type = \"%s\" (0x%08X)\n", 3947 (dump.id < nitems(iwn_fw_errmsg)) ? 3948 iwn_fw_errmsg[dump.id] : "UNKNOWN", 3949 dump.id); 3950 kprintf(" program counter = 0x%08X\n", dump.pc); 3951 kprintf(" source line = 0x%08X\n", dump.src_line); 3952 kprintf(" error data = 0x%08X%08X\n", 3953 dump.error_data[0], dump.error_data[1]); 3954 kprintf(" branch link = 0x%08X%08X\n", 3955 dump.branch_link[0], dump.branch_link[1]); 3956 kprintf(" interrupt link = 0x%08X%08X\n", 3957 dump.interrupt_link[0], dump.interrupt_link[1]); 3958 kprintf(" time = %u\n", dump.time[0]); 3959 3960 /* Dump driver status (TX and RX rings) while we're here. */ 3961 kprintf("driver status:\n"); 3962 for (i = 0; i < sc->ntxqs; i++) { 3963 struct iwn_tx_ring *ring = &sc->txq[i]; 3964 kprintf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 3965 i, ring->qid, ring->cur, ring->queued); 3966 } 3967 kprintf(" rx ring: cur=%d\n", sc->rxq.cur); 3968 } 3969 3970 static void 3971 iwn_intr(void *arg) 3972 { 3973 struct iwn_softc *sc = arg; 3974 struct ifnet *ifp = sc->sc_ifp; 3975 uint32_t r1, r2, tmp; 3976 3977 /* Disable interrupts. */ 3978 IWN_WRITE(sc, IWN_INT_MASK, 0); 3979 3980 /* Read interrupts from ICT (fast) or from registers (slow). */ 3981 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3982 tmp = 0; 3983 while (sc->ict[sc->ict_cur] != 0) { 3984 tmp |= sc->ict[sc->ict_cur]; 3985 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 3986 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 3987 } 3988 tmp = le32toh(tmp); 3989 if (tmp == 0xffffffff) /* Shouldn't happen. */ 3990 tmp = 0; 3991 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 3992 tmp |= 0x8000; 3993 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 3994 r2 = 0; /* Unused. */ 3995 } else { 3996 r1 = IWN_READ(sc, IWN_INT); 3997 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 3998 return; /* Hardware gone! */ 3999 r2 = IWN_READ(sc, IWN_FH_INT); 4000 } 4001 4002 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=0x%08x reg2=0x%08x\n" 4003 , r1, r2); 4004 4005 if (r1 == 0 && r2 == 0) 4006 goto done; /* Interrupt not for us. */ 4007 4008 /* Acknowledge interrupts. */ 4009 IWN_WRITE(sc, IWN_INT, r1); 4010 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 4011 IWN_WRITE(sc, IWN_FH_INT, r2); 4012 4013 if (r1 & IWN_INT_RF_TOGGLED) { 4014 iwn_rftoggle_intr(sc); 4015 goto done; 4016 } 4017 if (r1 & IWN_INT_CT_REACHED) { 4018 device_printf(sc->sc_dev, "%s: critical temperature reached!\n", 4019 __func__); 4020 } 4021 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 4022 device_printf(sc->sc_dev, "%s: fatal firmware error\n", 4023 __func__); 4024 #ifdef IWN_DEBUG 4025 iwn_debug_register(sc); 4026 #endif 4027 /* Dump firmware error log and stop. */ 4028 iwn_fatal_intr(sc); 4029 4030 taskqueue_enqueue(sc->sc_tq, &sc->sc_panic_task); 4031 goto done; 4032 } 4033 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 4034 (r2 & IWN_FH_INT_RX)) { 4035 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 4036 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 4037 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 4038 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4039 IWN_INT_PERIODIC_DIS); 4040 iwn_notif_intr(sc); 4041 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 4042 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 4043 IWN_INT_PERIODIC_ENA); 4044 } 4045 } else 4046 iwn_notif_intr(sc); 4047 } 4048 4049 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 4050 if (sc->sc_flags & IWN_FLAG_USE_ICT) 4051 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 4052 wakeup(sc); /* FH DMA transfer completed. */ 4053 } 4054 4055 if (r1 & IWN_INT_ALIVE) 4056 wakeup(sc); /* Firmware is alive. */ 4057 4058 if (r1 & IWN_INT_WAKEUP) 4059 iwn_wakeup_intr(sc); 4060 4061 done: 4062 /* Re-enable interrupts. */ 4063 if (ifp->if_flags & IFF_UP) 4064 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 4065 } 4066 4067 /* 4068 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 4069 * 5000 adapters use a slightly different format). 4070 */ 4071 static void 4072 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4073 uint16_t len) 4074 { 4075 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 4076 4077 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4078 4079 *w = htole16(len + 8); 4080 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4081 BUS_DMASYNC_PREWRITE); 4082 if (idx < IWN_SCHED_WINSZ) { 4083 *(w + IWN_TX_RING_COUNT) = *w; 4084 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4085 BUS_DMASYNC_PREWRITE); 4086 } 4087 } 4088 4089 static void 4090 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 4091 uint16_t len) 4092 { 4093 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4094 4095 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4096 4097 *w = htole16(id << 12 | (len + 8)); 4098 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4099 BUS_DMASYNC_PREWRITE); 4100 if (idx < IWN_SCHED_WINSZ) { 4101 *(w + IWN_TX_RING_COUNT) = *w; 4102 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4103 BUS_DMASYNC_PREWRITE); 4104 } 4105 } 4106 4107 #ifdef notyet 4108 static void 4109 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 4110 { 4111 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 4112 4113 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4114 4115 *w = (*w & htole16(0xf000)) | htole16(1); 4116 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4117 BUS_DMASYNC_PREWRITE); 4118 if (idx < IWN_SCHED_WINSZ) { 4119 *(w + IWN_TX_RING_COUNT) = *w; 4120 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map, 4121 BUS_DMASYNC_PREWRITE); 4122 } 4123 } 4124 #endif 4125 4126 /* 4127 * Check whether OFDM 11g protection will be enabled for the given rate. 4128 * 4129 * The original driver code only enabled protection for OFDM rates. 4130 * It didn't check to see whether it was operating in 11a or 11bg mode. 4131 */ 4132 static int 4133 iwn_check_rate_needs_protection(struct iwn_softc *sc, 4134 struct ieee80211vap *vap, uint8_t rate) 4135 { 4136 struct ieee80211com *ic = vap->iv_ic; 4137 4138 /* 4139 * Not in 2GHz mode? Then there's no need to enable OFDM 4140 * 11bg protection. 4141 */ 4142 if (! IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { 4143 return (0); 4144 } 4145 4146 /* 4147 * 11bg protection not enabled? Then don't use it. 4148 */ 4149 if ((ic->ic_flags & IEEE80211_F_USEPROT) == 0) 4150 return (0); 4151 4152 /* 4153 * If it's an 11n rate, then for now we enable 4154 * protection. 4155 */ 4156 if (rate & IEEE80211_RATE_MCS) { 4157 return (1); 4158 } 4159 4160 /* 4161 * Do a rate table lookup. If the PHY is CCK, 4162 * don't do protection. 4163 */ 4164 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_CCK) 4165 return (0); 4166 4167 /* 4168 * Yup, enable protection. 4169 */ 4170 return (1); 4171 } 4172 4173 /* 4174 * return a value between 0 and IWN_MAX_TX_RETRIES-1 as an index into 4175 * the link quality table that reflects this particular entry. 4176 */ 4177 static int 4178 iwn_tx_rate_to_linkq_offset(struct iwn_softc *sc, struct ieee80211_node *ni, 4179 uint8_t rate) 4180 { 4181 struct ieee80211_rateset *rs; 4182 int is_11n; 4183 int nr; 4184 int i; 4185 uint8_t cmp_rate; 4186 4187 /* 4188 * Figure out if we're using 11n or not here. 4189 */ 4190 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) 4191 is_11n = 1; 4192 else 4193 is_11n = 0; 4194 4195 /* 4196 * Use the correct rate table. 4197 */ 4198 if (is_11n) { 4199 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 4200 nr = ni->ni_htrates.rs_nrates; 4201 } else { 4202 rs = &ni->ni_rates; 4203 nr = rs->rs_nrates; 4204 } 4205 4206 /* 4207 * Find the relevant link quality entry in the table. 4208 */ 4209 for (i = 0; i < nr && i < IWN_MAX_TX_RETRIES - 1 ; i++) { 4210 /* 4211 * The link quality table index starts at 0 == highest 4212 * rate, so we walk the rate table backwards. 4213 */ 4214 cmp_rate = rs->rs_rates[(nr - 1) - i]; 4215 if (rate & IEEE80211_RATE_MCS) 4216 cmp_rate |= IEEE80211_RATE_MCS; 4217 4218 #if 0 4219 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: idx %d: nr=%d, rate=0x%02x, rateentry=0x%02x\n", 4220 __func__, 4221 i, 4222 nr, 4223 rate, 4224 cmp_rate); 4225 #endif 4226 4227 if (cmp_rate == rate) 4228 return (i); 4229 } 4230 4231 /* Failed? Start at the end */ 4232 return (IWN_MAX_TX_RETRIES - 1); 4233 } 4234 4235 static int 4236 iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 4237 { 4238 struct iwn_ops *ops = &sc->ops; 4239 const struct ieee80211_txparam *tp; 4240 struct ieee80211vap *vap = ni->ni_vap; 4241 struct ieee80211com *ic = ni->ni_ic; 4242 struct iwn_node *wn = (void *)ni; 4243 struct iwn_tx_ring *ring; 4244 struct iwn_tx_desc *desc; 4245 struct iwn_tx_data *data; 4246 struct iwn_tx_cmd *cmd; 4247 struct iwn_cmd_data *tx; 4248 struct ieee80211_frame *wh; 4249 struct ieee80211_key *k = NULL; 4250 struct mbuf *m1; 4251 uint32_t flags; 4252 uint16_t qos; 4253 u_int hdrlen; 4254 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4255 uint8_t tid, type; 4256 int ac, i, totlen, error, pad, nsegs = 0, rate; 4257 4258 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4259 4260 wh = mtod(m, struct ieee80211_frame *); 4261 hdrlen = ieee80211_anyhdrsize(wh); 4262 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4263 4264 /* Select EDCA Access Category and TX ring for this frame. */ 4265 if (IEEE80211_QOS_HAS_SEQ(wh)) { 4266 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 4267 tid = qos & IEEE80211_QOS_TID; 4268 } else { 4269 qos = 0; 4270 tid = 0; 4271 } 4272 ac = M_WME_GETAC(m); 4273 if (m->m_flags & M_AMPDU_MPDU) { 4274 uint16_t seqno; 4275 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac]; 4276 4277 if (!IEEE80211_AMPDU_RUNNING(tap)) { 4278 m_freem(m); 4279 return EINVAL; 4280 } 4281 4282 /* 4283 * Queue this frame to the hardware ring that we've 4284 * negotiated AMPDU TX on. 4285 * 4286 * Note that the sequence number must match the TX slot 4287 * being used! 4288 */ 4289 ac = *(int *)tap->txa_private; 4290 seqno = ni->ni_txseqs[tid]; 4291 *(uint16_t *)wh->i_seq = 4292 htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 4293 ring = &sc->txq[ac]; 4294 if ((seqno % 256) != ring->cur) { 4295 device_printf(sc->sc_dev, 4296 "%s: m=%p: seqno (%d) (%d) != ring index (%d) !\n", 4297 __func__, 4298 m, 4299 seqno, 4300 seqno % 256, 4301 ring->cur); 4302 } 4303 ni->ni_txseqs[tid]++; 4304 } 4305 ring = &sc->txq[ac]; 4306 desc = &ring->desc[ring->cur]; 4307 data = &ring->data[ring->cur]; 4308 4309 /* Choose a TX rate index. */ 4310 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 4311 if (type == IEEE80211_FC0_TYPE_MGT) 4312 rate = tp->mgmtrate; 4313 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 4314 rate = tp->mcastrate; 4315 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 4316 rate = tp->ucastrate; 4317 else if (m->m_flags & M_EAPOL) 4318 rate = tp->mgmtrate; 4319 else { 4320 /* XXX pass pktlen */ 4321 (void) ieee80211_ratectl_rate(ni, NULL, 0); 4322 rate = ni->ni_txrate; 4323 } 4324 4325 /* Encrypt the frame if need be. */ 4326 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 4327 /* Retrieve key for TX. */ 4328 k = ieee80211_crypto_encap(ni, m); 4329 if (k == NULL) { 4330 m_freem(m); 4331 return ENOBUFS; 4332 } 4333 /* 802.11 header may have moved. */ 4334 wh = mtod(m, struct ieee80211_frame *); 4335 } 4336 totlen = m->m_pkthdr.len; 4337 4338 if (ieee80211_radiotap_active_vap(vap)) { 4339 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4340 4341 tap->wt_flags = 0; 4342 tap->wt_rate = rate; 4343 if (k != NULL) 4344 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 4345 4346 ieee80211_radiotap_tx(vap, m); 4347 } 4348 4349 /* Prepare TX firmware command. */ 4350 cmd = &ring->cmd[ring->cur]; 4351 cmd->code = IWN_CMD_TX_DATA; 4352 cmd->flags = 0; 4353 cmd->qid = ring->qid; 4354 cmd->idx = ring->cur; 4355 4356 tx = (struct iwn_cmd_data *)cmd->data; 4357 /* NB: No need to clear tx, all fields are reinitialized here. */ 4358 tx->scratch = 0; /* clear "scratch" area */ 4359 4360 flags = 0; 4361 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4362 /* Unicast frame, check if an ACK is expected. */ 4363 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 4364 IEEE80211_QOS_ACKPOLICY_NOACK) 4365 flags |= IWN_TX_NEED_ACK; 4366 } 4367 if ((wh->i_fc[0] & 4368 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 4369 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR)) 4370 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */ 4371 4372 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 4373 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 4374 4375 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 4376 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 4377 /* NB: Group frames are sent using CCK in 802.11b/g. */ 4378 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) { 4379 flags |= IWN_TX_NEED_RTS; 4380 } else if (iwn_check_rate_needs_protection(sc, vap, rate)) { 4381 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 4382 flags |= IWN_TX_NEED_CTS; 4383 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 4384 flags |= IWN_TX_NEED_RTS; 4385 } 4386 4387 /* XXX HT protection? */ 4388 4389 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 4390 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4391 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4392 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 4393 flags |= IWN_TX_NEED_PROTECTION; 4394 } else 4395 flags |= IWN_TX_FULL_TXOP; 4396 } 4397 } 4398 4399 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 4400 type != IEEE80211_FC0_TYPE_DATA) 4401 tx->id = sc->broadcast_id; 4402 else 4403 tx->id = wn->id; 4404 4405 if (type == IEEE80211_FC0_TYPE_MGT) { 4406 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4407 4408 /* Tell HW to set timestamp in probe responses. */ 4409 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4410 flags |= IWN_TX_INSERT_TSTAMP; 4411 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4412 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4413 tx->timeout = htole16(3); 4414 else 4415 tx->timeout = htole16(2); 4416 } else 4417 tx->timeout = htole16(0); 4418 4419 if (hdrlen & 3) { 4420 /* First segment length must be a multiple of 4. */ 4421 flags |= IWN_TX_NEED_PADDING; 4422 pad = 4 - (hdrlen & 3); 4423 } else 4424 pad = 0; 4425 4426 tx->len = htole16(totlen); 4427 tx->tid = tid; 4428 tx->rts_ntries = 60; 4429 tx->data_ntries = 15; 4430 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4431 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4432 if (tx->id == sc->broadcast_id) { 4433 /* Group or management frame. */ 4434 tx->linkq = 0; 4435 } else { 4436 tx->linkq = iwn_tx_rate_to_linkq_offset(sc, ni, rate); 4437 flags |= IWN_TX_LINKQ; /* enable MRR */ 4438 } 4439 4440 /* Set physical address of "scratch area". */ 4441 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4442 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4443 4444 /* Copy 802.11 header in TX command. */ 4445 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4446 4447 /* Trim 802.11 header. */ 4448 m_adj(m, hdrlen); 4449 tx->security = 0; 4450 tx->flags = htole32(flags); 4451 4452 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map, 4453 m, segs, IWN_MAX_SCATTER - 1, 4454 &nsegs, BUS_DMA_NOWAIT); 4455 if (error != 0) { 4456 if (error != EFBIG) { 4457 device_printf(sc->sc_dev, 4458 "%s: can't map mbuf (error %d)\n", __func__, error); 4459 m_freem(m); 4460 return error; 4461 } 4462 /* Too many DMA segments, linearize mbuf. */ 4463 m1 = m_defrag(m, MB_DONTWAIT); 4464 if (m1 == NULL) { 4465 device_printf(sc->sc_dev, 4466 "%s: could not defrag mbuf\n", __func__); 4467 m_freem(m); 4468 return ENOBUFS; 4469 } 4470 m = m1; 4471 4472 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 4473 data->map, m, segs, 4474 IWN_MAX_SCATTER - 1, 4475 &nsegs, BUS_DMA_NOWAIT); 4476 if (error != 0) { 4477 device_printf(sc->sc_dev, 4478 "%s: can't map mbuf (error %d)\n", __func__, error); 4479 m_freem(m); 4480 return error; 4481 } 4482 } 4483 4484 data->m = m; 4485 data->ni = ni; 4486 4487 DPRINTF(sc, IWN_DEBUG_XMIT, 4488 "%s: qid %d idx %d len %d nsegs %d rate %04x plcp 0x%08x\n", 4489 __func__, 4490 ring->qid, 4491 ring->cur, 4492 m->m_pkthdr.len, 4493 nsegs, 4494 rate, 4495 tx->rate); 4496 4497 /* Fill TX descriptor. */ 4498 desc->nsegs = 1; 4499 if (m->m_len != 0) 4500 desc->nsegs += nsegs; 4501 /* First DMA segment is used by the TX command. */ 4502 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4503 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4504 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4505 /* Other DMA segments are for data payload. */ 4506 seg = &segs[0]; 4507 for (i = 1; i <= nsegs; i++) { 4508 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4509 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4510 seg->ds_len << 4); 4511 seg++; 4512 } 4513 4514 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4515 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4516 BUS_DMASYNC_PREWRITE); 4517 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4518 BUS_DMASYNC_PREWRITE); 4519 4520 /* Update TX scheduler. */ 4521 if (ring->qid >= sc->firstaggqueue) 4522 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4523 4524 /* Kick TX ring. */ 4525 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4526 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4527 4528 /* Mark TX ring as full if we reach a certain threshold. */ 4529 if (++ring->queued > IWN_TX_RING_HIMARK) 4530 sc->qfullmsk |= 1 << ring->qid; 4531 4532 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4533 4534 return 0; 4535 } 4536 4537 static int 4538 iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m, 4539 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 4540 { 4541 struct iwn_ops *ops = &sc->ops; 4542 // struct ifnet *ifp = sc->sc_ifp; 4543 struct ieee80211vap *vap = ni->ni_vap; 4544 // struct ieee80211com *ic = ifp->if_l2com; 4545 struct iwn_tx_cmd *cmd; 4546 struct iwn_cmd_data *tx; 4547 struct ieee80211_frame *wh; 4548 struct iwn_tx_ring *ring; 4549 struct iwn_tx_desc *desc; 4550 struct iwn_tx_data *data; 4551 struct mbuf *m1; 4552 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER]; 4553 uint32_t flags; 4554 u_int hdrlen; 4555 int ac, totlen, error, pad, nsegs = 0, i, rate; 4556 uint8_t type; 4557 4558 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4559 4560 wh = mtod(m, struct ieee80211_frame *); 4561 hdrlen = ieee80211_anyhdrsize(wh); 4562 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 4563 4564 ac = params->ibp_pri & 3; 4565 4566 ring = &sc->txq[ac]; 4567 desc = &ring->desc[ring->cur]; 4568 data = &ring->data[ring->cur]; 4569 4570 /* Choose a TX rate. */ 4571 rate = params->ibp_rate0; 4572 totlen = m->m_pkthdr.len; 4573 4574 /* Prepare TX firmware command. */ 4575 cmd = &ring->cmd[ring->cur]; 4576 cmd->code = IWN_CMD_TX_DATA; 4577 cmd->flags = 0; 4578 cmd->qid = ring->qid; 4579 cmd->idx = ring->cur; 4580 4581 tx = (struct iwn_cmd_data *)cmd->data; 4582 /* NB: No need to clear tx, all fields are reinitialized here. */ 4583 tx->scratch = 0; /* clear "scratch" area */ 4584 4585 flags = 0; 4586 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 4587 flags |= IWN_TX_NEED_ACK; 4588 if (params->ibp_flags & IEEE80211_BPF_RTS) { 4589 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4590 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4591 flags &= ~IWN_TX_NEED_RTS; 4592 flags |= IWN_TX_NEED_PROTECTION; 4593 } else 4594 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP; 4595 } 4596 if (params->ibp_flags & IEEE80211_BPF_CTS) { 4597 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 4598 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 4599 flags &= ~IWN_TX_NEED_CTS; 4600 flags |= IWN_TX_NEED_PROTECTION; 4601 } else 4602 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP; 4603 } 4604 if (type == IEEE80211_FC0_TYPE_MGT) { 4605 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 4606 4607 /* Tell HW to set timestamp in probe responses. */ 4608 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 4609 flags |= IWN_TX_INSERT_TSTAMP; 4610 4611 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 4612 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 4613 tx->timeout = htole16(3); 4614 else 4615 tx->timeout = htole16(2); 4616 } else 4617 tx->timeout = htole16(0); 4618 4619 if (hdrlen & 3) { 4620 /* First segment length must be a multiple of 4. */ 4621 flags |= IWN_TX_NEED_PADDING; 4622 pad = 4 - (hdrlen & 3); 4623 } else 4624 pad = 0; 4625 4626 if (ieee80211_radiotap_active_vap(vap)) { 4627 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 4628 4629 tap->wt_flags = 0; 4630 tap->wt_rate = rate; 4631 4632 ieee80211_radiotap_tx(vap, m); 4633 } 4634 4635 tx->len = htole16(totlen); 4636 tx->tid = 0; 4637 tx->id = sc->broadcast_id; 4638 tx->rts_ntries = params->ibp_try1; 4639 tx->data_ntries = params->ibp_try0; 4640 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 4641 tx->rate = iwn_rate_to_plcp(sc, ni, rate); 4642 4643 /* Group or management frame. */ 4644 tx->linkq = 0; 4645 4646 /* Set physical address of "scratch area". */ 4647 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 4648 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 4649 4650 /* Copy 802.11 header in TX command. */ 4651 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 4652 4653 /* Trim 802.11 header. */ 4654 m_adj(m, hdrlen); 4655 tx->security = 0; 4656 tx->flags = htole32(flags); 4657 4658 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map, 4659 m, segs, 4660 IWN_MAX_SCATTER - 1, 4661 &nsegs, BUS_DMA_NOWAIT); 4662 if (error != 0) { 4663 if (error != EFBIG) { 4664 device_printf(sc->sc_dev, 4665 "%s: can't map mbuf (error %d)\n", __func__, error); 4666 m_freem(m); 4667 return error; 4668 } 4669 /* Too many DMA segments, linearize mbuf. */ 4670 m1 = m_defrag(m, M_NOWAIT); 4671 if (m1 == NULL) { 4672 device_printf(sc->sc_dev, 4673 "%s: could not defrag mbuf\n", __func__); 4674 m_freem(m); 4675 return ENOBUFS; 4676 } 4677 m = m1; 4678 4679 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, 4680 data->map, m, segs, 4681 IWN_MAX_SCATTER - 1, 4682 &nsegs, BUS_DMA_NOWAIT); 4683 if (error != 0) { 4684 device_printf(sc->sc_dev, 4685 "%s: can't map mbuf (error %d)\n", __func__, error); 4686 m_freem(m); 4687 return error; 4688 } 4689 } 4690 4691 data->m = m; 4692 data->ni = ni; 4693 4694 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n", 4695 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs); 4696 4697 /* Fill TX descriptor. */ 4698 desc->nsegs = 1; 4699 if (m->m_len != 0) 4700 desc->nsegs += nsegs; 4701 /* First DMA segment is used by the TX command. */ 4702 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 4703 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 4704 (4 + sizeof (*tx) + hdrlen + pad) << 4); 4705 /* Other DMA segments are for data payload. */ 4706 seg = &segs[0]; 4707 for (i = 1; i <= nsegs; i++) { 4708 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 4709 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 4710 seg->ds_len << 4); 4711 seg++; 4712 } 4713 4714 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 4715 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4716 BUS_DMASYNC_PREWRITE); 4717 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4718 BUS_DMASYNC_PREWRITE); 4719 4720 /* Update TX scheduler. */ 4721 if (ring->qid >= sc->firstaggqueue) 4722 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 4723 4724 /* Kick TX ring. */ 4725 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4726 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4727 4728 /* Mark TX ring as full if we reach a certain threshold. */ 4729 if (++ring->queued > IWN_TX_RING_HIMARK) 4730 sc->qfullmsk |= 1 << ring->qid; 4731 4732 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4733 4734 return 0; 4735 } 4736 4737 static int 4738 iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 4739 const struct ieee80211_bpf_params *params) 4740 { 4741 struct ieee80211com *ic = ni->ni_ic; 4742 struct ifnet *ifp = ic->ic_ifp; 4743 struct iwn_softc *sc = ifp->if_softc; 4744 int error = 0; 4745 4746 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4747 4748 if ((ifp->if_flags & IFF_RUNNING) == 0) { 4749 ieee80211_free_node(ni); 4750 m_freem(m); 4751 return ENETDOWN; 4752 } 4753 4754 if (params == NULL) { 4755 /* 4756 * Legacy path; interpret frame contents to decide 4757 * precisely how to send the frame. 4758 */ 4759 error = iwn_tx_data(sc, m, ni); 4760 } else { 4761 /* 4762 * Caller supplied explicit parameters to use in 4763 * sending the frame. 4764 */ 4765 error = iwn_tx_data_raw(sc, m, ni, params); 4766 } 4767 if (error != 0) { 4768 /* NB: m is reclaimed on tx failure */ 4769 ieee80211_free_node(ni); 4770 IFNET_STAT_INC(ifp, oerrors, 1); 4771 } 4772 sc->sc_tx_timer = 5; 4773 4774 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4775 4776 return error; 4777 } 4778 4779 static void 4780 iwn_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 4781 { 4782 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 4783 iwn_start_locked(ifp); 4784 } 4785 4786 static void 4787 iwn_start_locked(struct ifnet *ifp) 4788 { 4789 struct iwn_softc *sc = ifp->if_softc; 4790 struct ieee80211_node *ni; 4791 struct mbuf *m; 4792 4793 wlan_assert_serialized(); 4794 4795 if ((ifp->if_flags & IFF_RUNNING) == 0 || 4796 ifq_is_oactive(&ifp->if_snd)) 4797 return; 4798 4799 for (;;) { 4800 if (sc->qfullmsk != 0) { 4801 ifq_set_oactive(&ifp->if_snd); 4802 break; 4803 } 4804 m = ifq_dequeue(&ifp->if_snd); 4805 if (m == NULL) 4806 break; 4807 KKASSERT(M_TRAILINGSPACE(m) >= 0); 4808 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 4809 if (iwn_tx_data(sc, m, ni) != 0) { 4810 ieee80211_free_node(ni); 4811 IFNET_STAT_INC(ifp, oerrors, 1); 4812 continue; 4813 } 4814 sc->sc_tx_timer = 5; 4815 } 4816 } 4817 4818 static void 4819 iwn_watchdog_timeout(void *arg) 4820 { 4821 struct iwn_softc *sc = arg; 4822 struct ifnet *ifp = sc->sc_ifp; 4823 struct ieee80211com *ic = ifp->if_l2com; 4824 4825 wlan_serialize_enter(); 4826 4827 KASSERT(ifp->if_flags & IFF_RUNNING, ("not running")); 4828 4829 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4830 4831 if (sc->sc_tx_timer > 0) { 4832 if (--sc->sc_tx_timer == 0) { 4833 if_printf(ifp, "device timeout\n"); 4834 ieee80211_runtask(ic, &sc->sc_reinit_task); 4835 wlan_serialize_exit(); 4836 return; 4837 } 4838 } 4839 callout_reset(&sc->watchdog_to, hz, iwn_watchdog_timeout, sc); 4840 wlan_serialize_exit(); 4841 } 4842 4843 static int 4844 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred) 4845 { 4846 struct iwn_softc *sc = ifp->if_softc; 4847 struct ieee80211com *ic = ifp->if_l2com; 4848 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4849 struct ifreq *ifr = (struct ifreq *) data; 4850 int error = 0, startall = 0, stop = 0; 4851 4852 wlan_assert_serialized(); 4853 4854 switch (cmd) { 4855 case SIOCGIFADDR: 4856 error = ether_ioctl(ifp, cmd, data); 4857 break; 4858 case SIOCSIFFLAGS: 4859 if (ifp->if_flags & IFF_UP) { 4860 if (!(ifp->if_flags & IFF_RUNNING)) { 4861 iwn_init_locked(sc); 4862 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL) 4863 startall = 1; 4864 else 4865 stop = 1; 4866 } 4867 } else { 4868 if (ifp->if_flags & IFF_RUNNING) 4869 iwn_stop_locked(sc); 4870 } 4871 if (startall) 4872 ieee80211_start_all(ic); 4873 else if (vap != NULL && stop) 4874 ieee80211_stop(vap); 4875 break; 4876 case SIOCGIFMEDIA: 4877 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 4878 break; 4879 case SIOCGIWNSTATS: 4880 IWN_LOCK(sc); 4881 /* XXX validate permissions/memory/etc? */ 4882 error = copyout(&sc->last_stat, ifr->ifr_data, 4883 sizeof(struct iwn_stats)); 4884 IWN_UNLOCK(sc); 4885 break; 4886 case SIOCZIWNSTATS: 4887 IWN_LOCK(sc); 4888 memset(&sc->last_stat, 0, sizeof(struct iwn_stats)); 4889 IWN_UNLOCK(sc); 4890 error = 0; 4891 break; 4892 default: 4893 error = EINVAL; 4894 break; 4895 } 4896 return error; 4897 } 4898 4899 /* 4900 * Send a command to the firmware. 4901 */ 4902 static int 4903 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 4904 { 4905 struct iwn_tx_ring *ring; 4906 struct iwn_tx_desc *desc; 4907 struct iwn_tx_data *data; 4908 struct iwn_tx_cmd *cmd; 4909 struct mbuf *m; 4910 bus_addr_t paddr; 4911 int totlen, error; 4912 int cmd_queue_num; 4913 4914 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 4915 4916 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 4917 cmd_queue_num = IWN_PAN_CMD_QUEUE; 4918 else 4919 cmd_queue_num = IWN_CMD_QUEUE_NUM; 4920 4921 ring = &sc->txq[cmd_queue_num]; 4922 desc = &ring->desc[ring->cur]; 4923 data = &ring->data[ring->cur]; 4924 totlen = 4 + size; 4925 4926 if (size > sizeof cmd->data) { 4927 /* Command is too large to fit in a descriptor. */ 4928 if (totlen > MJUMPAGESIZE) 4929 return EINVAL; 4930 m = m_getjcl(MB_DONTWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE); 4931 if (m == NULL) 4932 return ENOMEM; 4933 cmd = mtod(m, struct iwn_tx_cmd *); 4934 error = bus_dmamap_load(ring->data_dmat, data->map, cmd, 4935 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT); 4936 if (error != 0) { 4937 m_freem(m); 4938 return error; 4939 } 4940 data->m = m; 4941 } else { 4942 cmd = &ring->cmd[ring->cur]; 4943 paddr = data->cmd_paddr; 4944 } 4945 4946 cmd->code = code; 4947 cmd->flags = 0; 4948 cmd->qid = ring->qid; 4949 cmd->idx = ring->cur; 4950 memcpy(cmd->data, buf, size); 4951 4952 desc->nsegs = 1; 4953 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 4954 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 4955 4956 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n", 4957 __func__, iwn_intr_str(cmd->code), cmd->code, 4958 cmd->flags, cmd->qid, cmd->idx); 4959 4960 if (size > sizeof cmd->data) { 4961 bus_dmamap_sync(ring->data_dmat, data->map, 4962 BUS_DMASYNC_PREWRITE); 4963 } else { 4964 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map, 4965 BUS_DMASYNC_PREWRITE); 4966 } 4967 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map, 4968 BUS_DMASYNC_PREWRITE); 4969 4970 /* Kick command ring. */ 4971 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 4972 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 4973 4974 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 4975 4976 return async ? 0 : zsleep(desc, &wlan_global_serializer, 0, "iwncmd", hz); 4977 } 4978 4979 static int 4980 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 4981 { 4982 struct iwn4965_node_info hnode; 4983 caddr_t src, dst; 4984 4985 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 4986 4987 /* 4988 * We use the node structure for 5000 Series internally (it is 4989 * a superset of the one for 4965AGN). We thus copy the common 4990 * fields before sending the command. 4991 */ 4992 src = (caddr_t)node; 4993 dst = (caddr_t)&hnode; 4994 memcpy(dst, src, 48); 4995 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 4996 memcpy(dst + 48, src + 72, 20); 4997 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 4998 } 4999 5000 static int 5001 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 5002 { 5003 5004 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5005 5006 /* Direct mapping. */ 5007 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 5008 } 5009 5010 static int 5011 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 5012 { 5013 #define RV(v) ((v) & IEEE80211_RATE_VAL) 5014 struct iwn_node *wn = (void *)ni; 5015 struct ieee80211_rateset *rs; 5016 struct iwn_cmd_link_quality linkq; 5017 uint8_t txant; 5018 int i, rate, txrate; 5019 int is_11n; 5020 5021 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5022 5023 /* Use the first valid TX antenna. */ 5024 txant = IWN_LSB(sc->txchainmask); 5025 5026 memset(&linkq, 0, sizeof linkq); 5027 linkq.id = wn->id; 5028 linkq.antmsk_1stream = txant; 5029 5030 /* 5031 * The '2 stream' setup is a bit .. odd. 5032 * 5033 * For NICs that support only 1 antenna, default to IWN_ANT_AB or 5034 * the firmware panics (eg Intel 5100.) 5035 * 5036 * For NICs that support two antennas, we use ANT_AB. 5037 * 5038 * For NICs that support three antennas, we use the two that 5039 * wasn't the default one. 5040 * 5041 * XXX TODO: if bluetooth (full concurrent) is enabled, restrict 5042 * this to only one antenna. 5043 */ 5044 5045 /* So - if there's no secondary antenna, assume IWN_ANT_AB */ 5046 5047 /* Default - transmit on the other antennas */ 5048 linkq.antmsk_2stream = (sc->txchainmask & ~IWN_LSB(sc->txchainmask)); 5049 5050 /* Now, if it's zero, set it to IWN_ANT_AB, so to not panic firmware */ 5051 if (linkq.antmsk_2stream == 0) 5052 linkq.antmsk_2stream = IWN_ANT_AB; 5053 5054 /* 5055 * If the NIC is a two-stream TX NIC, configure the TX mask to 5056 * the default chainmask 5057 */ 5058 else if (sc->ntxchains == 2) 5059 linkq.antmsk_2stream = sc->txchainmask; 5060 5061 linkq.ampdu_max = 32; /* XXX negotiated? */ 5062 linkq.ampdu_threshold = 3; 5063 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5064 5065 DPRINTF(sc, IWN_DEBUG_XMIT, 5066 "%s: 1stream antenna=0x%02x, 2stream antenna=0x%02x, ntxstreams=%d\n", 5067 __func__, 5068 linkq.antmsk_1stream, 5069 linkq.antmsk_2stream, 5070 sc->ntxchains); 5071 5072 /* 5073 * Are we using 11n rates? Ensure the channel is 5074 * 11n _and_ we have some 11n rates, or don't 5075 * try. 5076 */ 5077 if (IEEE80211_IS_CHAN_HT(ni->ni_chan) && ni->ni_htrates.rs_nrates > 0) { 5078 rs = (struct ieee80211_rateset *) &ni->ni_htrates; 5079 is_11n = 1; 5080 } else { 5081 rs = &ni->ni_rates; 5082 is_11n = 0; 5083 } 5084 5085 /* Start at highest available bit-rate. */ 5086 /* 5087 * XXX this is all very dirty! 5088 */ 5089 if (is_11n) 5090 txrate = ni->ni_htrates.rs_nrates - 1; 5091 else 5092 txrate = rs->rs_nrates - 1; 5093 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) { 5094 uint32_t plcp; 5095 5096 if (is_11n) 5097 rate = IEEE80211_RATE_MCS | rs->rs_rates[txrate]; 5098 else 5099 rate = RV(rs->rs_rates[txrate]); 5100 5101 DPRINTF(sc, IWN_DEBUG_XMIT, 5102 "%s: i=%d, txrate=%d, rate=0x%02x\n", 5103 __func__, 5104 i, 5105 txrate, 5106 rate); 5107 5108 /* Do rate -> PLCP config mapping */ 5109 plcp = iwn_rate_to_plcp(sc, ni, rate); 5110 linkq.retry[i] = plcp; 5111 5112 /* 5113 * The mimo field is an index into the table which 5114 * indicates the first index where it and subsequent entries 5115 * will not be using MIMO. 5116 * 5117 * Since we're filling linkq from 0..15 and we're filling 5118 * from the higest MCS rates to the lowest rates, if we 5119 * _are_ doing a dual-stream rate, set mimo to idx+1 (ie, 5120 * the next entry.) That way if the next entry is a non-MIMO 5121 * entry, we're already pointing at it. 5122 */ 5123 if ((le32toh(plcp) & IWN_RFLAG_MCS) && 5124 RV(le32toh(plcp)) > 7) 5125 linkq.mimo = i + 1; 5126 5127 /* Next retry at immediate lower bit-rate. */ 5128 if (txrate > 0) 5129 txrate--; 5130 } 5131 5132 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5133 5134 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 5135 #undef RV 5136 } 5137 5138 /* 5139 * Broadcast node is used to send group-addressed and management frames. 5140 */ 5141 static int 5142 iwn_add_broadcast_node(struct iwn_softc *sc, int async) 5143 { 5144 struct iwn_ops *ops = &sc->ops; 5145 struct ifnet *ifp = sc->sc_ifp; 5146 struct ieee80211com *ic = ifp->if_l2com; 5147 struct iwn_node_info node; 5148 struct iwn_cmd_link_quality linkq; 5149 uint8_t txant; 5150 int i, error; 5151 5152 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5153 5154 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5155 5156 memset(&node, 0, sizeof node); 5157 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr); 5158 node.id = sc->broadcast_id; 5159 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__); 5160 if ((error = ops->add_node(sc, &node, async)) != 0) 5161 return error; 5162 5163 /* Use the first valid TX antenna. */ 5164 txant = IWN_LSB(sc->txchainmask); 5165 5166 memset(&linkq, 0, sizeof linkq); 5167 linkq.id = sc->broadcast_id; 5168 linkq.antmsk_1stream = txant; 5169 linkq.antmsk_2stream = IWN_ANT_AB; 5170 linkq.ampdu_max = 64; 5171 linkq.ampdu_threshold = 3; 5172 linkq.ampdu_limit = htole16(4000); /* 4ms */ 5173 5174 /* Use lowest mandatory bit-rate. */ 5175 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 5176 linkq.retry[0] = htole32(0xd); 5177 else 5178 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK); 5179 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant)); 5180 /* Use same bit-rate for all TX retries. */ 5181 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 5182 linkq.retry[i] = linkq.retry[0]; 5183 } 5184 5185 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5186 5187 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 5188 } 5189 5190 static int 5191 iwn_updateedca(struct ieee80211com *ic) 5192 { 5193 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 5194 struct iwn_softc *sc = ic->ic_ifp->if_softc; 5195 struct iwn_edca_params cmd; 5196 int aci; 5197 5198 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5199 5200 memset(&cmd, 0, sizeof cmd); 5201 cmd.flags = htole32(IWN_EDCA_UPDATE); 5202 for (aci = 0; aci < WME_NUM_AC; aci++) { 5203 const struct wmeParams *ac = 5204 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 5205 cmd.ac[aci].aifsn = ac->wmep_aifsn; 5206 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin)); 5207 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax)); 5208 cmd.ac[aci].txoplimit = 5209 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit)); 5210 } 5211 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 5212 5213 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5214 5215 return 0; 5216 #undef IWN_EXP2 5217 } 5218 5219 static void 5220 iwn_update_mcast(struct ifnet *ifp) 5221 { 5222 /* Ignore */ 5223 } 5224 5225 static void 5226 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 5227 { 5228 struct iwn_cmd_led led; 5229 5230 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5231 5232 #if 0 5233 /* XXX don't set LEDs during scan? */ 5234 if (sc->sc_is_scanning) 5235 return; 5236 #endif 5237 5238 /* Clear microcode LED ownership. */ 5239 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 5240 5241 led.which = which; 5242 led.unit = htole32(10000); /* on/off in unit of 100ms */ 5243 led.off = off; 5244 led.on = on; 5245 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 5246 } 5247 5248 /* 5249 * Set the critical temperature at which the firmware will stop the radio 5250 * and notify us. 5251 */ 5252 static int 5253 iwn_set_critical_temp(struct iwn_softc *sc) 5254 { 5255 struct iwn_critical_temp crit; 5256 int32_t temp; 5257 5258 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5259 5260 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 5261 5262 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 5263 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 5264 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 5265 temp = IWN_CTOK(110); 5266 else 5267 temp = 110; 5268 memset(&crit, 0, sizeof crit); 5269 crit.tempR = htole32(temp); 5270 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp); 5271 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 5272 } 5273 5274 static int 5275 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 5276 { 5277 struct iwn_cmd_timing cmd; 5278 uint64_t val, mod; 5279 5280 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5281 5282 memset(&cmd, 0, sizeof cmd); 5283 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t)); 5284 cmd.bintval = htole16(ni->ni_intval); 5285 cmd.lintval = htole16(10); 5286 5287 /* Compute remaining time until next beacon. */ 5288 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 5289 mod = le64toh(cmd.tstamp) % val; 5290 cmd.binitval = htole32((uint32_t)(val - mod)); 5291 5292 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n", 5293 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod)); 5294 5295 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 5296 } 5297 5298 static void 5299 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 5300 { 5301 struct ifnet *ifp = sc->sc_ifp; 5302 struct ieee80211com *ic = ifp->if_l2com; 5303 5304 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5305 5306 /* Adjust TX power if need be (delta >= 3 degC). */ 5307 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", 5308 __func__, sc->temp, temp); 5309 if (abs(temp - sc->temp) >= 3) { 5310 /* Record temperature of last calibration. */ 5311 sc->temp = temp; 5312 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1); 5313 } 5314 } 5315 5316 /* 5317 * Set TX power for current channel (each rate has its own power settings). 5318 * This function takes into account the regulatory information from EEPROM, 5319 * the current temperature and the current voltage. 5320 */ 5321 static int 5322 iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 5323 int async) 5324 { 5325 /* Fixed-point arithmetic division using a n-bit fractional part. */ 5326 #define fdivround(a, b, n) \ 5327 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 5328 /* Linear interpolation. */ 5329 #define interpolate(x, x1, y1, x2, y2, n) \ 5330 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 5331 5332 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 5333 struct iwn_ucode_info *uc = &sc->ucode_info; 5334 struct iwn4965_cmd_txpower cmd; 5335 struct iwn4965_eeprom_chan_samples *chans; 5336 const uint8_t *rf_gain, *dsp_gain; 5337 int32_t vdiff, tdiff; 5338 int i, c, grp, maxpwr; 5339 uint8_t chan; 5340 5341 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 5342 /* Retrieve current channel from last RXON. */ 5343 chan = sc->rxon->chan; 5344 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n", 5345 chan); 5346 5347 memset(&cmd, 0, sizeof cmd); 5348 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 5349 cmd.chan = chan; 5350 5351 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 5352 maxpwr = sc->maxpwr5GHz; 5353 rf_gain = iwn4965_rf_gain_5ghz; 5354 dsp_gain = iwn4965_dsp_gain_5ghz; 5355 } else { 5356 maxpwr = sc->maxpwr2GHz; 5357 rf_gain = iwn4965_rf_gain_2ghz; 5358 dsp_gain = iwn4965_dsp_gain_2ghz; 5359 } 5360 5361 /* Compute voltage compensation. */ 5362 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7; 5363 if (vdiff > 0) 5364 vdiff *= 2; 5365 if (abs(vdiff) > 2) 5366 vdiff = 0; 5367 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5368 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 5369 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage); 5370 5371 /* Get channel attenuation group. */ 5372 if (chan <= 20) /* 1-20 */ 5373 grp = 4; 5374 else if (chan <= 43) /* 34-43 */ 5375 grp = 0; 5376 else if (chan <= 70) /* 44-70 */ 5377 grp = 1; 5378 else if (chan <= 124) /* 71-124 */ 5379 grp = 2; 5380 else /* 125-200 */ 5381 grp = 3; 5382 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5383 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp); 5384 5385 /* Get channel sub-band. */ 5386 for (i = 0; i < IWN_NBANDS; i++) 5387 if (sc->bands[i].lo != 0 && 5388 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 5389 break; 5390 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 5391 return EINVAL; 5392 chans = sc->bands[i].chans; 5393 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5394 "%s: chan %d sub-band=%d\n", __func__, chan, i); 5395 5396 for (c = 0; c < 2; c++) { 5397 uint8_t power, gain, temp; 5398 int maxchpwr, pwr, ridx, idx; 5399 5400 power = interpolate(chan, 5401 chans[0].num, chans[0].samples[c][1].power, 5402 chans[1].num, chans[1].samples[c][1].power, 1); 5403 gain = interpolate(chan, 5404 chans[0].num, chans[0].samples[c][1].gain, 5405 chans[1].num, chans[1].samples[c][1].gain, 1); 5406 temp = interpolate(chan, 5407 chans[0].num, chans[0].samples[c][1].temp, 5408 chans[1].num, chans[1].samples[c][1].temp, 1); 5409 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5410 "%s: Tx chain %d: power=%d gain=%d temp=%d\n", 5411 __func__, c, power, gain, temp); 5412 5413 /* Compute temperature compensation. */ 5414 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 5415 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5416 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n", 5417 __func__, tdiff, sc->temp, temp); 5418 5419 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 5420 /* Convert dBm to half-dBm. */ 5421 maxchpwr = sc->maxpwr[chan] * 2; 5422 if ((ridx / 8) & 1) 5423 maxchpwr -= 6; /* MIMO 2T: -3dB */ 5424 5425 pwr = maxpwr; 5426 5427 /* Adjust TX power based on rate. */ 5428 if ((ridx % 8) == 5) 5429 pwr -= 15; /* OFDM48: -7.5dB */ 5430 else if ((ridx % 8) == 6) 5431 pwr -= 17; /* OFDM54: -8.5dB */ 5432 else if ((ridx % 8) == 7) 5433 pwr -= 20; /* OFDM60: -10dB */ 5434 else 5435 pwr -= 10; /* Others: -5dB */ 5436 5437 /* Do not exceed channel max TX power. */ 5438 if (pwr > maxchpwr) 5439 pwr = maxchpwr; 5440 5441 idx = gain - (pwr - power) - tdiff - vdiff; 5442 if ((ridx / 8) & 1) /* MIMO */ 5443 idx += (int32_t)le32toh(uc->atten[grp][c]); 5444 5445 if (cmd.band == 0) 5446 idx += 9; /* 5GHz */ 5447 if (ridx == IWN_RIDX_MAX) 5448 idx += 5; /* CCK */ 5449 5450 /* Make sure idx stays in a valid range. */ 5451 if (idx < 0) 5452 idx = 0; 5453 else if (idx > IWN4965_MAX_PWR_INDEX) 5454 idx = IWN4965_MAX_PWR_INDEX; 5455 5456 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5457 "%s: Tx chain %d, rate idx %d: power=%d\n", 5458 __func__, c, ridx, idx); 5459 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 5460 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 5461 } 5462 } 5463 5464 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW, 5465 "%s: set tx power for chan %d\n", __func__, chan); 5466 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 5467 5468 #undef interpolate 5469 #undef fdivround 5470 } 5471 5472 static int 5473 iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch, 5474 int async) 5475 { 5476 struct iwn5000_cmd_txpower cmd; 5477 5478 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5479 5480 /* 5481 * TX power calibration is handled automatically by the firmware 5482 * for 5000 Series. 5483 */ 5484 memset(&cmd, 0, sizeof cmd); 5485 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 5486 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 5487 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 5488 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__); 5489 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 5490 } 5491 5492 /* 5493 * Retrieve the maximum RSSI (in dBm) among receivers. 5494 */ 5495 static int 5496 iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5497 { 5498 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 5499 uint8_t mask, agc; 5500 int rssi; 5501 5502 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5503 5504 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC; 5505 agc = (le16toh(phy->agc) >> 7) & 0x7f; 5506 5507 rssi = 0; 5508 if (mask & IWN_ANT_A) 5509 rssi = MAX(rssi, phy->rssi[0]); 5510 if (mask & IWN_ANT_B) 5511 rssi = MAX(rssi, phy->rssi[2]); 5512 if (mask & IWN_ANT_C) 5513 rssi = MAX(rssi, phy->rssi[4]); 5514 5515 DPRINTF(sc, IWN_DEBUG_RECV, 5516 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc, 5517 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4], 5518 rssi - agc - IWN_RSSI_TO_DBM); 5519 return rssi - agc - IWN_RSSI_TO_DBM; 5520 } 5521 5522 static int 5523 iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat) 5524 { 5525 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 5526 uint8_t agc; 5527 int rssi; 5528 5529 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5530 5531 agc = (le32toh(phy->agc) >> 9) & 0x7f; 5532 5533 rssi = MAX(le16toh(phy->rssi[0]) & 0xff, 5534 le16toh(phy->rssi[1]) & 0xff); 5535 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi); 5536 5537 DPRINTF(sc, IWN_DEBUG_RECV, 5538 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc, 5539 phy->rssi[0], phy->rssi[1], phy->rssi[2], 5540 rssi - agc - IWN_RSSI_TO_DBM); 5541 return rssi - agc - IWN_RSSI_TO_DBM; 5542 } 5543 5544 /* 5545 * Retrieve the average noise (in dBm) among receivers. 5546 */ 5547 static int 5548 iwn_get_noise(const struct iwn_rx_general_stats *stats) 5549 { 5550 int i, total, nbant, noise; 5551 5552 total = nbant = 0; 5553 for (i = 0; i < 3; i++) { 5554 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0) 5555 continue; 5556 total += noise; 5557 nbant++; 5558 } 5559 /* There should be at least one antenna but check anyway. */ 5560 return (nbant == 0) ? -127 : (total / nbant) - 107; 5561 } 5562 5563 /* 5564 * Compute temperature (in degC) from last received statistics. 5565 */ 5566 static int 5567 iwn4965_get_temperature(struct iwn_softc *sc) 5568 { 5569 struct iwn_ucode_info *uc = &sc->ucode_info; 5570 int32_t r1, r2, r3, r4, temp; 5571 5572 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5573 5574 r1 = le32toh(uc->temp[0].chan20MHz); 5575 r2 = le32toh(uc->temp[1].chan20MHz); 5576 r3 = le32toh(uc->temp[2].chan20MHz); 5577 r4 = le32toh(sc->rawtemp); 5578 5579 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 5580 return 0; 5581 5582 /* Sign-extend 23-bit R4 value to 32-bit. */ 5583 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 5584 /* Compute temperature in Kelvin. */ 5585 temp = (259 * (r4 - r2)) / (r3 - r1); 5586 temp = (temp * 97) / 100 + 8; 5587 5588 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp, 5589 IWN_KTOC(temp)); 5590 return IWN_KTOC(temp); 5591 } 5592 5593 static int 5594 iwn5000_get_temperature(struct iwn_softc *sc) 5595 { 5596 int32_t temp; 5597 5598 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5599 5600 /* 5601 * Temperature is not used by the driver for 5000 Series because 5602 * TX power calibration is handled by firmware. 5603 */ 5604 temp = le32toh(sc->rawtemp); 5605 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 5606 temp = (temp / -5) + sc->temp_off; 5607 temp = IWN_KTOC(temp); 5608 } 5609 return temp; 5610 } 5611 5612 /* 5613 * Initialize sensitivity calibration state machine. 5614 */ 5615 static int 5616 iwn_init_sensitivity(struct iwn_softc *sc) 5617 { 5618 struct iwn_ops *ops = &sc->ops; 5619 struct iwn_calib_state *calib = &sc->calib; 5620 uint32_t flags; 5621 int error; 5622 5623 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5624 5625 /* Reset calibration state machine. */ 5626 memset(calib, 0, sizeof (*calib)); 5627 calib->state = IWN_CALIB_STATE_INIT; 5628 calib->cck_state = IWN_CCK_STATE_HIFA; 5629 /* Set initial correlation values. */ 5630 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 5631 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 5632 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 5633 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 5634 calib->cck_x4 = 125; 5635 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 5636 calib->energy_cck = sc->limits->energy_cck; 5637 5638 /* Write initial sensitivity. */ 5639 if ((error = iwn_send_sensitivity(sc)) != 0) 5640 return error; 5641 5642 /* Write initial gains. */ 5643 if ((error = ops->init_gains(sc)) != 0) 5644 return error; 5645 5646 /* Request statistics at each beacon interval. */ 5647 flags = 0; 5648 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n", 5649 __func__); 5650 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 5651 } 5652 5653 /* 5654 * Collect noise and RSSI statistics for the first 20 beacons received 5655 * after association and use them to determine connected antennas and 5656 * to set differential gains. 5657 */ 5658 static void 5659 iwn_collect_noise(struct iwn_softc *sc, 5660 const struct iwn_rx_general_stats *stats) 5661 { 5662 struct iwn_ops *ops = &sc->ops; 5663 struct iwn_calib_state *calib = &sc->calib; 5664 struct ifnet *ifp = sc->sc_ifp; 5665 struct ieee80211com *ic = ifp->if_l2com; 5666 uint32_t val; 5667 int i; 5668 5669 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5670 5671 /* Accumulate RSSI and noise for all 3 antennas. */ 5672 for (i = 0; i < 3; i++) { 5673 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff; 5674 calib->noise[i] += le32toh(stats->noise[i]) & 0xff; 5675 } 5676 /* NB: We update differential gains only once after 20 beacons. */ 5677 if (++calib->nbeacons < 20) 5678 return; 5679 5680 /* Determine highest average RSSI. */ 5681 val = MAX(calib->rssi[0], calib->rssi[1]); 5682 val = MAX(calib->rssi[2], val); 5683 5684 /* Determine which antennas are connected. */ 5685 sc->chainmask = sc->rxchainmask; 5686 for (i = 0; i < 3; i++) 5687 if (val - calib->rssi[i] > 15 * 20) 5688 sc->chainmask &= ~(1 << i); 5689 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5690 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n", 5691 __func__, sc->rxchainmask, sc->chainmask); 5692 5693 /* If none of the TX antennas are connected, keep at least one. */ 5694 if ((sc->chainmask & sc->txchainmask) == 0) 5695 sc->chainmask |= IWN_LSB(sc->txchainmask); 5696 5697 (void)ops->set_gains(sc); 5698 calib->state = IWN_CALIB_STATE_RUN; 5699 5700 #ifdef notyet 5701 /* XXX Disable RX chains with no antennas connected. */ 5702 sc->rxon->rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 5703 if (sc->sc_is_scanning) 5704 device_printf(sc->sc_dev, 5705 "%s: is_scanning set, before RXON\n", 5706 __func__); 5707 (void)iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 5708 #endif 5709 5710 /* Enable power-saving mode if requested by user. */ 5711 if (ic->ic_flags & IEEE80211_F_PMGTON) 5712 (void)iwn_set_pslevel(sc, 0, 3, 1); 5713 5714 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5715 5716 } 5717 5718 static int 5719 iwn4965_init_gains(struct iwn_softc *sc) 5720 { 5721 struct iwn_phy_calib_gain cmd; 5722 5723 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5724 5725 memset(&cmd, 0, sizeof cmd); 5726 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 5727 /* Differential gains initially set to 0 for all 3 antennas. */ 5728 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5729 "%s: setting initial differential gains\n", __func__); 5730 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5731 } 5732 5733 static int 5734 iwn5000_init_gains(struct iwn_softc *sc) 5735 { 5736 struct iwn_phy_calib cmd; 5737 5738 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5739 5740 memset(&cmd, 0, sizeof cmd); 5741 cmd.code = sc->reset_noise_gain; 5742 cmd.ngroups = 1; 5743 cmd.isvalid = 1; 5744 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5745 "%s: setting initial differential gains\n", __func__); 5746 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5747 } 5748 5749 static int 5750 iwn4965_set_gains(struct iwn_softc *sc) 5751 { 5752 struct iwn_calib_state *calib = &sc->calib; 5753 struct iwn_phy_calib_gain cmd; 5754 int i, delta, noise; 5755 5756 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5757 5758 /* Get minimal noise among connected antennas. */ 5759 noise = INT_MAX; /* NB: There's at least one antenna. */ 5760 for (i = 0; i < 3; i++) 5761 if (sc->chainmask & (1 << i)) 5762 noise = MIN(calib->noise[i], noise); 5763 5764 memset(&cmd, 0, sizeof cmd); 5765 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 5766 /* Set differential gains for connected antennas. */ 5767 for (i = 0; i < 3; i++) { 5768 if (sc->chainmask & (1 << i)) { 5769 /* Compute attenuation (in unit of 1.5dB). */ 5770 delta = (noise - (int32_t)calib->noise[i]) / 30; 5771 /* NB: delta <= 0 */ 5772 /* Limit to [-4.5dB,0]. */ 5773 cmd.gain[i] = MIN(abs(delta), 3); 5774 if (delta < 0) 5775 cmd.gain[i] |= 1 << 2; /* sign bit */ 5776 } 5777 } 5778 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5779 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 5780 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask); 5781 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5782 } 5783 5784 static int 5785 iwn5000_set_gains(struct iwn_softc *sc) 5786 { 5787 struct iwn_calib_state *calib = &sc->calib; 5788 struct iwn_phy_calib_gain cmd; 5789 int i, ant, div, delta; 5790 5791 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 5792 5793 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 5794 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 5795 5796 memset(&cmd, 0, sizeof cmd); 5797 cmd.code = sc->noise_gain; 5798 cmd.ngroups = 1; 5799 cmd.isvalid = 1; 5800 /* Get first available RX antenna as referential. */ 5801 ant = IWN_LSB(sc->rxchainmask); 5802 /* Set differential gains for other antennas. */ 5803 for (i = ant + 1; i < 3; i++) { 5804 if (sc->chainmask & (1 << i)) { 5805 /* The delta is relative to antenna "ant". */ 5806 delta = ((int32_t)calib->noise[ant] - 5807 (int32_t)calib->noise[i]) / div; 5808 /* Limit to [-4.5dB,+4.5dB]. */ 5809 cmd.gain[i - 1] = MIN(abs(delta), 3); 5810 if (delta < 0) 5811 cmd.gain[i - 1] |= 1 << 2; /* sign bit */ 5812 } 5813 } 5814 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5815 "setting differential gains Ant B/C: %x/%x (%x)\n", 5816 cmd.gain[0], cmd.gain[1], sc->chainmask); 5817 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 5818 } 5819 5820 /* 5821 * Tune RF RX sensitivity based on the number of false alarms detected 5822 * during the last beacon period. 5823 */ 5824 static void 5825 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 5826 { 5827 #define inc(val, inc, max) \ 5828 if ((val) < (max)) { \ 5829 if ((val) < (max) - (inc)) \ 5830 (val) += (inc); \ 5831 else \ 5832 (val) = (max); \ 5833 needs_update = 1; \ 5834 } 5835 #define dec(val, dec, min) \ 5836 if ((val) > (min)) { \ 5837 if ((val) > (min) + (dec)) \ 5838 (val) -= (dec); \ 5839 else \ 5840 (val) = (min); \ 5841 needs_update = 1; \ 5842 } 5843 5844 const struct iwn_sensitivity_limits *limits = sc->limits; 5845 struct iwn_calib_state *calib = &sc->calib; 5846 uint32_t val, rxena, fa; 5847 uint32_t energy[3], energy_min; 5848 uint8_t noise[3], noise_ref; 5849 int i, needs_update = 0; 5850 5851 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 5852 5853 /* Check that we've been enabled long enough. */ 5854 if ((rxena = le32toh(stats->general.load)) == 0){ 5855 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end not so long\n", __func__); 5856 return; 5857 } 5858 5859 /* Compute number of false alarms since last call for OFDM. */ 5860 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 5861 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm; 5862 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 5863 5864 if (fa > 50 * rxena) { 5865 /* High false alarm count, decrease sensitivity. */ 5866 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5867 "%s: OFDM high false alarm count: %u\n", __func__, fa); 5868 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 5869 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 5870 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 5871 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 5872 5873 } else if (fa < 5 * rxena) { 5874 /* Low false alarm count, increase sensitivity. */ 5875 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5876 "%s: OFDM low false alarm count: %u\n", __func__, fa); 5877 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 5878 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 5879 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 5880 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 5881 } 5882 5883 /* Compute maximum noise among 3 receivers. */ 5884 for (i = 0; i < 3; i++) 5885 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff; 5886 val = MAX(noise[0], noise[1]); 5887 val = MAX(noise[2], val); 5888 /* Insert it into our samples table. */ 5889 calib->noise_samples[calib->cur_noise_sample] = val; 5890 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 5891 5892 /* Compute maximum noise among last 20 samples. */ 5893 noise_ref = calib->noise_samples[0]; 5894 for (i = 1; i < 20; i++) 5895 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 5896 5897 /* Compute maximum energy among 3 receivers. */ 5898 for (i = 0; i < 3; i++) 5899 energy[i] = le32toh(stats->general.energy[i]); 5900 val = MIN(energy[0], energy[1]); 5901 val = MIN(energy[2], val); 5902 /* Insert it into our samples table. */ 5903 calib->energy_samples[calib->cur_energy_sample] = val; 5904 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 5905 5906 /* Compute minimum energy among last 10 samples. */ 5907 energy_min = calib->energy_samples[0]; 5908 for (i = 1; i < 10; i++) 5909 energy_min = MAX(energy_min, calib->energy_samples[i]); 5910 energy_min += 6; 5911 5912 /* Compute number of false alarms since last call for CCK. */ 5913 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck; 5914 fa += le32toh(stats->cck.fa) - calib->fa_cck; 5915 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 5916 5917 if (fa > 50 * rxena) { 5918 /* High false alarm count, decrease sensitivity. */ 5919 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5920 "%s: CCK high false alarm count: %u\n", __func__, fa); 5921 calib->cck_state = IWN_CCK_STATE_HIFA; 5922 calib->low_fa = 0; 5923 5924 if (calib->cck_x4 > 160) { 5925 calib->noise_ref = noise_ref; 5926 if (calib->energy_cck > 2) 5927 dec(calib->energy_cck, 2, energy_min); 5928 } 5929 if (calib->cck_x4 < 160) { 5930 calib->cck_x4 = 161; 5931 needs_update = 1; 5932 } else 5933 inc(calib->cck_x4, 3, limits->max_cck_x4); 5934 5935 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 5936 5937 } else if (fa < 5 * rxena) { 5938 /* Low false alarm count, increase sensitivity. */ 5939 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5940 "%s: CCK low false alarm count: %u\n", __func__, fa); 5941 calib->cck_state = IWN_CCK_STATE_LOFA; 5942 calib->low_fa++; 5943 5944 if (calib->cck_state != IWN_CCK_STATE_INIT && 5945 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 5946 calib->low_fa > 100)) { 5947 inc(calib->energy_cck, 2, limits->min_energy_cck); 5948 dec(calib->cck_x4, 3, limits->min_cck_x4); 5949 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 5950 } 5951 } else { 5952 /* Not worth to increase or decrease sensitivity. */ 5953 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 5954 "%s: CCK normal false alarm count: %u\n", __func__, fa); 5955 calib->low_fa = 0; 5956 calib->noise_ref = noise_ref; 5957 5958 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 5959 /* Previous interval had many false alarms. */ 5960 dec(calib->energy_cck, 8, energy_min); 5961 } 5962 calib->cck_state = IWN_CCK_STATE_INIT; 5963 } 5964 5965 if (needs_update) 5966 (void)iwn_send_sensitivity(sc); 5967 5968 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 5969 5970 #undef dec 5971 #undef inc 5972 } 5973 5974 static int 5975 iwn_send_sensitivity(struct iwn_softc *sc) 5976 { 5977 struct iwn_calib_state *calib = &sc->calib; 5978 struct iwn_enhanced_sensitivity_cmd cmd; 5979 int len; 5980 5981 memset(&cmd, 0, sizeof cmd); 5982 len = sizeof (struct iwn_sensitivity_cmd); 5983 cmd.which = IWN_SENSITIVITY_WORKTBL; 5984 /* OFDM modulation. */ 5985 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 5986 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 5987 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 5988 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 5989 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 5990 cmd.energy_ofdm_th = htole16(62); 5991 /* CCK modulation. */ 5992 cmd.corr_cck_x4 = htole16(calib->cck_x4); 5993 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 5994 cmd.energy_cck = htole16(calib->energy_cck); 5995 /* Barker modulation: use default values. */ 5996 cmd.corr_barker = htole16(190); 5997 cmd.corr_barker_mrc = htole16(sc->limits->barker_mrc); 5998 5999 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6000 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, 6001 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4, 6002 calib->ofdm_mrc_x4, calib->cck_x4, 6003 calib->cck_mrc_x4, calib->energy_cck); 6004 6005 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 6006 goto send; 6007 /* Enhanced sensitivity settings. */ 6008 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 6009 cmd.ofdm_det_slope_mrc = htole16(668); 6010 cmd.ofdm_det_icept_mrc = htole16(4); 6011 cmd.ofdm_det_slope = htole16(486); 6012 cmd.ofdm_det_icept = htole16(37); 6013 cmd.cck_det_slope_mrc = htole16(853); 6014 cmd.cck_det_icept_mrc = htole16(4); 6015 cmd.cck_det_slope = htole16(476); 6016 cmd.cck_det_icept = htole16(99); 6017 send: 6018 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 6019 } 6020 6021 /* 6022 * Look at the increase of PLCP errors over time; if it exceeds 6023 * a programmed threshold then trigger an RF retune. 6024 */ 6025 static void 6026 iwn_check_rx_recovery(struct iwn_softc *sc, struct iwn_stats *rs) 6027 { 6028 int32_t delta_ofdm, delta_ht, delta_cck; 6029 struct iwn_calib_state *calib = &sc->calib; 6030 int delta_ticks, cur_ticks; 6031 int delta_msec; 6032 int thresh; 6033 6034 /* 6035 * Calculate the difference between the current and 6036 * previous statistics. 6037 */ 6038 delta_cck = le32toh(rs->rx.cck.bad_plcp) - calib->bad_plcp_cck; 6039 delta_ofdm = le32toh(rs->rx.ofdm.bad_plcp) - calib->bad_plcp_ofdm; 6040 delta_ht = le32toh(rs->rx.ht.bad_plcp) - calib->bad_plcp_ht; 6041 6042 /* 6043 * Calculate the delta in time between successive statistics 6044 * messages. Yes, it can roll over; so we make sure that 6045 * this doesn't happen. 6046 * 6047 * XXX go figure out what to do about rollover 6048 * XXX go figure out what to do if ticks rolls over to -ve instead! 6049 * XXX go stab signed integer overflow undefined-ness in the face. 6050 */ 6051 cur_ticks = ticks; 6052 delta_ticks = cur_ticks - sc->last_calib_ticks; 6053 6054 /* 6055 * If any are negative, then the firmware likely reset; so just 6056 * bail. We'll pick this up next time. 6057 */ 6058 if (delta_cck < 0 || delta_ofdm < 0 || delta_ht < 0 || delta_ticks < 0) 6059 return; 6060 6061 /* 6062 * delta_ticks is in ticks; we need to convert it up to milliseconds 6063 * so we can do some useful math with it. 6064 */ 6065 delta_msec = ticks_to_msecs(delta_ticks); 6066 6067 /* 6068 * Calculate what our threshold is given the current delta_msec. 6069 */ 6070 thresh = sc->base_params->plcp_err_threshold * delta_msec; 6071 6072 DPRINTF(sc, IWN_DEBUG_STATE, 6073 "%s: time delta: %d; cck=%d, ofdm=%d, ht=%d, total=%d, thresh=%d\n", 6074 __func__, 6075 delta_msec, 6076 delta_cck, 6077 delta_ofdm, 6078 delta_ht, 6079 (delta_msec + delta_cck + delta_ofdm + delta_ht), 6080 thresh); 6081 6082 /* 6083 * If we need a retune, then schedule a single channel scan 6084 * to a channel that isn't the currently active one! 6085 * 6086 * The math from linux iwlwifi: 6087 * 6088 * if ((delta * 100 / msecs) > threshold) 6089 */ 6090 if (thresh > 0 && (delta_cck + delta_ofdm + delta_ht) * 100 > thresh) { 6091 DPRINTF(sc, IWN_DEBUG_ANY, 6092 "%s: PLCP error threshold raw (%d) comparison (%d) " 6093 "over limit (%d); retune!\n", 6094 __func__, 6095 (delta_cck + delta_ofdm + delta_ht), 6096 (delta_cck + delta_ofdm + delta_ht) * 100, 6097 thresh); 6098 } 6099 } 6100 6101 /* 6102 * Set STA mode power saving level (between 0 and 5). 6103 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 6104 */ 6105 static int 6106 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 6107 { 6108 struct iwn_pmgt_cmd cmd; 6109 const struct iwn_pmgt *pmgt; 6110 uint32_t max, skip_dtim; 6111 uint32_t reg; 6112 int i; 6113 6114 DPRINTF(sc, IWN_DEBUG_PWRSAVE, 6115 "%s: dtim=%d, level=%d, async=%d\n", 6116 __func__, 6117 dtim, 6118 level, 6119 async); 6120 6121 /* Select which PS parameters to use. */ 6122 if (dtim <= 2) 6123 pmgt = &iwn_pmgt[0][level]; 6124 else if (dtim <= 10) 6125 pmgt = &iwn_pmgt[1][level]; 6126 else 6127 pmgt = &iwn_pmgt[2][level]; 6128 6129 memset(&cmd, 0, sizeof cmd); 6130 if (level != 0) /* not CAM */ 6131 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 6132 if (level == 5) 6133 cmd.flags |= htole16(IWN_PS_FAST_PD); 6134 /* Retrieve PCIe Active State Power Management (ASPM). */ 6135 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 6136 if (!(reg & 0x1)) /* L0s Entry disabled. */ 6137 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 6138 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 6139 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 6140 6141 if (dtim == 0) { 6142 dtim = 1; 6143 skip_dtim = 0; 6144 } else 6145 skip_dtim = pmgt->skip_dtim; 6146 if (skip_dtim != 0) { 6147 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 6148 max = pmgt->intval[4]; 6149 if (max == (uint32_t)-1) 6150 max = dtim * (skip_dtim + 1); 6151 else if (max > dtim) 6152 max = (max / dtim) * dtim; 6153 } else 6154 max = dtim; 6155 for (i = 0; i < 5; i++) 6156 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 6157 6158 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n", 6159 level); 6160 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 6161 } 6162 6163 static int 6164 iwn_send_btcoex(struct iwn_softc *sc) 6165 { 6166 struct iwn_bluetooth cmd; 6167 6168 memset(&cmd, 0, sizeof cmd); 6169 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 6170 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 6171 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 6172 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n", 6173 __func__); 6174 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 6175 } 6176 6177 static int 6178 iwn_send_advanced_btcoex(struct iwn_softc *sc) 6179 { 6180 static const uint32_t btcoex_3wire[12] = { 6181 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 6182 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 6183 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 6184 }; 6185 struct iwn6000_btcoex_config btconfig; 6186 struct iwn2000_btcoex_config btconfig2k; 6187 struct iwn_btcoex_priotable btprio; 6188 struct iwn_btcoex_prot btprot; 6189 int error, i; 6190 uint8_t flags; 6191 6192 memset(&btconfig, 0, sizeof btconfig); 6193 memset(&btconfig2k, 0, sizeof btconfig2k); 6194 6195 flags = IWN_BT_FLAG_COEX6000_MODE_3W << 6196 IWN_BT_FLAG_COEX6000_MODE_SHIFT; // Done as is in linux kernel 3.2 6197 6198 if (sc->base_params->bt_sco_disable) 6199 flags &= ~IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6200 else 6201 flags |= IWN_BT_FLAG_SYNC_2_BT_DISABLE; 6202 6203 flags |= IWN_BT_FLAG_COEX6000_CHAN_INHIBITION; 6204 6205 /* Default flags result is 145 as old value */ 6206 6207 /* 6208 * Flags value has to be review. Values must change if we 6209 * which to disable it 6210 */ 6211 if (sc->base_params->bt_session_2) { 6212 btconfig2k.flags = flags; 6213 btconfig2k.max_kill = 5; 6214 btconfig2k.bt3_t7_timer = 1; 6215 btconfig2k.kill_ack = htole32(0xffff0000); 6216 btconfig2k.kill_cts = htole32(0xffff0000); 6217 btconfig2k.sample_time = 2; 6218 btconfig2k.bt3_t2_timer = 0xc; 6219 6220 for (i = 0; i < 12; i++) 6221 btconfig2k.lookup_table[i] = htole32(btcoex_3wire[i]); 6222 btconfig2k.valid = htole16(0xff); 6223 btconfig2k.prio_boost = htole32(0xf0); 6224 DPRINTF(sc, IWN_DEBUG_RESET, 6225 "%s: configuring advanced bluetooth coexistence" 6226 " session 2, flags : 0x%x\n", 6227 __func__, 6228 flags); 6229 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig2k, 6230 sizeof(btconfig2k), 1); 6231 } else { 6232 btconfig.flags = flags; 6233 btconfig.max_kill = 5; 6234 btconfig.bt3_t7_timer = 1; 6235 btconfig.kill_ack = htole32(0xffff0000); 6236 btconfig.kill_cts = htole32(0xffff0000); 6237 btconfig.sample_time = 2; 6238 btconfig.bt3_t2_timer = 0xc; 6239 6240 for (i = 0; i < 12; i++) 6241 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 6242 btconfig.valid = htole16(0xff); 6243 btconfig.prio_boost = 0xf0; 6244 DPRINTF(sc, IWN_DEBUG_RESET, 6245 "%s: configuring advanced bluetooth coexistence," 6246 " flags : 0x%x\n", 6247 __func__, 6248 flags); 6249 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 6250 sizeof(btconfig), 1); 6251 } 6252 6253 if (error != 0) 6254 return error; 6255 6256 memset(&btprio, 0, sizeof btprio); 6257 btprio.calib_init1 = 0x6; 6258 btprio.calib_init2 = 0x7; 6259 btprio.calib_periodic_low1 = 0x2; 6260 btprio.calib_periodic_low2 = 0x3; 6261 btprio.calib_periodic_high1 = 0x4; 6262 btprio.calib_periodic_high2 = 0x5; 6263 btprio.dtim = 0x6; 6264 btprio.scan52 = 0x8; 6265 btprio.scan24 = 0xa; 6266 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 6267 1); 6268 if (error != 0) 6269 return error; 6270 6271 /* Force BT state machine change. */ 6272 memset(&btprot, 0, sizeof btprot); 6273 btprot.open = 1; 6274 btprot.type = 1; 6275 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6276 if (error != 0) 6277 return error; 6278 btprot.open = 0; 6279 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 6280 } 6281 6282 static int 6283 iwn5000_runtime_calib(struct iwn_softc *sc) 6284 { 6285 struct iwn5000_calib_config cmd; 6286 6287 memset(&cmd, 0, sizeof cmd); 6288 cmd.ucode.once.enable = 0xffffffff; 6289 cmd.ucode.once.start = IWN5000_CALIB_DC; 6290 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 6291 "%s: configuring runtime calibration\n", __func__); 6292 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 6293 } 6294 6295 static int 6296 iwn_config(struct iwn_softc *sc) 6297 { 6298 struct iwn_ops *ops = &sc->ops; 6299 struct ifnet *ifp = sc->sc_ifp; 6300 struct ieee80211com *ic = ifp->if_l2com; 6301 uint32_t txmask; 6302 uint16_t rxchain; 6303 int error; 6304 6305 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6306 6307 if ((sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) 6308 && (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)) { 6309 device_printf(sc->sc_dev,"%s: temp_offset and temp_offsetv2 are" 6310 " exclusive each together. Review NIC config file. Conf" 6311 " : 0x%08x Flags : 0x%08x \n", __func__, 6312 sc->base_params->calib_need, 6313 (IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET | 6314 IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2)); 6315 return (EINVAL); 6316 } 6317 6318 /* Compute temperature calib if needed. Will be send by send calib */ 6319 if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSET) { 6320 error = iwn5000_temp_offset_calib(sc); 6321 if (error != 0) { 6322 device_printf(sc->sc_dev, 6323 "%s: could not set temperature offset\n", __func__); 6324 return (error); 6325 } 6326 } else if (sc->base_params->calib_need & IWN_FLG_NEED_PHY_CALIB_TEMP_OFFSETv2) { 6327 error = iwn5000_temp_offset_calibv2(sc); 6328 if (error != 0) { 6329 device_printf(sc->sc_dev, 6330 "%s: could not compute temperature offset v2\n", 6331 __func__); 6332 return (error); 6333 } 6334 } 6335 6336 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6337 /* Configure runtime DC calibration. */ 6338 error = iwn5000_runtime_calib(sc); 6339 if (error != 0) { 6340 device_printf(sc->sc_dev, 6341 "%s: could not configure runtime calibration\n", 6342 __func__); 6343 return error; 6344 } 6345 } 6346 6347 /* Configure valid TX chains for >=5000 Series. */ 6348 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 6349 txmask = htole32(sc->txchainmask); 6350 DPRINTF(sc, IWN_DEBUG_RESET, 6351 "%s: configuring valid TX chains 0x%x\n", __func__, txmask); 6352 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 6353 sizeof txmask, 0); 6354 if (error != 0) { 6355 device_printf(sc->sc_dev, 6356 "%s: could not configure valid TX chains, " 6357 "error %d\n", __func__, error); 6358 return error; 6359 } 6360 } 6361 6362 /* Configure bluetooth coexistence. */ 6363 error = 0; 6364 6365 /* Configure bluetooth coexistence if needed. */ 6366 if (sc->base_params->bt_mode == IWN_BT_ADVANCED) 6367 error = iwn_send_advanced_btcoex(sc); 6368 if (sc->base_params->bt_mode == IWN_BT_SIMPLE) 6369 error = iwn_send_btcoex(sc); 6370 6371 if (error != 0) { 6372 device_printf(sc->sc_dev, 6373 "%s: could not configure bluetooth coexistence, error %d\n", 6374 __func__, error); 6375 return error; 6376 } 6377 6378 /* Set mode, channel, RX filter and enable RX. */ 6379 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6380 memset(sc->rxon, 0, sizeof (struct iwn_rxon)); 6381 IEEE80211_ADDR_COPY(sc->rxon->myaddr, IF_LLADDR(ifp)); 6382 IEEE80211_ADDR_COPY(sc->rxon->wlap, IF_LLADDR(ifp)); 6383 sc->rxon->chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 6384 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6385 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) 6386 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6387 switch (ic->ic_opmode) { 6388 case IEEE80211_M_STA: 6389 sc->rxon->mode = IWN_MODE_STA; 6390 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST); 6391 break; 6392 case IEEE80211_M_MONITOR: 6393 sc->rxon->mode = IWN_MODE_MONITOR; 6394 sc->rxon->filter = htole32(IWN_FILTER_MULTICAST | 6395 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 6396 break; 6397 default: 6398 /* Should not get there. */ 6399 break; 6400 } 6401 sc->rxon->cck_mask = 0x0f; /* not yet negotiated */ 6402 sc->rxon->ofdm_mask = 0xff; /* not yet negotiated */ 6403 sc->rxon->ht_single_mask = 0xff; 6404 sc->rxon->ht_dual_mask = 0xff; 6405 sc->rxon->ht_triple_mask = 0xff; 6406 rxchain = 6407 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6408 IWN_RXCHAIN_MIMO_COUNT(2) | 6409 IWN_RXCHAIN_IDLE_COUNT(2); 6410 sc->rxon->rxchain = htole16(rxchain); 6411 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__); 6412 if (sc->sc_is_scanning) 6413 device_printf(sc->sc_dev, 6414 "%s: is_scanning set, before RXON\n", 6415 __func__); 6416 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 0); 6417 if (error != 0) { 6418 device_printf(sc->sc_dev, "%s: RXON command failed\n", 6419 __func__); 6420 return error; 6421 } 6422 6423 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) { 6424 device_printf(sc->sc_dev, "%s: could not add broadcast node\n", 6425 __func__); 6426 return error; 6427 } 6428 6429 /* Configuration has changed, set TX power accordingly. */ 6430 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) { 6431 device_printf(sc->sc_dev, "%s: could not set TX power\n", 6432 __func__); 6433 return error; 6434 } 6435 6436 if ((error = iwn_set_critical_temp(sc)) != 0) { 6437 device_printf(sc->sc_dev, 6438 "%s: could not set critical temperature\n", __func__); 6439 return error; 6440 } 6441 6442 /* Set power saving level to CAM during initialization. */ 6443 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 6444 device_printf(sc->sc_dev, 6445 "%s: could not set power saving level\n", __func__); 6446 return error; 6447 } 6448 6449 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6450 6451 return 0; 6452 } 6453 6454 /* 6455 * Add an ssid element to a frame. 6456 */ 6457 static uint8_t * 6458 ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len) 6459 { 6460 *frm++ = IEEE80211_ELEMID_SSID; 6461 *frm++ = len; 6462 memcpy(frm, ssid, len); 6463 return frm + len; 6464 } 6465 6466 static uint16_t 6467 iwn_get_active_dwell_time(struct iwn_softc *sc, 6468 struct ieee80211_channel *c, uint8_t n_probes) 6469 { 6470 /* No channel? Default to 2GHz settings */ 6471 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6472 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 6473 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 6474 } 6475 6476 /* 5GHz dwell time */ 6477 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 6478 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 6479 } 6480 6481 /* 6482 * Limit the total dwell time to 85% of the beacon interval. 6483 * 6484 * Returns the dwell time in milliseconds. 6485 */ 6486 static uint16_t 6487 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 6488 { 6489 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 6490 struct ieee80211vap *vap = NULL; 6491 int bintval = 0; 6492 6493 /* bintval is in TU (1.024mS) */ 6494 if (! TAILQ_EMPTY(&ic->ic_vaps)) { 6495 vap = TAILQ_FIRST(&ic->ic_vaps); 6496 bintval = vap->iv_bss->ni_intval; 6497 } 6498 6499 /* 6500 * If it's non-zero, we should calculate the minimum of 6501 * it and the DWELL_BASE. 6502 * 6503 * XXX Yes, the math should take into account that bintval 6504 * is 1.024mS, not 1mS.. 6505 */ 6506 if (bintval > 0) { 6507 DPRINTF(sc, IWN_DEBUG_SCAN, 6508 "%s: bintval=%d\n", 6509 __func__, 6510 bintval); 6511 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 6512 } 6513 6514 /* No association context? Default */ 6515 return (IWN_PASSIVE_DWELL_BASE); 6516 } 6517 6518 static uint16_t 6519 iwn_get_passive_dwell_time(struct iwn_softc *sc, struct ieee80211_channel *c) 6520 { 6521 uint16_t passive; 6522 6523 if (c == NULL || IEEE80211_IS_CHAN_2GHZ(c)) { 6524 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 6525 } else { 6526 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 6527 } 6528 6529 /* Clamp to the beacon interval if we're associated */ 6530 return (iwn_limit_dwell(sc, passive)); 6531 } 6532 6533 static int 6534 iwn_scan(struct iwn_softc *sc, struct ieee80211vap *vap, 6535 struct ieee80211_scan_state *ss, struct ieee80211_channel *c) 6536 { 6537 struct ifnet *ifp = sc->sc_ifp; 6538 struct ieee80211com *ic = ifp->if_l2com; 6539 struct ieee80211_node *ni = vap->iv_bss; 6540 struct iwn_scan_hdr *hdr; 6541 struct iwn_cmd_data *tx; 6542 struct iwn_scan_essid *essid; 6543 struct iwn_scan_chan *chan; 6544 struct ieee80211_frame *wh; 6545 struct ieee80211_rateset *rs; 6546 uint8_t *buf, *frm; 6547 uint16_t rxchain; 6548 uint8_t txant; 6549 int buflen, error; 6550 int is_active; 6551 uint16_t dwell_active, dwell_passive; 6552 uint32_t extra, scan_service_time; 6553 6554 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6555 6556 /* 6557 * We are absolutely not allowed to send a scan command when another 6558 * scan command is pending. 6559 */ 6560 if (sc->sc_is_scanning) { 6561 device_printf(sc->sc_dev, "%s: called whilst scanning!\n", 6562 __func__); 6563 return (EAGAIN); 6564 } 6565 6566 /* Assign the scan channel */ 6567 c = ic->ic_curchan; 6568 6569 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6570 buf = kmalloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_INTWAIT | M_ZERO); 6571 hdr = (struct iwn_scan_hdr *)buf; 6572 /* 6573 * Move to the next channel if no frames are received within 10ms 6574 * after sending the probe request. 6575 */ 6576 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 6577 hdr->quiet_threshold = htole16(1); /* min # of packets */ 6578 /* 6579 * Max needs to be greater than active and passive and quiet! 6580 * It's also in microseconds! 6581 */ 6582 hdr->max_svc = htole32(250 * 1024); 6583 6584 /* 6585 * Reset scan: interval=100 6586 * Normal scan: interval=becaon interval 6587 * suspend_time: 100 (TU) 6588 * 6589 */ 6590 extra = (100 /* suspend_time */ / 100 /* beacon interval */) << 22; 6591 //scan_service_time = extra | ((100 /* susp */ % 100 /* int */) * 1024); 6592 scan_service_time = (4 << 22) | (100 * 1024); /* Hardcode for now! */ 6593 hdr->pause_svc = htole32(scan_service_time); 6594 6595 /* Select antennas for scanning. */ 6596 rxchain = 6597 IWN_RXCHAIN_VALID(sc->rxchainmask) | 6598 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 6599 IWN_RXCHAIN_DRIVER_FORCE; 6600 if (IEEE80211_IS_CHAN_A(c) && 6601 sc->hw_type == IWN_HW_REV_TYPE_4965) { 6602 /* Ant A must be avoided in 5GHz because of an HW bug. */ 6603 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 6604 } else /* Use all available RX antennas. */ 6605 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 6606 hdr->rxchain = htole16(rxchain); 6607 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 6608 6609 tx = (struct iwn_cmd_data *)(hdr + 1); 6610 tx->flags = htole32(IWN_TX_AUTO_SEQ); 6611 tx->id = sc->broadcast_id; 6612 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 6613 6614 if (IEEE80211_IS_CHAN_5GHZ(c)) { 6615 /* Send probe requests at 6Mbps. */ 6616 tx->rate = htole32(0xd); 6617 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 6618 } else { 6619 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 6620 if (sc->hw_type == IWN_HW_REV_TYPE_4965 && 6621 sc->rxon->associd && sc->rxon->chan > 14) 6622 tx->rate = htole32(0xd); 6623 else { 6624 /* Send probe requests at 1Mbps. */ 6625 tx->rate = htole32(10 | IWN_RFLAG_CCK); 6626 } 6627 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 6628 } 6629 /* Use the first valid TX antenna. */ 6630 txant = IWN_LSB(sc->txchainmask); 6631 tx->rate |= htole32(IWN_RFLAG_ANT(txant)); 6632 6633 /* 6634 * Only do active scanning if we're announcing a probe request 6635 * for a given SSID (or more, if we ever add it to the driver.) 6636 */ 6637 is_active = 0; 6638 6639 /* 6640 * If we're scanning for a specific SSID, add it to the command. 6641 * 6642 * XXX maybe look at adding support for scanning multiple SSIDs? 6643 */ 6644 essid = (struct iwn_scan_essid *)(tx + 1); 6645 if (ss != NULL) { 6646 if (ss->ss_ssid[0].len != 0) { 6647 essid[0].id = IEEE80211_ELEMID_SSID; 6648 essid[0].len = ss->ss_ssid[0].len; 6649 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len); 6650 } 6651 6652 DPRINTF(sc, IWN_DEBUG_SCAN, "%s: ssid_len=%d, ssid=%*s\n", 6653 __func__, 6654 ss->ss_ssid[0].len, 6655 ss->ss_ssid[0].len, 6656 ss->ss_ssid[0].ssid); 6657 6658 if (ss->ss_nssid > 0) 6659 is_active = 1; 6660 } 6661 6662 /* 6663 * Build a probe request frame. Most of the following code is a 6664 * copy & paste of what is done in net80211. 6665 */ 6666 wh = (struct ieee80211_frame *)(essid + 20); 6667 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 6668 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 6669 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 6670 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr); 6671 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp)); 6672 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr); 6673 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 6674 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 6675 6676 frm = (uint8_t *)(wh + 1); 6677 frm = ieee80211_add_ssid(frm, NULL, 0); 6678 frm = ieee80211_add_rates(frm, rs); 6679 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 6680 frm = ieee80211_add_xrates(frm, rs); 6681 if (ic->ic_htcaps & IEEE80211_HTC_HT) 6682 frm = ieee80211_add_htcap(frm, ni); 6683 6684 /* Set length of probe request. */ 6685 tx->len = htole16(frm - (uint8_t *)wh); 6686 6687 /* 6688 * If active scanning is requested but a certain channel is 6689 * marked passive, we can do active scanning if we detect 6690 * transmissions. 6691 * 6692 * There is an issue with some firmware versions that triggers 6693 * a sysassert on a "good CRC threshold" of zero (== disabled), 6694 * on a radar channel even though this means that we should NOT 6695 * send probes. 6696 * 6697 * The "good CRC threshold" is the number of frames that we 6698 * need to receive during our dwell time on a channel before 6699 * sending out probes -- setting this to a huge value will 6700 * mean we never reach it, but at the same time work around 6701 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER 6702 * here instead of IWL_GOOD_CRC_TH_DISABLED. 6703 * 6704 * This was fixed in later versions along with some other 6705 * scan changes, and the threshold behaves as a flag in those 6706 * versions. 6707 */ 6708 6709 /* 6710 * If we're doing active scanning, set the crc_threshold 6711 * to a suitable value. This is different to active veruss 6712 * passive scanning depending upon the channel flags; the 6713 * firmware will obey that particular check for us. 6714 */ 6715 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 6716 hdr->crc_threshold = is_active ? 6717 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 6718 else 6719 hdr->crc_threshold = is_active ? 6720 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 6721 6722 chan = (struct iwn_scan_chan *)frm; 6723 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 6724 chan->flags = 0; 6725 if (ss->ss_nssid > 0) 6726 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 6727 chan->dsp_gain = 0x6e; 6728 6729 /* 6730 * Set the passive/active flag depending upon the channel mode. 6731 * XXX TODO: take the is_active flag into account as well? 6732 */ 6733 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 6734 chan->flags |= htole32(IWN_CHAN_PASSIVE); 6735 else 6736 chan->flags |= htole32(IWN_CHAN_ACTIVE); 6737 6738 /* 6739 * Calculate the active/passive dwell times. 6740 */ 6741 6742 dwell_active = iwn_get_active_dwell_time(sc, c, ss->ss_nssid); 6743 dwell_passive = iwn_get_passive_dwell_time(sc, c); 6744 6745 /* Make sure they're valid */ 6746 if (dwell_passive <= dwell_active) 6747 dwell_passive = dwell_active + 1; 6748 6749 chan->active = htole16(dwell_active); 6750 chan->passive = htole16(dwell_passive); 6751 6752 if (IEEE80211_IS_CHAN_5GHZ(c) && 6753 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 6754 chan->rf_gain = 0x3b; 6755 } else if (IEEE80211_IS_CHAN_5GHZ(c)) { 6756 chan->rf_gain = 0x3b; 6757 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) { 6758 chan->rf_gain = 0x28; 6759 } else { 6760 chan->rf_gain = 0x28; 6761 } 6762 6763 DPRINTF(sc, IWN_DEBUG_STATE, 6764 "%s: chan %u flags 0x%x rf_gain 0x%x " 6765 "dsp_gain 0x%x active %d passive %d scan_svc_time %d crc 0x%x " 6766 "isactive=%d numssid=%d\n", __func__, 6767 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain, 6768 dwell_active, dwell_passive, scan_service_time, 6769 hdr->crc_threshold, is_active, ss->ss_nssid); 6770 6771 hdr->nchan++; 6772 chan++; 6773 buflen = (uint8_t *)chan - buf; 6774 hdr->len = htole16(buflen); 6775 6776 if (sc->sc_is_scanning) { 6777 device_printf(sc->sc_dev, 6778 "%s: called with is_scanning set!\n", 6779 __func__); 6780 } 6781 sc->sc_is_scanning = 1; 6782 6783 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n", 6784 hdr->nchan); 6785 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 6786 kfree(buf, M_DEVBUF); 6787 6788 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6789 6790 return error; 6791 } 6792 6793 static int 6794 iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap) 6795 { 6796 struct iwn_ops *ops = &sc->ops; 6797 struct ifnet *ifp = sc->sc_ifp; 6798 struct ieee80211com *ic = ifp->if_l2com; 6799 struct ieee80211_node *ni = vap->iv_bss; 6800 int error; 6801 6802 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6803 6804 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6805 /* Update adapter configuration. */ 6806 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 6807 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 6808 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6809 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 6810 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6811 if (ic->ic_flags & IEEE80211_F_SHSLOT) 6812 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 6813 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 6814 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 6815 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 6816 sc->rxon->cck_mask = 0; 6817 sc->rxon->ofdm_mask = 0x15; 6818 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 6819 sc->rxon->cck_mask = 0x03; 6820 sc->rxon->ofdm_mask = 0; 6821 } else { 6822 /* Assume 802.11b/g. */ 6823 sc->rxon->cck_mask = 0x03; 6824 sc->rxon->ofdm_mask = 0x15; 6825 } 6826 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n", 6827 sc->rxon->chan, sc->rxon->flags, sc->rxon->cck_mask, 6828 sc->rxon->ofdm_mask); 6829 if (sc->sc_is_scanning) 6830 device_printf(sc->sc_dev, 6831 "%s: is_scanning set, before RXON\n", 6832 __func__); 6833 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 6834 if (error != 0) { 6835 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n", 6836 __func__, error); 6837 return error; 6838 } 6839 6840 /* Configuration has changed, set TX power accordingly. */ 6841 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 6842 device_printf(sc->sc_dev, 6843 "%s: could not set TX power, error %d\n", __func__, error); 6844 return error; 6845 } 6846 /* 6847 * Reconfiguring RXON clears the firmware nodes table so we must 6848 * add the broadcast node again. 6849 */ 6850 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) { 6851 device_printf(sc->sc_dev, 6852 "%s: could not add broadcast node, error %d\n", __func__, 6853 error); 6854 return error; 6855 } 6856 6857 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 6858 6859 return 0; 6860 } 6861 6862 static int 6863 iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap) 6864 { 6865 struct iwn_ops *ops = &sc->ops; 6866 struct ifnet *ifp = sc->sc_ifp; 6867 struct ieee80211com *ic = ifp->if_l2com; 6868 struct ieee80211_node *ni = vap->iv_bss; 6869 struct iwn_node_info node; 6870 uint32_t htflags = 0; 6871 int error; 6872 6873 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 6874 6875 sc->rxon = &sc->rx_on[IWN_RXON_BSS_CTX]; 6876 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 6877 /* Link LED blinks while monitoring. */ 6878 iwn_set_led(sc, IWN_LED_LINK, 5, 5); 6879 return 0; 6880 } 6881 if ((error = iwn_set_timing(sc, ni)) != 0) { 6882 device_printf(sc->sc_dev, 6883 "%s: could not set timing, error %d\n", __func__, error); 6884 return error; 6885 } 6886 6887 /* Update adapter configuration. */ 6888 IEEE80211_ADDR_COPY(sc->rxon->bssid, ni->ni_bssid); 6889 sc->rxon->associd = htole16(IEEE80211_AID(ni->ni_associd)); 6890 sc->rxon->chan = ieee80211_chan2ieee(ic, ni->ni_chan); 6891 sc->rxon->flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 6892 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) 6893 sc->rxon->flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 6894 if (ic->ic_flags & IEEE80211_F_SHSLOT) 6895 sc->rxon->flags |= htole32(IWN_RXON_SHSLOT); 6896 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 6897 sc->rxon->flags |= htole32(IWN_RXON_SHPREAMBLE); 6898 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) { 6899 sc->rxon->cck_mask = 0; 6900 sc->rxon->ofdm_mask = 0x15; 6901 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) { 6902 sc->rxon->cck_mask = 0x03; 6903 sc->rxon->ofdm_mask = 0; 6904 } else { 6905 /* Assume 802.11b/g. */ 6906 sc->rxon->cck_mask = 0x0f; 6907 sc->rxon->ofdm_mask = 0x15; 6908 } 6909 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 6910 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode); 6911 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) { 6912 switch (ic->ic_curhtprotmode) { 6913 case IEEE80211_HTINFO_OPMODE_HT20PR: 6914 htflags |= IWN_RXON_HT_MODEPURE40; 6915 break; 6916 default: 6917 htflags |= IWN_RXON_HT_MODEMIXED; 6918 break; 6919 } 6920 } 6921 if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan)) 6922 htflags |= IWN_RXON_HT_HT40MINUS; 6923 } 6924 sc->rxon->flags |= htole32(htflags); 6925 sc->rxon->filter |= htole32(IWN_FILTER_BSS); 6926 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n", 6927 sc->rxon->chan, sc->rxon->flags); 6928 if (sc->sc_is_scanning) 6929 device_printf(sc->sc_dev, 6930 "%s: is_scanning set, before RXON\n", 6931 __func__); 6932 error = iwn_cmd(sc, IWN_CMD_RXON, sc->rxon, sc->rxonsz, 1); 6933 if (error != 0) { 6934 device_printf(sc->sc_dev, 6935 "%s: could not update configuration, error %d\n", __func__, 6936 error); 6937 return error; 6938 } 6939 6940 /* Configuration has changed, set TX power accordingly. */ 6941 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) { 6942 device_printf(sc->sc_dev, 6943 "%s: could not set TX power, error %d\n", __func__, error); 6944 return error; 6945 } 6946 6947 /* Fake a join to initialize the TX rate. */ 6948 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 6949 iwn_newassoc(ni, 1); 6950 6951 /* Add BSS node. */ 6952 memset(&node, 0, sizeof node); 6953 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 6954 node.id = IWN_ID_BSS; 6955 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) { 6956 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) { 6957 case IEEE80211_HTCAP_SMPS_ENA: 6958 node.htflags |= htole32(IWN_SMPS_MIMO_DIS); 6959 break; 6960 case IEEE80211_HTCAP_SMPS_DYNAMIC: 6961 node.htflags |= htole32(IWN_SMPS_MIMO_PROT); 6962 break; 6963 } 6964 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) | 6965 IWN_AMDPU_DENSITY(5)); /* 4us */ 6966 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) 6967 node.htflags |= htole32(IWN_NODE_HT40); 6968 } 6969 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__); 6970 error = ops->add_node(sc, &node, 1); 6971 if (error != 0) { 6972 device_printf(sc->sc_dev, 6973 "%s: could not add BSS node, error %d\n", __func__, error); 6974 return error; 6975 } 6976 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n", 6977 __func__, node.id); 6978 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 6979 device_printf(sc->sc_dev, 6980 "%s: could not setup link quality for node %d, error %d\n", 6981 __func__, node.id, error); 6982 return error; 6983 } 6984 6985 if ((error = iwn_init_sensitivity(sc)) != 0) { 6986 device_printf(sc->sc_dev, 6987 "%s: could not set sensitivity, error %d\n", __func__, 6988 error); 6989 return error; 6990 } 6991 /* Start periodic calibration timer. */ 6992 sc->calib.state = IWN_CALIB_STATE_ASSOC; 6993 sc->calib_cnt = 0; 6994 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout, 6995 sc); 6996 6997 /* Link LED always on while associated. */ 6998 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 6999 7000 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7001 7002 return 0; 7003 } 7004 7005 /* 7006 * This function is called by upper layer when an ADDBA request is received 7007 * from another STA and before the ADDBA response is sent. 7008 */ 7009 static int 7010 iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap, 7011 int baparamset, int batimeout, int baseqctl) 7012 { 7013 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 7014 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7015 struct iwn_ops *ops = &sc->ops; 7016 struct iwn_node *wn = (void *)ni; 7017 struct iwn_node_info node; 7018 uint16_t ssn; 7019 uint8_t tid; 7020 int error; 7021 7022 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7023 7024 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID); 7025 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START); 7026 7027 memset(&node, 0, sizeof node); 7028 node.id = wn->id; 7029 node.control = IWN_NODE_UPDATE; 7030 node.flags = IWN_FLAG_SET_ADDBA; 7031 node.addba_tid = tid; 7032 node.addba_ssn = htole16(ssn); 7033 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n", 7034 wn->id, tid, ssn); 7035 error = ops->add_node(sc, &node, 1); 7036 if (error != 0) 7037 return error; 7038 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl); 7039 #undef MS 7040 } 7041 7042 /* 7043 * This function is called by upper layer on teardown of an HT-immediate 7044 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 7045 */ 7046 static void 7047 iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap) 7048 { 7049 struct ieee80211com *ic = ni->ni_ic; 7050 struct iwn_softc *sc = ic->ic_ifp->if_softc; 7051 struct iwn_ops *ops = &sc->ops; 7052 struct iwn_node *wn = (void *)ni; 7053 struct iwn_node_info node; 7054 uint8_t tid; 7055 7056 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7057 7058 /* XXX: tid as an argument */ 7059 for (tid = 0; tid < WME_NUM_TID; tid++) { 7060 if (&ni->ni_rx_ampdu[tid] == rap) 7061 break; 7062 } 7063 7064 memset(&node, 0, sizeof node); 7065 node.id = wn->id; 7066 node.control = IWN_NODE_UPDATE; 7067 node.flags = IWN_FLAG_SET_DELBA; 7068 node.delba_tid = tid; 7069 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid); 7070 (void)ops->add_node(sc, &node, 1); 7071 sc->sc_ampdu_rx_stop(ni, rap); 7072 } 7073 7074 static int 7075 iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7076 int dialogtoken, int baparamset, int batimeout) 7077 { 7078 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7079 int qid; 7080 7081 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7082 7083 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) { 7084 if (sc->qid2tap[qid] == NULL) 7085 break; 7086 } 7087 if (qid == sc->ntxqs) { 7088 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n", 7089 __func__); 7090 return 0; 7091 } 7092 tap->txa_private = kmalloc(sizeof(int), M_DEVBUF, M_INTWAIT); 7093 sc->qid2tap[qid] = tap; 7094 *(int *)tap->txa_private = qid; 7095 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 7096 batimeout); 7097 } 7098 7099 static int 7100 iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 7101 int code, int baparamset, int batimeout) 7102 { 7103 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7104 int qid = *(int *)tap->txa_private; 7105 uint8_t tid = tap->txa_ac; 7106 int ret; 7107 7108 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7109 7110 if (code == IEEE80211_STATUS_SUCCESS) { 7111 ni->ni_txseqs[tid] = tap->txa_start & 0xfff; 7112 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid); 7113 if (ret != 1) 7114 return ret; 7115 } else { 7116 sc->qid2tap[qid] = NULL; 7117 kfree(tap->txa_private, M_DEVBUF); 7118 tap->txa_private = NULL; 7119 } 7120 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout); 7121 } 7122 7123 /* 7124 * This function is called by upper layer when an ADDBA response is received 7125 * from another STA. 7126 */ 7127 static int 7128 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 7129 uint8_t tid) 7130 { 7131 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid]; 7132 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7133 struct iwn_ops *ops = &sc->ops; 7134 struct iwn_node *wn = (void *)ni; 7135 struct iwn_node_info node; 7136 int error, qid; 7137 7138 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7139 7140 /* Enable TX for the specified RA/TID. */ 7141 wn->disable_tid &= ~(1 << tid); 7142 memset(&node, 0, sizeof node); 7143 node.id = wn->id; 7144 node.control = IWN_NODE_UPDATE; 7145 node.flags = IWN_FLAG_SET_DISABLE_TID; 7146 node.disable_tid = htole16(wn->disable_tid); 7147 error = ops->add_node(sc, &node, 1); 7148 if (error != 0) 7149 return 0; 7150 7151 if ((error = iwn_nic_lock(sc)) != 0) 7152 return 0; 7153 qid = *(int *)tap->txa_private; 7154 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n", 7155 __func__, wn->id, tid, tap->txa_start, qid); 7156 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff); 7157 iwn_nic_unlock(sc); 7158 7159 iwn_set_link_quality(sc, ni); 7160 return 1; 7161 } 7162 7163 static void 7164 iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 7165 { 7166 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc; 7167 struct iwn_ops *ops = &sc->ops; 7168 uint8_t tid = tap->txa_ac; 7169 int qid; 7170 7171 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7172 7173 sc->sc_addba_stop(ni, tap); 7174 7175 if (tap->txa_private == NULL) 7176 return; 7177 7178 qid = *(int *)tap->txa_private; 7179 if (sc->txq[qid].queued != 0) 7180 return; 7181 if (iwn_nic_lock(sc) != 0) 7182 return; 7183 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff); 7184 iwn_nic_unlock(sc); 7185 sc->qid2tap[qid] = NULL; 7186 kfree(tap->txa_private, M_DEVBUF); 7187 tap->txa_private = NULL; 7188 } 7189 7190 static void 7191 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7192 int qid, uint8_t tid, uint16_t ssn) 7193 { 7194 struct iwn_node *wn = (void *)ni; 7195 7196 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7197 7198 /* Stop TX scheduler while we're changing its configuration. */ 7199 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7200 IWN4965_TXQ_STATUS_CHGACT); 7201 7202 /* Assign RA/TID translation to the queue. */ 7203 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 7204 wn->id << 4 | tid); 7205 7206 /* Enable chain-building mode for the queue. */ 7207 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 7208 7209 /* Set starting sequence number from the ADDBA request. */ 7210 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7211 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7212 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7213 7214 /* Set scheduler window size. */ 7215 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 7216 IWN_SCHED_WINSZ); 7217 /* Set scheduler frame limit. */ 7218 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7219 IWN_SCHED_LIMIT << 16); 7220 7221 /* Enable interrupts for the queue. */ 7222 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7223 7224 /* Mark the queue as active. */ 7225 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7226 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 7227 iwn_tid2fifo[tid] << 1); 7228 } 7229 7230 static void 7231 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7232 { 7233 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7234 7235 /* Stop TX scheduler while we're changing its configuration. */ 7236 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7237 IWN4965_TXQ_STATUS_CHGACT); 7238 7239 /* Set starting sequence number from the ADDBA request. */ 7240 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7241 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 7242 7243 /* Disable interrupts for the queue. */ 7244 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 7245 7246 /* Mark the queue as inactive. */ 7247 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7248 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 7249 } 7250 7251 static void 7252 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 7253 int qid, uint8_t tid, uint16_t ssn) 7254 { 7255 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7256 7257 struct iwn_node *wn = (void *)ni; 7258 7259 /* Stop TX scheduler while we're changing its configuration. */ 7260 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7261 IWN5000_TXQ_STATUS_CHGACT); 7262 7263 /* Assign RA/TID translation to the queue. */ 7264 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 7265 wn->id << 4 | tid); 7266 7267 /* Enable chain-building mode for the queue. */ 7268 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 7269 7270 /* Enable aggregation for the queue. */ 7271 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7272 7273 /* Set starting sequence number from the ADDBA request. */ 7274 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff); 7275 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7276 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7277 7278 /* Set scheduler window size and frame limit. */ 7279 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7280 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7281 7282 /* Enable interrupts for the queue. */ 7283 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7284 7285 /* Mark the queue as active. */ 7286 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7287 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 7288 } 7289 7290 static void 7291 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn) 7292 { 7293 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7294 7295 /* Stop TX scheduler while we're changing its configuration. */ 7296 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7297 IWN5000_TXQ_STATUS_CHGACT); 7298 7299 /* Disable aggregation for the queue. */ 7300 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 7301 7302 /* Set starting sequence number from the ADDBA request. */ 7303 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff)); 7304 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 7305 7306 /* Disable interrupts for the queue. */ 7307 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 7308 7309 /* Mark the queue as inactive. */ 7310 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7311 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 7312 } 7313 7314 /* 7315 * Query calibration tables from the initialization firmware. We do this 7316 * only once at first boot. Called from a process context. 7317 */ 7318 static int 7319 iwn5000_query_calibration(struct iwn_softc *sc) 7320 { 7321 struct iwn5000_calib_config cmd; 7322 int error; 7323 7324 memset(&cmd, 0, sizeof cmd); 7325 cmd.ucode.once.enable = htole32(0xffffffff); 7326 cmd.ucode.once.start = htole32(0xffffffff); 7327 cmd.ucode.once.send = htole32(0xffffffff); 7328 cmd.ucode.flags = htole32(0xffffffff); 7329 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n", 7330 __func__); 7331 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 7332 if (error != 0) 7333 return error; 7334 7335 /* Wait at most two seconds for calibration to complete. */ 7336 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 7337 error = zsleep(sc, &wlan_global_serializer, 0, "iwncal", 2 * hz); 7338 return error; 7339 } 7340 7341 /* 7342 * Send calibration results to the runtime firmware. These results were 7343 * obtained on first boot from the initialization firmware. 7344 */ 7345 static int 7346 iwn5000_send_calibration(struct iwn_softc *sc) 7347 { 7348 int idx, error; 7349 7350 for (idx = 0; idx < IWN5000_PHY_CALIB_MAX_RESULT; idx++) { 7351 if (!(sc->base_params->calib_need & (1<<idx))) { 7352 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7353 "No need of calib %d\n", 7354 idx); 7355 continue; /* no need for this calib */ 7356 } 7357 if (sc->calibcmd[idx].buf == NULL) { 7358 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7359 "Need calib idx : %d but no available data\n", 7360 idx); 7361 continue; 7362 } 7363 7364 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7365 "send calibration result idx=%d len=%d\n", idx, 7366 sc->calibcmd[idx].len); 7367 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 7368 sc->calibcmd[idx].len, 0); 7369 if (error != 0) { 7370 device_printf(sc->sc_dev, 7371 "%s: could not send calibration result, error %d\n", 7372 __func__, error); 7373 return error; 7374 } 7375 } 7376 return 0; 7377 } 7378 7379 static int 7380 iwn5000_send_wimax_coex(struct iwn_softc *sc) 7381 { 7382 struct iwn5000_wimax_coex wimax; 7383 7384 #if 0 7385 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 7386 /* Enable WiMAX coexistence for combo adapters. */ 7387 wimax.flags = 7388 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 7389 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 7390 IWN_WIMAX_COEX_STA_TABLE_VALID | 7391 IWN_WIMAX_COEX_ENABLE; 7392 memcpy(wimax.events, iwn6050_wimax_events, 7393 sizeof iwn6050_wimax_events); 7394 } else 7395 #endif 7396 { 7397 /* Disable WiMAX coexistence. */ 7398 wimax.flags = 0; 7399 memset(wimax.events, 0, sizeof wimax.events); 7400 } 7401 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n", 7402 __func__); 7403 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 7404 } 7405 7406 static int 7407 iwn5000_crystal_calib(struct iwn_softc *sc) 7408 { 7409 struct iwn5000_phy_calib_crystal cmd; 7410 7411 memset(&cmd, 0, sizeof cmd); 7412 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 7413 cmd.ngroups = 1; 7414 cmd.isvalid = 1; 7415 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff; 7416 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff; 7417 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n", 7418 cmd.cap_pin[0], cmd.cap_pin[1]); 7419 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7420 } 7421 7422 static int 7423 iwn5000_temp_offset_calib(struct iwn_softc *sc) 7424 { 7425 struct iwn5000_phy_calib_temp_offset cmd; 7426 7427 memset(&cmd, 0, sizeof cmd); 7428 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7429 cmd.ngroups = 1; 7430 cmd.isvalid = 1; 7431 if (sc->eeprom_temp != 0) 7432 cmd.offset = htole16(sc->eeprom_temp); 7433 else 7434 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 7435 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n", 7436 le16toh(cmd.offset)); 7437 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7438 } 7439 7440 static int 7441 iwn5000_temp_offset_calibv2(struct iwn_softc *sc) 7442 { 7443 struct iwn5000_phy_calib_temp_offsetv2 cmd; 7444 7445 memset(&cmd, 0, sizeof cmd); 7446 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET; 7447 cmd.ngroups = 1; 7448 cmd.isvalid = 1; 7449 if (sc->eeprom_temp != 0) { 7450 cmd.offset_low = htole16(sc->eeprom_temp); 7451 cmd.offset_high = htole16(sc->eeprom_temp_high); 7452 } else { 7453 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 7454 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 7455 } 7456 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 7457 7458 DPRINTF(sc, IWN_DEBUG_CALIBRATE, 7459 "setting radio sensor low offset to %d, high offset to %d, voltage to %d\n", 7460 le16toh(cmd.offset_low), 7461 le16toh(cmd.offset_high), 7462 le16toh(cmd.burnt_voltage_ref)); 7463 7464 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 7465 } 7466 7467 /* 7468 * This function is called after the runtime firmware notifies us of its 7469 * readiness (called in a process context). 7470 */ 7471 static int 7472 iwn4965_post_alive(struct iwn_softc *sc) 7473 { 7474 int error, qid; 7475 7476 if ((error = iwn_nic_lock(sc)) != 0) 7477 return error; 7478 7479 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7480 7481 /* Clear TX scheduler state in SRAM. */ 7482 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7483 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 7484 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 7485 7486 /* Set physical address of TX scheduler rings (1KB aligned). */ 7487 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7488 7489 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7490 7491 /* Disable chain mode for all our 16 queues. */ 7492 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 7493 7494 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 7495 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 7496 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7497 7498 /* Set scheduler window size. */ 7499 iwn_mem_write(sc, sc->sched_base + 7500 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 7501 /* Set scheduler frame limit. */ 7502 iwn_mem_write(sc, sc->sched_base + 7503 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 7504 IWN_SCHED_LIMIT << 16); 7505 } 7506 7507 /* Enable interrupts for all our 16 queues. */ 7508 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 7509 /* Identify TX FIFO rings (0-7). */ 7510 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 7511 7512 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7513 for (qid = 0; qid < 7; qid++) { 7514 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 7515 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 7516 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 7517 } 7518 iwn_nic_unlock(sc); 7519 return 0; 7520 } 7521 7522 /* 7523 * This function is called after the initialization or runtime firmware 7524 * notifies us of its readiness (called in a process context). 7525 */ 7526 static int 7527 iwn5000_post_alive(struct iwn_softc *sc) 7528 { 7529 int error, qid; 7530 7531 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 7532 7533 /* Switch to using ICT interrupt mode. */ 7534 iwn5000_ict_reset(sc); 7535 7536 if ((error = iwn_nic_lock(sc)) != 0){ 7537 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s end in error\n", __func__); 7538 return error; 7539 } 7540 7541 /* Clear TX scheduler state in SRAM. */ 7542 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 7543 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 7544 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 7545 7546 /* Set physical address of TX scheduler rings (1KB aligned). */ 7547 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 7548 7549 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 7550 7551 /* Enable chain mode for all queues, except command queue. */ 7552 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) 7553 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffdf); 7554 else 7555 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 7556 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 7557 7558 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 7559 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 7560 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 7561 7562 iwn_mem_write(sc, sc->sched_base + 7563 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 7564 /* Set scheduler window size and frame limit. */ 7565 iwn_mem_write(sc, sc->sched_base + 7566 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 7567 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 7568 } 7569 7570 /* Enable interrupts for all our 20 queues. */ 7571 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 7572 /* Identify TX FIFO rings (0-7). */ 7573 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 7574 7575 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7576 if (sc->sc_flags & IWN_FLAG_PAN_SUPPORT) { 7577 /* Mark TX rings as active. */ 7578 for (qid = 0; qid < 11; qid++) { 7579 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 0, 4, 2, 5, 4, 7, 5 }; 7580 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7581 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7582 } 7583 } else { 7584 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 7585 for (qid = 0; qid < 7; qid++) { 7586 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 7587 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 7588 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 7589 } 7590 } 7591 iwn_nic_unlock(sc); 7592 7593 /* Configure WiMAX coexistence for combo adapters. */ 7594 error = iwn5000_send_wimax_coex(sc); 7595 if (error != 0) { 7596 device_printf(sc->sc_dev, 7597 "%s: could not configure WiMAX coexistence, error %d\n", 7598 __func__, error); 7599 return error; 7600 } 7601 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 7602 /* Perform crystal calibration. */ 7603 error = iwn5000_crystal_calib(sc); 7604 if (error != 0) { 7605 device_printf(sc->sc_dev, 7606 "%s: crystal calibration failed, error %d\n", 7607 __func__, error); 7608 return error; 7609 } 7610 } 7611 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 7612 /* Query calibration from the initialization firmware. */ 7613 if ((error = iwn5000_query_calibration(sc)) != 0) { 7614 device_printf(sc->sc_dev, 7615 "%s: could not query calibration, error %d\n", 7616 __func__, error); 7617 return error; 7618 } 7619 /* 7620 * We have the calibration results now, reboot with the 7621 * runtime firmware (call ourselves recursively!) 7622 */ 7623 iwn_hw_stop(sc); 7624 error = iwn_hw_init(sc); 7625 } else { 7626 /* Send calibration results to runtime firmware. */ 7627 error = iwn5000_send_calibration(sc); 7628 } 7629 7630 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 7631 7632 return error; 7633 } 7634 7635 /* 7636 * The firmware boot code is small and is intended to be copied directly into 7637 * the NIC internal memory (no DMA transfer). 7638 */ 7639 static int 7640 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 7641 { 7642 int error, ntries; 7643 7644 size /= sizeof (uint32_t); 7645 7646 if ((error = iwn_nic_lock(sc)) != 0) 7647 return error; 7648 7649 /* Copy microcode image into NIC memory. */ 7650 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 7651 (const uint32_t *)ucode, size); 7652 7653 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 7654 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 7655 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 7656 7657 /* Start boot load now. */ 7658 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 7659 7660 /* Wait for transfer to complete. */ 7661 for (ntries = 0; ntries < 1000; ntries++) { 7662 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 7663 IWN_BSM_WR_CTRL_START)) 7664 break; 7665 DELAY(10); 7666 } 7667 if (ntries == 1000) { 7668 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 7669 __func__); 7670 iwn_nic_unlock(sc); 7671 return ETIMEDOUT; 7672 } 7673 7674 /* Enable boot after power up. */ 7675 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 7676 7677 iwn_nic_unlock(sc); 7678 return 0; 7679 } 7680 7681 static int 7682 iwn4965_load_firmware(struct iwn_softc *sc) 7683 { 7684 struct iwn_fw_info *fw = &sc->fw; 7685 struct iwn_dma_info *dma = &sc->fw_dma; 7686 int error; 7687 7688 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 7689 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 7690 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7691 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 7692 fw->init.text, fw->init.textsz); 7693 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7694 7695 /* Tell adapter where to find initialization sections. */ 7696 if ((error = iwn_nic_lock(sc)) != 0) 7697 return error; 7698 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 7699 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 7700 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 7701 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 7702 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 7703 iwn_nic_unlock(sc); 7704 7705 /* Load firmware boot code. */ 7706 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 7707 if (error != 0) { 7708 device_printf(sc->sc_dev, "%s: could not load boot firmware\n", 7709 __func__); 7710 return error; 7711 } 7712 /* Now press "execute". */ 7713 IWN_WRITE(sc, IWN_RESET, 0); 7714 7715 /* Wait at most one second for first alive notification. */ 7716 if ((error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz)) != 0) { 7717 device_printf(sc->sc_dev, 7718 "%s: timeout waiting for adapter to initialize, error %d\n", 7719 __func__, error); 7720 return error; 7721 } 7722 7723 /* Retrieve current temperature for initial TX power calibration. */ 7724 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 7725 sc->temp = iwn4965_get_temperature(sc); 7726 7727 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 7728 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 7729 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7730 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 7731 fw->main.text, fw->main.textsz); 7732 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7733 7734 /* Tell adapter where to find runtime sections. */ 7735 if ((error = iwn_nic_lock(sc)) != 0) 7736 return error; 7737 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 7738 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 7739 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 7740 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 7741 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 7742 IWN_FW_UPDATED | fw->main.textsz); 7743 iwn_nic_unlock(sc); 7744 7745 return 0; 7746 } 7747 7748 static int 7749 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 7750 const uint8_t *section, int size) 7751 { 7752 struct iwn_dma_info *dma = &sc->fw_dma; 7753 int error; 7754 7755 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7756 7757 /* Copy firmware section into pre-allocated DMA-safe memory. */ 7758 memcpy(dma->vaddr, section, size); 7759 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE); 7760 7761 if ((error = iwn_nic_lock(sc)) != 0) 7762 return error; 7763 7764 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 7765 IWN_FH_TX_CONFIG_DMA_PAUSE); 7766 7767 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 7768 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 7769 IWN_LOADDR(dma->paddr)); 7770 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 7771 IWN_HIADDR(dma->paddr) << 28 | size); 7772 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 7773 IWN_FH_TXBUF_STATUS_TBNUM(1) | 7774 IWN_FH_TXBUF_STATUS_TBIDX(1) | 7775 IWN_FH_TXBUF_STATUS_TFBD_VALID); 7776 7777 /* Kick Flow Handler to start DMA transfer. */ 7778 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 7779 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 7780 7781 iwn_nic_unlock(sc); 7782 7783 /* Wait at most five seconds for FH DMA transfer to complete. */ 7784 return zsleep(sc, &wlan_global_serializer, 0, "iwninit", 5 * hz); 7785 } 7786 7787 static int 7788 iwn5000_load_firmware(struct iwn_softc *sc) 7789 { 7790 struct iwn_fw_part *fw; 7791 int error; 7792 7793 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 7794 7795 /* Load the initialization firmware on first boot only. */ 7796 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 7797 &sc->fw.main : &sc->fw.init; 7798 7799 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 7800 fw->text, fw->textsz); 7801 if (error != 0) { 7802 device_printf(sc->sc_dev, 7803 "%s: could not load firmware %s section, error %d\n", 7804 __func__, ".text", error); 7805 return error; 7806 } 7807 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 7808 fw->data, fw->datasz); 7809 if (error != 0) { 7810 device_printf(sc->sc_dev, 7811 "%s: could not load firmware %s section, error %d\n", 7812 __func__, ".data", error); 7813 return error; 7814 } 7815 7816 /* Now press "execute". */ 7817 IWN_WRITE(sc, IWN_RESET, 0); 7818 return 0; 7819 } 7820 7821 /* 7822 * Extract text and data sections from a legacy firmware image. 7823 */ 7824 static int 7825 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 7826 { 7827 const uint32_t *ptr; 7828 size_t hdrlen = 24; 7829 uint32_t rev; 7830 7831 ptr = (const uint32_t *)fw->data; 7832 rev = le32toh(*ptr++); 7833 7834 /* Check firmware API version. */ 7835 if (IWN_FW_API(rev) <= 1) { 7836 device_printf(sc->sc_dev, 7837 "%s: bad firmware, need API version >=2\n", __func__); 7838 return EINVAL; 7839 } 7840 if (IWN_FW_API(rev) >= 3) { 7841 /* Skip build number (version 2 header). */ 7842 hdrlen += 4; 7843 ptr++; 7844 } 7845 if (fw->size < hdrlen) { 7846 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 7847 __func__, fw->size); 7848 return EINVAL; 7849 } 7850 fw->main.textsz = le32toh(*ptr++); 7851 fw->main.datasz = le32toh(*ptr++); 7852 fw->init.textsz = le32toh(*ptr++); 7853 fw->init.datasz = le32toh(*ptr++); 7854 fw->boot.textsz = le32toh(*ptr++); 7855 7856 /* Check that all firmware sections fit. */ 7857 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 7858 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 7859 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 7860 __func__, fw->size); 7861 return EINVAL; 7862 } 7863 7864 /* Get pointers to firmware sections. */ 7865 fw->main.text = (const uint8_t *)ptr; 7866 fw->main.data = fw->main.text + fw->main.textsz; 7867 fw->init.text = fw->main.data + fw->main.datasz; 7868 fw->init.data = fw->init.text + fw->init.textsz; 7869 fw->boot.text = fw->init.data + fw->init.datasz; 7870 return 0; 7871 } 7872 7873 /* 7874 * Extract text and data sections from a TLV firmware image. 7875 */ 7876 static int 7877 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 7878 uint16_t alt) 7879 { 7880 const struct iwn_fw_tlv_hdr *hdr; 7881 const struct iwn_fw_tlv *tlv; 7882 const uint8_t *ptr, *end; 7883 uint64_t altmask; 7884 uint32_t len, tmp; 7885 7886 if (fw->size < sizeof (*hdr)) { 7887 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 7888 __func__, fw->size); 7889 return EINVAL; 7890 } 7891 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 7892 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 7893 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n", 7894 __func__, le32toh(hdr->signature)); 7895 return EINVAL; 7896 } 7897 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr, 7898 le32toh(hdr->build)); 7899 7900 /* 7901 * Select the closest supported alternative that is less than 7902 * or equal to the specified one. 7903 */ 7904 altmask = le64toh(hdr->altmask); 7905 while (alt > 0 && !(altmask & (1ULL << alt))) 7906 alt--; /* Downgrade. */ 7907 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt); 7908 7909 ptr = (const uint8_t *)(hdr + 1); 7910 end = (const uint8_t *)(fw->data + fw->size); 7911 7912 /* Parse type-length-value fields. */ 7913 while (ptr + sizeof (*tlv) <= end) { 7914 tlv = (const struct iwn_fw_tlv *)ptr; 7915 len = le32toh(tlv->len); 7916 7917 ptr += sizeof (*tlv); 7918 if (ptr + len > end) { 7919 device_printf(sc->sc_dev, 7920 "%s: firmware too short: %zu bytes\n", __func__, 7921 fw->size); 7922 return EINVAL; 7923 } 7924 /* Skip other alternatives. */ 7925 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 7926 goto next; 7927 7928 switch (le16toh(tlv->type)) { 7929 case IWN_FW_TLV_MAIN_TEXT: 7930 fw->main.text = ptr; 7931 fw->main.textsz = len; 7932 break; 7933 case IWN_FW_TLV_MAIN_DATA: 7934 fw->main.data = ptr; 7935 fw->main.datasz = len; 7936 break; 7937 case IWN_FW_TLV_INIT_TEXT: 7938 fw->init.text = ptr; 7939 fw->init.textsz = len; 7940 break; 7941 case IWN_FW_TLV_INIT_DATA: 7942 fw->init.data = ptr; 7943 fw->init.datasz = len; 7944 break; 7945 case IWN_FW_TLV_BOOT_TEXT: 7946 fw->boot.text = ptr; 7947 fw->boot.textsz = len; 7948 break; 7949 case IWN_FW_TLV_ENH_SENS: 7950 if (!len) 7951 sc->sc_flags |= IWN_FLAG_ENH_SENS; 7952 break; 7953 case IWN_FW_TLV_PHY_CALIB: 7954 tmp = le32toh(*ptr); 7955 if (tmp < 253) { 7956 sc->reset_noise_gain = tmp; 7957 sc->noise_gain = tmp + 1; 7958 } 7959 break; 7960 case IWN_FW_TLV_PAN: 7961 sc->sc_flags |= IWN_FLAG_PAN_SUPPORT; 7962 DPRINTF(sc, IWN_DEBUG_RESET, 7963 "PAN Support found: %d\n", 1); 7964 break; 7965 case IWN_FW_TLV_FLAGS: 7966 if (len < sizeof(uint32_t)) 7967 break; 7968 if (len % sizeof(uint32_t)) 7969 break; 7970 sc->tlv_feature_flags = le32toh(*ptr); 7971 DPRINTF(sc, IWN_DEBUG_RESET, 7972 "%s: feature: 0x%08x\n", 7973 __func__, 7974 sc->tlv_feature_flags); 7975 break; 7976 case IWN_FW_TLV_PBREQ_MAXLEN: 7977 case IWN_FW_TLV_RUNT_EVTLOG_PTR: 7978 case IWN_FW_TLV_RUNT_EVTLOG_SIZE: 7979 case IWN_FW_TLV_RUNT_ERRLOG_PTR: 7980 case IWN_FW_TLV_INIT_EVTLOG_PTR: 7981 case IWN_FW_TLV_INIT_EVTLOG_SIZE: 7982 case IWN_FW_TLV_INIT_ERRLOG_PTR: 7983 case IWN_FW_TLV_WOWLAN_INST: 7984 case IWN_FW_TLV_WOWLAN_DATA: 7985 DPRINTF(sc, IWN_DEBUG_RESET, 7986 "TLV type %d recognized but not handled\n", 7987 le16toh(tlv->type)); 7988 break; 7989 default: 7990 DPRINTF(sc, IWN_DEBUG_RESET, 7991 "TLV type %d not handled\n", le16toh(tlv->type)); 7992 break; 7993 } 7994 next: /* TLV fields are 32-bit aligned. */ 7995 ptr += (len + 3) & ~3; 7996 } 7997 return 0; 7998 } 7999 8000 static int 8001 iwn_read_firmware(struct iwn_softc *sc) 8002 { 8003 struct iwn_fw_info *fw = &sc->fw; 8004 int error; 8005 8006 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8007 8008 wlan_assert_serialized(); 8009 memset(fw, 0, sizeof (*fw)); 8010 8011 /* 8012 * Read firmware image from filesystem. The firmware can block 8013 * in a taskq and deadlock against our serializer so unlock 8014 * while we do tihs. 8015 */ 8016 wlan_serialize_exit(); 8017 sc->fw_fp = firmware_get(sc->fwname); 8018 wlan_serialize_enter(); 8019 if (sc->fw_fp == NULL) { 8020 device_printf(sc->sc_dev, "%s: could not read firmware %s\n", 8021 __func__, sc->fwname); 8022 return EINVAL; 8023 } 8024 8025 fw->size = sc->fw_fp->datasize; 8026 fw->data = (const uint8_t *)sc->fw_fp->data; 8027 if (fw->size < sizeof (uint32_t)) { 8028 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n", 8029 __func__, fw->size); 8030 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8031 sc->fw_fp = NULL; 8032 return EINVAL; 8033 } 8034 8035 /* Retrieve text and data sections. */ 8036 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 8037 error = iwn_read_firmware_leg(sc, fw); 8038 else 8039 error = iwn_read_firmware_tlv(sc, fw, 1); 8040 if (error != 0) { 8041 device_printf(sc->sc_dev, 8042 "%s: could not read firmware sections, error %d\n", 8043 __func__, error); 8044 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8045 sc->fw_fp = NULL; 8046 return error; 8047 } 8048 8049 /* Make sure text and data sections fit in hardware memory. */ 8050 if (fw->main.textsz > sc->fw_text_maxsz || 8051 fw->main.datasz > sc->fw_data_maxsz || 8052 fw->init.textsz > sc->fw_text_maxsz || 8053 fw->init.datasz > sc->fw_data_maxsz || 8054 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 8055 (fw->boot.textsz & 3) != 0) { 8056 device_printf(sc->sc_dev, "%s: firmware sections too large\n", 8057 __func__); 8058 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8059 sc->fw_fp = NULL; 8060 return EINVAL; 8061 } 8062 8063 /* We can proceed with loading the firmware. */ 8064 return 0; 8065 } 8066 8067 static int 8068 iwn_clock_wait(struct iwn_softc *sc) 8069 { 8070 int ntries; 8071 8072 /* Set "initialization complete" bit. */ 8073 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8074 8075 /* Wait for clock stabilization. */ 8076 for (ntries = 0; ntries < 2500; ntries++) { 8077 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 8078 return 0; 8079 DELAY(10); 8080 } 8081 device_printf(sc->sc_dev, 8082 "%s: timeout waiting for clock stabilization\n", __func__); 8083 return ETIMEDOUT; 8084 } 8085 8086 static int 8087 iwn_apm_init(struct iwn_softc *sc) 8088 { 8089 uint32_t reg; 8090 int error; 8091 8092 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8093 8094 /* Disable L0s exit timer (NMI bug workaround). */ 8095 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 8096 /* Don't wait for ICH L0s (ICH bug workaround). */ 8097 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 8098 8099 /* Set FH wait threshold to max (HW bug under stress workaround). */ 8100 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 8101 8102 /* Enable HAP INTA to move adapter from L1a to L0s. */ 8103 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 8104 8105 /* Retrieve PCIe Active State Power Management (ASPM). */ 8106 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1); 8107 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 8108 if (reg & 0x02) /* L1 Entry enabled. */ 8109 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8110 else 8111 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 8112 8113 if (sc->base_params->pll_cfg_val) 8114 IWN_SETBITS(sc, IWN_ANA_PLL, sc->base_params->pll_cfg_val); 8115 8116 /* Wait for clock stabilization before accessing prph. */ 8117 if ((error = iwn_clock_wait(sc)) != 0) 8118 return error; 8119 8120 if ((error = iwn_nic_lock(sc)) != 0) 8121 return error; 8122 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 8123 /* Enable DMA and BSM (Bootstrap State Machine). */ 8124 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8125 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 8126 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 8127 } else { 8128 /* Enable DMA. */ 8129 iwn_prph_write(sc, IWN_APMG_CLK_EN, 8130 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8131 } 8132 DELAY(20); 8133 /* Disable L1-Active. */ 8134 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 8135 iwn_nic_unlock(sc); 8136 8137 return 0; 8138 } 8139 8140 static void 8141 iwn_apm_stop_master(struct iwn_softc *sc) 8142 { 8143 int ntries; 8144 8145 /* Stop busmaster DMA activity. */ 8146 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 8147 for (ntries = 0; ntries < 100; ntries++) { 8148 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 8149 return; 8150 DELAY(10); 8151 } 8152 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__); 8153 } 8154 8155 static void 8156 iwn_apm_stop(struct iwn_softc *sc) 8157 { 8158 iwn_apm_stop_master(sc); 8159 8160 /* Reset the entire device. */ 8161 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 8162 DELAY(10); 8163 /* Clear "initialization complete" bit. */ 8164 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 8165 } 8166 8167 static int 8168 iwn4965_nic_config(struct iwn_softc *sc) 8169 { 8170 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8171 8172 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 8173 /* 8174 * I don't believe this to be correct but this is what the 8175 * vendor driver is doing. Probably the bits should not be 8176 * shifted in IWN_RFCFG_*. 8177 */ 8178 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8179 IWN_RFCFG_TYPE(sc->rfcfg) | 8180 IWN_RFCFG_STEP(sc->rfcfg) | 8181 IWN_RFCFG_DASH(sc->rfcfg)); 8182 } 8183 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8184 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8185 return 0; 8186 } 8187 8188 static int 8189 iwn5000_nic_config(struct iwn_softc *sc) 8190 { 8191 uint32_t tmp; 8192 int error; 8193 8194 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8195 8196 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 8197 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8198 IWN_RFCFG_TYPE(sc->rfcfg) | 8199 IWN_RFCFG_STEP(sc->rfcfg) | 8200 IWN_RFCFG_DASH(sc->rfcfg)); 8201 } 8202 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 8203 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 8204 8205 if ((error = iwn_nic_lock(sc)) != 0) 8206 return error; 8207 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 8208 8209 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 8210 /* 8211 * Select first Switching Voltage Regulator (1.32V) to 8212 * solve a stability issue related to noisy DC2DC line 8213 * in the silicon of 1000 Series. 8214 */ 8215 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 8216 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 8217 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 8218 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 8219 } 8220 iwn_nic_unlock(sc); 8221 8222 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 8223 /* Use internal power amplifier only. */ 8224 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 8225 } 8226 if (sc->base_params->additional_nic_config && sc->calib_ver >= 6) { 8227 /* Indicate that ROM calibration version is >=6. */ 8228 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 8229 } 8230 if (sc->base_params->additional_gp_drv_bit) 8231 IWN_SETBITS(sc, IWN_GP_DRIVER, 8232 sc->base_params->additional_gp_drv_bit); 8233 return 0; 8234 } 8235 8236 /* 8237 * Take NIC ownership over Intel Active Management Technology (AMT). 8238 */ 8239 static int 8240 iwn_hw_prepare(struct iwn_softc *sc) 8241 { 8242 int ntries; 8243 8244 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8245 8246 /* Check if hardware is ready. */ 8247 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8248 for (ntries = 0; ntries < 5; ntries++) { 8249 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8250 IWN_HW_IF_CONFIG_NIC_READY) 8251 return 0; 8252 DELAY(10); 8253 } 8254 8255 /* Hardware not ready, force into ready state. */ 8256 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 8257 for (ntries = 0; ntries < 15000; ntries++) { 8258 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 8259 IWN_HW_IF_CONFIG_PREPARE_DONE)) 8260 break; 8261 DELAY(10); 8262 } 8263 if (ntries == 15000) 8264 return ETIMEDOUT; 8265 8266 /* Hardware should be ready now. */ 8267 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 8268 for (ntries = 0; ntries < 5; ntries++) { 8269 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 8270 IWN_HW_IF_CONFIG_NIC_READY) 8271 return 0; 8272 DELAY(10); 8273 } 8274 return ETIMEDOUT; 8275 } 8276 8277 static int 8278 iwn_hw_init(struct iwn_softc *sc) 8279 { 8280 struct iwn_ops *ops = &sc->ops; 8281 int error, chnl, qid; 8282 8283 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8284 8285 /* Clear pending interrupts. */ 8286 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8287 8288 if ((error = iwn_apm_init(sc)) != 0) { 8289 device_printf(sc->sc_dev, 8290 "%s: could not power ON adapter, error %d\n", __func__, 8291 error); 8292 return error; 8293 } 8294 8295 /* Select VMAIN power source. */ 8296 if ((error = iwn_nic_lock(sc)) != 0) 8297 return error; 8298 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 8299 iwn_nic_unlock(sc); 8300 8301 /* Perform adapter-specific initialization. */ 8302 if ((error = ops->nic_config(sc)) != 0) 8303 return error; 8304 8305 /* Initialize RX ring. */ 8306 if ((error = iwn_nic_lock(sc)) != 0) 8307 return error; 8308 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 8309 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 8310 /* Set physical address of RX ring (256-byte aligned). */ 8311 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 8312 /* Set physical address of RX status (16-byte aligned). */ 8313 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 8314 /* Enable RX. */ 8315 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 8316 IWN_FH_RX_CONFIG_ENA | 8317 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 8318 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 8319 IWN_FH_RX_CONFIG_SINGLE_FRAME | 8320 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) | 8321 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 8322 iwn_nic_unlock(sc); 8323 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 8324 8325 if ((error = iwn_nic_lock(sc)) != 0) 8326 return error; 8327 8328 /* Initialize TX scheduler. */ 8329 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8330 8331 /* Set physical address of "keep warm" page (16-byte aligned). */ 8332 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 8333 8334 /* Initialize TX rings. */ 8335 for (qid = 0; qid < sc->ntxqs; qid++) { 8336 struct iwn_tx_ring *txq = &sc->txq[qid]; 8337 8338 /* Set physical address of TX ring (256-byte aligned). */ 8339 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 8340 txq->desc_dma.paddr >> 8); 8341 } 8342 iwn_nic_unlock(sc); 8343 8344 /* Enable DMA channels. */ 8345 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8346 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 8347 IWN_FH_TX_CONFIG_DMA_ENA | 8348 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 8349 } 8350 8351 /* Clear "radio off" and "commands blocked" bits. */ 8352 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8353 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 8354 8355 /* Clear pending interrupts. */ 8356 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8357 /* Enable interrupt coalescing. */ 8358 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 8359 /* Enable interrupts. */ 8360 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8361 8362 /* _Really_ make sure "radio off" bit is cleared! */ 8363 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8364 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 8365 8366 /* Enable shadow registers. */ 8367 if (sc->base_params->shadow_reg_enable) 8368 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 8369 8370 if ((error = ops->load_firmware(sc)) != 0) { 8371 device_printf(sc->sc_dev, 8372 "%s: could not load firmware, error %d\n", __func__, 8373 error); 8374 return error; 8375 } 8376 /* Wait at most one second for firmware alive notification. */ 8377 if ((error = zsleep(sc, &wlan_global_serializer, 0, "iwninit", hz)) != 0) { 8378 device_printf(sc->sc_dev, 8379 "%s: timeout waiting for adapter to initialize, error %d\n", 8380 __func__, error); 8381 return error; 8382 } 8383 /* Do post-firmware initialization. */ 8384 8385 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8386 8387 return ops->post_alive(sc); 8388 } 8389 8390 static void 8391 iwn_hw_stop(struct iwn_softc *sc) 8392 { 8393 int chnl, qid, ntries; 8394 8395 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8396 8397 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 8398 8399 /* Disable interrupts. */ 8400 IWN_WRITE(sc, IWN_INT_MASK, 0); 8401 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8402 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 8403 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8404 8405 /* Make sure we no longer hold the NIC lock. */ 8406 iwn_nic_unlock(sc); 8407 8408 /* Stop TX scheduler. */ 8409 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 8410 8411 /* Stop all DMA channels. */ 8412 if (iwn_nic_lock(sc) == 0) { 8413 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 8414 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 8415 for (ntries = 0; ntries < 200; ntries++) { 8416 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 8417 IWN_FH_TX_STATUS_IDLE(chnl)) 8418 break; 8419 DELAY(10); 8420 } 8421 } 8422 iwn_nic_unlock(sc); 8423 } 8424 8425 /* Stop RX ring. */ 8426 iwn_reset_rx_ring(sc, &sc->rxq); 8427 8428 /* Reset all TX rings. */ 8429 for (qid = 0; qid < sc->ntxqs; qid++) 8430 iwn_reset_tx_ring(sc, &sc->txq[qid]); 8431 8432 if (iwn_nic_lock(sc) == 0) { 8433 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 8434 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 8435 iwn_nic_unlock(sc); 8436 } 8437 DELAY(5); 8438 /* Power OFF adapter. */ 8439 iwn_apm_stop(sc); 8440 } 8441 8442 static void 8443 iwn_radio_on_task(void *arg0, int pending) 8444 { 8445 struct iwn_softc *sc = arg0; 8446 struct ifnet *ifp; 8447 struct ieee80211com *ic; 8448 struct ieee80211vap *vap; 8449 8450 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8451 8452 wlan_serialize_enter(); 8453 ifp = sc->sc_ifp; 8454 ic = ifp->if_l2com; 8455 vap = TAILQ_FIRST(&ic->ic_vaps); 8456 if (vap != NULL) { 8457 iwn_init_locked(sc); 8458 ieee80211_init(vap); 8459 } 8460 wlan_serialize_exit(); 8461 } 8462 8463 static void 8464 iwn_radio_off_task(void *arg0, int pending) 8465 { 8466 struct iwn_softc *sc = arg0; 8467 struct ifnet *ifp; 8468 struct ieee80211com *ic; 8469 struct ieee80211vap *vap; 8470 8471 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8472 8473 wlan_serialize_enter(); 8474 ifp = sc->sc_ifp; 8475 ic = ifp->if_l2com; 8476 vap = TAILQ_FIRST(&ic->ic_vaps); 8477 iwn_stop_locked(sc); 8478 if (vap != NULL) 8479 ieee80211_stop(vap); 8480 8481 /* Enable interrupts to get RF toggle notification. */ 8482 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8483 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8484 wlan_serialize_exit(); 8485 } 8486 8487 static void 8488 iwn_panicked_task(void *arg0, int pending) 8489 { 8490 struct iwn_softc *sc = arg0; 8491 struct ifnet *ifp = sc->sc_ifp; 8492 struct ieee80211com *ic = ifp->if_l2com; 8493 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8494 int error; 8495 8496 if (vap == NULL) { 8497 kprintf("%s: null vap\n", __func__); 8498 return; 8499 } 8500 8501 device_printf(sc->sc_dev, "%s: controller panicked, iv_state = %d; " 8502 "resetting...\n", __func__, vap->iv_state); 8503 8504 wlan_serialize_enter(); 8505 8506 iwn_stop_locked(sc); 8507 iwn_init_locked(sc); 8508 if (vap->iv_state >= IEEE80211_S_AUTH && 8509 (error = iwn_auth(sc, vap)) != 0) { 8510 device_printf(sc->sc_dev, 8511 "%s: could not move to auth state\n", __func__); 8512 } 8513 if (vap->iv_state >= IEEE80211_S_RUN && 8514 (error = iwn_run(sc, vap)) != 0) { 8515 device_printf(sc->sc_dev, 8516 "%s: could not move to run state\n", __func__); 8517 } 8518 8519 /* Only run start once the NIC is in a useful state, like associated */ 8520 iwn_start_locked(sc->sc_ifp); 8521 8522 wlan_serialize_exit(); 8523 } 8524 8525 static void 8526 iwn_init_locked(struct iwn_softc *sc) 8527 { 8528 struct ifnet *ifp = sc->sc_ifp; 8529 int error; 8530 8531 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s begin\n", __func__); 8532 8533 /* 8534 * Make sure we hold the serializer or we will have timing issues 8535 * with the wlan subsystem. 8536 */ 8537 wlan_assert_serialized(); 8538 if ((error = iwn_hw_prepare(sc)) != 0) { 8539 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n", 8540 __func__, error); 8541 goto fail; 8542 } 8543 8544 /* Initialize interrupt mask to default value. */ 8545 sc->int_mask = IWN_INT_MASK_DEF; 8546 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 8547 8548 /* Check that the radio is not disabled by hardware switch. */ 8549 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 8550 device_printf(sc->sc_dev, 8551 "radio is disabled by hardware switch\n"); 8552 /* Enable interrupts to get RF toggle notifications. */ 8553 IWN_WRITE(sc, IWN_INT, 0xffffffff); 8554 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 8555 return; 8556 } 8557 8558 /* Read firmware images from the filesystem. */ 8559 if ((error = iwn_read_firmware(sc)) != 0) { 8560 device_printf(sc->sc_dev, 8561 "%s: could not read firmware, error %d\n", __func__, 8562 error); 8563 goto fail; 8564 } 8565 8566 /* Initialize hardware and upload firmware. */ 8567 error = iwn_hw_init(sc); 8568 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD); 8569 sc->fw_fp = NULL; 8570 if (error != 0) { 8571 device_printf(sc->sc_dev, 8572 "%s: could not initialize hardware, error %d\n", __func__, 8573 error); 8574 goto fail; 8575 } 8576 8577 /* Configure adapter now that it is ready. */ 8578 if ((error = iwn_config(sc)) != 0) { 8579 device_printf(sc->sc_dev, 8580 "%s: could not configure device, error %d\n", __func__, 8581 error); 8582 goto fail; 8583 } 8584 8585 ifq_clr_oactive(&ifp->if_snd); 8586 ifp->if_flags |= IFF_RUNNING; 8587 8588 callout_reset(&sc->watchdog_to, hz, iwn_watchdog_timeout, sc); 8589 8590 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end\n",__func__); 8591 8592 return; 8593 8594 fail: iwn_stop_locked(sc); 8595 DPRINTF(sc, IWN_DEBUG_TRACE, "->%s: end in error\n",__func__); 8596 } 8597 8598 static void 8599 iwn_init(void *arg) 8600 { 8601 struct iwn_softc *sc = arg; 8602 struct ifnet *ifp = sc->sc_ifp; 8603 struct ieee80211com *ic = ifp->if_l2com; 8604 8605 wlan_assert_serialized(); 8606 iwn_init_locked(sc); 8607 8608 if (ifp->if_flags & IFF_RUNNING) 8609 ieee80211_start_all(ic); 8610 } 8611 8612 static void 8613 iwn_stop_locked(struct iwn_softc *sc) 8614 { 8615 struct ifnet *ifp = sc->sc_ifp; 8616 8617 sc->sc_is_scanning = 0; 8618 sc->sc_tx_timer = 0; 8619 callout_stop(&sc->watchdog_to); 8620 callout_stop(&sc->calib_to); 8621 ifp->if_flags &= ~IFF_RUNNING; 8622 ifq_clr_oactive(&ifp->if_snd); 8623 8624 /* Power OFF hardware. */ 8625 iwn_hw_stop(sc); 8626 } 8627 8628 /* 8629 * Callback from net80211 to start a scan. 8630 */ 8631 static void 8632 iwn_scan_start(struct ieee80211com *ic) 8633 { 8634 struct ifnet *ifp = ic->ic_ifp; 8635 struct iwn_softc *sc = ifp->if_softc; 8636 8637 /* make the link LED blink while we're scanning */ 8638 iwn_set_led(sc, IWN_LED_LINK, 20, 2); 8639 } 8640 8641 /* 8642 * Callback from net80211 to terminate a scan. 8643 */ 8644 static void 8645 iwn_scan_end(struct ieee80211com *ic) 8646 { 8647 struct ifnet *ifp = ic->ic_ifp; 8648 struct iwn_softc *sc = ifp->if_softc; 8649 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 8650 8651 if (vap->iv_state == IEEE80211_S_RUN) { 8652 /* Set link LED to ON status if we are associated */ 8653 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 8654 } 8655 } 8656 8657 /* 8658 * Callback from net80211 to force a channel change. 8659 */ 8660 static void 8661 iwn_set_channel(struct ieee80211com *ic) 8662 { 8663 const struct ieee80211_channel *c = ic->ic_curchan; 8664 struct ifnet *ifp = ic->ic_ifp; 8665 struct iwn_softc *sc = ifp->if_softc; 8666 int error; 8667 8668 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8669 8670 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq); 8671 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags); 8672 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq); 8673 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags); 8674 8675 /* 8676 * Only need to set the channel in Monitor mode. AP scanning and auth 8677 * are already taken care of by their respective firmware commands. 8678 */ 8679 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 8680 error = iwn_config(sc); 8681 if (error != 0) 8682 device_printf(sc->sc_dev, 8683 "%s: error %d settting channel\n", __func__, error); 8684 } 8685 } 8686 8687 /* 8688 * Callback from net80211 to start scanning of the current channel. 8689 */ 8690 static void 8691 iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell) 8692 { 8693 struct ieee80211vap *vap = ss->ss_vap; 8694 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc; 8695 struct ieee80211com *ic = vap->iv_ic; 8696 int error; 8697 8698 error = iwn_scan(sc, vap, ss, ic->ic_curchan); 8699 if (error != 0) 8700 ieee80211_cancel_scan(vap); 8701 } 8702 8703 /* 8704 * Callback from net80211 to handle the minimum dwell time being met. 8705 * The intent is to terminate the scan but we just let the firmware 8706 * notify us when it's finished as we have no safe way to abort it. 8707 */ 8708 static void 8709 iwn_scan_mindwell(struct ieee80211_scan_state *ss) 8710 { 8711 /* NB: don't try to abort scan; wait for firmware to finish */ 8712 } 8713 8714 static void 8715 iwn_hw_reset_task(void *arg0, int pending) 8716 { 8717 struct iwn_softc *sc = arg0; 8718 struct ifnet *ifp; 8719 struct ieee80211com *ic; 8720 8721 DPRINTF(sc, IWN_DEBUG_TRACE, "->Doing %s\n", __func__); 8722 8723 wlan_serialize_enter(); 8724 ifp = sc->sc_ifp; 8725 ic = ifp->if_l2com; 8726 iwn_stop_locked(sc); 8727 iwn_init_locked(sc); 8728 ieee80211_notify_radio(ic, 1); 8729 wlan_serialize_exit(); 8730 } 8731 #ifdef IWN_DEBUG 8732 #define IWN_DESC(x) case x: return #x 8733 #define COUNTOF(array) (sizeof(array) / sizeof(array[0])) 8734 8735 /* 8736 * Translate CSR code to string 8737 */ 8738 static char *iwn_get_csr_string(int csr) 8739 { 8740 switch (csr) { 8741 IWN_DESC(IWN_HW_IF_CONFIG); 8742 IWN_DESC(IWN_INT_COALESCING); 8743 IWN_DESC(IWN_INT); 8744 IWN_DESC(IWN_INT_MASK); 8745 IWN_DESC(IWN_FH_INT); 8746 IWN_DESC(IWN_GPIO_IN); 8747 IWN_DESC(IWN_RESET); 8748 IWN_DESC(IWN_GP_CNTRL); 8749 IWN_DESC(IWN_HW_REV); 8750 IWN_DESC(IWN_EEPROM); 8751 IWN_DESC(IWN_EEPROM_GP); 8752 IWN_DESC(IWN_OTP_GP); 8753 IWN_DESC(IWN_GIO); 8754 IWN_DESC(IWN_GP_UCODE); 8755 IWN_DESC(IWN_GP_DRIVER); 8756 IWN_DESC(IWN_UCODE_GP1); 8757 IWN_DESC(IWN_UCODE_GP2); 8758 IWN_DESC(IWN_LED); 8759 IWN_DESC(IWN_DRAM_INT_TBL); 8760 IWN_DESC(IWN_GIO_CHICKEN); 8761 IWN_DESC(IWN_ANA_PLL); 8762 IWN_DESC(IWN_HW_REV_WA); 8763 IWN_DESC(IWN_DBG_HPET_MEM); 8764 default: 8765 return "UNKNOWN CSR"; 8766 } 8767 } 8768 8769 /* 8770 * This function print firmware register 8771 */ 8772 static void 8773 iwn_debug_register(struct iwn_softc *sc) 8774 { 8775 int i; 8776 static const uint32_t csr_tbl[] = { 8777 IWN_HW_IF_CONFIG, 8778 IWN_INT_COALESCING, 8779 IWN_INT, 8780 IWN_INT_MASK, 8781 IWN_FH_INT, 8782 IWN_GPIO_IN, 8783 IWN_RESET, 8784 IWN_GP_CNTRL, 8785 IWN_HW_REV, 8786 IWN_EEPROM, 8787 IWN_EEPROM_GP, 8788 IWN_OTP_GP, 8789 IWN_GIO, 8790 IWN_GP_UCODE, 8791 IWN_GP_DRIVER, 8792 IWN_UCODE_GP1, 8793 IWN_UCODE_GP2, 8794 IWN_LED, 8795 IWN_DRAM_INT_TBL, 8796 IWN_GIO_CHICKEN, 8797 IWN_ANA_PLL, 8798 IWN_HW_REV_WA, 8799 IWN_DBG_HPET_MEM, 8800 }; 8801 DPRINTF(sc, IWN_DEBUG_REGISTER, 8802 "CSR values: (2nd byte of IWN_INT_COALESCING is IWN_INT_PERIODIC)%s", 8803 "\n"); 8804 for (i = 0; i < COUNTOF(csr_tbl); i++){ 8805 DPRINTF(sc, IWN_DEBUG_REGISTER," %10s: 0x%08x ", 8806 iwn_get_csr_string(csr_tbl[i]), IWN_READ(sc, csr_tbl[i])); 8807 if ((i+1) % 3 == 0) 8808 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 8809 } 8810 DPRINTF(sc, IWN_DEBUG_REGISTER,"%s","\n"); 8811 } 8812 #endif 8813