1 /* 2 * Copyright (c) 2001-2013, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_IX_H_ 33 #define _IF_IX_H_ 34 35 /* Tunables */ 36 37 /* 38 * MSI-X count 39 */ 40 #define IX_MAX_MSIX 64 41 #define IX_MAX_MSIX_82598 16 42 43 /* 44 * RX ring count 45 */ 46 #define IX_MAX_RXRING 16 47 #define IX_MIN_RXRING_RSS 2 48 49 /* 50 * TX ring count 51 */ 52 #define IX_MAX_TXRING_82598 32 53 #define IX_MAX_TXRING_82599 64 54 #define IX_MAX_TXRING_X540 64 55 56 /* 57 * Default number of segments received before writing to RX related registers 58 */ 59 #define IX_DEF_RXWREG_NSEGS 32 60 61 /* 62 * Default number of segments sent before writing to TX related registers 63 */ 64 #define IX_DEF_TXWREG_NSEGS 8 65 66 /* 67 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 68 * number of transmit descriptors allocated by the driver. Increasing this 69 * value allows the driver to queue more transmits. Each descriptor is 16 70 * bytes. Performance tests have show the 2K value to be optimal for top 71 * performance. 72 */ 73 #define IX_DEF_TXD 1024 74 #define IX_PERF_TXD 2048 75 #define IX_MAX_TXD 4096 76 #define IX_MIN_TXD 64 77 78 /* 79 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 80 * number of receive descriptors allocated for each RX queue. Increasing this 81 * value allows the driver to buffer more incoming packets. Each descriptor 82 * is 16 bytes. A receive buffer is also allocated for each descriptor. 83 * 84 * Note: with 8 rings and a dual port card, it is possible to bump up 85 * against the system mbuf pool limit, you can tune nmbclusters 86 * to adjust for this. 87 */ 88 #define IX_DEF_RXD 1024 89 #define IX_PERF_RXD 2048 90 #define IX_MAX_RXD 4096 91 #define IX_MIN_RXD 64 92 93 /* Alignment for rings */ 94 #define IX_DBA_ALIGN 128 95 96 #define IX_MAX_FRAME_SIZE 0x3F00 97 98 /* Flow control constants */ 99 #define IX_FC_PAUSE 0xFFFF 100 #define IX_FC_HI 0x20000 101 #define IX_FC_LO 0x10000 102 103 /* 104 * RSS related registers 105 */ 106 #define IX_NRSSRK 10 107 #define IX_RSSRK_SIZE 4 108 #define IX_RSSRK_VAL(key, i) (key[(i) * IX_RSSRK_SIZE] | \ 109 key[(i) * IX_RSSRK_SIZE + 1] << 8 | \ 110 key[(i) * IX_RSSRK_SIZE + 2] << 16 | \ 111 key[(i) * IX_RSSRK_SIZE + 3] << 24) 112 #define IX_NRETA 32 113 #define IX_RETA_SIZE 4 114 115 /* 116 * EITR 117 */ 118 #define IX_EITR_INTVL_MASK_82598 0xffff 119 #define IX_EITR_INTVL_MASK 0x0fff 120 #define IX_EITR_INTVL_RSVD_MASK 0x0007 121 #define IX_EITR_INTVL_MIN IXGBE_MIN_EITR 122 #define IX_EITR_INTVL_MAX IXGBE_MAX_EITR 123 124 /* 125 * Used for optimizing small rx mbufs. Effort is made to keep the copy 126 * small and aligned for the CPU L1 cache. 127 * 128 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 129 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 130 * wasted. Getting 64 byte alignment, which _should_ be ideal for 131 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 132 * in observed efficiency of the optimization, 97.9% -> 81.8%. 133 */ 134 #define IX_RX_COPY_LEN 160 135 #define IX_RX_COPY_ALIGN (MHLEN - IX_RX_COPY_LEN) 136 137 #define IX_MAX_MCASTADDR 128 138 139 #define IX_MSIX_BAR_82598 3 140 #define IX_MSIX_BAR_82599 4 141 142 #define IX_TSO_SIZE (IP_MAXPACKET + \ 143 sizeof(struct ether_vlan_header)) 144 145 /* 146 * MUST be less than 38. Though 82598 does not have this limit, 147 * we don't want long TX chain. 33 should be large enough even 148 * for 64K TSO (32 x 2K mbuf cluster and 1 x mbuf header). 149 * 150 * Reference: 151 * - 82599 datasheet 7.2.1.1 152 * - X540 datasheet 7.2.1.1 153 */ 154 #define IX_MAX_SCATTER 33 155 #define IX_TX_RESERVED 3 /* 1 for TX ctx, 2 reserved */ 156 157 /* MSI and legacy interrupt */ 158 #define IX_TX_INTR_VEC 0 159 #define IX_TX_INTR_MASK (1 << IX_TX_INTR_VEC) 160 #define IX_RX0_INTR_VEC 1 161 #define IX_RX0_INTR_MASK (1 << IX_RX0_INTR_VEC) 162 #define IX_RX1_INTR_VEC 2 163 #define IX_RX1_INTR_MASK (1 << IX_RX1_INTR_VEC) 164 165 #define IX_INTR_RATE 8000 166 #define IX_MSIX_RX_RATE 8000 167 #define IX_MSIX_TX_RATE 6000 168 169 /* IOCTL define to gather SFP+ Diagnostic data */ 170 #define SIOCGI2C SIOCGIFGENERIC 171 172 /* TX checksum offload */ 173 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 174 175 #define IX_EICR_STATUS (IXGBE_EICR_LSC | IXGBE_EICR_ECC | \ 176 IXGBE_EICR_GPI_SDP1 | IXGBE_EICR_GPI_SDP2 | \ 177 IXGBE_EICR_TS) 178 179 /* This is used to get SFP+ module data */ 180 struct ix_i2c_req { 181 uint8_t dev_addr; 182 uint8_t offset; 183 uint8_t len; 184 uint8_t data[8]; 185 }; 186 187 struct ix_tx_buf { 188 struct mbuf *m_head; 189 bus_dmamap_t map; 190 }; 191 192 struct ix_rx_buf { 193 struct mbuf *m_head; 194 struct mbuf *fmp; 195 struct mbuf *lmp; 196 bus_dmamap_t map; 197 bus_addr_t paddr; 198 u_int flags; 199 #define IX_RX_COPY 0x1 200 }; 201 202 struct ix_softc; 203 204 struct ix_tx_ring { 205 struct lwkt_serialize tx_serialize; 206 struct ifaltq_subque *tx_ifsq; 207 struct ix_softc *tx_sc; 208 volatile uint32_t *tx_hdr; 209 union ixgbe_adv_tx_desc *tx_base; 210 struct ix_tx_buf *tx_buf; 211 bus_dma_tag_t tx_tag; 212 uint16_t tx_flags; 213 #define IX_TXFLAG_ENABLED 0x1 214 uint16_t tx_pad; 215 uint32_t tx_idx; 216 uint16_t tx_avail; 217 uint16_t tx_next_avail; 218 uint16_t tx_next_clean; 219 uint16_t tx_ndesc; 220 uint16_t tx_wreg_nsegs; 221 uint16_t tx_intr_nsegs; 222 uint16_t tx_nsegs; 223 int16_t tx_intr_vec; 224 int tx_intr_cpuid; 225 uint32_t tx_eims; 226 uint32_t tx_eims_val; 227 struct ifsubq_watchdog tx_watchdog; 228 229 bus_dma_tag_t tx_base_dtag; 230 bus_dmamap_t tx_base_map; 231 bus_addr_t tx_base_paddr; 232 233 bus_dma_tag_t tx_hdr_dtag; 234 bus_dmamap_t tx_hdr_map; 235 bus_addr_t tx_hdr_paddr; 236 } __cachealign; 237 238 struct ix_rx_ring { 239 struct lwkt_serialize rx_serialize; 240 struct ix_softc *rx_sc; 241 union ixgbe_adv_rx_desc *rx_base; 242 struct ix_rx_buf *rx_buf; 243 bus_dma_tag_t rx_tag; 244 bus_dmamap_t rx_sparemap; 245 uint32_t rx_idx; 246 uint16_t rx_flags; 247 #define IX_RXRING_FLAG_LRO 0x01 248 #define IX_RXRING_FLAG_DISC 0x02 249 uint16_t rx_next_check; 250 uint16_t rx_ndesc; 251 uint16_t rx_mbuf_sz; 252 uint16_t rx_wreg_nsegs; 253 int16_t rx_intr_vec; 254 uint32_t rx_eims; 255 uint32_t rx_eims_val; 256 struct ix_tx_ring *rx_txr; /* piggybacked TX ring */ 257 258 #ifdef IX_RSS_DEBUG 259 u_long rx_pkts; 260 #endif 261 262 bus_dma_tag_t rx_base_dtag; 263 bus_dmamap_t rx_base_map; 264 bus_addr_t rx_base_paddr; 265 } __cachealign; 266 267 struct ix_intr_data { 268 struct lwkt_serialize *intr_serialize; 269 driver_intr_t *intr_func; 270 void *intr_hand; 271 struct resource *intr_res; 272 void *intr_funcarg; 273 int intr_rid; 274 int intr_cpuid; 275 int intr_rate; 276 int intr_use; 277 #define IX_INTR_USE_RXTX 0 278 #define IX_INTR_USE_STATUS 1 279 #define IX_INTR_USE_RX 2 280 #define IX_INTR_USE_TX 3 281 const char *intr_desc; 282 char intr_desc0[64]; 283 }; 284 285 struct ix_softc { 286 struct arpcom arpcom; 287 288 struct ixgbe_hw hw; 289 struct ixgbe_osdep osdep; 290 291 struct lwkt_serialize main_serialize; 292 uint32_t intr_mask; 293 294 boolean_t link_active; 295 296 int rx_ring_inuse; 297 int tx_ring_inuse; 298 299 struct ix_rx_ring *rx_rings; 300 struct ix_tx_ring *tx_rings; 301 302 struct callout timer; 303 int timer_cpuid; 304 305 uint32_t optics; 306 uint32_t fc; /* local flow ctrl setting */ 307 uint32_t link_speed; 308 bool link_up; 309 boolean_t sfp_probe; /* plyggable optics */ 310 311 struct ixgbe_hw_stats stats; 312 313 int rx_ring_cnt; 314 int rx_ring_msix; 315 316 int tx_ring_cnt; 317 int tx_ring_msix; 318 319 int intr_type; 320 int intr_cnt; 321 struct ix_intr_data *intr_data; 322 323 device_t dev; 324 bus_dma_tag_t parent_tag; 325 struct ifmedia media; 326 327 struct resource *mem_res; 328 int mem_rid; 329 330 struct resource *msix_mem_res; 331 int msix_mem_rid; 332 333 int nserialize; 334 struct lwkt_serialize **serializes; 335 336 uint8_t *mta; /* Multicast array memory */ 337 338 int if_flags; 339 int advspeed; /* advertised link speeds */ 340 uint16_t max_frame_size; 341 int16_t sts_msix_vec; /* status MSI-X vector */ 342 343 int rx_npoll_off; 344 int tx_npoll_off; 345 346 #ifdef IX_RSS_DEBUG 347 int rss_debug; 348 #endif 349 }; 350 351 #define IX_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1) 352 #define IX_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1) 353 354 #endif /* _IF_IX_H_ */ 355