1 /* 2 * Copyright (c) 2001-2013, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_IX_H_ 33 #define _IF_IX_H_ 34 35 /* Tunables */ 36 37 /* 38 * RX ring count 39 */ 40 #define IX_MAX_RXRING 16 41 #define IX_MIN_RXRING_RSS 2 42 43 /* 44 * Default number of segments received before writing to RX related registers 45 */ 46 #define IX_DEF_RXWREG_NSEGS 32 47 48 /* 49 * Default number of segments sent before writing to TX related registers 50 */ 51 #define IX_DEF_TXWREG_NSEGS 8 52 53 /* 54 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 55 * number of transmit descriptors allocated by the driver. Increasing this 56 * value allows the driver to queue more transmits. Each descriptor is 16 57 * bytes. Performance tests have show the 2K value to be optimal for top 58 * performance. 59 */ 60 #define IX_DEF_TXD 1024 61 #define IX_PERF_TXD 2048 62 #define IX_MAX_TXD 4096 63 #define IX_MIN_TXD 64 64 65 /* 66 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 67 * number of receive descriptors allocated for each RX queue. Increasing this 68 * value allows the driver to buffer more incoming packets. Each descriptor 69 * is 16 bytes. A receive buffer is also allocated for each descriptor. 70 * 71 * Note: with 8 rings and a dual port card, it is possible to bump up 72 * against the system mbuf pool limit, you can tune nmbclusters 73 * to adjust for this. 74 */ 75 #define IX_DEF_RXD 1024 76 #define IX_PERF_RXD 2048 77 #define IX_MAX_RXD 4096 78 #define IX_MIN_RXD 64 79 80 /* Alignment for rings */ 81 #define IX_DBA_ALIGN 128 82 83 #define IX_MAX_FRAME_SIZE 0x3F00 84 85 /* Flow control constants */ 86 #define IX_FC_PAUSE 0xFFFF 87 #define IX_FC_HI 0x20000 88 #define IX_FC_LO 0x10000 89 90 /* 91 * RSS related registers 92 */ 93 #define IX_NRSSRK 10 94 #define IX_RSSRK_SIZE 4 95 #define IX_RSSRK_VAL(key, i) (key[(i) * IX_RSSRK_SIZE] | \ 96 key[(i) * IX_RSSRK_SIZE + 1] << 8 | \ 97 key[(i) * IX_RSSRK_SIZE + 2] << 16 | \ 98 key[(i) * IX_RSSRK_SIZE + 3] << 24) 99 #define IX_NRETA 32 100 #define IX_RETA_SIZE 4 101 102 /* 103 * EITR 104 */ 105 #define IX_EITR_INTVL_MASK_82598 0xffff 106 #define IX_EITR_INTVL_MASK 0x0fff 107 #define IX_EITR_INTVL_RSVD_MASK 0x0007 108 #define IX_EITR_INTVL_MIN IXGBE_MIN_EITR 109 #define IX_EITR_INTVL_MAX IXGBE_MAX_EITR 110 111 /* 112 * Used for optimizing small rx mbufs. Effort is made to keep the copy 113 * small and aligned for the CPU L1 cache. 114 * 115 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 116 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 117 * wasted. Getting 64 byte alignment, which _should_ be ideal for 118 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 119 * in observed efficiency of the optimization, 97.9% -> 81.8%. 120 */ 121 #define IX_RX_COPY_LEN 160 122 #define IX_RX_COPY_ALIGN (MHLEN - IX_RX_COPY_LEN) 123 124 #define IX_MAX_MCASTADDR 128 125 126 #define MSIX_82598_BAR 3 127 #define MSIX_82599_BAR 4 128 129 #define IX_TSO_SIZE (IP_MAXPACKET + \ 130 sizeof(struct ether_vlan_header)) 131 132 /* 133 * MUST be less than 38. Though 82598 does not have this limit, 134 * we don't want long TX chain. 33 should be large enough even 135 * for 64K TSO (32 x 2K mbuf cluster and 1 x mbuf header). 136 * 137 * Reference: 138 * - 82599 datasheet 7.2.1.1 139 * - X540 datasheet 7.2.1.1 140 */ 141 #define IX_MAX_SCATTER 33 142 #define IX_TX_RESERVED 3 /* 1 for TX ctx, 2 reserved */ 143 144 /* MSI and legacy interrupt */ 145 #define IX_TX_INTR_VEC 0 146 #define IX_TX_INTR_MASK (1 << IX_TX_INTR_VEC) 147 #define IX_RX0_INTR_VEC 1 148 #define IX_RX0_INTR_MASK (1 << IX_RX0_INTR_VEC) 149 #define IX_RX1_INTR_VEC 2 150 #define IX_RX1_INTR_MASK (1 << IX_RX1_INTR_VEC) 151 152 #define IX_INTR_RATE 8000 153 154 /* IOCTL define to gather SFP+ Diagnostic data */ 155 #define SIOCGI2C SIOCGIFGENERIC 156 157 /* TX checksum offload */ 158 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 159 160 /* This is used to get SFP+ module data */ 161 struct ix_i2c_req { 162 uint8_t dev_addr; 163 uint8_t offset; 164 uint8_t len; 165 uint8_t data[8]; 166 }; 167 168 struct ix_tx_buf { 169 struct mbuf *m_head; 170 bus_dmamap_t map; 171 }; 172 173 struct ix_rx_buf { 174 struct mbuf *m_head; 175 struct mbuf *fmp; 176 struct mbuf *lmp; 177 bus_dmamap_t map; 178 bus_addr_t paddr; 179 u_int flags; 180 #define IX_RX_COPY 0x1 181 }; 182 183 struct ix_softc; 184 185 struct ix_tx_ring { 186 struct lwkt_serialize tx_serialize; 187 struct ifaltq_subque *tx_ifsq; 188 struct ix_softc *tx_sc; 189 volatile uint32_t *tx_hdr; 190 union ixgbe_adv_tx_desc *tx_base; 191 struct ix_tx_buf *tx_buf; 192 bus_dma_tag_t tx_tag; 193 uint32_t tx_idx; 194 uint16_t tx_avail; 195 uint16_t tx_next_avail; 196 uint16_t tx_next_clean; 197 uint16_t tx_ndesc; 198 uint16_t tx_wreg_nsegs; 199 uint16_t tx_intr_nsegs; 200 uint16_t tx_nsegs; 201 int16_t tx_intr_vec; 202 int tx_intr_cpuid; 203 struct ifsubq_watchdog tx_watchdog; 204 205 bus_dma_tag_t tx_base_dtag; 206 bus_dmamap_t tx_base_map; 207 bus_addr_t tx_base_paddr; 208 209 bus_dma_tag_t tx_hdr_dtag; 210 bus_dmamap_t tx_hdr_map; 211 bus_addr_t tx_hdr_paddr; 212 } __cachealign; 213 214 struct ix_rx_ring { 215 struct lwkt_serialize rx_serialize; 216 struct ix_softc *rx_sc; 217 union ixgbe_adv_rx_desc *rx_base; 218 struct ix_rx_buf *rx_buf; 219 bus_dma_tag_t rx_tag; 220 bus_dmamap_t rx_sparemap; 221 uint32_t rx_idx; 222 uint16_t rx_flags; 223 #define IX_RXRING_FLAG_LRO 0x01 224 #define IX_RXRING_FLAG_DISC 0x02 225 uint16_t rx_next_check; 226 uint16_t rx_ndesc; 227 uint16_t rx_mbuf_sz; 228 uint16_t rx_wreg_nsegs; 229 int16_t rx_intr_vec; 230 231 #ifdef IX_RSS_DEBUG 232 u_long rx_pkts; 233 #endif 234 235 bus_dma_tag_t rx_base_dtag; 236 bus_dmamap_t rx_base_map; 237 bus_addr_t rx_base_paddr; 238 } __cachealign; 239 240 struct ix_intr_data { 241 struct lwkt_serialize *intr_serialize; 242 driver_intr_t *intr_func; 243 void *intr_hand; 244 struct resource *intr_res; 245 void *intr_funcarg; 246 int intr_rid; 247 int intr_cpuid; 248 int intr_rate; 249 int intr_use; 250 #define IX_INTR_USE_RXTX 0 251 #define IX_INTR_USE_STATUS 1 252 #define IX_INTR_USE_RX 2 253 #define IX_INTR_USE_TX 3 254 const char *intr_desc; 255 char intr_desc0[64]; 256 }; 257 258 struct ix_softc { 259 struct arpcom arpcom; 260 261 struct ixgbe_hw hw; 262 struct ixgbe_osdep osdep; 263 264 struct lwkt_serialize main_serialize; 265 uint32_t intr_mask; 266 267 boolean_t link_active; 268 269 int tx_ring_cnt; 270 int tx_ring_inuse; 271 struct ix_tx_ring *tx_rings; 272 273 int rx_ring_cnt; 274 int rx_ring_inuse; 275 struct ix_rx_ring *rx_rings; 276 277 struct callout timer; 278 int timer_cpuid; 279 280 uint32_t optics; 281 uint32_t fc; /* local flow ctrl setting */ 282 uint32_t link_speed; 283 bool link_up; 284 boolean_t sfp_probe; /* plyggable optics */ 285 286 struct ixgbe_hw_stats stats; 287 288 int intr_type; 289 int intr_cnt; 290 struct ix_intr_data *intr_data; 291 292 /* sysctl tree glue */ 293 struct sysctl_ctx_list sysctl_ctx; 294 struct sysctl_oid *sysctl_tree; 295 296 device_t dev; 297 bus_dma_tag_t parent_tag; 298 struct ifmedia media; 299 300 struct resource *mem_res; 301 int mem_rid; 302 303 int nserialize; 304 struct lwkt_serialize **serializes; 305 306 uint8_t *mta; /* Multicast array memory */ 307 308 int if_flags; 309 int advspeed; /* advertised link speeds */ 310 uint16_t max_frame_size; 311 312 #ifdef IX_RSS_DEBUG 313 int rss_debug; 314 #endif 315 }; 316 317 #define IX_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1) 318 #define IX_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1) 319 320 #endif /* _IF_IX_H_ */ 321