1 /* 2 * Copyright (c) 2001-2013, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _IF_IX_H_ 33 #define _IF_IX_H_ 34 35 /* Tunables */ 36 37 /* 38 * MSI-X count 39 */ 40 #define IX_MAX_MSIX 64 41 #define IX_MAX_MSIX_82598 16 42 43 /* 44 * RX ring count 45 */ 46 #define IX_MAX_RXRING 16 47 #define IX_MAX_RXRING_X550 64 48 #define IX_MIN_RXRING_RSS 2 49 50 /* 51 * TX ring count 52 */ 53 #define IX_MAX_TXRING 16 54 #define IX_MAX_TXRING_82598 32 55 #define IX_MAX_TXRING_82599 64 56 #define IX_MAX_TXRING_X540 64 57 #define IX_MAX_TXRING_X550 64 58 59 /* 60 * Default number of segments received before writing to RX related registers 61 */ 62 #define IX_DEF_RXWREG_NSEGS 32 63 64 /* 65 * Default number of segments sent before writing to TX related registers 66 */ 67 #define IX_DEF_TXWREG_NSEGS 8 68 69 /* 70 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 71 * number of transmit descriptors allocated by the driver. Increasing this 72 * value allows the driver to queue more transmits. Each descriptor is 16 73 * bytes. Performance tests have show the 2K value to be optimal for top 74 * performance. 75 */ 76 #define IX_DEF_TXD 1024 77 #define IX_PERF_TXD 2048 78 #define IX_MAX_TXD 4096 79 #define IX_MIN_TXD 64 80 81 /* 82 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 83 * number of receive descriptors allocated for each RX queue. Increasing this 84 * value allows the driver to buffer more incoming packets. Each descriptor 85 * is 16 bytes. A receive buffer is also allocated for each descriptor. 86 * 87 * Note: with 8 rings and a dual port card, it is possible to bump up 88 * against the system mbuf pool limit, you can tune nmbclusters 89 * to adjust for this. 90 */ 91 #define IX_DEF_RXD 1024 92 #define IX_PERF_RXD 2048 93 #define IX_MAX_RXD 4096 94 #define IX_MIN_RXD 64 95 96 /* Alignment for rings */ 97 #define IX_DBA_ALIGN 128 98 99 #define IX_MAX_FRAME_SIZE 9728 100 #define IX_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN) 101 #define IX_MAX_MTU (IX_MAX_FRAME_SIZE - IX_MTU_HDR) 102 103 104 /* Flow control constants */ 105 #define IX_FC_PAUSE 0xFFFF 106 #define IX_FC_HI 0x20000 107 #define IX_FC_LO 0x10000 108 109 /* 110 * RSS related registers 111 */ 112 #define IX_NRSSRK 10 113 #define IX_RSSRK_SIZE 4 114 #define IX_RSSRK_VAL(key, i) (key[(i) * IX_RSSRK_SIZE] | \ 115 key[(i) * IX_RSSRK_SIZE + 1] << 8 | \ 116 key[(i) * IX_RSSRK_SIZE + 2] << 16 | \ 117 key[(i) * IX_RSSRK_SIZE + 3] << 24) 118 #define IX_NRETA 32 119 #define IX_NRETA_X550 128 120 #define IX_NRETA_MAX 128 121 #define IX_RETA_SIZE 4 122 123 #define IX_RDRTABLE_SIZE (IX_NRETA_MAX * IX_RETA_SIZE) 124 125 /* 126 * EITR 127 */ 128 #define IX_EITR_INTVL_MASK_82598 0xffff 129 #define IX_EITR_INTVL_MASK 0x0fff 130 #define IX_EITR_INTVL_RSVD_MASK 0x0007 131 #define IX_EITR_INTVL_MIN IXGBE_MIN_EITR 132 #define IX_EITR_INTVL_MAX IXGBE_MAX_EITR 133 134 /* 135 * Used for optimizing small rx mbufs. Effort is made to keep the copy 136 * small and aligned for the CPU L1 cache. 137 * 138 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 139 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 140 * wasted. Getting 64 byte alignment, which _should_ be ideal for 141 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 142 * in observed efficiency of the optimization, 97.9% -> 81.8%. 143 */ 144 #define IX_RX_COPY_LEN 160 145 #define IX_RX_COPY_ALIGN (MHLEN - IX_RX_COPY_LEN) 146 147 #define IX_MAX_MCASTADDR 128 148 149 #define IX_MSIX_BAR_82598 3 150 #define IX_MSIX_BAR_82599 4 151 152 #define IX_TSO_SIZE (IP_MAXPACKET + \ 153 sizeof(struct ether_vlan_header)) 154 155 /* 156 * MUST be less than 38. Though 82598 does not have this limit, 157 * we don't want long TX chain. 33 should be large enough even 158 * for 64K TSO (32 x 2K mbuf cluster and 1 x mbuf header). 159 * 160 * Reference: 161 * - 82599 datasheet 7.2.1.1 162 * - X540 datasheet 7.2.1.1 163 */ 164 #define IX_MAX_SCATTER 33 165 #define IX_TX_RESERVED 3 /* 1 for TX ctx, 2 reserved */ 166 167 /* MSI and legacy interrupt */ 168 #define IX_TX_INTR_VEC 0 169 #define IX_TX_INTR_MASK (1 << IX_TX_INTR_VEC) 170 #define IX_RX0_INTR_VEC 1 171 #define IX_RX0_INTR_MASK (1 << IX_RX0_INTR_VEC) 172 #define IX_RX1_INTR_VEC 2 173 #define IX_RX1_INTR_MASK (1 << IX_RX1_INTR_VEC) 174 175 #define IX_INTR_RATE 8000 176 #define IX_MSIX_RX_RATE 8000 177 #define IX_MSIX_TX_RATE 6000 178 179 /* IOCTL define to gather SFP+ Diagnostic data */ 180 #define SIOCGI2C SIOCGIFGENERIC 181 182 /* TX checksum offload */ 183 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 184 185 #define IX_EICR_STATUS (IXGBE_EICR_LSC | IXGBE_EICR_ECC | \ 186 IXGBE_EICR_GPI_SDP1 | IXGBE_EICR_GPI_SDP2 | \ 187 IXGBE_EICR_TS) 188 189 /* This is used to get SFP+ module data */ 190 struct ix_i2c_req { 191 uint8_t dev_addr; 192 uint8_t offset; 193 uint8_t len; 194 uint8_t data[8]; 195 }; 196 197 struct ix_tx_buf { 198 struct mbuf *m_head; 199 bus_dmamap_t map; 200 }; 201 202 struct ix_rx_buf { 203 struct mbuf *m_head; 204 struct mbuf *fmp; 205 struct mbuf *lmp; 206 bus_dmamap_t map; 207 bus_addr_t paddr; 208 u_int flags; 209 #define IX_RX_COPY 0x1 210 }; 211 212 struct ix_softc; 213 214 struct ix_tx_ring { 215 struct lwkt_serialize tx_serialize; 216 struct ifaltq_subque *tx_ifsq; 217 struct ix_softc *tx_sc; 218 volatile uint32_t *tx_hdr; 219 union ixgbe_adv_tx_desc *tx_base; 220 struct ix_tx_buf *tx_buf; 221 bus_dma_tag_t tx_tag; 222 uint16_t tx_flags; 223 #define IX_TXFLAG_ENABLED 0x1 224 uint16_t tx_pad; 225 uint32_t tx_idx; 226 uint16_t tx_avail; 227 uint16_t tx_next_avail; 228 uint16_t tx_next_clean; 229 uint16_t tx_ndesc; 230 uint16_t tx_wreg_nsegs; 231 uint16_t tx_intr_nsegs; 232 uint16_t tx_nsegs; 233 int16_t tx_intr_vec; 234 int tx_intr_cpuid; 235 uint32_t tx_eims; 236 uint32_t tx_eims_val; 237 struct ifsubq_watchdog tx_watchdog; 238 239 bus_dma_tag_t tx_base_dtag; 240 bus_dmamap_t tx_base_map; 241 bus_addr_t tx_base_paddr; 242 243 bus_dma_tag_t tx_hdr_dtag; 244 bus_dmamap_t tx_hdr_map; 245 bus_addr_t tx_hdr_paddr; 246 } __cachealign; 247 248 struct ix_rx_ring { 249 struct lwkt_serialize rx_serialize; 250 struct ix_softc *rx_sc; 251 union ixgbe_adv_rx_desc *rx_base; 252 struct ix_rx_buf *rx_buf; 253 bus_dma_tag_t rx_tag; 254 bus_dmamap_t rx_sparemap; 255 uint32_t rx_idx; 256 uint16_t rx_flags; 257 #define IX_RXRING_FLAG_LRO 0x01 258 #define IX_RXRING_FLAG_DISC 0x02 259 uint16_t rx_next_check; 260 uint16_t rx_ndesc; 261 uint16_t rx_mbuf_sz; 262 uint16_t rx_wreg_nsegs; 263 int16_t rx_intr_vec; 264 uint32_t rx_eims; 265 uint32_t rx_eims_val; 266 struct ix_tx_ring *rx_txr; /* piggybacked TX ring */ 267 268 #ifdef IX_RSS_DEBUG 269 u_long rx_pkts; 270 #endif 271 272 bus_dma_tag_t rx_base_dtag; 273 bus_dmamap_t rx_base_map; 274 bus_addr_t rx_base_paddr; 275 } __cachealign; 276 277 struct ix_intr_data { 278 struct lwkt_serialize *intr_serialize; 279 driver_intr_t *intr_func; 280 void *intr_hand; 281 struct resource *intr_res; 282 void *intr_funcarg; 283 int intr_rid; 284 int intr_cpuid; 285 int intr_rate; 286 int intr_use; 287 #define IX_INTR_USE_RXTX 0 288 #define IX_INTR_USE_STATUS 1 289 #define IX_INTR_USE_RX 2 290 #define IX_INTR_USE_TX 3 291 const char *intr_desc; 292 char intr_desc0[64]; 293 }; 294 295 struct ix_softc { 296 struct arpcom arpcom; 297 298 struct ixgbe_hw hw; 299 struct ixgbe_osdep osdep; 300 301 struct lwkt_serialize main_serialize; 302 uint32_t intr_mask; 303 304 boolean_t link_active; 305 306 int rx_ring_inuse; 307 int tx_ring_inuse; 308 309 struct ix_rx_ring *rx_rings; 310 struct ix_tx_ring *tx_rings; 311 312 struct callout timer; 313 int timer_cpuid; 314 315 int ifm_media; /* IFM_ */ 316 uint32_t link_speed; 317 bool link_up; 318 boolean_t sfp_probe; /* plyggable optics */ 319 320 struct ixgbe_hw_stats stats; 321 322 int rx_ring_cnt; 323 int rx_ring_msix; 324 325 int tx_ring_cnt; 326 int tx_ring_msix; 327 328 int intr_type; 329 int intr_cnt; 330 struct ix_intr_data *intr_data; 331 332 device_t dev; 333 bus_dma_tag_t parent_tag; 334 struct ifmedia media; 335 336 struct resource *mem_res; 337 int mem_rid; 338 339 struct resource *msix_mem_res; 340 int msix_mem_rid; 341 342 int nserialize; 343 struct lwkt_serialize **serializes; 344 345 uint8_t *mta; /* Multicast array memory */ 346 347 int if_flags; 348 int advspeed; /* advertised link speeds */ 349 uint32_t wufc; /* power management */ 350 uint16_t dmac; /* DMA coalescing */ 351 uint16_t max_frame_size; 352 int16_t sts_msix_vec; /* status MSI-X vector */ 353 354 struct if_ringmap *tx_rmap; 355 struct if_ringmap *tx_rmap_intr; 356 struct if_ringmap *rx_rmap; 357 struct if_ringmap *rx_rmap_intr; 358 359 int rdr_table[IX_RDRTABLE_SIZE]; 360 361 #ifdef IX_RSS_DEBUG 362 int rss_debug; 363 #endif 364 }; 365 366 #define IX_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1) 367 #define IX_ENABLE_HWTSS(sc) ((sc)->tx_ring_cnt > 1) 368 369 #endif /* _IF_IX_H_ */ 370