1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 #define IXGBE_EMPTY_PARAM 39 40 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 41 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 42 }; 43 44 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 45 IXGBE_MVALS_INIT(_X540) 46 }; 47 48 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 49 IXGBE_MVALS_INIT(_X550) 50 }; 51 52 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 53 IXGBE_MVALS_INIT(_X550EM_x) 54 }; 55 56 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 57 IXGBE_MVALS_INIT(_X550EM_a) 58 }; 59 60 /** 61 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 62 * @hw: pointer to hardware structure 63 * @map: pointer to u8 arr for returning map 64 * 65 * Read the rtrup2tc HW register and resolve its content into map 66 **/ 67 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 68 { 69 if (hw->mac.ops.get_rtrup2tc) 70 hw->mac.ops.get_rtrup2tc(hw, map); 71 } 72 73 /** 74 * ixgbe_init_shared_code - Initialize the shared code 75 * @hw: pointer to hardware structure 76 * 77 * This will assign function pointers and assign the MAC type and PHY code. 78 * Does not touch the hardware. This function must be called prior to any 79 * other function in the shared code. The ixgbe_hw structure should be 80 * memset to 0 prior to calling this function. The following fields in 81 * hw structure should be filled in prior to calling this function: 82 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 83 * subsystem_vendor_id, and revision_id 84 **/ 85 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 86 { 87 s32 status; 88 89 DEBUGFUNC("ixgbe_init_shared_code"); 90 91 /* 92 * Set the mac type 93 */ 94 ixgbe_set_mac_type(hw); 95 96 switch (hw->mac.type) { 97 case ixgbe_mac_82598EB: 98 status = ixgbe_init_ops_82598(hw); 99 break; 100 case ixgbe_mac_82599EB: 101 status = ixgbe_init_ops_82599(hw); 102 break; 103 case ixgbe_mac_X540: 104 status = ixgbe_init_ops_X540(hw); 105 break; 106 case ixgbe_mac_X550: 107 status = ixgbe_init_ops_X550(hw); 108 break; 109 case ixgbe_mac_X550EM_x: 110 status = ixgbe_init_ops_X550EM_x(hw); 111 break; 112 case ixgbe_mac_X550EM_a: 113 status = ixgbe_init_ops_X550EM_a(hw); 114 break; 115 default: 116 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 117 break; 118 } 119 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 120 121 return status; 122 } 123 124 /** 125 * ixgbe_set_mac_type - Sets MAC type 126 * @hw: pointer to the HW structure 127 * 128 * This function sets the mac type of the adapter based on the 129 * vendor ID and device ID stored in the hw structure. 130 **/ 131 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 132 { 133 s32 ret_val = IXGBE_SUCCESS; 134 135 DEBUGFUNC("ixgbe_set_mac_type\n"); 136 137 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 138 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 139 "Unsupported vendor id: %x", hw->vendor_id); 140 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 141 } 142 143 hw->mvals = ixgbe_mvals_base; 144 145 switch (hw->device_id) { 146 case IXGBE_DEV_ID_82598: 147 case IXGBE_DEV_ID_82598_BX: 148 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 149 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 150 case IXGBE_DEV_ID_82598AT: 151 case IXGBE_DEV_ID_82598AT2: 152 case IXGBE_DEV_ID_82598EB_CX4: 153 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 154 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 155 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 156 case IXGBE_DEV_ID_82598EB_XF_LR: 157 case IXGBE_DEV_ID_82598EB_SFP_LOM: 158 hw->mac.type = ixgbe_mac_82598EB; 159 break; 160 case IXGBE_DEV_ID_82599_KX4: 161 case IXGBE_DEV_ID_82599_KX4_MEZZ: 162 case IXGBE_DEV_ID_82599_XAUI_LOM: 163 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 164 case IXGBE_DEV_ID_82599_KR: 165 case IXGBE_DEV_ID_82599_SFP: 166 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 167 case IXGBE_DEV_ID_82599_SFP_FCOE: 168 case IXGBE_DEV_ID_82599_SFP_EM: 169 case IXGBE_DEV_ID_82599_SFP_SF2: 170 case IXGBE_DEV_ID_82599_SFP_SF_QP: 171 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 172 case IXGBE_DEV_ID_82599EN_SFP: 173 case IXGBE_DEV_ID_82599_CX4: 174 case IXGBE_DEV_ID_82599_BYPASS: 175 case IXGBE_DEV_ID_82599_T3_LOM: 176 hw->mac.type = ixgbe_mac_82599EB; 177 break; 178 case IXGBE_DEV_ID_X540T: 179 case IXGBE_DEV_ID_X540T1: 180 case IXGBE_DEV_ID_X540_BYPASS: 181 hw->mac.type = ixgbe_mac_X540; 182 hw->mvals = ixgbe_mvals_X540; 183 break; 184 case IXGBE_DEV_ID_X550T: 185 case IXGBE_DEV_ID_X550T1: 186 hw->mac.type = ixgbe_mac_X550; 187 hw->mvals = ixgbe_mvals_X550; 188 break; 189 case IXGBE_DEV_ID_X550EM_X_KX4: 190 case IXGBE_DEV_ID_X550EM_X_KR: 191 case IXGBE_DEV_ID_X550EM_X_10G_T: 192 case IXGBE_DEV_ID_X550EM_X_1G_T: 193 case IXGBE_DEV_ID_X550EM_X_SFP: 194 case IXGBE_DEV_ID_X550EM_X_XFI: 195 hw->mac.type = ixgbe_mac_X550EM_x; 196 hw->mvals = ixgbe_mvals_X550EM_x; 197 break; 198 case IXGBE_DEV_ID_X550EM_A_KR: 199 case IXGBE_DEV_ID_X550EM_A_KR_L: 200 case IXGBE_DEV_ID_X550EM_A_SFP_N: 201 case IXGBE_DEV_ID_X550EM_A_SGMII: 202 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 203 case IXGBE_DEV_ID_X550EM_A_1G_T: 204 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 205 case IXGBE_DEV_ID_X550EM_A_10G_T: 206 case IXGBE_DEV_ID_X550EM_A_QSFP: 207 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 208 case IXGBE_DEV_ID_X550EM_A_SFP: 209 hw->mac.type = ixgbe_mac_X550EM_a; 210 hw->mvals = ixgbe_mvals_X550EM_a; 211 break; 212 default: 213 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 214 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 215 "Unsupported device id: %x", 216 hw->device_id); 217 break; 218 } 219 220 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 221 hw->mac.type, ret_val); 222 return ret_val; 223 } 224 225 /** 226 * ixgbe_init_hw - Initialize the hardware 227 * @hw: pointer to hardware structure 228 * 229 * Initialize the hardware by resetting and then starting the hardware 230 **/ 231 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 232 { 233 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 234 IXGBE_NOT_IMPLEMENTED); 235 } 236 237 /** 238 * ixgbe_reset_hw - Performs a hardware reset 239 * @hw: pointer to hardware structure 240 * 241 * Resets the hardware by resetting the transmit and receive units, masks and 242 * clears all interrupts, performs a PHY reset, and performs a MAC reset 243 **/ 244 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 245 { 246 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 247 IXGBE_NOT_IMPLEMENTED); 248 } 249 250 /** 251 * ixgbe_start_hw - Prepares hardware for Rx/Tx 252 * @hw: pointer to hardware structure 253 * 254 * Starts the hardware by filling the bus info structure and media type, 255 * clears all on chip counters, initializes receive address registers, 256 * multicast table, VLAN filter table, calls routine to setup link and 257 * flow control settings, and leaves transmit and receive units disabled 258 * and uninitialized. 259 **/ 260 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 261 { 262 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 263 IXGBE_NOT_IMPLEMENTED); 264 } 265 266 /** 267 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 268 * which is disabled by default in ixgbe_start_hw(); 269 * 270 * @hw: pointer to hardware structure 271 * 272 * Enable relaxed ordering; 273 **/ 274 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 275 { 276 if (hw->mac.ops.enable_relaxed_ordering) 277 hw->mac.ops.enable_relaxed_ordering(hw); 278 } 279 280 /** 281 * ixgbe_clear_hw_cntrs - Clear hardware counters 282 * @hw: pointer to hardware structure 283 * 284 * Clears all hardware statistics counters by reading them from the hardware 285 * Statistics counters are clear on read. 286 **/ 287 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 288 { 289 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 290 IXGBE_NOT_IMPLEMENTED); 291 } 292 293 /** 294 * ixgbe_get_media_type - Get media type 295 * @hw: pointer to hardware structure 296 * 297 * Returns the media type (fiber, copper, backplane) 298 **/ 299 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 300 { 301 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 302 ixgbe_media_type_unknown); 303 } 304 305 /** 306 * ixgbe_get_mac_addr - Get MAC address 307 * @hw: pointer to hardware structure 308 * @mac_addr: Adapter MAC address 309 * 310 * Reads the adapter's MAC address from the first Receive Address Register 311 * (RAR0) A reset of the adapter must have been performed prior to calling 312 * this function in order for the MAC address to have been loaded from the 313 * EEPROM into RAR0 314 **/ 315 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 316 { 317 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 318 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 319 } 320 321 /** 322 * ixgbe_get_san_mac_addr - Get SAN MAC address 323 * @hw: pointer to hardware structure 324 * @san_mac_addr: SAN MAC address 325 * 326 * Reads the SAN MAC address from the EEPROM, if it's available. This is 327 * per-port, so set_lan_id() must be called before reading the addresses. 328 **/ 329 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 330 { 331 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 332 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 333 } 334 335 /** 336 * ixgbe_set_san_mac_addr - Write a SAN MAC address 337 * @hw: pointer to hardware structure 338 * @san_mac_addr: SAN MAC address 339 * 340 * Writes A SAN MAC address to the EEPROM. 341 **/ 342 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 343 { 344 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 345 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 346 } 347 348 /** 349 * ixgbe_get_device_caps - Get additional device capabilities 350 * @hw: pointer to hardware structure 351 * @device_caps: the EEPROM word for device capabilities 352 * 353 * Reads the extra device capabilities from the EEPROM 354 **/ 355 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 356 { 357 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 358 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 359 } 360 361 /** 362 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 363 * @hw: pointer to hardware structure 364 * @wwnn_prefix: the alternative WWNN prefix 365 * @wwpn_prefix: the alternative WWPN prefix 366 * 367 * This function will read the EEPROM from the alternative SAN MAC address 368 * block to check the support for the alternative WWNN/WWPN prefix support. 369 **/ 370 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 371 u16 *wwpn_prefix) 372 { 373 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 374 (hw, wwnn_prefix, wwpn_prefix), 375 IXGBE_NOT_IMPLEMENTED); 376 } 377 378 /** 379 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 380 * @hw: pointer to hardware structure 381 * @bs: the fcoe boot status 382 * 383 * This function will read the FCOE boot status from the iSCSI FCOE block 384 **/ 385 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 386 { 387 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 388 (hw, bs), 389 IXGBE_NOT_IMPLEMENTED); 390 } 391 392 /** 393 * ixgbe_get_bus_info - Set PCI bus info 394 * @hw: pointer to hardware structure 395 * 396 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 397 **/ 398 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 399 { 400 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 401 IXGBE_NOT_IMPLEMENTED); 402 } 403 404 /** 405 * ixgbe_get_num_of_tx_queues - Get Tx queues 406 * @hw: pointer to hardware structure 407 * 408 * Returns the number of transmit queues for the given adapter. 409 **/ 410 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 411 { 412 return hw->mac.max_tx_queues; 413 } 414 415 /** 416 * ixgbe_get_num_of_rx_queues - Get Rx queues 417 * @hw: pointer to hardware structure 418 * 419 * Returns the number of receive queues for the given adapter. 420 **/ 421 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 422 { 423 return hw->mac.max_rx_queues; 424 } 425 426 /** 427 * ixgbe_stop_adapter - Disable Rx/Tx units 428 * @hw: pointer to hardware structure 429 * 430 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 431 * disables transmit and receive units. The adapter_stopped flag is used by 432 * the shared code and drivers to determine if the adapter is in a stopped 433 * state and should not touch the hardware. 434 **/ 435 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 436 { 437 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 438 IXGBE_NOT_IMPLEMENTED); 439 } 440 441 /** 442 * ixgbe_read_pba_string - Reads part number string from EEPROM 443 * @hw: pointer to hardware structure 444 * @pba_num: stores the part number string from the EEPROM 445 * @pba_num_size: part number string buffer length 446 * 447 * Reads the part number string from the EEPROM. 448 **/ 449 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 450 { 451 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 452 } 453 454 /** 455 * ixgbe_read_pba_num - Reads part number from EEPROM 456 * @hw: pointer to hardware structure 457 * @pba_num: stores the part number from the EEPROM 458 * 459 * Reads the part number from the EEPROM. 460 **/ 461 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 462 { 463 return ixgbe_read_pba_num_generic(hw, pba_num); 464 } 465 466 /** 467 * ixgbe_identify_phy - Get PHY type 468 * @hw: pointer to hardware structure 469 * 470 * Determines the physical layer module found on the current adapter. 471 **/ 472 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 473 { 474 s32 status = IXGBE_SUCCESS; 475 476 if (hw->phy.type == ixgbe_phy_unknown) { 477 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 478 IXGBE_NOT_IMPLEMENTED); 479 } 480 481 return status; 482 } 483 484 /** 485 * ixgbe_reset_phy - Perform a PHY reset 486 * @hw: pointer to hardware structure 487 **/ 488 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 489 { 490 s32 status = IXGBE_SUCCESS; 491 492 if (hw->phy.type == ixgbe_phy_unknown) { 493 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 494 status = IXGBE_ERR_PHY; 495 } 496 497 if (status == IXGBE_SUCCESS) { 498 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 499 IXGBE_NOT_IMPLEMENTED); 500 } 501 return status; 502 } 503 504 /** 505 * ixgbe_get_phy_firmware_version - 506 * @hw: pointer to hardware structure 507 * @firmware_version: pointer to firmware version 508 **/ 509 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 510 { 511 s32 status = IXGBE_SUCCESS; 512 513 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 514 (hw, firmware_version), 515 IXGBE_NOT_IMPLEMENTED); 516 return status; 517 } 518 519 /** 520 * ixgbe_read_phy_reg - Read PHY register 521 * @hw: pointer to hardware structure 522 * @reg_addr: 32 bit address of PHY register to read 523 * @phy_data: Pointer to read data from PHY register 524 * 525 * Reads a value from a specified PHY register 526 **/ 527 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 528 u16 *phy_data) 529 { 530 if (hw->phy.id == 0) 531 ixgbe_identify_phy(hw); 532 533 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 534 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 535 } 536 537 /** 538 * ixgbe_write_phy_reg - Write PHY register 539 * @hw: pointer to hardware structure 540 * @reg_addr: 32 bit PHY register to write 541 * @phy_data: Data to write to the PHY register 542 * 543 * Writes a value to specified PHY register 544 **/ 545 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 546 u16 phy_data) 547 { 548 if (hw->phy.id == 0) 549 ixgbe_identify_phy(hw); 550 551 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 552 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 553 } 554 555 /** 556 * ixgbe_setup_phy_link - Restart PHY autoneg 557 * @hw: pointer to hardware structure 558 * 559 * Restart autonegotiation and PHY and waits for completion. 560 **/ 561 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 562 { 563 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 564 IXGBE_NOT_IMPLEMENTED); 565 } 566 567 /** 568 * ixgbe_setup_internal_phy - Configure integrated PHY 569 * @hw: pointer to hardware structure 570 * 571 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 572 * Returns success if not implemented, since nothing needs to be done in this 573 * case. 574 */ 575 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 576 { 577 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 578 IXGBE_SUCCESS); 579 } 580 581 /** 582 * ixgbe_check_phy_link - Determine link and speed status 583 * @hw: pointer to hardware structure 584 * 585 * Reads a PHY register to determine if link is up and the current speed for 586 * the PHY. 587 **/ 588 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 589 bool *link_up) 590 { 591 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 592 link_up), IXGBE_NOT_IMPLEMENTED); 593 } 594 595 /** 596 * ixgbe_setup_phy_link_speed - Set auto advertise 597 * @hw: pointer to hardware structure 598 * @speed: new link speed 599 * 600 * Sets the auto advertised capabilities 601 **/ 602 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 603 bool autoneg_wait_to_complete) 604 { 605 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 606 autoneg_wait_to_complete), 607 IXGBE_NOT_IMPLEMENTED); 608 } 609 610 /** 611 * ixgbe_set_phy_power - Control the phy power state 612 * @hw: pointer to hardware structure 613 * @on: TRUE for on, FALSE for off 614 */ 615 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 616 { 617 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 618 IXGBE_NOT_IMPLEMENTED); 619 } 620 621 /** 622 * ixgbe_check_link - Get link and speed status 623 * @hw: pointer to hardware structure 624 * 625 * Reads the links register to determine if link is up and the current speed 626 **/ 627 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 628 bool *link_up, bool link_up_wait_to_complete) 629 { 630 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 631 link_up, link_up_wait_to_complete), 632 IXGBE_NOT_IMPLEMENTED); 633 } 634 635 /** 636 * ixgbe_disable_tx_laser - Disable Tx laser 637 * @hw: pointer to hardware structure 638 * 639 * If the driver needs to disable the laser on SFI optics. 640 **/ 641 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 642 { 643 if (hw->mac.ops.disable_tx_laser) 644 hw->mac.ops.disable_tx_laser(hw); 645 } 646 647 /** 648 * ixgbe_enable_tx_laser - Enable Tx laser 649 * @hw: pointer to hardware structure 650 * 651 * If the driver needs to enable the laser on SFI optics. 652 **/ 653 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 654 { 655 if (hw->mac.ops.enable_tx_laser) 656 hw->mac.ops.enable_tx_laser(hw); 657 } 658 659 /** 660 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 661 * @hw: pointer to hardware structure 662 * 663 * When the driver changes the link speeds that it can support then 664 * flap the tx laser to alert the link partner to start autotry 665 * process on its end. 666 **/ 667 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 668 { 669 if (hw->mac.ops.flap_tx_laser) 670 hw->mac.ops.flap_tx_laser(hw); 671 } 672 673 /** 674 * ixgbe_setup_link - Set link speed 675 * @hw: pointer to hardware structure 676 * @speed: new link speed 677 * 678 * Configures link settings. Restarts the link. 679 * Performs autonegotiation if needed. 680 **/ 681 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 682 bool autoneg_wait_to_complete) 683 { 684 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 685 autoneg_wait_to_complete), 686 IXGBE_NOT_IMPLEMENTED); 687 } 688 689 /** 690 * ixgbe_setup_mac_link - Set link speed 691 * @hw: pointer to hardware structure 692 * @speed: new link speed 693 * 694 * Configures link settings. Restarts the link. 695 * Performs autonegotiation if needed. 696 **/ 697 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 698 bool autoneg_wait_to_complete) 699 { 700 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 701 autoneg_wait_to_complete), 702 IXGBE_NOT_IMPLEMENTED); 703 } 704 705 /** 706 * ixgbe_get_link_capabilities - Returns link capabilities 707 * @hw: pointer to hardware structure 708 * 709 * Determines the link capabilities of the current configuration. 710 **/ 711 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 712 bool *autoneg) 713 { 714 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 715 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 716 } 717 718 /** 719 * ixgbe_led_on - Turn on LEDs 720 * @hw: pointer to hardware structure 721 * @index: led number to turn on 722 * 723 * Turns on the software controllable LEDs. 724 **/ 725 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 726 { 727 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 728 IXGBE_NOT_IMPLEMENTED); 729 } 730 731 /** 732 * ixgbe_led_off - Turn off LEDs 733 * @hw: pointer to hardware structure 734 * @index: led number to turn off 735 * 736 * Turns off the software controllable LEDs. 737 **/ 738 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 739 { 740 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 741 IXGBE_NOT_IMPLEMENTED); 742 } 743 744 /** 745 * ixgbe_blink_led_start - Blink LEDs 746 * @hw: pointer to hardware structure 747 * @index: led number to blink 748 * 749 * Blink LED based on index. 750 **/ 751 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 752 { 753 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 754 IXGBE_NOT_IMPLEMENTED); 755 } 756 757 /** 758 * ixgbe_blink_led_stop - Stop blinking LEDs 759 * @hw: pointer to hardware structure 760 * 761 * Stop blinking LED based on index. 762 **/ 763 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 764 { 765 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 766 IXGBE_NOT_IMPLEMENTED); 767 } 768 769 /** 770 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 771 * @hw: pointer to hardware structure 772 * 773 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 774 * ixgbe_hw struct in order to set up EEPROM access. 775 **/ 776 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 777 { 778 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 779 IXGBE_NOT_IMPLEMENTED); 780 } 781 782 783 /** 784 * ixgbe_write_eeprom - Write word to EEPROM 785 * @hw: pointer to hardware structure 786 * @offset: offset within the EEPROM to be written to 787 * @data: 16 bit word to be written to the EEPROM 788 * 789 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 790 * called after this function, the EEPROM will most likely contain an 791 * invalid checksum. 792 **/ 793 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 794 { 795 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 796 IXGBE_NOT_IMPLEMENTED); 797 } 798 799 /** 800 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 801 * @hw: pointer to hardware structure 802 * @offset: offset within the EEPROM to be written to 803 * @data: 16 bit word(s) to be written to the EEPROM 804 * @words: number of words 805 * 806 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 807 * called after this function, the EEPROM will most likely contain an 808 * invalid checksum. 809 **/ 810 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 811 u16 *data) 812 { 813 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 814 (hw, offset, words, data), 815 IXGBE_NOT_IMPLEMENTED); 816 } 817 818 /** 819 * ixgbe_read_eeprom - Read word from EEPROM 820 * @hw: pointer to hardware structure 821 * @offset: offset within the EEPROM to be read 822 * @data: read 16 bit value from EEPROM 823 * 824 * Reads 16 bit value from EEPROM 825 **/ 826 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 827 { 828 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 829 IXGBE_NOT_IMPLEMENTED); 830 } 831 832 /** 833 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 834 * @hw: pointer to hardware structure 835 * @offset: offset within the EEPROM to be read 836 * @data: read 16 bit word(s) from EEPROM 837 * @words: number of words 838 * 839 * Reads 16 bit word(s) from EEPROM 840 **/ 841 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 842 u16 words, u16 *data) 843 { 844 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 845 (hw, offset, words, data), 846 IXGBE_NOT_IMPLEMENTED); 847 } 848 849 /** 850 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 851 * @hw: pointer to hardware structure 852 * @checksum_val: calculated checksum 853 * 854 * Performs checksum calculation and validates the EEPROM checksum 855 **/ 856 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 857 { 858 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 859 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 860 } 861 862 /** 863 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 864 * @hw: pointer to hardware structure 865 **/ 866 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 867 { 868 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 869 IXGBE_NOT_IMPLEMENTED); 870 } 871 872 /** 873 * ixgbe_insert_mac_addr - Find a RAR for this mac address 874 * @hw: pointer to hardware structure 875 * @addr: Address to put into receive address register 876 * @vmdq: VMDq pool to assign 877 * 878 * Puts an ethernet address into a receive address register, or 879 * finds the rar that it is aleady in; adds to the pool list 880 **/ 881 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 882 { 883 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 884 (hw, addr, vmdq), 885 IXGBE_NOT_IMPLEMENTED); 886 } 887 888 /** 889 * ixgbe_set_rar - Set Rx address register 890 * @hw: pointer to hardware structure 891 * @index: Receive address register to write 892 * @addr: Address to put into receive address register 893 * @vmdq: VMDq "set" 894 * @enable_addr: set flag that address is active 895 * 896 * Puts an ethernet address into a receive address register. 897 **/ 898 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 899 u32 enable_addr) 900 { 901 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 902 enable_addr), IXGBE_NOT_IMPLEMENTED); 903 } 904 905 /** 906 * ixgbe_clear_rar - Clear Rx address register 907 * @hw: pointer to hardware structure 908 * @index: Receive address register to write 909 * 910 * Puts an ethernet address into a receive address register. 911 **/ 912 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 913 { 914 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 915 IXGBE_NOT_IMPLEMENTED); 916 } 917 918 /** 919 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 920 * @hw: pointer to hardware structure 921 * @rar: receive address register index to associate with VMDq index 922 * @vmdq: VMDq set or pool index 923 **/ 924 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 925 { 926 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 927 IXGBE_NOT_IMPLEMENTED); 928 929 } 930 931 /** 932 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 933 * @hw: pointer to hardware structure 934 * @vmdq: VMDq default pool index 935 **/ 936 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 937 { 938 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 939 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 940 } 941 942 /** 943 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 944 * @hw: pointer to hardware structure 945 * @rar: receive address register index to disassociate with VMDq index 946 * @vmdq: VMDq set or pool index 947 **/ 948 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 949 { 950 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 951 IXGBE_NOT_IMPLEMENTED); 952 } 953 954 /** 955 * ixgbe_init_rx_addrs - Initializes receive address filters. 956 * @hw: pointer to hardware structure 957 * 958 * Places the MAC address in receive address register 0 and clears the rest 959 * of the receive address registers. Clears the multicast table. Assumes 960 * the receiver is in reset when the routine is called. 961 **/ 962 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 963 { 964 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 965 IXGBE_NOT_IMPLEMENTED); 966 } 967 968 /** 969 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 970 * @hw: pointer to hardware structure 971 **/ 972 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 973 { 974 return hw->mac.num_rar_entries; 975 } 976 977 /** 978 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 979 * @hw: pointer to hardware structure 980 * @addr_list: the list of new multicast addresses 981 * @addr_count: number of addresses 982 * @func: iterator function to walk the multicast address list 983 * 984 * The given list replaces any existing list. Clears the secondary addrs from 985 * receive address registers. Uses unused receive address registers for the 986 * first secondary addresses, and falls back to promiscuous mode as needed. 987 **/ 988 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 989 u32 addr_count, ixgbe_mc_addr_itr func) 990 { 991 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 992 addr_list, addr_count, func), 993 IXGBE_NOT_IMPLEMENTED); 994 } 995 996 /** 997 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 998 * @hw: pointer to hardware structure 999 * @mc_addr_list: the list of new multicast addresses 1000 * @mc_addr_count: number of addresses 1001 * @func: iterator function to walk the multicast address list 1002 * 1003 * The given list replaces any existing list. Clears the MC addrs from receive 1004 * address registers and the multicast table. Uses unused receive address 1005 * registers for the first multicast addresses, and hashes the rest into the 1006 * multicast table. 1007 **/ 1008 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1009 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1010 bool clear) 1011 { 1012 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1013 mc_addr_list, mc_addr_count, func, clear), 1014 IXGBE_NOT_IMPLEMENTED); 1015 } 1016 1017 /** 1018 * ixgbe_enable_mc - Enable multicast address in RAR 1019 * @hw: pointer to hardware structure 1020 * 1021 * Enables multicast address in RAR and the use of the multicast hash table. 1022 **/ 1023 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1024 { 1025 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1026 IXGBE_NOT_IMPLEMENTED); 1027 } 1028 1029 /** 1030 * ixgbe_disable_mc - Disable multicast address in RAR 1031 * @hw: pointer to hardware structure 1032 * 1033 * Disables multicast address in RAR and the use of the multicast hash table. 1034 **/ 1035 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1036 { 1037 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1038 IXGBE_NOT_IMPLEMENTED); 1039 } 1040 1041 /** 1042 * ixgbe_clear_vfta - Clear VLAN filter table 1043 * @hw: pointer to hardware structure 1044 * 1045 * Clears the VLAN filer table, and the VMDq index associated with the filter 1046 **/ 1047 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1048 { 1049 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1050 IXGBE_NOT_IMPLEMENTED); 1051 } 1052 1053 /** 1054 * ixgbe_set_vfta - Set VLAN filter table 1055 * @hw: pointer to hardware structure 1056 * @vlan: VLAN id to write to VLAN filter 1057 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1058 * @vlan_on: boolean flag to turn on/off VLAN 1059 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1060 * 1061 * Turn on/off specified VLAN in the VLAN filter table. 1062 **/ 1063 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1064 bool vlvf_bypass) 1065 { 1066 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1067 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1068 } 1069 1070 /** 1071 * ixgbe_set_vlvf - Set VLAN Pool Filter 1072 * @hw: pointer to hardware structure 1073 * @vlan: VLAN id to write to VLAN filter 1074 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1075 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1076 * @vfta_delta: pointer to the difference between the current value of VFTA 1077 * and the desired value 1078 * @vfta: the desired value of the VFTA 1079 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1080 * 1081 * Turn on/off specified bit in VLVF table. 1082 **/ 1083 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1084 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1085 { 1086 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1087 vlan_on, vfta_delta, vfta, vlvf_bypass), 1088 IXGBE_NOT_IMPLEMENTED); 1089 } 1090 1091 /** 1092 * ixgbe_fc_enable - Enable flow control 1093 * @hw: pointer to hardware structure 1094 * 1095 * Configures the flow control settings based on SW configuration. 1096 **/ 1097 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1098 { 1099 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1100 IXGBE_NOT_IMPLEMENTED); 1101 } 1102 1103 /** 1104 * ixgbe_setup_fc - Set up flow control 1105 * @hw: pointer to hardware structure 1106 * 1107 * Called at init time to set up flow control. 1108 **/ 1109 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1110 { 1111 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1112 IXGBE_NOT_IMPLEMENTED); 1113 } 1114 1115 /** 1116 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1117 * @hw: pointer to hardware structure 1118 * @maj: driver major number to be sent to firmware 1119 * @min: driver minor number to be sent to firmware 1120 * @build: driver build number to be sent to firmware 1121 * @ver: driver version number to be sent to firmware 1122 * @len: length of driver_ver string 1123 * @driver_ver: driver string 1124 **/ 1125 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1126 u8 ver, u16 len, char *driver_ver) 1127 { 1128 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1129 build, ver, len, driver_ver), 1130 IXGBE_NOT_IMPLEMENTED); 1131 } 1132 1133 1134 1135 /** 1136 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1137 * @hw: pointer to hardware structure 1138 * 1139 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1140 * When disabling dmac, dmac enable dmac bit is cleared. 1141 **/ 1142 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1143 { 1144 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1145 IXGBE_NOT_IMPLEMENTED); 1146 } 1147 1148 /** 1149 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1150 * @hw: pointer to hardware structure 1151 * 1152 * Disables dmac, updates per TC settings, and then enable dmac. 1153 **/ 1154 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1155 { 1156 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1157 IXGBE_NOT_IMPLEMENTED); 1158 } 1159 1160 /** 1161 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1162 * @hw: pointer to hardware structure 1163 * 1164 * Configure DMA coalescing threshold per TC and set high priority bit for 1165 * FCOE TC. The dmac enable bit must be cleared before configuring. 1166 **/ 1167 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1168 { 1169 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1170 IXGBE_NOT_IMPLEMENTED); 1171 } 1172 1173 /** 1174 * ixgbe_setup_eee - Enable/disable EEE support 1175 * @hw: pointer to the HW structure 1176 * @enable_eee: boolean flag to enable EEE 1177 * 1178 * Enable/disable EEE based on enable_ee flag. 1179 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1180 * are modified. 1181 * 1182 **/ 1183 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1184 { 1185 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1186 IXGBE_NOT_IMPLEMENTED); 1187 } 1188 1189 /** 1190 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1191 * @hw: pointer to hardware structure 1192 * @enbale: enable or disable source address pruning 1193 * @pool: Rx pool - Rx pool to toggle source address pruning 1194 **/ 1195 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1196 unsigned int pool) 1197 { 1198 if (hw->mac.ops.set_source_address_pruning) 1199 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1200 } 1201 1202 /** 1203 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1204 * @hw: pointer to hardware structure 1205 * @enable: enable or disable switch for Ethertype anti-spoofing 1206 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1207 * 1208 **/ 1209 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1210 { 1211 if (hw->mac.ops.set_ethertype_anti_spoofing) 1212 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1213 } 1214 1215 /** 1216 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1217 * @hw: pointer to hardware structure 1218 * @reg_addr: 32 bit address of PHY register to read 1219 * @device_type: type of device you want to communicate with 1220 * @phy_data: Pointer to read data from PHY register 1221 * 1222 * Reads a value from a specified PHY register 1223 **/ 1224 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1225 u32 device_type, u32 *phy_data) 1226 { 1227 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1228 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1229 } 1230 1231 /** 1232 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1233 * @hw: pointer to hardware structure 1234 * @reg_addr: 32 bit PHY register to write 1235 * @device_type: type of device you want to communicate with 1236 * @phy_data: Data to write to the PHY register 1237 * 1238 * Writes a value to specified PHY register 1239 **/ 1240 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1241 u32 device_type, u32 phy_data) 1242 { 1243 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1244 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1245 } 1246 1247 /** 1248 * ixgbe_disable_mdd - Disable malicious driver detection 1249 * @hw: pointer to hardware structure 1250 * 1251 **/ 1252 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1253 { 1254 if (hw->mac.ops.disable_mdd) 1255 hw->mac.ops.disable_mdd(hw); 1256 } 1257 1258 /** 1259 * ixgbe_enable_mdd - Enable malicious driver detection 1260 * @hw: pointer to hardware structure 1261 * 1262 **/ 1263 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1264 { 1265 if (hw->mac.ops.enable_mdd) 1266 hw->mac.ops.enable_mdd(hw); 1267 } 1268 1269 /** 1270 * ixgbe_mdd_event - Handle malicious driver detection event 1271 * @hw: pointer to hardware structure 1272 * @vf_bitmap: vf bitmap of malicious vfs 1273 * 1274 **/ 1275 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1276 { 1277 if (hw->mac.ops.mdd_event) 1278 hw->mac.ops.mdd_event(hw, vf_bitmap); 1279 } 1280 1281 /** 1282 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1283 * detection event 1284 * @hw: pointer to hardware structure 1285 * @vf: vf index 1286 * 1287 **/ 1288 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1289 { 1290 if (hw->mac.ops.restore_mdd_vf) 1291 hw->mac.ops.restore_mdd_vf(hw, vf); 1292 } 1293 1294 /** 1295 * ixgbe_enter_lplu - Transition to low power states 1296 * @hw: pointer to hardware structure 1297 * 1298 * Configures Low Power Link Up on transition to low power states 1299 * (from D0 to non-D0). 1300 **/ 1301 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1302 { 1303 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1304 IXGBE_NOT_IMPLEMENTED); 1305 } 1306 1307 /** 1308 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1309 * @hw: pointer to hardware structure 1310 * 1311 * Handle external Base T PHY interrupt. If high temperature 1312 * failure alarm then return error, else if link status change 1313 * then setup internal/external PHY link 1314 * 1315 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1316 * failure alarm, else return PHY access status. 1317 */ 1318 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1319 { 1320 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1321 IXGBE_NOT_IMPLEMENTED); 1322 } 1323 1324 /** 1325 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1326 * @hw: pointer to hardware structure 1327 * @cmd: Command we send to the FW 1328 * @status: The reply from the FW 1329 * 1330 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1331 **/ 1332 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1333 { 1334 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1335 IXGBE_NOT_IMPLEMENTED); 1336 } 1337 1338 #if 0 1339 /** 1340 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1341 * 1342 * If we send a write we can't be sure it took until we can read back 1343 * that same register. It can be a problem as some of the feilds may 1344 * for valid reasons change inbetween the time wrote the register and 1345 * we read it again to verify. So this function check everything we 1346 * can check and then assumes it worked. 1347 * 1348 * @u32 in_reg - The register cmd for the bit-bang read. 1349 * @u32 out_reg - The register returned from a bit-bang read. 1350 **/ 1351 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1352 { 1353 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1354 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1355 } 1356 #endif 1357 1358 /** 1359 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1360 * @hw: pointer to hardware structure 1361 * @cmd: The control word we are setting. 1362 * @event: The event we are setting in the FW. This also happens to 1363 * be the mask for the event we are setting (handy) 1364 * @action: The action we set the event to in the FW. This is in a 1365 * bit field that happens to be what we want to put in 1366 * the event spot (also handy) 1367 * 1368 * Writes to the cmd control the bits in actions. 1369 **/ 1370 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1371 { 1372 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1373 (hw, cmd, event, action), 1374 IXGBE_NOT_IMPLEMENTED); 1375 } 1376 1377 /** 1378 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1379 * @hw: pointer to hardware structure 1380 * @addr: The bypass eeprom address to read. 1381 * @value: The 8b of data at the address above. 1382 **/ 1383 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1384 { 1385 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1386 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1387 } 1388 1389 /** 1390 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1391 * @hw: pointer to hardware structure 1392 * @reg: analog register to read 1393 * @val: read value 1394 * 1395 * Performs write operation to analog register specified. 1396 **/ 1397 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1398 { 1399 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1400 val), IXGBE_NOT_IMPLEMENTED); 1401 } 1402 1403 /** 1404 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1405 * @hw: pointer to hardware structure 1406 * @reg: analog register to write 1407 * @val: value to write 1408 * 1409 * Performs write operation to Atlas analog register specified. 1410 **/ 1411 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1412 { 1413 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1414 val), IXGBE_NOT_IMPLEMENTED); 1415 } 1416 1417 /** 1418 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1419 * @hw: pointer to hardware structure 1420 * 1421 * Initializes the Unicast Table Arrays to zero on device load. This 1422 * is part of the Rx init addr execution path. 1423 **/ 1424 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1425 { 1426 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1427 IXGBE_NOT_IMPLEMENTED); 1428 } 1429 1430 /** 1431 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1432 * @hw: pointer to hardware structure 1433 * @byte_offset: byte offset to read 1434 * @dev_addr: I2C bus address to read from 1435 * @data: value read 1436 * 1437 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1438 **/ 1439 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1440 u8 *data) 1441 { 1442 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1443 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1444 } 1445 1446 /** 1447 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1448 * @hw: pointer to hardware structure 1449 * @byte_offset: byte offset to read 1450 * @dev_addr: I2C bus address to read from 1451 * @data: value read 1452 * 1453 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1454 **/ 1455 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1456 u8 dev_addr, u8 *data) 1457 { 1458 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1459 (hw, byte_offset, dev_addr, data), 1460 IXGBE_NOT_IMPLEMENTED); 1461 } 1462 1463 /** 1464 * ixgbe_read_link - Perform read operation on link device 1465 * @hw: pointer to the hardware structure 1466 * @addr: bus address to read from 1467 * @reg: device register to read from 1468 * @val: pointer to location to receive read value 1469 * 1470 * Returns an error code on error. 1471 */ 1472 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1473 { 1474 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1475 reg, val), IXGBE_NOT_IMPLEMENTED); 1476 } 1477 1478 /** 1479 * ixgbe_read_link_unlocked - Perform read operation on link device 1480 * @hw: pointer to the hardware structure 1481 * @addr: bus address to read from 1482 * @reg: device register to read from 1483 * @val: pointer to location to receive read value 1484 * 1485 * Returns an error code on error. 1486 **/ 1487 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1488 { 1489 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1490 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1491 } 1492 1493 /** 1494 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1495 * @hw: pointer to hardware structure 1496 * @byte_offset: byte offset to write 1497 * @dev_addr: I2C bus address to write to 1498 * @data: value to write 1499 * 1500 * Performs byte write operation to SFP module's EEPROM over I2C interface 1501 * at a specified device address. 1502 **/ 1503 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1504 u8 data) 1505 { 1506 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1507 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1508 } 1509 1510 /** 1511 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1512 * @hw: pointer to hardware structure 1513 * @byte_offset: byte offset to write 1514 * @dev_addr: I2C bus address to write to 1515 * @data: value to write 1516 * 1517 * Performs byte write operation to SFP module's EEPROM over I2C interface 1518 * at a specified device address. 1519 **/ 1520 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1521 u8 dev_addr, u8 data) 1522 { 1523 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1524 (hw, byte_offset, dev_addr, data), 1525 IXGBE_NOT_IMPLEMENTED); 1526 } 1527 1528 /** 1529 * ixgbe_write_link - Perform write operation on link device 1530 * @hw: pointer to the hardware structure 1531 * @addr: bus address to write to 1532 * @reg: device register to write to 1533 * @val: value to write 1534 * 1535 * Returns an error code on error. 1536 */ 1537 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1538 { 1539 return ixgbe_call_func(hw, hw->link.ops.write_link, 1540 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1541 } 1542 1543 /** 1544 * ixgbe_write_link_unlocked - Perform write operation on link device 1545 * @hw: pointer to the hardware structure 1546 * @addr: bus address to write to 1547 * @reg: device register to write to 1548 * @val: value to write 1549 * 1550 * Returns an error code on error. 1551 **/ 1552 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1553 { 1554 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1555 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1556 } 1557 1558 /** 1559 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1560 * @hw: pointer to hardware structure 1561 * @byte_offset: EEPROM byte offset to write 1562 * @eeprom_data: value to write 1563 * 1564 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1565 **/ 1566 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1567 u8 byte_offset, u8 eeprom_data) 1568 { 1569 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1570 (hw, byte_offset, eeprom_data), 1571 IXGBE_NOT_IMPLEMENTED); 1572 } 1573 1574 /** 1575 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1576 * @hw: pointer to hardware structure 1577 * @byte_offset: EEPROM byte offset to read 1578 * @eeprom_data: value read 1579 * 1580 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1581 **/ 1582 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1583 { 1584 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1585 (hw, byte_offset, eeprom_data), 1586 IXGBE_NOT_IMPLEMENTED); 1587 } 1588 1589 /** 1590 * ixgbe_get_supported_physical_layer - Returns physical layer type 1591 * @hw: pointer to hardware structure 1592 * 1593 * Determines physical layer capabilities of the current configuration. 1594 **/ 1595 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1596 { 1597 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1598 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1599 } 1600 1601 /** 1602 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1603 * @hw: pointer to hardware structure 1604 * @regval: bitfield to write to the Rx DMA register 1605 * 1606 * Enables the Rx DMA unit of the device. 1607 **/ 1608 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1609 { 1610 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1611 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1612 } 1613 1614 /** 1615 * ixgbe_disable_sec_rx_path - Stops the receive data path 1616 * @hw: pointer to hardware structure 1617 * 1618 * Stops the receive data path. 1619 **/ 1620 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1621 { 1622 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1623 (hw), IXGBE_NOT_IMPLEMENTED); 1624 } 1625 1626 /** 1627 * ixgbe_enable_sec_rx_path - Enables the receive data path 1628 * @hw: pointer to hardware structure 1629 * 1630 * Enables the receive data path. 1631 **/ 1632 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1633 { 1634 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1635 (hw), IXGBE_NOT_IMPLEMENTED); 1636 } 1637 1638 /** 1639 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1640 * @hw: pointer to hardware structure 1641 * @mask: Mask to specify which semaphore to acquire 1642 * 1643 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1644 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1645 **/ 1646 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1647 { 1648 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1649 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1650 } 1651 1652 /** 1653 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1654 * @hw: pointer to hardware structure 1655 * @mask: Mask to specify which semaphore to release 1656 * 1657 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1658 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1659 **/ 1660 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1661 { 1662 if (hw->mac.ops.release_swfw_sync) 1663 hw->mac.ops.release_swfw_sync(hw, mask); 1664 } 1665 1666 /** 1667 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1668 * @hw: pointer to hardware structure 1669 * 1670 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1671 * Regardless of whether is succeeds or not it then release the semaphore. 1672 * This is function is called to recover from catastrophic failures that 1673 * may have left the semaphore locked. 1674 **/ 1675 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1676 { 1677 if (hw->mac.ops.init_swfw_sync) 1678 hw->mac.ops.init_swfw_sync(hw); 1679 } 1680 1681 1682 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1683 { 1684 if (hw->mac.ops.disable_rx) 1685 hw->mac.ops.disable_rx(hw); 1686 } 1687 1688 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1689 { 1690 if (hw->mac.ops.enable_rx) 1691 hw->mac.ops.enable_rx(hw); 1692 } 1693 1694 /** 1695 * ixgbe_set_rate_select_speed - Set module link speed 1696 * @hw: pointer to hardware structure 1697 * @speed: link speed to set 1698 * 1699 * Set module link speed via the rate select. 1700 */ 1701 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1702 { 1703 if (hw->mac.ops.set_rate_select_speed) 1704 hw->mac.ops.set_rate_select_speed(hw, speed); 1705 } 1706