1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 /** 39 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 40 * @hw: pointer to hardware structure 41 * @map: pointer to u8 arr for returning map 42 * 43 * Read the rtrup2tc HW register and resolve its content into map 44 **/ 45 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 46 { 47 if (hw->mac.ops.get_rtrup2tc) 48 hw->mac.ops.get_rtrup2tc(hw, map); 49 } 50 51 /** 52 * ixgbe_init_shared_code - Initialize the shared code 53 * @hw: pointer to hardware structure 54 * 55 * This will assign function pointers and assign the MAC type and PHY code. 56 * Does not touch the hardware. This function must be called prior to any 57 * other function in the shared code. The ixgbe_hw structure should be 58 * memset to 0 prior to calling this function. The following fields in 59 * hw structure should be filled in prior to calling this function: 60 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 61 * subsystem_vendor_id, and revision_id 62 **/ 63 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 64 { 65 s32 status; 66 67 DEBUGFUNC("ixgbe_init_shared_code"); 68 69 /* 70 * Set the mac type 71 */ 72 ixgbe_set_mac_type(hw); 73 74 switch (hw->mac.type) { 75 case ixgbe_mac_82598EB: 76 status = ixgbe_init_ops_82598(hw); 77 break; 78 case ixgbe_mac_82599EB: 79 status = ixgbe_init_ops_82599(hw); 80 break; 81 case ixgbe_mac_X540: 82 status = ixgbe_init_ops_X540(hw); 83 break; 84 case ixgbe_mac_X550: 85 status = ixgbe_init_ops_X550(hw); 86 break; 87 case ixgbe_mac_X550EM_x: 88 case ixgbe_mac_X550EM_a: 89 status = ixgbe_init_ops_X550EM(hw); 90 break; 91 case ixgbe_mac_82599_vf: 92 case ixgbe_mac_X540_vf: 93 case ixgbe_mac_X550_vf: 94 case ixgbe_mac_X550EM_x_vf: 95 case ixgbe_mac_X550EM_a_vf: 96 status = ixgbe_init_ops_vf(hw); 97 break; 98 default: 99 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 100 break; 101 } 102 103 return status; 104 } 105 106 /** 107 * ixgbe_set_mac_type - Sets MAC type 108 * @hw: pointer to the HW structure 109 * 110 * This function sets the mac type of the adapter based on the 111 * vendor ID and device ID stored in the hw structure. 112 **/ 113 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 114 { 115 s32 ret_val = IXGBE_SUCCESS; 116 117 DEBUGFUNC("ixgbe_set_mac_type\n"); 118 119 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 120 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 121 "Unsupported vendor id: %x", hw->vendor_id); 122 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 123 } 124 125 switch (hw->device_id) { 126 case IXGBE_DEV_ID_82598: 127 case IXGBE_DEV_ID_82598_BX: 128 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 129 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 130 case IXGBE_DEV_ID_82598AT: 131 case IXGBE_DEV_ID_82598AT2: 132 case IXGBE_DEV_ID_82598EB_CX4: 133 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 134 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 135 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 136 case IXGBE_DEV_ID_82598EB_XF_LR: 137 case IXGBE_DEV_ID_82598EB_SFP_LOM: 138 hw->mac.type = ixgbe_mac_82598EB; 139 break; 140 case IXGBE_DEV_ID_82599_KX4: 141 case IXGBE_DEV_ID_82599_KX4_MEZZ: 142 case IXGBE_DEV_ID_82599_XAUI_LOM: 143 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 144 case IXGBE_DEV_ID_82599_KR: 145 case IXGBE_DEV_ID_82599_SFP: 146 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 147 case IXGBE_DEV_ID_82599_SFP_FCOE: 148 case IXGBE_DEV_ID_82599_SFP_EM: 149 case IXGBE_DEV_ID_82599_SFP_SF2: 150 case IXGBE_DEV_ID_82599_SFP_SF_QP: 151 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 152 case IXGBE_DEV_ID_82599EN_SFP: 153 case IXGBE_DEV_ID_82599_CX4: 154 case IXGBE_DEV_ID_82599_BYPASS: 155 case IXGBE_DEV_ID_82599_T3_LOM: 156 hw->mac.type = ixgbe_mac_82599EB; 157 break; 158 case IXGBE_DEV_ID_82599_VF: 159 case IXGBE_DEV_ID_82599_VF_HV: 160 hw->mac.type = ixgbe_mac_82599_vf; 161 break; 162 case IXGBE_DEV_ID_X540_VF: 163 case IXGBE_DEV_ID_X540_VF_HV: 164 hw->mac.type = ixgbe_mac_X540_vf; 165 break; 166 case IXGBE_DEV_ID_X540T: 167 case IXGBE_DEV_ID_X540T1: 168 case IXGBE_DEV_ID_X540_BYPASS: 169 hw->mac.type = ixgbe_mac_X540; 170 break; 171 case IXGBE_DEV_ID_X550T: 172 hw->mac.type = ixgbe_mac_X550; 173 break; 174 case IXGBE_DEV_ID_X550EM_X_KX4: 175 case IXGBE_DEV_ID_X550EM_X_KR: 176 case IXGBE_DEV_ID_X550EM_X_10G_T: 177 case IXGBE_DEV_ID_X550EM_X_1G_T: 178 case IXGBE_DEV_ID_X550EM_X_SFP: 179 hw->mac.type = ixgbe_mac_X550EM_x; 180 break; 181 case IXGBE_DEV_ID_X550EM_A_KR: 182 case IXGBE_DEV_ID_X550EM_A_KR_L: 183 case IXGBE_DEV_ID_X550EM_A_SFP_N: 184 case IXGBE_DEV_ID_X550EM_A_1G_T: 185 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 186 case IXGBE_DEV_ID_X550EM_A_10G_T: 187 case IXGBE_DEV_ID_X550EM_A_QSFP: 188 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 189 case IXGBE_DEV_ID_X550EM_A_SFP: 190 hw->mac.type = ixgbe_mac_X550EM_a; 191 break; 192 case IXGBE_DEV_ID_X550_VF: 193 case IXGBE_DEV_ID_X550_VF_HV: 194 hw->mac.type = ixgbe_mac_X550_vf; 195 break; 196 case IXGBE_DEV_ID_X550EM_X_VF: 197 case IXGBE_DEV_ID_X550EM_X_VF_HV: 198 hw->mac.type = ixgbe_mac_X550EM_x_vf; 199 break; 200 case IXGBE_DEV_ID_X550EM_A_VF: 201 case IXGBE_DEV_ID_X550EM_A_VF_HV: 202 hw->mac.type = ixgbe_mac_X550EM_a_vf; 203 break; 204 default: 205 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 206 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 207 "Unsupported device id: %x", 208 hw->device_id); 209 break; 210 } 211 212 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 213 hw->mac.type, ret_val); 214 return ret_val; 215 } 216 217 /** 218 * ixgbe_init_hw - Initialize the hardware 219 * @hw: pointer to hardware structure 220 * 221 * Initialize the hardware by resetting and then starting the hardware 222 **/ 223 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 224 { 225 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 226 IXGBE_NOT_IMPLEMENTED); 227 } 228 229 /** 230 * ixgbe_reset_hw - Performs a hardware reset 231 * @hw: pointer to hardware structure 232 * 233 * Resets the hardware by resetting the transmit and receive units, masks and 234 * clears all interrupts, performs a PHY reset, and performs a MAC reset 235 **/ 236 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 237 { 238 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 239 IXGBE_NOT_IMPLEMENTED); 240 } 241 242 /** 243 * ixgbe_start_hw - Prepares hardware for Rx/Tx 244 * @hw: pointer to hardware structure 245 * 246 * Starts the hardware by filling the bus info structure and media type, 247 * clears all on chip counters, initializes receive address registers, 248 * multicast table, VLAN filter table, calls routine to setup link and 249 * flow control settings, and leaves transmit and receive units disabled 250 * and uninitialized. 251 **/ 252 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 253 { 254 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 255 IXGBE_NOT_IMPLEMENTED); 256 } 257 258 /** 259 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 260 * which is disabled by default in ixgbe_start_hw(); 261 * 262 * @hw: pointer to hardware structure 263 * 264 * Enable relaxed ordering; 265 **/ 266 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 267 { 268 if (hw->mac.ops.enable_relaxed_ordering) 269 hw->mac.ops.enable_relaxed_ordering(hw); 270 } 271 272 /** 273 * ixgbe_clear_hw_cntrs - Clear hardware counters 274 * @hw: pointer to hardware structure 275 * 276 * Clears all hardware statistics counters by reading them from the hardware 277 * Statistics counters are clear on read. 278 **/ 279 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 280 { 281 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 282 IXGBE_NOT_IMPLEMENTED); 283 } 284 285 /** 286 * ixgbe_get_media_type - Get media type 287 * @hw: pointer to hardware structure 288 * 289 * Returns the media type (fiber, copper, backplane) 290 **/ 291 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 292 { 293 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 294 ixgbe_media_type_unknown); 295 } 296 297 /** 298 * ixgbe_get_mac_addr - Get MAC address 299 * @hw: pointer to hardware structure 300 * @mac_addr: Adapter MAC address 301 * 302 * Reads the adapter's MAC address from the first Receive Address Register 303 * (RAR0) A reset of the adapter must have been performed prior to calling 304 * this function in order for the MAC address to have been loaded from the 305 * EEPROM into RAR0 306 **/ 307 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 308 { 309 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 310 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 311 } 312 313 /** 314 * ixgbe_get_san_mac_addr - Get SAN MAC address 315 * @hw: pointer to hardware structure 316 * @san_mac_addr: SAN MAC address 317 * 318 * Reads the SAN MAC address from the EEPROM, if it's available. This is 319 * per-port, so set_lan_id() must be called before reading the addresses. 320 **/ 321 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 322 { 323 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 324 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 325 } 326 327 /** 328 * ixgbe_set_san_mac_addr - Write a SAN MAC address 329 * @hw: pointer to hardware structure 330 * @san_mac_addr: SAN MAC address 331 * 332 * Writes A SAN MAC address to the EEPROM. 333 **/ 334 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 335 { 336 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 337 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 338 } 339 340 /** 341 * ixgbe_get_device_caps - Get additional device capabilities 342 * @hw: pointer to hardware structure 343 * @device_caps: the EEPROM word for device capabilities 344 * 345 * Reads the extra device capabilities from the EEPROM 346 **/ 347 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 348 { 349 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 350 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 351 } 352 353 /** 354 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 355 * @hw: pointer to hardware structure 356 * @wwnn_prefix: the alternative WWNN prefix 357 * @wwpn_prefix: the alternative WWPN prefix 358 * 359 * This function will read the EEPROM from the alternative SAN MAC address 360 * block to check the support for the alternative WWNN/WWPN prefix support. 361 **/ 362 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 363 u16 *wwpn_prefix) 364 { 365 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 366 (hw, wwnn_prefix, wwpn_prefix), 367 IXGBE_NOT_IMPLEMENTED); 368 } 369 370 /** 371 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 372 * @hw: pointer to hardware structure 373 * @bs: the fcoe boot status 374 * 375 * This function will read the FCOE boot status from the iSCSI FCOE block 376 **/ 377 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 378 { 379 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 380 (hw, bs), 381 IXGBE_NOT_IMPLEMENTED); 382 } 383 384 /** 385 * ixgbe_get_bus_info - Set PCI bus info 386 * @hw: pointer to hardware structure 387 * 388 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 389 **/ 390 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 391 { 392 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 393 IXGBE_NOT_IMPLEMENTED); 394 } 395 396 /** 397 * ixgbe_get_num_of_tx_queues - Get Tx queues 398 * @hw: pointer to hardware structure 399 * 400 * Returns the number of transmit queues for the given adapter. 401 **/ 402 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 403 { 404 return hw->mac.max_tx_queues; 405 } 406 407 /** 408 * ixgbe_get_num_of_rx_queues - Get Rx queues 409 * @hw: pointer to hardware structure 410 * 411 * Returns the number of receive queues for the given adapter. 412 **/ 413 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 414 { 415 return hw->mac.max_rx_queues; 416 } 417 418 /** 419 * ixgbe_stop_adapter - Disable Rx/Tx units 420 * @hw: pointer to hardware structure 421 * 422 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 423 * disables transmit and receive units. The adapter_stopped flag is used by 424 * the shared code and drivers to determine if the adapter is in a stopped 425 * state and should not touch the hardware. 426 **/ 427 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 428 { 429 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 430 IXGBE_NOT_IMPLEMENTED); 431 } 432 433 /** 434 * ixgbe_read_pba_string - Reads part number string from EEPROM 435 * @hw: pointer to hardware structure 436 * @pba_num: stores the part number string from the EEPROM 437 * @pba_num_size: part number string buffer length 438 * 439 * Reads the part number string from the EEPROM. 440 **/ 441 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 442 { 443 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 444 } 445 446 /** 447 * ixgbe_read_pba_num - Reads part number from EEPROM 448 * @hw: pointer to hardware structure 449 * @pba_num: stores the part number from the EEPROM 450 * 451 * Reads the part number from the EEPROM. 452 **/ 453 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 454 { 455 return ixgbe_read_pba_num_generic(hw, pba_num); 456 } 457 458 /** 459 * ixgbe_identify_phy - Get PHY type 460 * @hw: pointer to hardware structure 461 * 462 * Determines the physical layer module found on the current adapter. 463 **/ 464 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 465 { 466 s32 status = IXGBE_SUCCESS; 467 468 if (hw->phy.type == ixgbe_phy_unknown) { 469 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 470 IXGBE_NOT_IMPLEMENTED); 471 } 472 473 return status; 474 } 475 476 /** 477 * ixgbe_reset_phy - Perform a PHY reset 478 * @hw: pointer to hardware structure 479 **/ 480 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 481 { 482 s32 status = IXGBE_SUCCESS; 483 484 if (hw->phy.type == ixgbe_phy_unknown) { 485 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 486 status = IXGBE_ERR_PHY; 487 } 488 489 if (status == IXGBE_SUCCESS) { 490 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 491 IXGBE_NOT_IMPLEMENTED); 492 } 493 return status; 494 } 495 496 /** 497 * ixgbe_get_phy_firmware_version - 498 * @hw: pointer to hardware structure 499 * @firmware_version: pointer to firmware version 500 **/ 501 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 502 { 503 s32 status = IXGBE_SUCCESS; 504 505 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 506 (hw, firmware_version), 507 IXGBE_NOT_IMPLEMENTED); 508 return status; 509 } 510 511 /** 512 * ixgbe_read_phy_reg - Read PHY register 513 * @hw: pointer to hardware structure 514 * @reg_addr: 32 bit address of PHY register to read 515 * @phy_data: Pointer to read data from PHY register 516 * 517 * Reads a value from a specified PHY register 518 **/ 519 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 520 u16 *phy_data) 521 { 522 if (hw->phy.id == 0) 523 ixgbe_identify_phy(hw); 524 525 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 526 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 527 } 528 529 /** 530 * ixgbe_write_phy_reg - Write PHY register 531 * @hw: pointer to hardware structure 532 * @reg_addr: 32 bit PHY register to write 533 * @phy_data: Data to write to the PHY register 534 * 535 * Writes a value to specified PHY register 536 **/ 537 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 538 u16 phy_data) 539 { 540 if (hw->phy.id == 0) 541 ixgbe_identify_phy(hw); 542 543 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 544 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 545 } 546 547 /** 548 * ixgbe_setup_phy_link - Restart PHY autoneg 549 * @hw: pointer to hardware structure 550 * 551 * Restart autonegotiation and PHY and waits for completion. 552 **/ 553 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 554 { 555 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 556 IXGBE_NOT_IMPLEMENTED); 557 } 558 559 /** 560 * ixgbe_setup_internal_phy - Configure integrated PHY 561 * @hw: pointer to hardware structure 562 * 563 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 564 * Returns success if not implemented, since nothing needs to be done in this 565 * case. 566 */ 567 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 568 { 569 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 570 IXGBE_SUCCESS); 571 } 572 573 /** 574 * ixgbe_check_phy_link - Determine link and speed status 575 * @hw: pointer to hardware structure 576 * 577 * Reads a PHY register to determine if link is up and the current speed for 578 * the PHY. 579 **/ 580 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 581 bool *link_up) 582 { 583 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 584 link_up), IXGBE_NOT_IMPLEMENTED); 585 } 586 587 /** 588 * ixgbe_setup_phy_link_speed - Set auto advertise 589 * @hw: pointer to hardware structure 590 * @speed: new link speed 591 * 592 * Sets the auto advertised capabilities 593 **/ 594 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 595 bool autoneg_wait_to_complete) 596 { 597 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 598 autoneg_wait_to_complete), 599 IXGBE_NOT_IMPLEMENTED); 600 } 601 602 /** 603 * ixgbe_set_phy_power - Control the phy power state 604 * @hw: pointer to hardware structure 605 * @on: TRUE for on, FALSE for off 606 */ 607 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 608 { 609 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 610 IXGBE_NOT_IMPLEMENTED); 611 } 612 613 /** 614 * ixgbe_check_link - Get link and speed status 615 * @hw: pointer to hardware structure 616 * 617 * Reads the links register to determine if link is up and the current speed 618 **/ 619 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 620 bool *link_up, bool link_up_wait_to_complete) 621 { 622 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 623 link_up, link_up_wait_to_complete), 624 IXGBE_NOT_IMPLEMENTED); 625 } 626 627 /** 628 * ixgbe_disable_tx_laser - Disable Tx laser 629 * @hw: pointer to hardware structure 630 * 631 * If the driver needs to disable the laser on SFI optics. 632 **/ 633 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 634 { 635 if (hw->mac.ops.disable_tx_laser) 636 hw->mac.ops.disable_tx_laser(hw); 637 } 638 639 /** 640 * ixgbe_enable_tx_laser - Enable Tx laser 641 * @hw: pointer to hardware structure 642 * 643 * If the driver needs to enable the laser on SFI optics. 644 **/ 645 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 646 { 647 if (hw->mac.ops.enable_tx_laser) 648 hw->mac.ops.enable_tx_laser(hw); 649 } 650 651 /** 652 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 653 * @hw: pointer to hardware structure 654 * 655 * When the driver changes the link speeds that it can support then 656 * flap the tx laser to alert the link partner to start autotry 657 * process on its end. 658 **/ 659 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 660 { 661 if (hw->mac.ops.flap_tx_laser) 662 hw->mac.ops.flap_tx_laser(hw); 663 } 664 665 /** 666 * ixgbe_setup_link - Set link speed 667 * @hw: pointer to hardware structure 668 * @speed: new link speed 669 * 670 * Configures link settings. Restarts the link. 671 * Performs autonegotiation if needed. 672 **/ 673 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 674 bool autoneg_wait_to_complete) 675 { 676 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 677 autoneg_wait_to_complete), 678 IXGBE_NOT_IMPLEMENTED); 679 } 680 681 /** 682 * ixgbe_setup_mac_link - Set link speed 683 * @hw: pointer to hardware structure 684 * @speed: new link speed 685 * 686 * Configures link settings. Restarts the link. 687 * Performs autonegotiation if needed. 688 **/ 689 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 690 bool autoneg_wait_to_complete) 691 { 692 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 693 autoneg_wait_to_complete), 694 IXGBE_NOT_IMPLEMENTED); 695 } 696 697 /** 698 * ixgbe_get_link_capabilities - Returns link capabilities 699 * @hw: pointer to hardware structure 700 * 701 * Determines the link capabilities of the current configuration. 702 **/ 703 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 704 bool *autoneg) 705 { 706 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 707 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 708 } 709 710 /** 711 * ixgbe_led_on - Turn on LEDs 712 * @hw: pointer to hardware structure 713 * @index: led number to turn on 714 * 715 * Turns on the software controllable LEDs. 716 **/ 717 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 718 { 719 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 720 IXGBE_NOT_IMPLEMENTED); 721 } 722 723 /** 724 * ixgbe_led_off - Turn off LEDs 725 * @hw: pointer to hardware structure 726 * @index: led number to turn off 727 * 728 * Turns off the software controllable LEDs. 729 **/ 730 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 731 { 732 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 733 IXGBE_NOT_IMPLEMENTED); 734 } 735 736 /** 737 * ixgbe_blink_led_start - Blink LEDs 738 * @hw: pointer to hardware structure 739 * @index: led number to blink 740 * 741 * Blink LED based on index. 742 **/ 743 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 744 { 745 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 746 IXGBE_NOT_IMPLEMENTED); 747 } 748 749 /** 750 * ixgbe_blink_led_stop - Stop blinking LEDs 751 * @hw: pointer to hardware structure 752 * 753 * Stop blinking LED based on index. 754 **/ 755 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 756 { 757 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 758 IXGBE_NOT_IMPLEMENTED); 759 } 760 761 /** 762 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 763 * @hw: pointer to hardware structure 764 * 765 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 766 * ixgbe_hw struct in order to set up EEPROM access. 767 **/ 768 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 769 { 770 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 771 IXGBE_NOT_IMPLEMENTED); 772 } 773 774 775 /** 776 * ixgbe_write_eeprom - Write word to EEPROM 777 * @hw: pointer to hardware structure 778 * @offset: offset within the EEPROM to be written to 779 * @data: 16 bit word to be written to the EEPROM 780 * 781 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 782 * called after this function, the EEPROM will most likely contain an 783 * invalid checksum. 784 **/ 785 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 786 { 787 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 788 IXGBE_NOT_IMPLEMENTED); 789 } 790 791 /** 792 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 793 * @hw: pointer to hardware structure 794 * @offset: offset within the EEPROM to be written to 795 * @data: 16 bit word(s) to be written to the EEPROM 796 * @words: number of words 797 * 798 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 799 * called after this function, the EEPROM will most likely contain an 800 * invalid checksum. 801 **/ 802 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 803 u16 *data) 804 { 805 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 806 (hw, offset, words, data), 807 IXGBE_NOT_IMPLEMENTED); 808 } 809 810 /** 811 * ixgbe_read_eeprom - Read word from EEPROM 812 * @hw: pointer to hardware structure 813 * @offset: offset within the EEPROM to be read 814 * @data: read 16 bit value from EEPROM 815 * 816 * Reads 16 bit value from EEPROM 817 **/ 818 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 819 { 820 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 821 IXGBE_NOT_IMPLEMENTED); 822 } 823 824 /** 825 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 826 * @hw: pointer to hardware structure 827 * @offset: offset within the EEPROM to be read 828 * @data: read 16 bit word(s) from EEPROM 829 * @words: number of words 830 * 831 * Reads 16 bit word(s) from EEPROM 832 **/ 833 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 834 u16 words, u16 *data) 835 { 836 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 837 (hw, offset, words, data), 838 IXGBE_NOT_IMPLEMENTED); 839 } 840 841 /** 842 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 843 * @hw: pointer to hardware structure 844 * @checksum_val: calculated checksum 845 * 846 * Performs checksum calculation and validates the EEPROM checksum 847 **/ 848 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 849 { 850 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 851 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 852 } 853 854 /** 855 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 856 * @hw: pointer to hardware structure 857 **/ 858 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 859 { 860 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 861 IXGBE_NOT_IMPLEMENTED); 862 } 863 864 /** 865 * ixgbe_insert_mac_addr - Find a RAR for this mac address 866 * @hw: pointer to hardware structure 867 * @addr: Address to put into receive address register 868 * @vmdq: VMDq pool to assign 869 * 870 * Puts an ethernet address into a receive address register, or 871 * finds the rar that it is aleady in; adds to the pool list 872 **/ 873 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 874 { 875 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 876 (hw, addr, vmdq), 877 IXGBE_NOT_IMPLEMENTED); 878 } 879 880 /** 881 * ixgbe_set_rar - Set Rx address register 882 * @hw: pointer to hardware structure 883 * @index: Receive address register to write 884 * @addr: Address to put into receive address register 885 * @vmdq: VMDq "set" 886 * @enable_addr: set flag that address is active 887 * 888 * Puts an ethernet address into a receive address register. 889 **/ 890 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 891 u32 enable_addr) 892 { 893 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 894 enable_addr), IXGBE_NOT_IMPLEMENTED); 895 } 896 897 /** 898 * ixgbe_clear_rar - Clear Rx address register 899 * @hw: pointer to hardware structure 900 * @index: Receive address register to write 901 * 902 * Puts an ethernet address into a receive address register. 903 **/ 904 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 905 { 906 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 907 IXGBE_NOT_IMPLEMENTED); 908 } 909 910 /** 911 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 912 * @hw: pointer to hardware structure 913 * @rar: receive address register index to associate with VMDq index 914 * @vmdq: VMDq set or pool index 915 **/ 916 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 917 { 918 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 919 IXGBE_NOT_IMPLEMENTED); 920 921 } 922 923 /** 924 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 925 * @hw: pointer to hardware structure 926 * @vmdq: VMDq default pool index 927 **/ 928 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 929 { 930 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 931 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 932 } 933 934 /** 935 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 936 * @hw: pointer to hardware structure 937 * @rar: receive address register index to disassociate with VMDq index 938 * @vmdq: VMDq set or pool index 939 **/ 940 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 941 { 942 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 943 IXGBE_NOT_IMPLEMENTED); 944 } 945 946 /** 947 * ixgbe_init_rx_addrs - Initializes receive address filters. 948 * @hw: pointer to hardware structure 949 * 950 * Places the MAC address in receive address register 0 and clears the rest 951 * of the receive address registers. Clears the multicast table. Assumes 952 * the receiver is in reset when the routine is called. 953 **/ 954 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 955 { 956 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 957 IXGBE_NOT_IMPLEMENTED); 958 } 959 960 /** 961 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 962 * @hw: pointer to hardware structure 963 **/ 964 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 965 { 966 return hw->mac.num_rar_entries; 967 } 968 969 /** 970 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 971 * @hw: pointer to hardware structure 972 * @addr_list: the list of new multicast addresses 973 * @addr_count: number of addresses 974 * @func: iterator function to walk the multicast address list 975 * 976 * The given list replaces any existing list. Clears the secondary addrs from 977 * receive address registers. Uses unused receive address registers for the 978 * first secondary addresses, and falls back to promiscuous mode as needed. 979 **/ 980 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 981 u32 addr_count, ixgbe_mc_addr_itr func) 982 { 983 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 984 addr_list, addr_count, func), 985 IXGBE_NOT_IMPLEMENTED); 986 } 987 988 /** 989 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 990 * @hw: pointer to hardware structure 991 * @mc_addr_list: the list of new multicast addresses 992 * @mc_addr_count: number of addresses 993 * @func: iterator function to walk the multicast address list 994 * 995 * The given list replaces any existing list. Clears the MC addrs from receive 996 * address registers and the multicast table. Uses unused receive address 997 * registers for the first multicast addresses, and hashes the rest into the 998 * multicast table. 999 **/ 1000 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1001 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1002 bool clear) 1003 { 1004 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1005 mc_addr_list, mc_addr_count, func, clear), 1006 IXGBE_NOT_IMPLEMENTED); 1007 } 1008 1009 /** 1010 * ixgbe_enable_mc - Enable multicast address in RAR 1011 * @hw: pointer to hardware structure 1012 * 1013 * Enables multicast address in RAR and the use of the multicast hash table. 1014 **/ 1015 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1016 { 1017 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1018 IXGBE_NOT_IMPLEMENTED); 1019 } 1020 1021 /** 1022 * ixgbe_disable_mc - Disable multicast address in RAR 1023 * @hw: pointer to hardware structure 1024 * 1025 * Disables multicast address in RAR and the use of the multicast hash table. 1026 **/ 1027 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1028 { 1029 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1030 IXGBE_NOT_IMPLEMENTED); 1031 } 1032 1033 /** 1034 * ixgbe_clear_vfta - Clear VLAN filter table 1035 * @hw: pointer to hardware structure 1036 * 1037 * Clears the VLAN filer table, and the VMDq index associated with the filter 1038 **/ 1039 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1040 { 1041 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1042 IXGBE_NOT_IMPLEMENTED); 1043 } 1044 1045 /** 1046 * ixgbe_set_vfta - Set VLAN filter table 1047 * @hw: pointer to hardware structure 1048 * @vlan: VLAN id to write to VLAN filter 1049 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1050 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1051 * 1052 * Turn on/off specified VLAN in the VLAN filter table. 1053 **/ 1054 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 1055 { 1056 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1057 vlan_on), IXGBE_NOT_IMPLEMENTED); 1058 } 1059 1060 /** 1061 * ixgbe_set_vlvf - Set VLAN Pool Filter 1062 * @hw: pointer to hardware structure 1063 * @vlan: VLAN id to write to VLAN filter 1064 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 1065 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 1066 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 1067 * should be changed 1068 * 1069 * Turn on/off specified bit in VLVF table. 1070 **/ 1071 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1072 bool *vfta_changed) 1073 { 1074 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1075 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED); 1076 } 1077 1078 /** 1079 * ixgbe_fc_enable - Enable flow control 1080 * @hw: pointer to hardware structure 1081 * 1082 * Configures the flow control settings based on SW configuration. 1083 **/ 1084 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1085 { 1086 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1087 IXGBE_NOT_IMPLEMENTED); 1088 } 1089 1090 /** 1091 * ixgbe_setup_fc - Set up flow control 1092 * @hw: pointer to hardware structure 1093 * 1094 * Called at init time to set up flow control. 1095 **/ 1096 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1097 { 1098 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1099 IXGBE_NOT_IMPLEMENTED); 1100 } 1101 1102 /** 1103 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1104 * @hw: pointer to hardware structure 1105 * @maj: driver major number to be sent to firmware 1106 * @min: driver minor number to be sent to firmware 1107 * @build: driver build number to be sent to firmware 1108 * @ver: driver version number to be sent to firmware 1109 **/ 1110 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1111 u8 ver) 1112 { 1113 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1114 build, ver), IXGBE_NOT_IMPLEMENTED); 1115 } 1116 1117 1118 1119 /** 1120 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1121 * @hw: pointer to hardware structure 1122 * 1123 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1124 * When disabling dmac, dmac enable dmac bit is cleared. 1125 **/ 1126 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1127 { 1128 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1129 IXGBE_NOT_IMPLEMENTED); 1130 } 1131 1132 /** 1133 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1134 * @hw: pointer to hardware structure 1135 * 1136 * Disables dmac, updates per TC settings, and then enable dmac. 1137 **/ 1138 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1139 { 1140 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1141 IXGBE_NOT_IMPLEMENTED); 1142 } 1143 1144 /** 1145 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1146 * @hw: pointer to hardware structure 1147 * 1148 * Configure DMA coalescing threshold per TC and set high priority bit for 1149 * FCOE TC. The dmac enable bit must be cleared before configuring. 1150 **/ 1151 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1152 { 1153 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1154 IXGBE_NOT_IMPLEMENTED); 1155 } 1156 1157 /** 1158 * ixgbe_setup_eee - Enable/disable EEE support 1159 * @hw: pointer to the HW structure 1160 * @enable_eee: boolean flag to enable EEE 1161 * 1162 * Enable/disable EEE based on enable_ee flag. 1163 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1164 * are modified. 1165 * 1166 **/ 1167 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1168 { 1169 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1170 IXGBE_NOT_IMPLEMENTED); 1171 } 1172 1173 /** 1174 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1175 * @hw: pointer to hardware structure 1176 * @enbale: enable or disable source address pruning 1177 * @pool: Rx pool - Rx pool to toggle source address pruning 1178 **/ 1179 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1180 unsigned int pool) 1181 { 1182 if (hw->mac.ops.set_source_address_pruning) 1183 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1184 } 1185 1186 /** 1187 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1188 * @hw: pointer to hardware structure 1189 * @enable: enable or disable switch for Ethertype anti-spoofing 1190 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1191 * 1192 **/ 1193 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1194 { 1195 if (hw->mac.ops.set_ethertype_anti_spoofing) 1196 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1197 } 1198 1199 /** 1200 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1201 * @hw: pointer to hardware structure 1202 * @reg_addr: 32 bit address of PHY register to read 1203 * @device_type: type of device you want to communicate with 1204 * @phy_data: Pointer to read data from PHY register 1205 * 1206 * Reads a value from a specified PHY register 1207 **/ 1208 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1209 u32 device_type, u32 *phy_data) 1210 { 1211 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1212 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1213 } 1214 1215 /** 1216 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1217 * @hw: pointer to hardware structure 1218 * @reg_addr: 32 bit PHY register to write 1219 * @device_type: type of device you want to communicate with 1220 * @phy_data: Data to write to the PHY register 1221 * 1222 * Writes a value to specified PHY register 1223 **/ 1224 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1225 u32 device_type, u32 phy_data) 1226 { 1227 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1228 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1229 } 1230 1231 /** 1232 * ixgbe_disable_mdd - Disable malicious driver detection 1233 * @hw: pointer to hardware structure 1234 * 1235 **/ 1236 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1237 { 1238 if (hw->mac.ops.disable_mdd) 1239 hw->mac.ops.disable_mdd(hw); 1240 } 1241 1242 /** 1243 * ixgbe_enable_mdd - Enable malicious driver detection 1244 * @hw: pointer to hardware structure 1245 * 1246 **/ 1247 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1248 { 1249 if (hw->mac.ops.enable_mdd) 1250 hw->mac.ops.enable_mdd(hw); 1251 } 1252 1253 /** 1254 * ixgbe_mdd_event - Handle malicious driver detection event 1255 * @hw: pointer to hardware structure 1256 * @vf_bitmap: vf bitmap of malicious vfs 1257 * 1258 **/ 1259 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1260 { 1261 if (hw->mac.ops.mdd_event) 1262 hw->mac.ops.mdd_event(hw, vf_bitmap); 1263 } 1264 1265 /** 1266 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1267 * detection event 1268 * @hw: pointer to hardware structure 1269 * @vf: vf index 1270 * 1271 **/ 1272 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1273 { 1274 if (hw->mac.ops.restore_mdd_vf) 1275 hw->mac.ops.restore_mdd_vf(hw, vf); 1276 } 1277 1278 /** 1279 * ixgbe_enter_lplu - Transition to low power states 1280 * @hw: pointer to hardware structure 1281 * 1282 * Configures Low Power Link Up on transition to low power states 1283 * (from D0 to non-D0). 1284 **/ 1285 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1286 { 1287 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1288 IXGBE_NOT_IMPLEMENTED); 1289 } 1290 1291 /** 1292 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1293 * @hw: pointer to hardware structure 1294 * 1295 * Handle external Base T PHY interrupt. If high temperature 1296 * failure alarm then return error, else if link status change 1297 * then setup internal/external PHY link 1298 * 1299 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1300 * failure alarm, else return PHY access status. 1301 */ 1302 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1303 { 1304 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1305 IXGBE_NOT_IMPLEMENTED); 1306 } 1307 1308 /** 1309 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1310 * @hw: pointer to hardware structure 1311 * @reg: analog register to read 1312 * @val: read value 1313 * 1314 * Performs write operation to analog register specified. 1315 **/ 1316 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1317 { 1318 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1319 val), IXGBE_NOT_IMPLEMENTED); 1320 } 1321 1322 /** 1323 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1324 * @hw: pointer to hardware structure 1325 * @reg: analog register to write 1326 * @val: value to write 1327 * 1328 * Performs write operation to Atlas analog register specified. 1329 **/ 1330 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1331 { 1332 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1333 val), IXGBE_NOT_IMPLEMENTED); 1334 } 1335 1336 /** 1337 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1338 * @hw: pointer to hardware structure 1339 * 1340 * Initializes the Unicast Table Arrays to zero on device load. This 1341 * is part of the Rx init addr execution path. 1342 **/ 1343 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1344 { 1345 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1346 IXGBE_NOT_IMPLEMENTED); 1347 } 1348 1349 /** 1350 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1351 * @hw: pointer to hardware structure 1352 * @byte_offset: byte offset to read 1353 * @dev_addr: I2C bus address to read from 1354 * @data: value read 1355 * 1356 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1357 **/ 1358 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1359 u8 *data) 1360 { 1361 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1362 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1363 } 1364 1365 /** 1366 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1367 * @hw: pointer to hardware structure 1368 * @byte_offset: byte offset to read 1369 * @dev_addr: I2C bus address to read from 1370 * @data: value read 1371 * 1372 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1373 **/ 1374 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1375 u8 dev_addr, u8 *data) 1376 { 1377 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1378 (hw, byte_offset, dev_addr, data), 1379 IXGBE_NOT_IMPLEMENTED); 1380 } 1381 1382 /** 1383 * ixgbe_read_i2c_combined - Perform I2C read combined operation 1384 * @hw: pointer to the hardware structure 1385 * @addr: I2C bus address to read from 1386 * @reg: I2C device register to read from 1387 * @val: pointer to location to receive read value 1388 * 1389 * Returns an error code on error. 1390 */ 1391 s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1392 { 1393 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr, 1394 reg, val), IXGBE_NOT_IMPLEMENTED); 1395 } 1396 1397 /** 1398 * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation 1399 * @hw: pointer to the hardware structure 1400 * @addr: I2C bus address to read from 1401 * @reg: I2C device register to read from 1402 * @val: pointer to location to receive read value 1403 * 1404 * Returns an error code on error. 1405 **/ 1406 s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1407 u16 *val) 1408 { 1409 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked, 1410 (hw, addr, reg, val), 1411 IXGBE_NOT_IMPLEMENTED); 1412 } 1413 1414 /** 1415 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1416 * @hw: pointer to hardware structure 1417 * @byte_offset: byte offset to write 1418 * @dev_addr: I2C bus address to write to 1419 * @data: value to write 1420 * 1421 * Performs byte write operation to SFP module's EEPROM over I2C interface 1422 * at a specified device address. 1423 **/ 1424 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1425 u8 data) 1426 { 1427 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1428 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1429 } 1430 1431 /** 1432 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1433 * @hw: pointer to hardware structure 1434 * @byte_offset: byte offset to write 1435 * @dev_addr: I2C bus address to write to 1436 * @data: value to write 1437 * 1438 * Performs byte write operation to SFP module's EEPROM over I2C interface 1439 * at a specified device address. 1440 **/ 1441 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1442 u8 dev_addr, u8 data) 1443 { 1444 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1445 (hw, byte_offset, dev_addr, data), 1446 IXGBE_NOT_IMPLEMENTED); 1447 } 1448 1449 /** 1450 * ixgbe_write_i2c_combined - Perform I2C write combined operation 1451 * @hw: pointer to the hardware structure 1452 * @addr: I2C bus address to write to 1453 * @reg: I2C device register to write to 1454 * @val: value to write 1455 * 1456 * Returns an error code on error. 1457 */ 1458 s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1459 { 1460 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr, 1461 reg, val), IXGBE_NOT_IMPLEMENTED); 1462 } 1463 1464 /** 1465 * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation 1466 * @hw: pointer to the hardware structure 1467 * @addr: I2C bus address to write to 1468 * @reg: I2C device register to write to 1469 * @val: value to write 1470 * 1471 * Returns an error code on error. 1472 **/ 1473 s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1474 u16 val) 1475 { 1476 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked, 1477 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1478 } 1479 1480 /** 1481 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1482 * @hw: pointer to hardware structure 1483 * @byte_offset: EEPROM byte offset to write 1484 * @eeprom_data: value to write 1485 * 1486 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1487 **/ 1488 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1489 u8 byte_offset, u8 eeprom_data) 1490 { 1491 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1492 (hw, byte_offset, eeprom_data), 1493 IXGBE_NOT_IMPLEMENTED); 1494 } 1495 1496 /** 1497 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1498 * @hw: pointer to hardware structure 1499 * @byte_offset: EEPROM byte offset to read 1500 * @eeprom_data: value read 1501 * 1502 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1503 **/ 1504 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1505 { 1506 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1507 (hw, byte_offset, eeprom_data), 1508 IXGBE_NOT_IMPLEMENTED); 1509 } 1510 1511 /** 1512 * ixgbe_get_supported_physical_layer - Returns physical layer type 1513 * @hw: pointer to hardware structure 1514 * 1515 * Determines physical layer capabilities of the current configuration. 1516 **/ 1517 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1518 { 1519 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1520 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1521 } 1522 1523 /** 1524 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1525 * @hw: pointer to hardware structure 1526 * @regval: bitfield to write to the Rx DMA register 1527 * 1528 * Enables the Rx DMA unit of the device. 1529 **/ 1530 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1531 { 1532 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1533 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1534 } 1535 1536 /** 1537 * ixgbe_disable_sec_rx_path - Stops the receive data path 1538 * @hw: pointer to hardware structure 1539 * 1540 * Stops the receive data path. 1541 **/ 1542 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1543 { 1544 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1545 (hw), IXGBE_NOT_IMPLEMENTED); 1546 } 1547 1548 /** 1549 * ixgbe_enable_sec_rx_path - Enables the receive data path 1550 * @hw: pointer to hardware structure 1551 * 1552 * Enables the receive data path. 1553 **/ 1554 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1555 { 1556 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1557 (hw), IXGBE_NOT_IMPLEMENTED); 1558 } 1559 1560 /** 1561 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1562 * @hw: pointer to hardware structure 1563 * @mask: Mask to specify which semaphore to acquire 1564 * 1565 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1566 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1567 **/ 1568 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1569 { 1570 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1571 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1572 } 1573 1574 /** 1575 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1576 * @hw: pointer to hardware structure 1577 * @mask: Mask to specify which semaphore to release 1578 * 1579 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1580 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1581 **/ 1582 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1583 { 1584 if (hw->mac.ops.release_swfw_sync) 1585 hw->mac.ops.release_swfw_sync(hw, mask); 1586 } 1587 1588 1589 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1590 { 1591 if (hw->mac.ops.disable_rx) 1592 hw->mac.ops.disable_rx(hw); 1593 } 1594 1595 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1596 { 1597 if (hw->mac.ops.enable_rx) 1598 hw->mac.ops.enable_rx(hw); 1599 } 1600 1601 /** 1602 * ixgbe_set_rate_select_speed - Set module link speed 1603 * @hw: pointer to hardware structure 1604 * @speed: link speed to set 1605 * 1606 * Set module link speed via the rate select. 1607 */ 1608 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1609 { 1610 if (hw->mac.ops.set_rate_select_speed) 1611 hw->mac.ops.set_rate_select_speed(hw, speed); 1612 } 1613