1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 38 #define IXGBE_EMPTY_PARAM 39 40 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 41 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 42 }; 43 44 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 45 IXGBE_MVALS_INIT(_X540) 46 }; 47 48 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 49 IXGBE_MVALS_INIT(_X550) 50 }; 51 52 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 53 IXGBE_MVALS_INIT(_X550EM_x) 54 }; 55 56 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 57 IXGBE_MVALS_INIT(_X550EM_a) 58 }; 59 60 /** 61 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 62 * @hw: pointer to hardware structure 63 * @map: pointer to u8 arr for returning map 64 * 65 * Read the rtrup2tc HW register and resolve its content into map 66 **/ 67 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 68 { 69 if (hw->mac.ops.get_rtrup2tc) 70 hw->mac.ops.get_rtrup2tc(hw, map); 71 } 72 73 /** 74 * ixgbe_init_shared_code - Initialize the shared code 75 * @hw: pointer to hardware structure 76 * 77 * This will assign function pointers and assign the MAC type and PHY code. 78 * Does not touch the hardware. This function must be called prior to any 79 * other function in the shared code. The ixgbe_hw structure should be 80 * memset to 0 prior to calling this function. The following fields in 81 * hw structure should be filled in prior to calling this function: 82 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 83 * subsystem_vendor_id, and revision_id 84 **/ 85 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 86 { 87 s32 status; 88 89 DEBUGFUNC("ixgbe_init_shared_code"); 90 91 /* 92 * Set the mac type 93 */ 94 ixgbe_set_mac_type(hw); 95 96 switch (hw->mac.type) { 97 case ixgbe_mac_82598EB: 98 status = ixgbe_init_ops_82598(hw); 99 break; 100 case ixgbe_mac_82599EB: 101 status = ixgbe_init_ops_82599(hw); 102 break; 103 case ixgbe_mac_X540: 104 status = ixgbe_init_ops_X540(hw); 105 break; 106 case ixgbe_mac_X550: 107 status = ixgbe_init_ops_X550(hw); 108 break; 109 case ixgbe_mac_X550EM_x: 110 status = ixgbe_init_ops_X550EM_x(hw); 111 break; 112 case ixgbe_mac_X550EM_a: 113 status = ixgbe_init_ops_X550EM_a(hw); 114 break; 115 default: 116 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 117 break; 118 } 119 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 120 121 return status; 122 } 123 124 /** 125 * ixgbe_set_mac_type - Sets MAC type 126 * @hw: pointer to the HW structure 127 * 128 * This function sets the mac type of the adapter based on the 129 * vendor ID and device ID stored in the hw structure. 130 **/ 131 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 132 { 133 s32 ret_val = IXGBE_SUCCESS; 134 135 DEBUGFUNC("ixgbe_set_mac_type\n"); 136 137 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 138 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 139 "Unsupported vendor id: %x", hw->vendor_id); 140 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 141 } 142 143 hw->mvals = ixgbe_mvals_base; 144 145 switch (hw->device_id) { 146 case IXGBE_DEV_ID_82598: 147 case IXGBE_DEV_ID_82598_BX: 148 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 149 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 150 case IXGBE_DEV_ID_82598AT: 151 case IXGBE_DEV_ID_82598AT2: 152 case IXGBE_DEV_ID_82598EB_CX4: 153 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 154 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 155 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 156 case IXGBE_DEV_ID_82598EB_XF_LR: 157 case IXGBE_DEV_ID_82598EB_SFP_LOM: 158 hw->mac.type = ixgbe_mac_82598EB; 159 break; 160 case IXGBE_DEV_ID_82599_KX4: 161 case IXGBE_DEV_ID_82599_KX4_MEZZ: 162 case IXGBE_DEV_ID_82599_XAUI_LOM: 163 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 164 case IXGBE_DEV_ID_82599_KR: 165 case IXGBE_DEV_ID_82599_SFP: 166 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 167 case IXGBE_DEV_ID_82599_SFP_FCOE: 168 case IXGBE_DEV_ID_82599_SFP_EM: 169 case IXGBE_DEV_ID_82599_SFP_SF2: 170 case IXGBE_DEV_ID_82599_SFP_SF_QP: 171 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 172 case IXGBE_DEV_ID_82599EN_SFP: 173 case IXGBE_DEV_ID_82599_CX4: 174 case IXGBE_DEV_ID_82599_BYPASS: 175 case IXGBE_DEV_ID_82599_T3_LOM: 176 hw->mac.type = ixgbe_mac_82599EB; 177 break; 178 case IXGBE_DEV_ID_X540T: 179 case IXGBE_DEV_ID_X540T1: 180 case IXGBE_DEV_ID_X540_BYPASS: 181 hw->mac.type = ixgbe_mac_X540; 182 hw->mvals = ixgbe_mvals_X540; 183 break; 184 case IXGBE_DEV_ID_X550T: 185 case IXGBE_DEV_ID_X550T1: 186 hw->mac.type = ixgbe_mac_X550; 187 hw->mvals = ixgbe_mvals_X550; 188 break; 189 case IXGBE_DEV_ID_X550EM_X_KX4: 190 case IXGBE_DEV_ID_X550EM_X_KR: 191 case IXGBE_DEV_ID_X550EM_X_10G_T: 192 case IXGBE_DEV_ID_X550EM_X_1G_T: 193 case IXGBE_DEV_ID_X550EM_X_SFP: 194 case IXGBE_DEV_ID_X550EM_X_XFI: 195 hw->mac.type = ixgbe_mac_X550EM_x; 196 hw->mvals = ixgbe_mvals_X550EM_x; 197 break; 198 case IXGBE_DEV_ID_X550EM_A_KR: 199 case IXGBE_DEV_ID_X550EM_A_KR_L: 200 case IXGBE_DEV_ID_X550EM_A_SFP_N: 201 case IXGBE_DEV_ID_X550EM_A_SGMII: 202 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 203 case IXGBE_DEV_ID_X550EM_A_1G_T: 204 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 205 case IXGBE_DEV_ID_X550EM_A_10G_T: 206 case IXGBE_DEV_ID_X550EM_A_QSFP: 207 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 208 case IXGBE_DEV_ID_X550EM_A_SFP: 209 hw->mac.type = ixgbe_mac_X550EM_a; 210 hw->mvals = ixgbe_mvals_X550EM_a; 211 break; 212 default: 213 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 214 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 215 "Unsupported device id: %x", 216 hw->device_id); 217 break; 218 } 219 220 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 221 hw->mac.type, ret_val); 222 return ret_val; 223 } 224 225 /** 226 * ixgbe_init_hw - Initialize the hardware 227 * @hw: pointer to hardware structure 228 * 229 * Initialize the hardware by resetting and then starting the hardware 230 **/ 231 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 232 { 233 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 234 IXGBE_NOT_IMPLEMENTED); 235 } 236 237 /** 238 * ixgbe_reset_hw - Performs a hardware reset 239 * @hw: pointer to hardware structure 240 * 241 * Resets the hardware by resetting the transmit and receive units, masks and 242 * clears all interrupts, performs a PHY reset, and performs a MAC reset 243 **/ 244 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 245 { 246 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 247 IXGBE_NOT_IMPLEMENTED); 248 } 249 250 /** 251 * ixgbe_start_hw - Prepares hardware for Rx/Tx 252 * @hw: pointer to hardware structure 253 * 254 * Starts the hardware by filling the bus info structure and media type, 255 * clears all on chip counters, initializes receive address registers, 256 * multicast table, VLAN filter table, calls routine to setup link and 257 * flow control settings, and leaves transmit and receive units disabled 258 * and uninitialized. 259 **/ 260 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 261 { 262 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 263 IXGBE_NOT_IMPLEMENTED); 264 } 265 266 /** 267 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 268 * which is disabled by default in ixgbe_start_hw(); 269 * 270 * @hw: pointer to hardware structure 271 * 272 * Enable relaxed ordering; 273 **/ 274 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 275 { 276 if (hw->mac.ops.enable_relaxed_ordering) 277 hw->mac.ops.enable_relaxed_ordering(hw); 278 } 279 280 /** 281 * ixgbe_clear_hw_cntrs - Clear hardware counters 282 * @hw: pointer to hardware structure 283 * 284 * Clears all hardware statistics counters by reading them from the hardware 285 * Statistics counters are clear on read. 286 **/ 287 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 288 { 289 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 290 IXGBE_NOT_IMPLEMENTED); 291 } 292 293 /** 294 * ixgbe_get_media_type - Get media type 295 * @hw: pointer to hardware structure 296 * 297 * Returns the media type (fiber, copper, backplane) 298 **/ 299 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 300 { 301 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 302 ixgbe_media_type_unknown); 303 } 304 305 /** 306 * ixgbe_get_mac_addr - Get MAC address 307 * @hw: pointer to hardware structure 308 * @mac_addr: Adapter MAC address 309 * 310 * Reads the adapter's MAC address from the first Receive Address Register 311 * (RAR0) A reset of the adapter must have been performed prior to calling 312 * this function in order for the MAC address to have been loaded from the 313 * EEPROM into RAR0 314 **/ 315 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 316 { 317 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 318 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 319 } 320 321 /** 322 * ixgbe_get_san_mac_addr - Get SAN MAC address 323 * @hw: pointer to hardware structure 324 * @san_mac_addr: SAN MAC address 325 * 326 * Reads the SAN MAC address from the EEPROM, if it's available. This is 327 * per-port, so set_lan_id() must be called before reading the addresses. 328 **/ 329 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 330 { 331 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 332 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 333 } 334 335 /** 336 * ixgbe_set_san_mac_addr - Write a SAN MAC address 337 * @hw: pointer to hardware structure 338 * @san_mac_addr: SAN MAC address 339 * 340 * Writes A SAN MAC address to the EEPROM. 341 **/ 342 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 343 { 344 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 345 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 346 } 347 348 /** 349 * ixgbe_get_device_caps - Get additional device capabilities 350 * @hw: pointer to hardware structure 351 * @device_caps: the EEPROM word for device capabilities 352 * 353 * Reads the extra device capabilities from the EEPROM 354 **/ 355 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 356 { 357 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 358 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 359 } 360 361 /** 362 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 363 * @hw: pointer to hardware structure 364 * @wwnn_prefix: the alternative WWNN prefix 365 * @wwpn_prefix: the alternative WWPN prefix 366 * 367 * This function will read the EEPROM from the alternative SAN MAC address 368 * block to check the support for the alternative WWNN/WWPN prefix support. 369 **/ 370 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 371 u16 *wwpn_prefix) 372 { 373 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 374 (hw, wwnn_prefix, wwpn_prefix), 375 IXGBE_NOT_IMPLEMENTED); 376 } 377 378 /** 379 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 380 * @hw: pointer to hardware structure 381 * @bs: the fcoe boot status 382 * 383 * This function will read the FCOE boot status from the iSCSI FCOE block 384 **/ 385 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 386 { 387 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 388 (hw, bs), 389 IXGBE_NOT_IMPLEMENTED); 390 } 391 392 /** 393 * ixgbe_get_bus_info - Set PCI bus info 394 * @hw: pointer to hardware structure 395 * 396 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 397 **/ 398 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 399 { 400 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 401 IXGBE_NOT_IMPLEMENTED); 402 } 403 404 /** 405 * ixgbe_get_num_of_tx_queues - Get Tx queues 406 * @hw: pointer to hardware structure 407 * 408 * Returns the number of transmit queues for the given adapter. 409 **/ 410 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 411 { 412 return hw->mac.max_tx_queues; 413 } 414 415 /** 416 * ixgbe_get_num_of_rx_queues - Get Rx queues 417 * @hw: pointer to hardware structure 418 * 419 * Returns the number of receive queues for the given adapter. 420 **/ 421 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 422 { 423 return hw->mac.max_rx_queues; 424 } 425 426 /** 427 * ixgbe_stop_adapter - Disable Rx/Tx units 428 * @hw: pointer to hardware structure 429 * 430 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 431 * disables transmit and receive units. The adapter_stopped flag is used by 432 * the shared code and drivers to determine if the adapter is in a stopped 433 * state and should not touch the hardware. 434 **/ 435 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 436 { 437 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 438 IXGBE_NOT_IMPLEMENTED); 439 } 440 441 /** 442 * ixgbe_read_pba_string - Reads part number string from EEPROM 443 * @hw: pointer to hardware structure 444 * @pba_num: stores the part number string from the EEPROM 445 * @pba_num_size: part number string buffer length 446 * 447 * Reads the part number string from the EEPROM. 448 **/ 449 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 450 { 451 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 452 } 453 454 /** 455 * ixgbe_read_pba_num - Reads part number from EEPROM 456 * @hw: pointer to hardware structure 457 * @pba_num: stores the part number from the EEPROM 458 * 459 * Reads the part number from the EEPROM. 460 **/ 461 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 462 { 463 return ixgbe_read_pba_num_generic(hw, pba_num); 464 } 465 466 /** 467 * ixgbe_identify_phy - Get PHY type 468 * @hw: pointer to hardware structure 469 * 470 * Determines the physical layer module found on the current adapter. 471 **/ 472 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 473 { 474 s32 status = IXGBE_SUCCESS; 475 476 if (hw->phy.type == ixgbe_phy_unknown) { 477 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 478 IXGBE_NOT_IMPLEMENTED); 479 } 480 481 return status; 482 } 483 484 /** 485 * ixgbe_reset_phy - Perform a PHY reset 486 * @hw: pointer to hardware structure 487 **/ 488 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 489 { 490 s32 status = IXGBE_SUCCESS; 491 492 if (hw->phy.type == ixgbe_phy_unknown) { 493 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 494 status = IXGBE_ERR_PHY; 495 } 496 497 if (status == IXGBE_SUCCESS) { 498 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 499 IXGBE_NOT_IMPLEMENTED); 500 } 501 return status; 502 } 503 504 /** 505 * ixgbe_get_phy_firmware_version - 506 * @hw: pointer to hardware structure 507 * @firmware_version: pointer to firmware version 508 **/ 509 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 510 { 511 s32 status = IXGBE_SUCCESS; 512 513 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 514 (hw, firmware_version), 515 IXGBE_NOT_IMPLEMENTED); 516 return status; 517 } 518 519 /** 520 * ixgbe_read_phy_reg - Read PHY register 521 * @hw: pointer to hardware structure 522 * @reg_addr: 32 bit address of PHY register to read 523 * @device_type: type of device you want to communicate with 524 * @phy_data: Pointer to read data from PHY register 525 * 526 * Reads a value from a specified PHY register 527 **/ 528 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 529 u16 *phy_data) 530 { 531 if (hw->phy.id == 0) 532 ixgbe_identify_phy(hw); 533 534 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 535 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 536 } 537 538 /** 539 * ixgbe_write_phy_reg - Write PHY register 540 * @hw: pointer to hardware structure 541 * @reg_addr: 32 bit PHY register to write 542 * @device_type: type of device you want to communicate with 543 * @phy_data: Data to write to the PHY register 544 * 545 * Writes a value to specified PHY register 546 **/ 547 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 548 u16 phy_data) 549 { 550 if (hw->phy.id == 0) 551 ixgbe_identify_phy(hw); 552 553 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 554 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 555 } 556 557 /** 558 * ixgbe_setup_phy_link - Restart PHY autoneg 559 * @hw: pointer to hardware structure 560 * 561 * Restart autonegotiation and PHY and waits for completion. 562 **/ 563 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 564 { 565 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 566 IXGBE_NOT_IMPLEMENTED); 567 } 568 569 /** 570 * ixgbe_setup_internal_phy - Configure integrated PHY 571 * @hw: pointer to hardware structure 572 * 573 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 574 * Returns success if not implemented, since nothing needs to be done in this 575 * case. 576 */ 577 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 578 { 579 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 580 IXGBE_SUCCESS); 581 } 582 583 /** 584 * ixgbe_check_phy_link - Determine link and speed status 585 * @hw: pointer to hardware structure 586 * @speed: link speed 587 * @link_up: TRUE when link is up 588 * 589 * Reads a PHY register to determine if link is up and the current speed for 590 * the PHY. 591 **/ 592 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 593 bool *link_up) 594 { 595 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 596 link_up), IXGBE_NOT_IMPLEMENTED); 597 } 598 599 /** 600 * ixgbe_setup_phy_link_speed - Set auto advertise 601 * @hw: pointer to hardware structure 602 * @speed: new link speed 603 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 604 * 605 * Sets the auto advertised capabilities 606 **/ 607 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 608 bool autoneg_wait_to_complete) 609 { 610 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 611 autoneg_wait_to_complete), 612 IXGBE_NOT_IMPLEMENTED); 613 } 614 615 /** 616 * ixgbe_set_phy_power - Control the phy power state 617 * @hw: pointer to hardware structure 618 * @on: TRUE for on, FALSE for off 619 */ 620 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 621 { 622 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 623 IXGBE_NOT_IMPLEMENTED); 624 } 625 626 /** 627 * ixgbe_check_link - Get link and speed status 628 * @hw: pointer to hardware structure 629 * @speed: pointer to link speed 630 * @link_up: TRUE when link is up 631 * @link_up_wait_to_complete: bool used to wait for link up or not 632 * 633 * Reads the links register to determine if link is up and the current speed 634 **/ 635 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 636 bool *link_up, bool link_up_wait_to_complete) 637 { 638 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 639 link_up, link_up_wait_to_complete), 640 IXGBE_NOT_IMPLEMENTED); 641 } 642 643 /** 644 * ixgbe_disable_tx_laser - Disable Tx laser 645 * @hw: pointer to hardware structure 646 * 647 * If the driver needs to disable the laser on SFI optics. 648 **/ 649 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 650 { 651 if (hw->mac.ops.disable_tx_laser) 652 hw->mac.ops.disable_tx_laser(hw); 653 } 654 655 /** 656 * ixgbe_enable_tx_laser - Enable Tx laser 657 * @hw: pointer to hardware structure 658 * 659 * If the driver needs to enable the laser on SFI optics. 660 **/ 661 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 662 { 663 if (hw->mac.ops.enable_tx_laser) 664 hw->mac.ops.enable_tx_laser(hw); 665 } 666 667 /** 668 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 669 * @hw: pointer to hardware structure 670 * 671 * When the driver changes the link speeds that it can support then 672 * flap the tx laser to alert the link partner to start autotry 673 * process on its end. 674 **/ 675 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 676 { 677 if (hw->mac.ops.flap_tx_laser) 678 hw->mac.ops.flap_tx_laser(hw); 679 } 680 681 /** 682 * ixgbe_setup_link - Set link speed 683 * @hw: pointer to hardware structure 684 * @speed: new link speed 685 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 686 * 687 * Configures link settings. Restarts the link. 688 * Performs autonegotiation if needed. 689 **/ 690 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 691 bool autoneg_wait_to_complete) 692 { 693 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 694 autoneg_wait_to_complete), 695 IXGBE_NOT_IMPLEMENTED); 696 } 697 698 /** 699 * ixgbe_setup_mac_link - Set link speed 700 * @hw: pointer to hardware structure 701 * @speed: new link speed 702 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 703 * 704 * Configures link settings. Restarts the link. 705 * Performs autonegotiation if needed. 706 **/ 707 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 708 bool autoneg_wait_to_complete) 709 { 710 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 711 autoneg_wait_to_complete), 712 IXGBE_NOT_IMPLEMENTED); 713 } 714 715 /** 716 * ixgbe_get_link_capabilities - Returns link capabilities 717 * @hw: pointer to hardware structure 718 * @speed: link speed capabilities 719 * @autoneg: TRUE when autoneg or autotry is enabled 720 * 721 * Determines the link capabilities of the current configuration. 722 **/ 723 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 724 bool *autoneg) 725 { 726 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 727 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 728 } 729 730 /** 731 * ixgbe_led_on - Turn on LEDs 732 * @hw: pointer to hardware structure 733 * @index: led number to turn on 734 * 735 * Turns on the software controllable LEDs. 736 **/ 737 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 738 { 739 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 740 IXGBE_NOT_IMPLEMENTED); 741 } 742 743 /** 744 * ixgbe_led_off - Turn off LEDs 745 * @hw: pointer to hardware structure 746 * @index: led number to turn off 747 * 748 * Turns off the software controllable LEDs. 749 **/ 750 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 751 { 752 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 753 IXGBE_NOT_IMPLEMENTED); 754 } 755 756 /** 757 * ixgbe_blink_led_start - Blink LEDs 758 * @hw: pointer to hardware structure 759 * @index: led number to blink 760 * 761 * Blink LED based on index. 762 **/ 763 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 764 { 765 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 766 IXGBE_NOT_IMPLEMENTED); 767 } 768 769 /** 770 * ixgbe_blink_led_stop - Stop blinking LEDs 771 * @hw: pointer to hardware structure 772 * @index: led number to stop 773 * 774 * Stop blinking LED based on index. 775 **/ 776 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 777 { 778 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 779 IXGBE_NOT_IMPLEMENTED); 780 } 781 782 /** 783 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 784 * @hw: pointer to hardware structure 785 * 786 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 787 * ixgbe_hw struct in order to set up EEPROM access. 788 **/ 789 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 790 { 791 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 792 IXGBE_NOT_IMPLEMENTED); 793 } 794 795 796 /** 797 * ixgbe_write_eeprom - Write word to EEPROM 798 * @hw: pointer to hardware structure 799 * @offset: offset within the EEPROM to be written to 800 * @data: 16 bit word to be written to the EEPROM 801 * 802 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 803 * called after this function, the EEPROM will most likely contain an 804 * invalid checksum. 805 **/ 806 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 807 { 808 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 809 IXGBE_NOT_IMPLEMENTED); 810 } 811 812 /** 813 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 814 * @hw: pointer to hardware structure 815 * @offset: offset within the EEPROM to be written to 816 * @data: 16 bit word(s) to be written to the EEPROM 817 * @words: number of words 818 * 819 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 820 * called after this function, the EEPROM will most likely contain an 821 * invalid checksum. 822 **/ 823 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 824 u16 *data) 825 { 826 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 827 (hw, offset, words, data), 828 IXGBE_NOT_IMPLEMENTED); 829 } 830 831 /** 832 * ixgbe_read_eeprom - Read word from EEPROM 833 * @hw: pointer to hardware structure 834 * @offset: offset within the EEPROM to be read 835 * @data: read 16 bit value from EEPROM 836 * 837 * Reads 16 bit value from EEPROM 838 **/ 839 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 840 { 841 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 842 IXGBE_NOT_IMPLEMENTED); 843 } 844 845 /** 846 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 847 * @hw: pointer to hardware structure 848 * @offset: offset within the EEPROM to be read 849 * @data: read 16 bit word(s) from EEPROM 850 * @words: number of words 851 * 852 * Reads 16 bit word(s) from EEPROM 853 **/ 854 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 855 u16 words, u16 *data) 856 { 857 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 858 (hw, offset, words, data), 859 IXGBE_NOT_IMPLEMENTED); 860 } 861 862 /** 863 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 864 * @hw: pointer to hardware structure 865 * @checksum_val: calculated checksum 866 * 867 * Performs checksum calculation and validates the EEPROM checksum 868 **/ 869 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 870 { 871 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 872 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 873 } 874 875 /** 876 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 877 * @hw: pointer to hardware structure 878 **/ 879 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 880 { 881 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 882 IXGBE_NOT_IMPLEMENTED); 883 } 884 885 /** 886 * ixgbe_insert_mac_addr - Find a RAR for this mac address 887 * @hw: pointer to hardware structure 888 * @addr: Address to put into receive address register 889 * @vmdq: VMDq pool to assign 890 * 891 * Puts an ethernet address into a receive address register, or 892 * finds the rar that it is aleady in; adds to the pool list 893 **/ 894 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 895 { 896 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 897 (hw, addr, vmdq), 898 IXGBE_NOT_IMPLEMENTED); 899 } 900 901 /** 902 * ixgbe_set_rar - Set Rx address register 903 * @hw: pointer to hardware structure 904 * @index: Receive address register to write 905 * @addr: Address to put into receive address register 906 * @vmdq: VMDq "set" 907 * @enable_addr: set flag that address is active 908 * 909 * Puts an ethernet address into a receive address register. 910 **/ 911 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 912 u32 enable_addr) 913 { 914 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 915 enable_addr), IXGBE_NOT_IMPLEMENTED); 916 } 917 918 /** 919 * ixgbe_clear_rar - Clear Rx address register 920 * @hw: pointer to hardware structure 921 * @index: Receive address register to write 922 * 923 * Puts an ethernet address into a receive address register. 924 **/ 925 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 926 { 927 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 928 IXGBE_NOT_IMPLEMENTED); 929 } 930 931 /** 932 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 933 * @hw: pointer to hardware structure 934 * @rar: receive address register index to associate with VMDq index 935 * @vmdq: VMDq set or pool index 936 **/ 937 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 938 { 939 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 940 IXGBE_NOT_IMPLEMENTED); 941 942 } 943 944 /** 945 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 946 * @hw: pointer to hardware structure 947 * @vmdq: VMDq default pool index 948 **/ 949 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 950 { 951 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 952 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 953 } 954 955 /** 956 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 957 * @hw: pointer to hardware structure 958 * @rar: receive address register index to disassociate with VMDq index 959 * @vmdq: VMDq set or pool index 960 **/ 961 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 962 { 963 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 964 IXGBE_NOT_IMPLEMENTED); 965 } 966 967 /** 968 * ixgbe_init_rx_addrs - Initializes receive address filters. 969 * @hw: pointer to hardware structure 970 * 971 * Places the MAC address in receive address register 0 and clears the rest 972 * of the receive address registers. Clears the multicast table. Assumes 973 * the receiver is in reset when the routine is called. 974 **/ 975 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 976 { 977 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 978 IXGBE_NOT_IMPLEMENTED); 979 } 980 981 /** 982 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 983 * @hw: pointer to hardware structure 984 **/ 985 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 986 { 987 return hw->mac.num_rar_entries; 988 } 989 990 /** 991 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 992 * @hw: pointer to hardware structure 993 * @addr_list: the list of new multicast addresses 994 * @addr_count: number of addresses 995 * @func: iterator function to walk the multicast address list 996 * 997 * The given list replaces any existing list. Clears the secondary addrs from 998 * receive address registers. Uses unused receive address registers for the 999 * first secondary addresses, and falls back to promiscuous mode as needed. 1000 **/ 1001 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1002 u32 addr_count, ixgbe_mc_addr_itr func) 1003 { 1004 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1005 addr_list, addr_count, func), 1006 IXGBE_NOT_IMPLEMENTED); 1007 } 1008 1009 /** 1010 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1011 * @hw: pointer to hardware structure 1012 * @mc_addr_list: the list of new multicast addresses 1013 * @mc_addr_count: number of addresses 1014 * @func: iterator function to walk the multicast address list 1015 * @clear: flag, when set clears the table beforehand 1016 * 1017 * The given list replaces any existing list. Clears the MC addrs from receive 1018 * address registers and the multicast table. Uses unused receive address 1019 * registers for the first multicast addresses, and hashes the rest into the 1020 * multicast table. 1021 **/ 1022 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1023 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1024 bool clear) 1025 { 1026 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1027 mc_addr_list, mc_addr_count, func, clear), 1028 IXGBE_NOT_IMPLEMENTED); 1029 } 1030 1031 /** 1032 * ixgbe_enable_mc - Enable multicast address in RAR 1033 * @hw: pointer to hardware structure 1034 * 1035 * Enables multicast address in RAR and the use of the multicast hash table. 1036 **/ 1037 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1038 { 1039 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1040 IXGBE_NOT_IMPLEMENTED); 1041 } 1042 1043 /** 1044 * ixgbe_disable_mc - Disable multicast address in RAR 1045 * @hw: pointer to hardware structure 1046 * 1047 * Disables multicast address in RAR and the use of the multicast hash table. 1048 **/ 1049 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1050 { 1051 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1052 IXGBE_NOT_IMPLEMENTED); 1053 } 1054 1055 /** 1056 * ixgbe_clear_vfta - Clear VLAN filter table 1057 * @hw: pointer to hardware structure 1058 * 1059 * Clears the VLAN filer table, and the VMDq index associated with the filter 1060 **/ 1061 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1062 { 1063 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1064 IXGBE_NOT_IMPLEMENTED); 1065 } 1066 1067 /** 1068 * ixgbe_set_vfta - Set VLAN filter table 1069 * @hw: pointer to hardware structure 1070 * @vlan: VLAN id to write to VLAN filter 1071 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1072 * @vlan_on: boolean flag to turn on/off VLAN 1073 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1074 * 1075 * Turn on/off specified VLAN in the VLAN filter table. 1076 **/ 1077 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1078 bool vlvf_bypass) 1079 { 1080 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1081 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1082 } 1083 1084 /** 1085 * ixgbe_set_vlvf - Set VLAN Pool Filter 1086 * @hw: pointer to hardware structure 1087 * @vlan: VLAN id to write to VLAN filter 1088 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1089 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1090 * @vfta_delta: pointer to the difference between the current value of VFTA 1091 * and the desired value 1092 * @vfta: the desired value of the VFTA 1093 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1094 * 1095 * Turn on/off specified bit in VLVF table. 1096 **/ 1097 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1098 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1099 { 1100 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1101 vlan_on, vfta_delta, vfta, vlvf_bypass), 1102 IXGBE_NOT_IMPLEMENTED); 1103 } 1104 1105 /** 1106 * ixgbe_fc_enable - Enable flow control 1107 * @hw: pointer to hardware structure 1108 * 1109 * Configures the flow control settings based on SW configuration. 1110 **/ 1111 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1112 { 1113 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1114 IXGBE_NOT_IMPLEMENTED); 1115 } 1116 1117 /** 1118 * ixgbe_setup_fc - Set up flow control 1119 * @hw: pointer to hardware structure 1120 * 1121 * Called at init time to set up flow control. 1122 **/ 1123 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1124 { 1125 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1126 IXGBE_NOT_IMPLEMENTED); 1127 } 1128 1129 /** 1130 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1131 * @hw: pointer to hardware structure 1132 * @maj: driver major number to be sent to firmware 1133 * @min: driver minor number to be sent to firmware 1134 * @build: driver build number to be sent to firmware 1135 * @ver: driver version number to be sent to firmware 1136 * @len: length of driver_ver string 1137 * @driver_ver: driver string 1138 **/ 1139 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1140 u8 ver, u16 len, char *driver_ver) 1141 { 1142 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1143 build, ver, len, driver_ver), 1144 IXGBE_NOT_IMPLEMENTED); 1145 } 1146 1147 1148 1149 /** 1150 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1151 * @hw: pointer to hardware structure 1152 * 1153 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1154 * When disabling dmac, dmac enable dmac bit is cleared. 1155 **/ 1156 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1157 { 1158 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1159 IXGBE_NOT_IMPLEMENTED); 1160 } 1161 1162 /** 1163 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1164 * @hw: pointer to hardware structure 1165 * 1166 * Disables dmac, updates per TC settings, and then enable dmac. 1167 **/ 1168 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1169 { 1170 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1171 IXGBE_NOT_IMPLEMENTED); 1172 } 1173 1174 /** 1175 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1176 * @hw: pointer to hardware structure 1177 * 1178 * Configure DMA coalescing threshold per TC and set high priority bit for 1179 * FCOE TC. The dmac enable bit must be cleared before configuring. 1180 **/ 1181 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1182 { 1183 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1184 IXGBE_NOT_IMPLEMENTED); 1185 } 1186 1187 /** 1188 * ixgbe_setup_eee - Enable/disable EEE support 1189 * @hw: pointer to the HW structure 1190 * @enable_eee: boolean flag to enable EEE 1191 * 1192 * Enable/disable EEE based on enable_ee flag. 1193 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1194 * are modified. 1195 * 1196 **/ 1197 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1198 { 1199 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1200 IXGBE_NOT_IMPLEMENTED); 1201 } 1202 1203 /** 1204 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1205 * @hw: pointer to hardware structure 1206 * @enable: enable or disable source address pruning 1207 * @pool: Rx pool - Rx pool to toggle source address pruning 1208 **/ 1209 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1210 unsigned int pool) 1211 { 1212 if (hw->mac.ops.set_source_address_pruning) 1213 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1214 } 1215 1216 /** 1217 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1218 * @hw: pointer to hardware structure 1219 * @enable: enable or disable switch for Ethertype anti-spoofing 1220 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1221 * 1222 **/ 1223 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1224 { 1225 if (hw->mac.ops.set_ethertype_anti_spoofing) 1226 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1227 } 1228 1229 /** 1230 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1231 * @hw: pointer to hardware structure 1232 * @reg_addr: 32 bit address of PHY register to read 1233 * @device_type: type of device you want to communicate with 1234 * @phy_data: Pointer to read data from PHY register 1235 * 1236 * Reads a value from a specified PHY register 1237 **/ 1238 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1239 u32 device_type, u32 *phy_data) 1240 { 1241 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1242 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1243 } 1244 1245 /** 1246 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1247 * @hw: pointer to hardware structure 1248 * @reg_addr: 32 bit PHY register to write 1249 * @device_type: type of device you want to communicate with 1250 * @phy_data: Data to write to the PHY register 1251 * 1252 * Writes a value to specified PHY register 1253 **/ 1254 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1255 u32 device_type, u32 phy_data) 1256 { 1257 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1258 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1259 } 1260 1261 /** 1262 * ixgbe_disable_mdd - Disable malicious driver detection 1263 * @hw: pointer to hardware structure 1264 * 1265 **/ 1266 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1267 { 1268 if (hw->mac.ops.disable_mdd) 1269 hw->mac.ops.disable_mdd(hw); 1270 } 1271 1272 /** 1273 * ixgbe_enable_mdd - Enable malicious driver detection 1274 * @hw: pointer to hardware structure 1275 * 1276 **/ 1277 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1278 { 1279 if (hw->mac.ops.enable_mdd) 1280 hw->mac.ops.enable_mdd(hw); 1281 } 1282 1283 /** 1284 * ixgbe_mdd_event - Handle malicious driver detection event 1285 * @hw: pointer to hardware structure 1286 * @vf_bitmap: vf bitmap of malicious vfs 1287 * 1288 **/ 1289 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1290 { 1291 if (hw->mac.ops.mdd_event) 1292 hw->mac.ops.mdd_event(hw, vf_bitmap); 1293 } 1294 1295 /** 1296 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1297 * detection event 1298 * @hw: pointer to hardware structure 1299 * @vf: vf index 1300 * 1301 **/ 1302 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1303 { 1304 if (hw->mac.ops.restore_mdd_vf) 1305 hw->mac.ops.restore_mdd_vf(hw, vf); 1306 } 1307 1308 /** 1309 * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode 1310 * @hw: pointer to hardware structure 1311 * 1312 **/ 1313 bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw) 1314 { 1315 if (hw->mac.ops.fw_recovery_mode) 1316 return hw->mac.ops.fw_recovery_mode(hw); 1317 return FALSE; 1318 } 1319 1320 /** 1321 * ixgbe_enter_lplu - Transition to low power states 1322 * @hw: pointer to hardware structure 1323 * 1324 * Configures Low Power Link Up on transition to low power states 1325 * (from D0 to non-D0). 1326 **/ 1327 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1328 { 1329 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1330 IXGBE_NOT_IMPLEMENTED); 1331 } 1332 1333 /** 1334 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1335 * @hw: pointer to hardware structure 1336 * 1337 * Handle external Base T PHY interrupt. If high temperature 1338 * failure alarm then return error, else if link status change 1339 * then setup internal/external PHY link 1340 * 1341 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1342 * failure alarm, else return PHY access status. 1343 */ 1344 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1345 { 1346 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1347 IXGBE_NOT_IMPLEMENTED); 1348 } 1349 1350 /** 1351 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1352 * @hw: pointer to hardware structure 1353 * @cmd: Command we send to the FW 1354 * @status: The reply from the FW 1355 * 1356 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1357 **/ 1358 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1359 { 1360 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1361 IXGBE_NOT_IMPLEMENTED); 1362 } 1363 1364 #if 0 1365 /** 1366 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1367 * 1368 * If we send a write we can't be sure it took until we can read back 1369 * that same register. It can be a problem as some of the feilds may 1370 * for valid reasons change inbetween the time wrote the register and 1371 * we read it again to verify. So this function check everything we 1372 * can check and then assumes it worked. 1373 * 1374 * @u32 in_reg - The register cmd for the bit-bang read. 1375 * @u32 out_reg - The register returned from a bit-bang read. 1376 **/ 1377 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1378 { 1379 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1380 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1381 } 1382 #endif 1383 1384 /** 1385 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1386 * @hw: pointer to hardware structure 1387 * @cmd: The control word we are setting. 1388 * @event: The event we are setting in the FW. This also happens to 1389 * be the mask for the event we are setting (handy) 1390 * @action: The action we set the event to in the FW. This is in a 1391 * bit field that happens to be what we want to put in 1392 * the event spot (also handy) 1393 * 1394 * Writes to the cmd control the bits in actions. 1395 **/ 1396 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1397 { 1398 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1399 (hw, cmd, event, action), 1400 IXGBE_NOT_IMPLEMENTED); 1401 } 1402 1403 /** 1404 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1405 * @hw: pointer to hardware structure 1406 * @addr: The bypass eeprom address to read. 1407 * @value: The 8b of data at the address above. 1408 **/ 1409 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1410 { 1411 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1412 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1413 } 1414 1415 /** 1416 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1417 * @hw: pointer to hardware structure 1418 * @reg: analog register to read 1419 * @val: read value 1420 * 1421 * Performs write operation to analog register specified. 1422 **/ 1423 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1424 { 1425 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1426 val), IXGBE_NOT_IMPLEMENTED); 1427 } 1428 1429 /** 1430 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1431 * @hw: pointer to hardware structure 1432 * @reg: analog register to write 1433 * @val: value to write 1434 * 1435 * Performs write operation to Atlas analog register specified. 1436 **/ 1437 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1438 { 1439 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1440 val), IXGBE_NOT_IMPLEMENTED); 1441 } 1442 1443 /** 1444 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1445 * @hw: pointer to hardware structure 1446 * 1447 * Initializes the Unicast Table Arrays to zero on device load. This 1448 * is part of the Rx init addr execution path. 1449 **/ 1450 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1451 { 1452 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1453 IXGBE_NOT_IMPLEMENTED); 1454 } 1455 1456 /** 1457 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1458 * @hw: pointer to hardware structure 1459 * @byte_offset: byte offset to read 1460 * @dev_addr: I2C bus address to read from 1461 * @data: value read 1462 * 1463 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1464 **/ 1465 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1466 u8 *data) 1467 { 1468 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1469 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1470 } 1471 1472 /** 1473 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1474 * @hw: pointer to hardware structure 1475 * @byte_offset: byte offset to read 1476 * @dev_addr: I2C bus address to read from 1477 * @data: value read 1478 * 1479 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1480 **/ 1481 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1482 u8 dev_addr, u8 *data) 1483 { 1484 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1485 (hw, byte_offset, dev_addr, data), 1486 IXGBE_NOT_IMPLEMENTED); 1487 } 1488 1489 /** 1490 * ixgbe_read_link - Perform read operation on link device 1491 * @hw: pointer to the hardware structure 1492 * @addr: bus address to read from 1493 * @reg: device register to read from 1494 * @val: pointer to location to receive read value 1495 * 1496 * Returns an error code on error. 1497 */ 1498 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1499 { 1500 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1501 reg, val), IXGBE_NOT_IMPLEMENTED); 1502 } 1503 1504 /** 1505 * ixgbe_read_link_unlocked - Perform read operation on link device 1506 * @hw: pointer to the hardware structure 1507 * @addr: bus address to read from 1508 * @reg: device register to read from 1509 * @val: pointer to location to receive read value 1510 * 1511 * Returns an error code on error. 1512 **/ 1513 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1514 { 1515 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1516 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1517 } 1518 1519 /** 1520 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1521 * @hw: pointer to hardware structure 1522 * @byte_offset: byte offset to write 1523 * @dev_addr: I2C bus address to write to 1524 * @data: value to write 1525 * 1526 * Performs byte write operation to SFP module's EEPROM over I2C interface 1527 * at a specified device address. 1528 **/ 1529 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1530 u8 data) 1531 { 1532 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1533 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1534 } 1535 1536 /** 1537 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1538 * @hw: pointer to hardware structure 1539 * @byte_offset: byte offset to write 1540 * @dev_addr: I2C bus address to write to 1541 * @data: value to write 1542 * 1543 * Performs byte write operation to SFP module's EEPROM over I2C interface 1544 * at a specified device address. 1545 **/ 1546 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1547 u8 dev_addr, u8 data) 1548 { 1549 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1550 (hw, byte_offset, dev_addr, data), 1551 IXGBE_NOT_IMPLEMENTED); 1552 } 1553 1554 /** 1555 * ixgbe_write_link - Perform write operation on link device 1556 * @hw: pointer to the hardware structure 1557 * @addr: bus address to write to 1558 * @reg: device register to write to 1559 * @val: value to write 1560 * 1561 * Returns an error code on error. 1562 */ 1563 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1564 { 1565 return ixgbe_call_func(hw, hw->link.ops.write_link, 1566 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1567 } 1568 1569 /** 1570 * ixgbe_write_link_unlocked - Perform write operation on link device 1571 * @hw: pointer to the hardware structure 1572 * @addr: bus address to write to 1573 * @reg: device register to write to 1574 * @val: value to write 1575 * 1576 * Returns an error code on error. 1577 **/ 1578 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1579 { 1580 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1581 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1582 } 1583 1584 /** 1585 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1586 * @hw: pointer to hardware structure 1587 * @byte_offset: EEPROM byte offset to write 1588 * @eeprom_data: value to write 1589 * 1590 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1591 **/ 1592 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1593 u8 byte_offset, u8 eeprom_data) 1594 { 1595 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1596 (hw, byte_offset, eeprom_data), 1597 IXGBE_NOT_IMPLEMENTED); 1598 } 1599 1600 /** 1601 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1602 * @hw: pointer to hardware structure 1603 * @byte_offset: EEPROM byte offset to read 1604 * @eeprom_data: value read 1605 * 1606 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1607 **/ 1608 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1609 { 1610 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1611 (hw, byte_offset, eeprom_data), 1612 IXGBE_NOT_IMPLEMENTED); 1613 } 1614 1615 /** 1616 * ixgbe_get_supported_physical_layer - Returns physical layer type 1617 * @hw: pointer to hardware structure 1618 * 1619 * Determines physical layer capabilities of the current configuration. 1620 **/ 1621 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1622 { 1623 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1624 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1625 } 1626 1627 /** 1628 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1629 * @hw: pointer to hardware structure 1630 * @regval: bitfield to write to the Rx DMA register 1631 * 1632 * Enables the Rx DMA unit of the device. 1633 **/ 1634 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1635 { 1636 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1637 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1638 } 1639 1640 /** 1641 * ixgbe_disable_sec_rx_path - Stops the receive data path 1642 * @hw: pointer to hardware structure 1643 * 1644 * Stops the receive data path. 1645 **/ 1646 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1647 { 1648 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1649 (hw), IXGBE_NOT_IMPLEMENTED); 1650 } 1651 1652 /** 1653 * ixgbe_enable_sec_rx_path - Enables the receive data path 1654 * @hw: pointer to hardware structure 1655 * 1656 * Enables the receive data path. 1657 **/ 1658 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1659 { 1660 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1661 (hw), IXGBE_NOT_IMPLEMENTED); 1662 } 1663 1664 /** 1665 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1666 * @hw: pointer to hardware structure 1667 * @mask: Mask to specify which semaphore to acquire 1668 * 1669 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1670 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1671 **/ 1672 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1673 { 1674 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1675 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1676 } 1677 1678 /** 1679 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1680 * @hw: pointer to hardware structure 1681 * @mask: Mask to specify which semaphore to release 1682 * 1683 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1684 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1685 **/ 1686 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1687 { 1688 if (hw->mac.ops.release_swfw_sync) 1689 hw->mac.ops.release_swfw_sync(hw, mask); 1690 } 1691 1692 /** 1693 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1694 * @hw: pointer to hardware structure 1695 * 1696 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1697 * Regardless of whether is succeeds or not it then release the semaphore. 1698 * This is function is called to recover from catastrophic failures that 1699 * may have left the semaphore locked. 1700 **/ 1701 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1702 { 1703 if (hw->mac.ops.init_swfw_sync) 1704 hw->mac.ops.init_swfw_sync(hw); 1705 } 1706 1707 1708 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1709 { 1710 if (hw->mac.ops.disable_rx) 1711 hw->mac.ops.disable_rx(hw); 1712 } 1713 1714 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1715 { 1716 if (hw->mac.ops.enable_rx) 1717 hw->mac.ops.enable_rx(hw); 1718 } 1719 1720 /** 1721 * ixgbe_set_rate_select_speed - Set module link speed 1722 * @hw: pointer to hardware structure 1723 * @speed: link speed to set 1724 * 1725 * Set module link speed via the rate select. 1726 */ 1727 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1728 { 1729 if (hw->mac.ops.set_rate_select_speed) 1730 hw->mac.ops.set_rate_select_speed(hw, speed); 1731 } 1732