1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_common.h" 36 #include "ixgbe_phy.h" 37 #include "ixgbe_dcb.h" 38 #include "ixgbe_dcb_82599.h" 39 #include "ixgbe_api.h" 40 41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 47 u16 count); 48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 52 53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 55 u16 *san_mac_offset); 56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 57 u16 words, u16 *data); 58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 59 u16 words, u16 *data); 60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 61 u16 offset); 62 63 /** 64 * ixgbe_init_ops_generic - Inits function ptrs 65 * @hw: pointer to the hardware structure 66 * 67 * Initialize the function pointers. 68 **/ 69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 70 { 71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 72 struct ixgbe_mac_info *mac = &hw->mac; 73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 74 75 DEBUGFUNC("ixgbe_init_ops_generic"); 76 77 /* EEPROM */ 78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; 79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 80 if (eec & IXGBE_EEC_PRES) { 81 eeprom->ops.read = ixgbe_read_eerd_generic; 82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; 83 } else { 84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; 85 eeprom->ops.read_buffer = 86 ixgbe_read_eeprom_buffer_bit_bang_generic; 87 } 88 eeprom->ops.write = ixgbe_write_eeprom_generic; 89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; 90 eeprom->ops.validate_checksum = 91 ixgbe_validate_eeprom_checksum_generic; 92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; 93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; 94 95 /* MAC */ 96 mac->ops.init_hw = ixgbe_init_hw_generic; 97 mac->ops.reset_hw = NULL; 98 mac->ops.start_hw = ixgbe_start_hw_generic; 99 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; 100 mac->ops.get_media_type = NULL; 101 mac->ops.get_supported_physical_layer = NULL; 102 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; 103 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; 104 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; 105 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; 106 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; 107 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; 108 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; 109 mac->ops.prot_autoc_read = prot_autoc_read_generic; 110 mac->ops.prot_autoc_write = prot_autoc_write_generic; 111 112 /* LEDs */ 113 mac->ops.led_on = ixgbe_led_on_generic; 114 mac->ops.led_off = ixgbe_led_off_generic; 115 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; 116 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; 117 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; 118 119 /* RAR, Multicast, VLAN */ 120 mac->ops.set_rar = ixgbe_set_rar_generic; 121 mac->ops.clear_rar = ixgbe_clear_rar_generic; 122 mac->ops.insert_mac_addr = NULL; 123 mac->ops.set_vmdq = NULL; 124 mac->ops.clear_vmdq = NULL; 125 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; 126 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; 127 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; 128 mac->ops.enable_mc = ixgbe_enable_mc_generic; 129 mac->ops.disable_mc = ixgbe_disable_mc_generic; 130 mac->ops.clear_vfta = NULL; 131 mac->ops.set_vfta = NULL; 132 mac->ops.set_vlvf = NULL; 133 mac->ops.init_uta_tables = NULL; 134 mac->ops.enable_rx = ixgbe_enable_rx_generic; 135 mac->ops.disable_rx = ixgbe_disable_rx_generic; 136 137 /* Flow Control */ 138 mac->ops.fc_enable = ixgbe_fc_enable_generic; 139 mac->ops.setup_fc = ixgbe_setup_fc_generic; 140 mac->ops.fc_autoneg = ixgbe_fc_autoneg; 141 142 /* Link */ 143 mac->ops.get_link_capabilities = NULL; 144 mac->ops.setup_link = NULL; 145 mac->ops.check_link = NULL; 146 mac->ops.dmac_config = NULL; 147 mac->ops.dmac_update_tcs = NULL; 148 mac->ops.dmac_config_tcs = NULL; 149 150 return IXGBE_SUCCESS; 151 } 152 153 /** 154 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 155 * of flow control 156 * @hw: pointer to hardware structure 157 * 158 * This function returns TRUE if the device supports flow control 159 * autonegotiation, and FALSE if it does not. 160 * 161 **/ 162 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 163 { 164 bool supported = FALSE; 165 ixgbe_link_speed speed; 166 bool link_up; 167 168 DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 169 170 switch (hw->phy.media_type) { 171 case ixgbe_media_type_fiber_fixed: 172 case ixgbe_media_type_fiber_qsfp: 173 case ixgbe_media_type_fiber: 174 /* flow control autoneg black list */ 175 switch (hw->device_id) { 176 case IXGBE_DEV_ID_X550EM_A_SFP: 177 case IXGBE_DEV_ID_X550EM_A_SFP_N: 178 case IXGBE_DEV_ID_X550EM_A_QSFP: 179 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 180 supported = FALSE; 181 break; 182 default: 183 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 184 /* if link is down, assume supported */ 185 if (link_up) 186 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 187 TRUE : FALSE; 188 else 189 supported = TRUE; 190 } 191 192 break; 193 case ixgbe_media_type_backplane: 194 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) 195 supported = FALSE; 196 else 197 supported = TRUE; 198 break; 199 case ixgbe_media_type_copper: 200 /* only some copper devices support flow control autoneg */ 201 switch (hw->device_id) { 202 case IXGBE_DEV_ID_82599_T3_LOM: 203 case IXGBE_DEV_ID_X540T: 204 case IXGBE_DEV_ID_X540T1: 205 case IXGBE_DEV_ID_X540_BYPASS: 206 case IXGBE_DEV_ID_X550T: 207 case IXGBE_DEV_ID_X550T1: 208 case IXGBE_DEV_ID_X550EM_X_10G_T: 209 case IXGBE_DEV_ID_X550EM_A_10G_T: 210 case IXGBE_DEV_ID_X550EM_A_1G_T: 211 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 212 supported = TRUE; 213 break; 214 default: 215 supported = FALSE; 216 } 217 default: 218 break; 219 } 220 221 if (!supported) 222 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 223 "Device %x does not support flow control autoneg", 224 hw->device_id); 225 return supported; 226 } 227 228 /** 229 * ixgbe_setup_fc_generic - Set up flow control 230 * @hw: pointer to hardware structure 231 * 232 * Called at init time to set up flow control. 233 **/ 234 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) 235 { 236 s32 ret_val = IXGBE_SUCCESS; 237 u32 reg = 0, reg_bp = 0; 238 u16 reg_cu = 0; 239 bool locked = FALSE; 240 241 DEBUGFUNC("ixgbe_setup_fc_generic"); 242 243 /* Validate the requested mode */ 244 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 245 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 246 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 247 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 248 goto out; 249 } 250 251 /* 252 * 10gig parts do not have a word in the EEPROM to determine the 253 * default flow control setting, so we explicitly set it to full. 254 */ 255 if (hw->fc.requested_mode == ixgbe_fc_default) 256 hw->fc.requested_mode = ixgbe_fc_full; 257 258 /* 259 * Set up the 1G and 10G flow control advertisement registers so the 260 * HW will be able to do fc autoneg once the cable is plugged in. If 261 * we link at 10G, the 1G advertisement is harmless and vice versa. 262 */ 263 switch (hw->phy.media_type) { 264 case ixgbe_media_type_backplane: 265 /* some MAC's need RMW protection on AUTOC */ 266 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); 267 if (ret_val != IXGBE_SUCCESS) 268 goto out; 269 270 /* fall through - only backplane uses autoc */ 271 case ixgbe_media_type_fiber_fixed: 272 case ixgbe_media_type_fiber_qsfp: 273 case ixgbe_media_type_fiber: 274 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 275 276 break; 277 case ixgbe_media_type_copper: 278 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 279 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 280 break; 281 default: 282 break; 283 } 284 285 /* 286 * The possible values of fc.requested_mode are: 287 * 0: Flow control is completely disabled 288 * 1: Rx flow control is enabled (we can receive pause frames, 289 * but not send pause frames). 290 * 2: Tx flow control is enabled (we can send pause frames but 291 * we do not support receiving pause frames). 292 * 3: Both Rx and Tx flow control (symmetric) are enabled. 293 * other: Invalid. 294 */ 295 switch (hw->fc.requested_mode) { 296 case ixgbe_fc_none: 297 /* Flow control completely disabled by software override. */ 298 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 299 if (hw->phy.media_type == ixgbe_media_type_backplane) 300 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 301 IXGBE_AUTOC_ASM_PAUSE); 302 else if (hw->phy.media_type == ixgbe_media_type_copper) 303 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 304 break; 305 case ixgbe_fc_tx_pause: 306 /* 307 * Tx Flow control is enabled, and Rx Flow control is 308 * disabled by software override. 309 */ 310 reg |= IXGBE_PCS1GANA_ASM_PAUSE; 311 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 312 if (hw->phy.media_type == ixgbe_media_type_backplane) { 313 reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 314 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 315 } else if (hw->phy.media_type == ixgbe_media_type_copper) { 316 reg_cu |= IXGBE_TAF_ASM_PAUSE; 317 reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 318 } 319 break; 320 case ixgbe_fc_rx_pause: 321 /* 322 * Rx Flow control is enabled and Tx Flow control is 323 * disabled by software override. Since there really 324 * isn't a way to advertise that we are capable of RX 325 * Pause ONLY, we will advertise that we support both 326 * symmetric and asymmetric Rx PAUSE, as such we fall 327 * through to the fc_full statement. Later, we will 328 * disable the adapter's ability to send PAUSE frames. 329 */ 330 case ixgbe_fc_full: 331 /* Flow control (both Rx and Tx) is enabled by SW override. */ 332 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 333 if (hw->phy.media_type == ixgbe_media_type_backplane) 334 reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 335 IXGBE_AUTOC_ASM_PAUSE; 336 else if (hw->phy.media_type == ixgbe_media_type_copper) 337 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 338 break; 339 default: 340 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 341 "Flow control param set incorrectly\n"); 342 ret_val = IXGBE_ERR_CONFIG; 343 goto out; 344 break; 345 } 346 347 if (hw->mac.type < ixgbe_mac_X540) { 348 /* 349 * Enable auto-negotiation between the MAC & PHY; 350 * the MAC will advertise clause 37 flow control. 351 */ 352 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 353 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 354 355 /* Disable AN timeout */ 356 if (hw->fc.strict_ieee) 357 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 358 359 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 360 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 361 } 362 363 /* 364 * AUTOC restart handles negotiation of 1G and 10G on backplane 365 * and copper. There is no need to set the PCS1GCTL register. 366 * 367 */ 368 if (hw->phy.media_type == ixgbe_media_type_backplane) { 369 reg_bp |= IXGBE_AUTOC_AN_RESTART; 370 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); 371 if (ret_val) 372 goto out; 373 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 374 (ixgbe_device_supports_autoneg_fc(hw))) { 375 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 376 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 377 } 378 379 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 380 out: 381 return ret_val; 382 } 383 384 /** 385 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 386 * @hw: pointer to hardware structure 387 * 388 * Starts the hardware by filling the bus info structure and media type, clears 389 * all on chip counters, initializes receive address registers, multicast 390 * table, VLAN filter table, calls routine to set up link and flow control 391 * settings, and leaves transmit and receive units disabled and uninitialized 392 **/ 393 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 394 { 395 s32 ret_val; 396 u32 ctrl_ext; 397 u16 device_caps; 398 399 DEBUGFUNC("ixgbe_start_hw_generic"); 400 401 /* Set the media type */ 402 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 403 404 /* PHY ops initialization must be done in reset_hw() */ 405 406 /* Clear the VLAN filter table */ 407 hw->mac.ops.clear_vfta(hw); 408 409 /* Clear statistics registers */ 410 hw->mac.ops.clear_hw_cntrs(hw); 411 412 /* Set No Snoop Disable */ 413 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 414 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 415 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 416 IXGBE_WRITE_FLUSH(hw); 417 418 /* Setup flow control */ 419 ret_val = ixgbe_setup_fc(hw); 420 if (ret_val != IXGBE_SUCCESS && ret_val != IXGBE_NOT_IMPLEMENTED) { 421 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); 422 return ret_val; 423 } 424 425 /* Cache bit indicating need for crosstalk fix */ 426 switch (hw->mac.type) { 427 case ixgbe_mac_82599EB: 428 case ixgbe_mac_X550EM_x: 429 case ixgbe_mac_X550EM_a: 430 hw->mac.ops.get_device_caps(hw, &device_caps); 431 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) 432 hw->need_crosstalk_fix = FALSE; 433 else 434 hw->need_crosstalk_fix = TRUE; 435 break; 436 default: 437 hw->need_crosstalk_fix = FALSE; 438 break; 439 } 440 441 /* Clear adapter stopped flag */ 442 hw->adapter_stopped = FALSE; 443 444 return IXGBE_SUCCESS; 445 } 446 447 /** 448 * ixgbe_start_hw_gen2 - Init sequence for common device family 449 * @hw: pointer to hw structure 450 * 451 * Performs the init sequence common to the second generation 452 * of 10 GbE devices. 453 * Devices in the second generation: 454 * 82599 455 * X540 456 **/ 457 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 458 { 459 u32 i; 460 u32 regval; 461 462 /* Clear the rate limiters */ 463 for (i = 0; i < hw->mac.max_tx_queues; i++) { 464 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 465 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 466 } 467 IXGBE_WRITE_FLUSH(hw); 468 469 /* Disable relaxed ordering */ 470 for (i = 0; i < hw->mac.max_tx_queues; i++) { 471 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 472 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 473 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 474 } 475 476 for (i = 0; i < hw->mac.max_rx_queues; i++) { 477 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 478 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 479 IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 480 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 481 } 482 483 return IXGBE_SUCCESS; 484 } 485 486 /** 487 * ixgbe_init_hw_generic - Generic hardware initialization 488 * @hw: pointer to hardware structure 489 * 490 * Initialize the hardware by resetting the hardware, filling the bus info 491 * structure and media type, clears all on chip counters, initializes receive 492 * address registers, multicast table, VLAN filter table, calls routine to set 493 * up link and flow control settings, and leaves transmit and receive units 494 * disabled and uninitialized 495 **/ 496 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 497 { 498 s32 status; 499 500 DEBUGFUNC("ixgbe_init_hw_generic"); 501 502 /* Reset the hardware */ 503 status = hw->mac.ops.reset_hw(hw); 504 505 if (status == IXGBE_SUCCESS || status == IXGBE_ERR_SFP_NOT_PRESENT) { 506 /* Start the HW */ 507 status = hw->mac.ops.start_hw(hw); 508 } 509 510 /* Initialize the LED link active for LED blink support */ 511 if (hw->mac.ops.init_led_link_act) 512 hw->mac.ops.init_led_link_act(hw); 513 514 if (status != IXGBE_SUCCESS) 515 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); 516 517 return status; 518 } 519 520 /** 521 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 522 * @hw: pointer to hardware structure 523 * 524 * Clears all hardware statistics counters by reading them from the hardware 525 * Statistics counters are clear on read. 526 **/ 527 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 528 { 529 u16 i = 0; 530 531 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 532 533 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 534 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 535 IXGBE_READ_REG(hw, IXGBE_ERRBC); 536 IXGBE_READ_REG(hw, IXGBE_MSPDC); 537 for (i = 0; i < 8; i++) 538 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 539 540 IXGBE_READ_REG(hw, IXGBE_MLFC); 541 IXGBE_READ_REG(hw, IXGBE_MRFC); 542 IXGBE_READ_REG(hw, IXGBE_RLEC); 543 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 544 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 545 if (hw->mac.type >= ixgbe_mac_82599EB) { 546 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 547 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 548 } else { 549 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 550 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 551 } 552 553 for (i = 0; i < 8; i++) { 554 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 555 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 556 if (hw->mac.type >= ixgbe_mac_82599EB) { 557 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 558 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 559 } else { 560 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 561 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 562 } 563 } 564 if (hw->mac.type >= ixgbe_mac_82599EB) 565 for (i = 0; i < 8; i++) 566 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 567 IXGBE_READ_REG(hw, IXGBE_PRC64); 568 IXGBE_READ_REG(hw, IXGBE_PRC127); 569 IXGBE_READ_REG(hw, IXGBE_PRC255); 570 IXGBE_READ_REG(hw, IXGBE_PRC511); 571 IXGBE_READ_REG(hw, IXGBE_PRC1023); 572 IXGBE_READ_REG(hw, IXGBE_PRC1522); 573 IXGBE_READ_REG(hw, IXGBE_GPRC); 574 IXGBE_READ_REG(hw, IXGBE_BPRC); 575 IXGBE_READ_REG(hw, IXGBE_MPRC); 576 IXGBE_READ_REG(hw, IXGBE_GPTC); 577 IXGBE_READ_REG(hw, IXGBE_GORCL); 578 IXGBE_READ_REG(hw, IXGBE_GORCH); 579 IXGBE_READ_REG(hw, IXGBE_GOTCL); 580 IXGBE_READ_REG(hw, IXGBE_GOTCH); 581 if (hw->mac.type == ixgbe_mac_82598EB) 582 for (i = 0; i < 8; i++) 583 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 584 IXGBE_READ_REG(hw, IXGBE_RUC); 585 IXGBE_READ_REG(hw, IXGBE_RFC); 586 IXGBE_READ_REG(hw, IXGBE_ROC); 587 IXGBE_READ_REG(hw, IXGBE_RJC); 588 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 589 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 590 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 591 IXGBE_READ_REG(hw, IXGBE_TORL); 592 IXGBE_READ_REG(hw, IXGBE_TORH); 593 IXGBE_READ_REG(hw, IXGBE_TPR); 594 IXGBE_READ_REG(hw, IXGBE_TPT); 595 IXGBE_READ_REG(hw, IXGBE_PTC64); 596 IXGBE_READ_REG(hw, IXGBE_PTC127); 597 IXGBE_READ_REG(hw, IXGBE_PTC255); 598 IXGBE_READ_REG(hw, IXGBE_PTC511); 599 IXGBE_READ_REG(hw, IXGBE_PTC1023); 600 IXGBE_READ_REG(hw, IXGBE_PTC1522); 601 IXGBE_READ_REG(hw, IXGBE_MPTC); 602 IXGBE_READ_REG(hw, IXGBE_BPTC); 603 for (i = 0; i < 16; i++) { 604 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 605 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 606 if (hw->mac.type >= ixgbe_mac_82599EB) { 607 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 608 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 609 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 610 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 611 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 612 } else { 613 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 614 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 615 } 616 } 617 618 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { 619 if (hw->phy.id == 0) 620 ixgbe_identify_phy(hw); 621 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 622 IXGBE_MDIO_PCS_DEV_TYPE, &i); 623 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 624 IXGBE_MDIO_PCS_DEV_TYPE, &i); 625 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 626 IXGBE_MDIO_PCS_DEV_TYPE, &i); 627 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 628 IXGBE_MDIO_PCS_DEV_TYPE, &i); 629 } 630 631 return IXGBE_SUCCESS; 632 } 633 634 /** 635 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 636 * @hw: pointer to hardware structure 637 * @pba_num: stores the part number string from the EEPROM 638 * @pba_num_size: part number string buffer length 639 * 640 * Reads the part number string from the EEPROM. 641 **/ 642 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 643 u32 pba_num_size) 644 { 645 s32 ret_val; 646 u16 data; 647 u16 pba_ptr; 648 u16 offset; 649 u16 length; 650 651 DEBUGFUNC("ixgbe_read_pba_string_generic"); 652 653 if (pba_num == NULL) { 654 DEBUGOUT("PBA string buffer was null\n"); 655 return IXGBE_ERR_INVALID_ARGUMENT; 656 } 657 658 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 659 if (ret_val) { 660 DEBUGOUT("NVM Read Error\n"); 661 return ret_val; 662 } 663 664 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 665 if (ret_val) { 666 DEBUGOUT("NVM Read Error\n"); 667 return ret_val; 668 } 669 670 /* 671 * if data is not ptr guard the PBA must be in legacy format which 672 * means pba_ptr is actually our second data word for the PBA number 673 * and we can decode it into an ascii string 674 */ 675 if (data != IXGBE_PBANUM_PTR_GUARD) { 676 DEBUGOUT("NVM PBA number is not stored as string\n"); 677 678 /* we will need 11 characters to store the PBA */ 679 if (pba_num_size < 11) { 680 DEBUGOUT("PBA string buffer too small\n"); 681 return IXGBE_ERR_NO_SPACE; 682 } 683 684 /* extract hex string from data and pba_ptr */ 685 pba_num[0] = (data >> 12) & 0xF; 686 pba_num[1] = (data >> 8) & 0xF; 687 pba_num[2] = (data >> 4) & 0xF; 688 pba_num[3] = data & 0xF; 689 pba_num[4] = (pba_ptr >> 12) & 0xF; 690 pba_num[5] = (pba_ptr >> 8) & 0xF; 691 pba_num[6] = '-'; 692 pba_num[7] = 0; 693 pba_num[8] = (pba_ptr >> 4) & 0xF; 694 pba_num[9] = pba_ptr & 0xF; 695 696 /* put a null character on the end of our string */ 697 pba_num[10] = '\0'; 698 699 /* switch all the data but the '-' to hex char */ 700 for (offset = 0; offset < 10; offset++) { 701 if (pba_num[offset] < 0xA) 702 pba_num[offset] += '0'; 703 else if (pba_num[offset] < 0x10) 704 pba_num[offset] += 'A' - 0xA; 705 } 706 707 return IXGBE_SUCCESS; 708 } 709 710 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 711 if (ret_val) { 712 DEBUGOUT("NVM Read Error\n"); 713 return ret_val; 714 } 715 716 if (length == 0xFFFF || length == 0) { 717 DEBUGOUT("NVM PBA number section invalid length\n"); 718 return IXGBE_ERR_PBA_SECTION; 719 } 720 721 /* check if pba_num buffer is big enough */ 722 if (pba_num_size < (((u32)length * 2) - 1)) { 723 DEBUGOUT("PBA string buffer too small\n"); 724 return IXGBE_ERR_NO_SPACE; 725 } 726 727 /* trim pba length from start of string */ 728 pba_ptr++; 729 length--; 730 731 for (offset = 0; offset < length; offset++) { 732 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 733 if (ret_val) { 734 DEBUGOUT("NVM Read Error\n"); 735 return ret_val; 736 } 737 pba_num[offset * 2] = (u8)(data >> 8); 738 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 739 } 740 pba_num[offset * 2] = '\0'; 741 742 return IXGBE_SUCCESS; 743 } 744 745 /** 746 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 747 * @hw: pointer to hardware structure 748 * @pba_num: stores the part number from the EEPROM 749 * 750 * Reads the part number from the EEPROM. 751 **/ 752 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 753 { 754 s32 ret_val; 755 u16 data; 756 757 DEBUGFUNC("ixgbe_read_pba_num_generic"); 758 759 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 760 if (ret_val) { 761 DEBUGOUT("NVM Read Error\n"); 762 return ret_val; 763 } else if (data == IXGBE_PBANUM_PTR_GUARD) { 764 DEBUGOUT("NVM Not supported\n"); 765 return IXGBE_NOT_IMPLEMENTED; 766 } 767 *pba_num = (u32)(data << 16); 768 769 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 770 if (ret_val) { 771 DEBUGOUT("NVM Read Error\n"); 772 return ret_val; 773 } 774 *pba_num |= data; 775 776 return IXGBE_SUCCESS; 777 } 778 779 /** 780 * ixgbe_read_pba_raw 781 * @hw: pointer to the HW structure 782 * @eeprom_buf: optional pointer to EEPROM image 783 * @eeprom_buf_size: size of EEPROM image in words 784 * @max_pba_block_size: PBA block size limit 785 * @pba: pointer to output PBA structure 786 * 787 * Reads PBA from EEPROM image when eeprom_buf is not NULL. 788 * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 789 * 790 **/ 791 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 792 u32 eeprom_buf_size, u16 max_pba_block_size, 793 struct ixgbe_pba *pba) 794 { 795 s32 ret_val; 796 u16 pba_block_size; 797 798 if (pba == NULL) 799 return IXGBE_ERR_PARAM; 800 801 if (eeprom_buf == NULL) { 802 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 803 &pba->word[0]); 804 if (ret_val) 805 return ret_val; 806 } else { 807 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 808 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 809 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 810 } else { 811 return IXGBE_ERR_PARAM; 812 } 813 } 814 815 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 816 if (pba->pba_block == NULL) 817 return IXGBE_ERR_PARAM; 818 819 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 820 eeprom_buf_size, 821 &pba_block_size); 822 if (ret_val) 823 return ret_val; 824 825 if (pba_block_size > max_pba_block_size) 826 return IXGBE_ERR_PARAM; 827 828 if (eeprom_buf == NULL) { 829 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 830 pba_block_size, 831 pba->pba_block); 832 if (ret_val) 833 return ret_val; 834 } else { 835 if (eeprom_buf_size > (u32)(pba->word[1] + 836 pba_block_size)) { 837 memcpy(pba->pba_block, 838 &eeprom_buf[pba->word[1]], 839 pba_block_size * sizeof(u16)); 840 } else { 841 return IXGBE_ERR_PARAM; 842 } 843 } 844 } 845 846 return IXGBE_SUCCESS; 847 } 848 849 /** 850 * ixgbe_write_pba_raw 851 * @hw: pointer to the HW structure 852 * @eeprom_buf: optional pointer to EEPROM image 853 * @eeprom_buf_size: size of EEPROM image in words 854 * @pba: pointer to PBA structure 855 * 856 * Writes PBA to EEPROM image when eeprom_buf is not NULL. 857 * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 858 * 859 **/ 860 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 861 u32 eeprom_buf_size, struct ixgbe_pba *pba) 862 { 863 s32 ret_val; 864 865 if (pba == NULL) 866 return IXGBE_ERR_PARAM; 867 868 if (eeprom_buf == NULL) { 869 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 870 &pba->word[0]); 871 if (ret_val) 872 return ret_val; 873 } else { 874 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 875 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 876 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 877 } else { 878 return IXGBE_ERR_PARAM; 879 } 880 } 881 882 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 883 if (pba->pba_block == NULL) 884 return IXGBE_ERR_PARAM; 885 886 if (eeprom_buf == NULL) { 887 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 888 pba->pba_block[0], 889 pba->pba_block); 890 if (ret_val) 891 return ret_val; 892 } else { 893 if (eeprom_buf_size > (u32)(pba->word[1] + 894 pba->pba_block[0])) { 895 memcpy(&eeprom_buf[pba->word[1]], 896 pba->pba_block, 897 pba->pba_block[0] * sizeof(u16)); 898 } else { 899 return IXGBE_ERR_PARAM; 900 } 901 } 902 } 903 904 return IXGBE_SUCCESS; 905 } 906 907 /** 908 * ixgbe_get_pba_block_size 909 * @hw: pointer to the HW structure 910 * @eeprom_buf: optional pointer to EEPROM image 911 * @eeprom_buf_size: size of EEPROM image in words 912 * @pba_data_size: pointer to output variable 913 * 914 * Returns the size of the PBA block in words. Function operates on EEPROM 915 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 916 * EEPROM device. 917 * 918 **/ 919 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 920 u32 eeprom_buf_size, u16 *pba_block_size) 921 { 922 s32 ret_val; 923 u16 pba_word[2]; 924 u16 length; 925 926 DEBUGFUNC("ixgbe_get_pba_block_size"); 927 928 if (eeprom_buf == NULL) { 929 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 930 &pba_word[0]); 931 if (ret_val) 932 return ret_val; 933 } else { 934 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 935 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 936 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 937 } else { 938 return IXGBE_ERR_PARAM; 939 } 940 } 941 942 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 943 if (eeprom_buf == NULL) { 944 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 945 &length); 946 if (ret_val) 947 return ret_val; 948 } else { 949 if (eeprom_buf_size > pba_word[1]) 950 length = eeprom_buf[pba_word[1] + 0]; 951 else 952 return IXGBE_ERR_PARAM; 953 } 954 955 if (length == 0xFFFF || length == 0) 956 return IXGBE_ERR_PBA_SECTION; 957 } else { 958 /* PBA number in legacy format, there is no PBA Block. */ 959 length = 0; 960 } 961 962 if (pba_block_size != NULL) 963 *pba_block_size = length; 964 965 return IXGBE_SUCCESS; 966 } 967 968 /** 969 * ixgbe_get_mac_addr_generic - Generic get MAC address 970 * @hw: pointer to hardware structure 971 * @mac_addr: Adapter MAC address 972 * 973 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 974 * A reset of the adapter must be performed prior to calling this function 975 * in order for the MAC address to have been loaded from the EEPROM into RAR0 976 **/ 977 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 978 { 979 u32 rar_high; 980 u32 rar_low; 981 u16 i; 982 983 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 984 985 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 986 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 987 988 for (i = 0; i < 4; i++) 989 mac_addr[i] = (u8)(rar_low >> (i*8)); 990 991 for (i = 0; i < 2; i++) 992 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 993 994 return IXGBE_SUCCESS; 995 } 996 997 /** 998 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 999 * @hw: pointer to hardware structure 1000 * @link_status: the link status returned by the PCI config space 1001 * 1002 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 1003 **/ 1004 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 1005 { 1006 struct ixgbe_mac_info *mac = &hw->mac; 1007 1008 if (hw->bus.type == ixgbe_bus_type_unknown) 1009 hw->bus.type = ixgbe_bus_type_pci_express; 1010 1011 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 1012 case IXGBE_PCI_LINK_WIDTH_1: 1013 hw->bus.width = ixgbe_bus_width_pcie_x1; 1014 break; 1015 case IXGBE_PCI_LINK_WIDTH_2: 1016 hw->bus.width = ixgbe_bus_width_pcie_x2; 1017 break; 1018 case IXGBE_PCI_LINK_WIDTH_4: 1019 hw->bus.width = ixgbe_bus_width_pcie_x4; 1020 break; 1021 case IXGBE_PCI_LINK_WIDTH_8: 1022 hw->bus.width = ixgbe_bus_width_pcie_x8; 1023 break; 1024 default: 1025 hw->bus.width = ixgbe_bus_width_unknown; 1026 break; 1027 } 1028 1029 switch (link_status & IXGBE_PCI_LINK_SPEED) { 1030 case IXGBE_PCI_LINK_SPEED_2500: 1031 hw->bus.speed = ixgbe_bus_speed_2500; 1032 break; 1033 case IXGBE_PCI_LINK_SPEED_5000: 1034 hw->bus.speed = ixgbe_bus_speed_5000; 1035 break; 1036 case IXGBE_PCI_LINK_SPEED_8000: 1037 hw->bus.speed = ixgbe_bus_speed_8000; 1038 break; 1039 default: 1040 hw->bus.speed = ixgbe_bus_speed_unknown; 1041 break; 1042 } 1043 1044 mac->ops.set_lan_id(hw); 1045 } 1046 1047 /** 1048 * ixgbe_get_bus_info_generic - Generic set PCI bus info 1049 * @hw: pointer to hardware structure 1050 * 1051 * Gets the PCI bus info (speed, width, type) then calls helper function to 1052 * store this data within the ixgbe_hw structure. 1053 **/ 1054 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1055 { 1056 u16 link_status; 1057 1058 DEBUGFUNC("ixgbe_get_bus_info_generic"); 1059 1060 /* Get the negotiated link width and speed from PCI config space */ 1061 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1062 1063 ixgbe_set_pci_config_data_generic(hw, link_status); 1064 1065 return IXGBE_SUCCESS; 1066 } 1067 1068 /** 1069 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1070 * @hw: pointer to the HW structure 1071 * 1072 * Determines the LAN function id by reading memory-mapped registers and swaps 1073 * the port value if requested, and set MAC instance for devices that share 1074 * CS4227. 1075 **/ 1076 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1077 { 1078 struct ixgbe_bus_info *bus = &hw->bus; 1079 u32 reg; 1080 u16 ee_ctrl_4; 1081 1082 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1083 1084 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1085 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1086 bus->lan_id = (u8)bus->func; 1087 1088 /* check for a port swap */ 1089 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 1090 if (reg & IXGBE_FACTPS_LFS) 1091 bus->func ^= 0x1; 1092 1093 /* Get MAC instance from EEPROM for configuring CS4227 */ 1094 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { 1095 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); 1096 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> 1097 IXGBE_EE_CTRL_4_INST_ID_SHIFT; 1098 } 1099 } 1100 1101 /** 1102 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1103 * @hw: pointer to hardware structure 1104 * 1105 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1106 * disables transmit and receive units. The adapter_stopped flag is used by 1107 * the shared code and drivers to determine if the adapter is in a stopped 1108 * state and should not touch the hardware. 1109 **/ 1110 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1111 { 1112 u32 reg_val; 1113 u16 i; 1114 1115 DEBUGFUNC("ixgbe_stop_adapter_generic"); 1116 1117 /* 1118 * Set the adapter_stopped flag so other driver functions stop touching 1119 * the hardware 1120 */ 1121 hw->adapter_stopped = TRUE; 1122 1123 /* Disable the receive unit */ 1124 ixgbe_disable_rx(hw); 1125 1126 /* Clear interrupt mask to stop interrupts from being generated */ 1127 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1128 1129 /* Clear any pending interrupts, flush previous writes */ 1130 IXGBE_READ_REG(hw, IXGBE_EICR); 1131 1132 /* Disable the transmit unit. Each queue must be disabled. */ 1133 for (i = 0; i < hw->mac.max_tx_queues; i++) 1134 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1135 1136 /* Disable the receive unit by stopping each queue */ 1137 for (i = 0; i < hw->mac.max_rx_queues; i++) { 1138 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1139 reg_val &= ~IXGBE_RXDCTL_ENABLE; 1140 reg_val |= IXGBE_RXDCTL_SWFLSH; 1141 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1142 } 1143 1144 /* flush all queues disables */ 1145 IXGBE_WRITE_FLUSH(hw); 1146 msec_delay(2); 1147 1148 /* 1149 * Prevent the PCI-E bus from hanging by disabling PCI-E master 1150 * access and verify no pending requests 1151 */ 1152 return ixgbe_disable_pcie_master(hw); 1153 } 1154 1155 /** 1156 * ixgbe_init_led_link_act_generic - Store the LED index link/activity. 1157 * @hw: pointer to hardware structure 1158 * 1159 * Store the index for the link active LED. This will be used to support 1160 * blinking the LED. 1161 **/ 1162 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) 1163 { 1164 struct ixgbe_mac_info *mac = &hw->mac; 1165 u32 led_reg, led_mode; 1166 u8 i; 1167 1168 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1169 1170 /* Get LED link active from the LEDCTL register */ 1171 for (i = 0; i < 4; i++) { 1172 led_mode = led_reg >> IXGBE_LED_MODE_SHIFT(i); 1173 1174 if ((led_mode & IXGBE_LED_MODE_MASK_BASE) == 1175 IXGBE_LED_LINK_ACTIVE) { 1176 mac->led_link_act = i; 1177 return IXGBE_SUCCESS; 1178 } 1179 } 1180 1181 /* 1182 * If LEDCTL register does not have the LED link active set, then use 1183 * known MAC defaults. 1184 */ 1185 switch (hw->mac.type) { 1186 case ixgbe_mac_X550EM_a: 1187 case ixgbe_mac_X550EM_x: 1188 mac->led_link_act = 1; 1189 break; 1190 default: 1191 mac->led_link_act = 2; 1192 } 1193 return IXGBE_SUCCESS; 1194 } 1195 1196 /** 1197 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1198 * @hw: pointer to hardware structure 1199 * @index: led number to turn on 1200 **/ 1201 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1202 { 1203 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1204 1205 DEBUGFUNC("ixgbe_led_on_generic"); 1206 1207 if (index > 3) 1208 return IXGBE_ERR_PARAM; 1209 1210 /* To turn on the LED, set mode to ON. */ 1211 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1212 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1213 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1214 IXGBE_WRITE_FLUSH(hw); 1215 1216 return IXGBE_SUCCESS; 1217 } 1218 1219 /** 1220 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1221 * @hw: pointer to hardware structure 1222 * @index: led number to turn off 1223 **/ 1224 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1225 { 1226 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1227 1228 DEBUGFUNC("ixgbe_led_off_generic"); 1229 1230 if (index > 3) 1231 return IXGBE_ERR_PARAM; 1232 1233 /* To turn off the LED, set mode to OFF. */ 1234 led_reg &= ~IXGBE_LED_MODE_MASK(index); 1235 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1236 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1237 IXGBE_WRITE_FLUSH(hw); 1238 1239 return IXGBE_SUCCESS; 1240 } 1241 1242 /** 1243 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1244 * @hw: pointer to hardware structure 1245 * 1246 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1247 * ixgbe_hw struct in order to set up EEPROM access. 1248 **/ 1249 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1250 { 1251 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1252 u32 eec; 1253 u16 eeprom_size; 1254 1255 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1256 1257 if (eeprom->type == ixgbe_eeprom_uninitialized) { 1258 eeprom->type = ixgbe_eeprom_none; 1259 /* Set default semaphore delay to 10ms which is a well 1260 * tested value */ 1261 eeprom->semaphore_delay = 10; 1262 /* Clear EEPROM page size, it will be initialized as needed */ 1263 eeprom->word_page_size = 0; 1264 1265 /* 1266 * Check for EEPROM present first. 1267 * If not present leave as none 1268 */ 1269 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1270 if (eec & IXGBE_EEC_PRES) { 1271 eeprom->type = ixgbe_eeprom_spi; 1272 1273 /* 1274 * SPI EEPROM is assumed here. This code would need to 1275 * change if a future EEPROM is not SPI. 1276 */ 1277 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1278 IXGBE_EEC_SIZE_SHIFT); 1279 eeprom->word_size = 1 << (eeprom_size + 1280 IXGBE_EEPROM_WORD_SIZE_SHIFT); 1281 } 1282 1283 if (eec & IXGBE_EEC_ADDR_SIZE) 1284 eeprom->address_bits = 16; 1285 else 1286 eeprom->address_bits = 8; 1287 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1288 "%d\n", eeprom->type, eeprom->word_size, 1289 eeprom->address_bits); 1290 } 1291 1292 return IXGBE_SUCCESS; 1293 } 1294 1295 /** 1296 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1297 * @hw: pointer to hardware structure 1298 * @offset: offset within the EEPROM to write 1299 * @words: number of word(s) 1300 * @data: 16 bit word(s) to write to EEPROM 1301 * 1302 * Reads 16 bit word(s) from EEPROM through bit-bang method 1303 **/ 1304 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1305 u16 words, u16 *data) 1306 { 1307 s32 status = IXGBE_SUCCESS; 1308 u16 i, count; 1309 1310 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1311 1312 hw->eeprom.ops.init_params(hw); 1313 1314 if (words == 0) { 1315 status = IXGBE_ERR_INVALID_ARGUMENT; 1316 goto out; 1317 } 1318 1319 if (offset + words > hw->eeprom.word_size) { 1320 status = IXGBE_ERR_EEPROM; 1321 goto out; 1322 } 1323 1324 /* 1325 * The EEPROM page size cannot be queried from the chip. We do lazy 1326 * initialization. It is worth to do that when we write large buffer. 1327 */ 1328 if ((hw->eeprom.word_page_size == 0) && 1329 (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1330 ixgbe_detect_eeprom_page_size_generic(hw, offset); 1331 1332 /* 1333 * We cannot hold synchronization semaphores for too long 1334 * to avoid other entity starvation. However it is more efficient 1335 * to read in bursts than synchronizing access for each word. 1336 */ 1337 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1338 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1339 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1340 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1341 count, &data[i]); 1342 1343 if (status != IXGBE_SUCCESS) 1344 break; 1345 } 1346 1347 out: 1348 return status; 1349 } 1350 1351 /** 1352 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1353 * @hw: pointer to hardware structure 1354 * @offset: offset within the EEPROM to be written to 1355 * @words: number of word(s) 1356 * @data: 16 bit word(s) to be written to the EEPROM 1357 * 1358 * If ixgbe_eeprom_update_checksum is not called after this function, the 1359 * EEPROM will most likely contain an invalid checksum. 1360 **/ 1361 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1362 u16 words, u16 *data) 1363 { 1364 s32 status; 1365 u16 word; 1366 u16 page_size; 1367 u16 i; 1368 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1369 1370 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1371 1372 /* Prepare the EEPROM for writing */ 1373 status = ixgbe_acquire_eeprom(hw); 1374 1375 if (status == IXGBE_SUCCESS) { 1376 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1377 ixgbe_release_eeprom(hw); 1378 status = IXGBE_ERR_EEPROM; 1379 } 1380 } 1381 1382 if (status == IXGBE_SUCCESS) { 1383 for (i = 0; i < words; i++) { 1384 ixgbe_standby_eeprom(hw); 1385 1386 /* Send the WRITE ENABLE command (8 bit opcode ) */ 1387 ixgbe_shift_out_eeprom_bits(hw, 1388 IXGBE_EEPROM_WREN_OPCODE_SPI, 1389 IXGBE_EEPROM_OPCODE_BITS); 1390 1391 ixgbe_standby_eeprom(hw); 1392 1393 /* 1394 * Some SPI eeproms use the 8th address bit embedded 1395 * in the opcode 1396 */ 1397 if ((hw->eeprom.address_bits == 8) && 1398 ((offset + i) >= 128)) 1399 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1400 1401 /* Send the Write command (8-bit opcode + addr) */ 1402 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1403 IXGBE_EEPROM_OPCODE_BITS); 1404 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1405 hw->eeprom.address_bits); 1406 1407 page_size = hw->eeprom.word_page_size; 1408 1409 /* Send the data in burst via SPI*/ 1410 do { 1411 word = data[i]; 1412 word = (word >> 8) | (word << 8); 1413 ixgbe_shift_out_eeprom_bits(hw, word, 16); 1414 1415 if (page_size == 0) 1416 break; 1417 1418 /* do not wrap around page */ 1419 if (((offset + i) & (page_size - 1)) == 1420 (page_size - 1)) 1421 break; 1422 } while (++i < words); 1423 1424 ixgbe_standby_eeprom(hw); 1425 msec_delay(10); 1426 } 1427 /* Done with writing - release the EEPROM */ 1428 ixgbe_release_eeprom(hw); 1429 } 1430 1431 return status; 1432 } 1433 1434 /** 1435 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1436 * @hw: pointer to hardware structure 1437 * @offset: offset within the EEPROM to be written to 1438 * @data: 16 bit word to be written to the EEPROM 1439 * 1440 * If ixgbe_eeprom_update_checksum is not called after this function, the 1441 * EEPROM will most likely contain an invalid checksum. 1442 **/ 1443 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1444 { 1445 s32 status; 1446 1447 DEBUGFUNC("ixgbe_write_eeprom_generic"); 1448 1449 hw->eeprom.ops.init_params(hw); 1450 1451 if (offset >= hw->eeprom.word_size) { 1452 status = IXGBE_ERR_EEPROM; 1453 goto out; 1454 } 1455 1456 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1457 1458 out: 1459 return status; 1460 } 1461 1462 /** 1463 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1464 * @hw: pointer to hardware structure 1465 * @offset: offset within the EEPROM to be read 1466 * @data: read 16 bit words(s) from EEPROM 1467 * @words: number of word(s) 1468 * 1469 * Reads 16 bit word(s) from EEPROM through bit-bang method 1470 **/ 1471 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1472 u16 words, u16 *data) 1473 { 1474 s32 status = IXGBE_SUCCESS; 1475 u16 i, count; 1476 1477 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1478 1479 hw->eeprom.ops.init_params(hw); 1480 1481 if (words == 0) { 1482 status = IXGBE_ERR_INVALID_ARGUMENT; 1483 goto out; 1484 } 1485 1486 if (offset + words > hw->eeprom.word_size) { 1487 status = IXGBE_ERR_EEPROM; 1488 goto out; 1489 } 1490 1491 /* 1492 * We cannot hold synchronization semaphores for too long 1493 * to avoid other entity starvation. However it is more efficient 1494 * to read in bursts than synchronizing access for each word. 1495 */ 1496 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1497 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1498 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1499 1500 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1501 count, &data[i]); 1502 1503 if (status != IXGBE_SUCCESS) 1504 break; 1505 } 1506 1507 out: 1508 return status; 1509 } 1510 1511 /** 1512 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1513 * @hw: pointer to hardware structure 1514 * @offset: offset within the EEPROM to be read 1515 * @words: number of word(s) 1516 * @data: read 16 bit word(s) from EEPROM 1517 * 1518 * Reads 16 bit word(s) from EEPROM through bit-bang method 1519 **/ 1520 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1521 u16 words, u16 *data) 1522 { 1523 s32 status; 1524 u16 word_in; 1525 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1526 u16 i; 1527 1528 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1529 1530 /* Prepare the EEPROM for reading */ 1531 status = ixgbe_acquire_eeprom(hw); 1532 1533 if (status == IXGBE_SUCCESS) { 1534 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1535 ixgbe_release_eeprom(hw); 1536 status = IXGBE_ERR_EEPROM; 1537 } 1538 } 1539 1540 if (status == IXGBE_SUCCESS) { 1541 for (i = 0; i < words; i++) { 1542 ixgbe_standby_eeprom(hw); 1543 /* 1544 * Some SPI eeproms use the 8th address bit embedded 1545 * in the opcode 1546 */ 1547 if ((hw->eeprom.address_bits == 8) && 1548 ((offset + i) >= 128)) 1549 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1550 1551 /* Send the READ command (opcode + addr) */ 1552 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1553 IXGBE_EEPROM_OPCODE_BITS); 1554 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1555 hw->eeprom.address_bits); 1556 1557 /* Read the data. */ 1558 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1559 data[i] = (word_in >> 8) | (word_in << 8); 1560 } 1561 1562 /* End this read operation */ 1563 ixgbe_release_eeprom(hw); 1564 } 1565 1566 return status; 1567 } 1568 1569 /** 1570 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1571 * @hw: pointer to hardware structure 1572 * @offset: offset within the EEPROM to be read 1573 * @data: read 16 bit value from EEPROM 1574 * 1575 * Reads 16 bit value from EEPROM through bit-bang method 1576 **/ 1577 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1578 u16 *data) 1579 { 1580 s32 status; 1581 1582 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1583 1584 hw->eeprom.ops.init_params(hw); 1585 1586 if (offset >= hw->eeprom.word_size) { 1587 status = IXGBE_ERR_EEPROM; 1588 goto out; 1589 } 1590 1591 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1592 1593 out: 1594 return status; 1595 } 1596 1597 /** 1598 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1599 * @hw: pointer to hardware structure 1600 * @offset: offset of word in the EEPROM to read 1601 * @words: number of word(s) 1602 * @data: 16 bit word(s) from the EEPROM 1603 * 1604 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1605 **/ 1606 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1607 u16 words, u16 *data) 1608 { 1609 u32 eerd; 1610 s32 status = IXGBE_SUCCESS; 1611 u32 i; 1612 1613 DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1614 1615 hw->eeprom.ops.init_params(hw); 1616 1617 if (words == 0) { 1618 status = IXGBE_ERR_INVALID_ARGUMENT; 1619 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1620 goto out; 1621 } 1622 1623 if (offset >= hw->eeprom.word_size) { 1624 status = IXGBE_ERR_EEPROM; 1625 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1626 goto out; 1627 } 1628 1629 for (i = 0; i < words; i++) { 1630 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1631 IXGBE_EEPROM_RW_REG_START; 1632 1633 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1634 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1635 1636 if (status == IXGBE_SUCCESS) { 1637 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1638 IXGBE_EEPROM_RW_REG_DATA); 1639 } else { 1640 DEBUGOUT("Eeprom read timed out\n"); 1641 goto out; 1642 } 1643 } 1644 out: 1645 return status; 1646 } 1647 1648 /** 1649 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1650 * @hw: pointer to hardware structure 1651 * @offset: offset within the EEPROM to be used as a scratch pad 1652 * 1653 * Discover EEPROM page size by writing marching data at given offset. 1654 * This function is called only when we are writing a new large buffer 1655 * at given offset so the data would be overwritten anyway. 1656 **/ 1657 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1658 u16 offset) 1659 { 1660 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1661 s32 status = IXGBE_SUCCESS; 1662 u16 i; 1663 1664 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1665 1666 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1667 data[i] = i; 1668 1669 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1670 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1671 IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1672 hw->eeprom.word_page_size = 0; 1673 if (status != IXGBE_SUCCESS) 1674 goto out; 1675 1676 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1677 if (status != IXGBE_SUCCESS) 1678 goto out; 1679 1680 /* 1681 * When writing in burst more than the actual page size 1682 * EEPROM address wraps around current page. 1683 */ 1684 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1685 1686 DEBUGOUT1("Detected EEPROM page size = %d words.", 1687 hw->eeprom.word_page_size); 1688 out: 1689 return status; 1690 } 1691 1692 /** 1693 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1694 * @hw: pointer to hardware structure 1695 * @offset: offset of word in the EEPROM to read 1696 * @data: word read from the EEPROM 1697 * 1698 * Reads a 16 bit word from the EEPROM using the EERD register. 1699 **/ 1700 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1701 { 1702 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1703 } 1704 1705 /** 1706 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1707 * @hw: pointer to hardware structure 1708 * @offset: offset of word in the EEPROM to write 1709 * @words: number of word(s) 1710 * @data: word(s) write to the EEPROM 1711 * 1712 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1713 **/ 1714 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1715 u16 words, u16 *data) 1716 { 1717 u32 eewr; 1718 s32 status = IXGBE_SUCCESS; 1719 u16 i; 1720 1721 DEBUGFUNC("ixgbe_write_eewr_generic"); 1722 1723 hw->eeprom.ops.init_params(hw); 1724 1725 if (words == 0) { 1726 status = IXGBE_ERR_INVALID_ARGUMENT; 1727 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1728 goto out; 1729 } 1730 1731 if (offset >= hw->eeprom.word_size) { 1732 status = IXGBE_ERR_EEPROM; 1733 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1734 goto out; 1735 } 1736 1737 for (i = 0; i < words; i++) { 1738 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1739 (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1740 IXGBE_EEPROM_RW_REG_START; 1741 1742 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1743 if (status != IXGBE_SUCCESS) { 1744 DEBUGOUT("Eeprom write EEWR timed out\n"); 1745 goto out; 1746 } 1747 1748 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1749 1750 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1751 if (status != IXGBE_SUCCESS) { 1752 DEBUGOUT("Eeprom write EEWR timed out\n"); 1753 goto out; 1754 } 1755 } 1756 1757 out: 1758 return status; 1759 } 1760 1761 /** 1762 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1763 * @hw: pointer to hardware structure 1764 * @offset: offset of word in the EEPROM to write 1765 * @data: word write to the EEPROM 1766 * 1767 * Write a 16 bit word to the EEPROM using the EEWR register. 1768 **/ 1769 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1770 { 1771 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1772 } 1773 1774 /** 1775 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1776 * @hw: pointer to hardware structure 1777 * @ee_reg: EEPROM flag for polling 1778 * 1779 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1780 * read or write is done respectively. 1781 **/ 1782 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1783 { 1784 u32 i; 1785 u32 reg; 1786 s32 status = IXGBE_ERR_EEPROM; 1787 1788 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1789 1790 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1791 if (ee_reg == IXGBE_NVM_POLL_READ) 1792 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1793 else 1794 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1795 1796 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1797 status = IXGBE_SUCCESS; 1798 break; 1799 } 1800 usec_delay(5); 1801 } 1802 1803 if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1804 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1805 "EEPROM read/write done polling timed out"); 1806 1807 return status; 1808 } 1809 1810 /** 1811 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1812 * @hw: pointer to hardware structure 1813 * 1814 * Prepares EEPROM for access using bit-bang method. This function should 1815 * be called before issuing a command to the EEPROM. 1816 **/ 1817 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1818 { 1819 s32 status = IXGBE_SUCCESS; 1820 u32 eec; 1821 u32 i; 1822 1823 DEBUGFUNC("ixgbe_acquire_eeprom"); 1824 1825 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1826 != IXGBE_SUCCESS) 1827 status = IXGBE_ERR_SWFW_SYNC; 1828 1829 if (status == IXGBE_SUCCESS) { 1830 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1831 1832 /* Request EEPROM Access */ 1833 eec |= IXGBE_EEC_REQ; 1834 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1835 1836 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1837 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 1838 if (eec & IXGBE_EEC_GNT) 1839 break; 1840 usec_delay(5); 1841 } 1842 1843 /* Release if grant not acquired */ 1844 if (!(eec & IXGBE_EEC_GNT)) { 1845 eec &= ~IXGBE_EEC_REQ; 1846 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1847 DEBUGOUT("Could not acquire EEPROM grant\n"); 1848 1849 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1850 status = IXGBE_ERR_EEPROM; 1851 } 1852 1853 /* Setup EEPROM for Read/Write */ 1854 if (status == IXGBE_SUCCESS) { 1855 /* Clear CS and SK */ 1856 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1857 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 1858 IXGBE_WRITE_FLUSH(hw); 1859 usec_delay(1); 1860 } 1861 } 1862 return status; 1863 } 1864 1865 /** 1866 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1867 * @hw: pointer to hardware structure 1868 * 1869 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1870 **/ 1871 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1872 { 1873 s32 status = IXGBE_ERR_EEPROM; 1874 u32 timeout = 2000; 1875 u32 i; 1876 u32 swsm; 1877 1878 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1879 1880 1881 /* Get SMBI software semaphore between device drivers first */ 1882 for (i = 0; i < timeout; i++) { 1883 /* 1884 * If the SMBI bit is 0 when we read it, then the bit will be 1885 * set and we have the semaphore 1886 */ 1887 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1888 if (!(swsm & IXGBE_SWSM_SMBI)) { 1889 status = IXGBE_SUCCESS; 1890 break; 1891 } 1892 usec_delay(50); 1893 } 1894 1895 if (i == timeout) { 1896 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1897 "not granted.\n"); 1898 /* 1899 * this release is particularly important because our attempts 1900 * above to get the semaphore may have succeeded, and if there 1901 * was a timeout, we should unconditionally clear the semaphore 1902 * bits to free the driver to make progress 1903 */ 1904 ixgbe_release_eeprom_semaphore(hw); 1905 1906 usec_delay(50); 1907 /* 1908 * one last try 1909 * If the SMBI bit is 0 when we read it, then the bit will be 1910 * set and we have the semaphore 1911 */ 1912 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1913 if (!(swsm & IXGBE_SWSM_SMBI)) 1914 status = IXGBE_SUCCESS; 1915 } 1916 1917 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1918 if (status == IXGBE_SUCCESS) { 1919 for (i = 0; i < timeout; i++) { 1920 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1921 1922 /* Set the SW EEPROM semaphore bit to request access */ 1923 swsm |= IXGBE_SWSM_SWESMBI; 1924 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 1925 1926 /* 1927 * If we set the bit successfully then we got the 1928 * semaphore. 1929 */ 1930 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 1931 if (swsm & IXGBE_SWSM_SWESMBI) 1932 break; 1933 1934 usec_delay(50); 1935 } 1936 1937 /* 1938 * Release semaphores and return error if SW EEPROM semaphore 1939 * was not granted because we don't have access to the EEPROM 1940 */ 1941 if (i >= timeout) { 1942 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1943 "SWESMBI Software EEPROM semaphore not granted.\n"); 1944 ixgbe_release_eeprom_semaphore(hw); 1945 status = IXGBE_ERR_EEPROM; 1946 } 1947 } else { 1948 ERROR_REPORT1(IXGBE_ERROR_POLLING, 1949 "Software semaphore SMBI between device drivers " 1950 "not granted.\n"); 1951 } 1952 1953 return status; 1954 } 1955 1956 /** 1957 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1958 * @hw: pointer to hardware structure 1959 * 1960 * This function clears hardware semaphore bits. 1961 **/ 1962 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1963 { 1964 u32 swsm; 1965 1966 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1967 1968 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1969 1970 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1971 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1972 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1973 IXGBE_WRITE_FLUSH(hw); 1974 } 1975 1976 /** 1977 * ixgbe_ready_eeprom - Polls for EEPROM ready 1978 * @hw: pointer to hardware structure 1979 **/ 1980 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1981 { 1982 s32 status = IXGBE_SUCCESS; 1983 u16 i; 1984 u8 spi_stat_reg; 1985 1986 DEBUGFUNC("ixgbe_ready_eeprom"); 1987 1988 /* 1989 * Read "Status Register" repeatedly until the LSB is cleared. The 1990 * EEPROM will signal that the command has been completed by clearing 1991 * bit 0 of the internal status register. If it's not cleared within 1992 * 5 milliseconds, then error out. 1993 */ 1994 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1995 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1996 IXGBE_EEPROM_OPCODE_BITS); 1997 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1998 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1999 break; 2000 2001 usec_delay(5); 2002 ixgbe_standby_eeprom(hw); 2003 }; 2004 2005 /* 2006 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 2007 * devices (and only 0-5mSec on 5V devices) 2008 */ 2009 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 2010 DEBUGOUT("SPI EEPROM Status error\n"); 2011 status = IXGBE_ERR_EEPROM; 2012 } 2013 2014 return status; 2015 } 2016 2017 /** 2018 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 2019 * @hw: pointer to hardware structure 2020 **/ 2021 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 2022 { 2023 u32 eec; 2024 2025 DEBUGFUNC("ixgbe_standby_eeprom"); 2026 2027 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2028 2029 /* Toggle CS to flush commands */ 2030 eec |= IXGBE_EEC_CS; 2031 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2032 IXGBE_WRITE_FLUSH(hw); 2033 usec_delay(1); 2034 eec &= ~IXGBE_EEC_CS; 2035 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2036 IXGBE_WRITE_FLUSH(hw); 2037 usec_delay(1); 2038 } 2039 2040 /** 2041 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 2042 * @hw: pointer to hardware structure 2043 * @data: data to send to the EEPROM 2044 * @count: number of bits to shift out 2045 **/ 2046 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 2047 u16 count) 2048 { 2049 u32 eec; 2050 u32 mask; 2051 u32 i; 2052 2053 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 2054 2055 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2056 2057 /* 2058 * Mask is used to shift "count" bits of "data" out to the EEPROM 2059 * one bit at a time. Determine the starting bit based on count 2060 */ 2061 mask = 0x01 << (count - 1); 2062 2063 for (i = 0; i < count; i++) { 2064 /* 2065 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 2066 * "1", and then raising and then lowering the clock (the SK 2067 * bit controls the clock input to the EEPROM). A "0" is 2068 * shifted out to the EEPROM by setting "DI" to "0" and then 2069 * raising and then lowering the clock. 2070 */ 2071 if (data & mask) 2072 eec |= IXGBE_EEC_DI; 2073 else 2074 eec &= ~IXGBE_EEC_DI; 2075 2076 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2077 IXGBE_WRITE_FLUSH(hw); 2078 2079 usec_delay(1); 2080 2081 ixgbe_raise_eeprom_clk(hw, &eec); 2082 ixgbe_lower_eeprom_clk(hw, &eec); 2083 2084 /* 2085 * Shift mask to signify next bit of data to shift in to the 2086 * EEPROM 2087 */ 2088 mask = mask >> 1; 2089 }; 2090 2091 /* We leave the "DI" bit set to "0" when we leave this routine. */ 2092 eec &= ~IXGBE_EEC_DI; 2093 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2094 IXGBE_WRITE_FLUSH(hw); 2095 } 2096 2097 /** 2098 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2099 * @hw: pointer to hardware structure 2100 **/ 2101 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2102 { 2103 u32 eec; 2104 u32 i; 2105 u16 data = 0; 2106 2107 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2108 2109 /* 2110 * In order to read a register from the EEPROM, we need to shift 2111 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2112 * the clock input to the EEPROM (setting the SK bit), and then reading 2113 * the value of the "DO" bit. During this "shifting in" process the 2114 * "DI" bit should always be clear. 2115 */ 2116 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2117 2118 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2119 2120 for (i = 0; i < count; i++) { 2121 data = data << 1; 2122 ixgbe_raise_eeprom_clk(hw, &eec); 2123 2124 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2125 2126 eec &= ~(IXGBE_EEC_DI); 2127 if (eec & IXGBE_EEC_DO) 2128 data |= 1; 2129 2130 ixgbe_lower_eeprom_clk(hw, &eec); 2131 } 2132 2133 return data; 2134 } 2135 2136 /** 2137 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2138 * @hw: pointer to hardware structure 2139 * @eec: EEC register's current value 2140 **/ 2141 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2142 { 2143 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2144 2145 /* 2146 * Raise the clock input to the EEPROM 2147 * (setting the SK bit), then delay 2148 */ 2149 *eec = *eec | IXGBE_EEC_SK; 2150 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2151 IXGBE_WRITE_FLUSH(hw); 2152 usec_delay(1); 2153 } 2154 2155 /** 2156 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2157 * @hw: pointer to hardware structure 2158 * @eecd: EECD's current value 2159 **/ 2160 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2161 { 2162 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2163 2164 /* 2165 * Lower the clock input to the EEPROM (clearing the SK bit), then 2166 * delay 2167 */ 2168 *eec = *eec & ~IXGBE_EEC_SK; 2169 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); 2170 IXGBE_WRITE_FLUSH(hw); 2171 usec_delay(1); 2172 } 2173 2174 /** 2175 * ixgbe_release_eeprom - Release EEPROM, release semaphores 2176 * @hw: pointer to hardware structure 2177 **/ 2178 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2179 { 2180 u32 eec; 2181 2182 DEBUGFUNC("ixgbe_release_eeprom"); 2183 2184 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 2185 2186 eec |= IXGBE_EEC_CS; /* Pull CS high */ 2187 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2188 2189 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2190 IXGBE_WRITE_FLUSH(hw); 2191 2192 usec_delay(1); 2193 2194 /* Stop requesting EEPROM access */ 2195 eec &= ~IXGBE_EEC_REQ; 2196 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); 2197 2198 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2199 2200 /* Delay before attempt to obtain semaphore again to allow FW access */ 2201 msec_delay(hw->eeprom.semaphore_delay); 2202 } 2203 2204 /** 2205 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2206 * @hw: pointer to hardware structure 2207 * 2208 * Returns a negative error code on error, or the 16-bit checksum 2209 **/ 2210 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2211 { 2212 u16 i; 2213 u16 j; 2214 u16 checksum = 0; 2215 u16 length = 0; 2216 u16 pointer = 0; 2217 u16 word = 0; 2218 2219 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2220 2221 /* Include 0x0-0x3F in the checksum */ 2222 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2223 if (hw->eeprom.ops.read(hw, i, &word)) { 2224 DEBUGOUT("EEPROM read failed\n"); 2225 return IXGBE_ERR_EEPROM; 2226 } 2227 checksum += word; 2228 } 2229 2230 /* Include all data from pointers except for the fw pointer */ 2231 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2232 if (hw->eeprom.ops.read(hw, i, &pointer)) { 2233 DEBUGOUT("EEPROM read failed\n"); 2234 return IXGBE_ERR_EEPROM; 2235 } 2236 2237 /* If the pointer seems invalid */ 2238 if (pointer == 0xFFFF || pointer == 0) 2239 continue; 2240 2241 if (hw->eeprom.ops.read(hw, pointer, &length)) { 2242 DEBUGOUT("EEPROM read failed\n"); 2243 return IXGBE_ERR_EEPROM; 2244 } 2245 2246 if (length == 0xFFFF || length == 0) 2247 continue; 2248 2249 for (j = pointer + 1; j <= pointer + length; j++) { 2250 if (hw->eeprom.ops.read(hw, j, &word)) { 2251 DEBUGOUT("EEPROM read failed\n"); 2252 return IXGBE_ERR_EEPROM; 2253 } 2254 checksum += word; 2255 } 2256 } 2257 2258 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2259 2260 return (s32)checksum; 2261 } 2262 2263 /** 2264 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2265 * @hw: pointer to hardware structure 2266 * @checksum_val: calculated checksum 2267 * 2268 * Performs checksum calculation and validates the EEPROM checksum. If the 2269 * caller does not need checksum_val, the value can be NULL. 2270 **/ 2271 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2272 u16 *checksum_val) 2273 { 2274 s32 status; 2275 u16 checksum; 2276 u16 read_checksum = 0; 2277 2278 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2279 2280 /* Read the first word from the EEPROM. If this times out or fails, do 2281 * not continue or we could be in for a very long wait while every 2282 * EEPROM read fails 2283 */ 2284 status = hw->eeprom.ops.read(hw, 0, &checksum); 2285 if (status) { 2286 DEBUGOUT("EEPROM read failed\n"); 2287 return status; 2288 } 2289 2290 status = hw->eeprom.ops.calc_checksum(hw); 2291 if (status < 0) 2292 return status; 2293 2294 checksum = (u16)(status & 0xffff); 2295 2296 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2297 if (status) { 2298 DEBUGOUT("EEPROM read failed\n"); 2299 return status; 2300 } 2301 2302 /* Verify read checksum from EEPROM is the same as 2303 * calculated checksum 2304 */ 2305 if (read_checksum != checksum) 2306 status = IXGBE_ERR_EEPROM_CHECKSUM; 2307 2308 /* If the user cares, return the calculated checksum */ 2309 if (checksum_val) 2310 *checksum_val = checksum; 2311 2312 return status; 2313 } 2314 2315 /** 2316 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2317 * @hw: pointer to hardware structure 2318 **/ 2319 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2320 { 2321 s32 status; 2322 u16 checksum; 2323 2324 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2325 2326 /* Read the first word from the EEPROM. If this times out or fails, do 2327 * not continue or we could be in for a very long wait while every 2328 * EEPROM read fails 2329 */ 2330 status = hw->eeprom.ops.read(hw, 0, &checksum); 2331 if (status) { 2332 DEBUGOUT("EEPROM read failed\n"); 2333 return status; 2334 } 2335 2336 status = hw->eeprom.ops.calc_checksum(hw); 2337 if (status < 0) 2338 return status; 2339 2340 checksum = (u16)(status & 0xffff); 2341 2342 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); 2343 2344 return status; 2345 } 2346 2347 /** 2348 * ixgbe_validate_mac_addr - Validate MAC address 2349 * @mac_addr: pointer to MAC address. 2350 * 2351 * Tests a MAC address to ensure it is a valid Individual Address. 2352 **/ 2353 s32 ixgbe_validate_mac_addr(u8 *mac_addr) 2354 { 2355 s32 status = IXGBE_SUCCESS; 2356 2357 DEBUGFUNC("ixgbe_validate_mac_addr"); 2358 2359 /* Make sure it is not a multicast address */ 2360 if (IXGBE_IS_MULTICAST(mac_addr)) { 2361 status = IXGBE_ERR_INVALID_MAC_ADDR; 2362 /* Not a broadcast address */ 2363 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2364 status = IXGBE_ERR_INVALID_MAC_ADDR; 2365 /* Reject the zero address */ 2366 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2367 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2368 status = IXGBE_ERR_INVALID_MAC_ADDR; 2369 } 2370 return status; 2371 } 2372 2373 /** 2374 * ixgbe_set_rar_generic - Set Rx address register 2375 * @hw: pointer to hardware structure 2376 * @index: Receive address register to write 2377 * @addr: Address to put into receive address register 2378 * @vmdq: VMDq "set" or "pool" index 2379 * @enable_addr: set flag that address is active 2380 * 2381 * Puts an ethernet address into a receive address register. 2382 **/ 2383 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2384 u32 enable_addr) 2385 { 2386 u32 rar_low, rar_high; 2387 u32 rar_entries = hw->mac.num_rar_entries; 2388 2389 DEBUGFUNC("ixgbe_set_rar_generic"); 2390 2391 /* Make sure we are using a valid rar index range */ 2392 if (index >= rar_entries) { 2393 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2394 "RAR index %d is out of range.\n", index); 2395 return IXGBE_ERR_INVALID_ARGUMENT; 2396 } 2397 2398 /* setup VMDq pool selection before this RAR gets enabled */ 2399 hw->mac.ops.set_vmdq(hw, index, vmdq); 2400 2401 /* 2402 * HW expects these in little endian so we reverse the byte 2403 * order from network order (big endian) to little endian 2404 */ 2405 rar_low = ((u32)addr[0] | 2406 ((u32)addr[1] << 8) | 2407 ((u32)addr[2] << 16) | 2408 ((u32)addr[3] << 24)); 2409 /* 2410 * Some parts put the VMDq setting in the extra RAH bits, 2411 * so save everything except the lower 16 bits that hold part 2412 * of the address and the address valid bit. 2413 */ 2414 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2415 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2416 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2417 2418 if (enable_addr != 0) 2419 rar_high |= IXGBE_RAH_AV; 2420 2421 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2422 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2423 2424 return IXGBE_SUCCESS; 2425 } 2426 2427 /** 2428 * ixgbe_clear_rar_generic - Remove Rx address register 2429 * @hw: pointer to hardware structure 2430 * @index: Receive address register to write 2431 * 2432 * Clears an ethernet address from a receive address register. 2433 **/ 2434 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2435 { 2436 u32 rar_high; 2437 u32 rar_entries = hw->mac.num_rar_entries; 2438 2439 DEBUGFUNC("ixgbe_clear_rar_generic"); 2440 2441 /* Make sure we are using a valid rar index range */ 2442 if (index >= rar_entries) { 2443 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2444 "RAR index %d is out of range.\n", index); 2445 return IXGBE_ERR_INVALID_ARGUMENT; 2446 } 2447 2448 /* 2449 * Some parts put the VMDq setting in the extra RAH bits, 2450 * so save everything except the lower 16 bits that hold part 2451 * of the address and the address valid bit. 2452 */ 2453 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2454 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2455 2456 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2457 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2458 2459 /* clear VMDq pool/queue selection for this RAR */ 2460 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2461 2462 return IXGBE_SUCCESS; 2463 } 2464 2465 /** 2466 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2467 * @hw: pointer to hardware structure 2468 * 2469 * Places the MAC address in receive address register 0 and clears the rest 2470 * of the receive address registers. Clears the multicast table. Assumes 2471 * the receiver is in reset when the routine is called. 2472 **/ 2473 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2474 { 2475 u32 i; 2476 u32 rar_entries = hw->mac.num_rar_entries; 2477 2478 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2479 2480 /* 2481 * If the current mac address is valid, assume it is a software override 2482 * to the permanent address. 2483 * Otherwise, use the permanent address from the eeprom. 2484 */ 2485 if (ixgbe_validate_mac_addr(hw->mac.addr) == 2486 IXGBE_ERR_INVALID_MAC_ADDR) { 2487 /* Get the MAC address from the RAR0 for later reference */ 2488 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2489 2490 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2491 hw->mac.addr[0], hw->mac.addr[1], 2492 hw->mac.addr[2]); 2493 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2494 hw->mac.addr[4], hw->mac.addr[5]); 2495 } else { 2496 /* Setup the receive address. */ 2497 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2498 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2499 hw->mac.addr[0], hw->mac.addr[1], 2500 hw->mac.addr[2]); 2501 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2502 hw->mac.addr[4], hw->mac.addr[5]); 2503 2504 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2505 } 2506 2507 /* clear VMDq pool/queue selection for RAR 0 */ 2508 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2509 2510 hw->addr_ctrl.overflow_promisc = 0; 2511 2512 hw->addr_ctrl.rar_used_count = 1; 2513 2514 /* Zero out the other receive addresses. */ 2515 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2516 for (i = 1; i < rar_entries; i++) { 2517 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2518 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2519 } 2520 2521 /* Clear the MTA */ 2522 hw->addr_ctrl.mta_in_use = 0; 2523 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2524 2525 DEBUGOUT(" Clearing MTA\n"); 2526 for (i = 0; i < hw->mac.mcft_size; i++) 2527 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2528 2529 ixgbe_init_uta_tables(hw); 2530 2531 return IXGBE_SUCCESS; 2532 } 2533 2534 /** 2535 * ixgbe_add_uc_addr - Adds a secondary unicast address. 2536 * @hw: pointer to hardware structure 2537 * @addr: new address 2538 * 2539 * Adds it to unused receive address register or goes into promiscuous mode. 2540 **/ 2541 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2542 { 2543 u32 rar_entries = hw->mac.num_rar_entries; 2544 u32 rar; 2545 2546 DEBUGFUNC("ixgbe_add_uc_addr"); 2547 2548 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2549 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2550 2551 /* 2552 * Place this address in the RAR if there is room, 2553 * else put the controller into promiscuous mode 2554 */ 2555 if (hw->addr_ctrl.rar_used_count < rar_entries) { 2556 rar = hw->addr_ctrl.rar_used_count; 2557 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2558 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2559 hw->addr_ctrl.rar_used_count++; 2560 } else { 2561 hw->addr_ctrl.overflow_promisc++; 2562 } 2563 2564 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2565 } 2566 2567 /** 2568 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2569 * @hw: pointer to hardware structure 2570 * @addr_list: the list of new addresses 2571 * @addr_count: number of addresses 2572 * @next: iterator function to walk the address list 2573 * 2574 * The given list replaces any existing list. Clears the secondary addrs from 2575 * receive address registers. Uses unused receive address registers for the 2576 * first secondary addresses, and falls back to promiscuous mode as needed. 2577 * 2578 * Drivers using secondary unicast addresses must set user_set_promisc when 2579 * manually putting the device into promiscuous mode. 2580 **/ 2581 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2582 u32 addr_count, ixgbe_mc_addr_itr next) 2583 { 2584 u8 *addr; 2585 u32 i; 2586 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2587 u32 uc_addr_in_use; 2588 u32 fctrl; 2589 u32 vmdq; 2590 2591 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2592 2593 /* 2594 * Clear accounting of old secondary address list, 2595 * don't count RAR[0] 2596 */ 2597 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2598 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2599 hw->addr_ctrl.overflow_promisc = 0; 2600 2601 /* Zero out the other receive addresses */ 2602 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2603 for (i = 0; i < uc_addr_in_use; i++) { 2604 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2605 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2606 } 2607 2608 /* Add the new addresses */ 2609 for (i = 0; i < addr_count; i++) { 2610 DEBUGOUT(" Adding the secondary addresses:\n"); 2611 addr = next(hw, &addr_list, &vmdq); 2612 ixgbe_add_uc_addr(hw, addr, vmdq); 2613 } 2614 2615 if (hw->addr_ctrl.overflow_promisc) { 2616 /* enable promisc if not already in overflow or set by user */ 2617 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2618 DEBUGOUT(" Entering address overflow promisc mode\n"); 2619 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2620 fctrl |= IXGBE_FCTRL_UPE; 2621 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2622 } 2623 } else { 2624 /* only disable if set by overflow, not by user */ 2625 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2626 DEBUGOUT(" Leaving address overflow promisc mode\n"); 2627 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2628 fctrl &= ~IXGBE_FCTRL_UPE; 2629 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2630 } 2631 } 2632 2633 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2634 return IXGBE_SUCCESS; 2635 } 2636 2637 /** 2638 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2639 * @hw: pointer to hardware structure 2640 * @mc_addr: the multicast address 2641 * 2642 * Extracts the 12 bits, from a multicast address, to determine which 2643 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2644 * incoming rx multicast addresses, to determine the bit-vector to check in 2645 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2646 * by the MO field of the MCSTCTRL. The MO field is set during initialization 2647 * to mc_filter_type. 2648 **/ 2649 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2650 { 2651 u32 vector = 0; 2652 2653 DEBUGFUNC("ixgbe_mta_vector"); 2654 2655 switch (hw->mac.mc_filter_type) { 2656 case 0: /* use bits [47:36] of the address */ 2657 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2658 break; 2659 case 1: /* use bits [46:35] of the address */ 2660 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2661 break; 2662 case 2: /* use bits [45:34] of the address */ 2663 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2664 break; 2665 case 3: /* use bits [43:32] of the address */ 2666 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2667 break; 2668 default: /* Invalid mc_filter_type */ 2669 DEBUGOUT("MC filter type param set incorrectly\n"); 2670 ASSERT(0); 2671 break; 2672 } 2673 2674 /* vector can only be 12-bits or boundary will be exceeded */ 2675 vector &= 0xFFF; 2676 return vector; 2677 } 2678 2679 /** 2680 * ixgbe_set_mta - Set bit-vector in multicast table 2681 * @hw: pointer to hardware structure 2682 * @hash_value: Multicast address hash value 2683 * 2684 * Sets the bit-vector in the multicast table. 2685 **/ 2686 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2687 { 2688 u32 vector; 2689 u32 vector_bit; 2690 u32 vector_reg; 2691 2692 DEBUGFUNC("ixgbe_set_mta"); 2693 2694 hw->addr_ctrl.mta_in_use++; 2695 2696 vector = ixgbe_mta_vector(hw, mc_addr); 2697 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2698 2699 /* 2700 * The MTA is a register array of 128 32-bit registers. It is treated 2701 * like an array of 4096 bits. We want to set bit 2702 * BitArray[vector_value]. So we figure out what register the bit is 2703 * in, read it, OR in the new bit, then write back the new value. The 2704 * register is determined by the upper 7 bits of the vector value and 2705 * the bit within that register are determined by the lower 5 bits of 2706 * the value. 2707 */ 2708 vector_reg = (vector >> 5) & 0x7F; 2709 vector_bit = vector & 0x1F; 2710 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2711 } 2712 2713 /** 2714 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2715 * @hw: pointer to hardware structure 2716 * @mc_addr_list: the list of new multicast addresses 2717 * @mc_addr_count: number of addresses 2718 * @next: iterator function to walk the multicast address list 2719 * @clear: flag, when set clears the table beforehand 2720 * 2721 * When the clear flag is set, the given list replaces any existing list. 2722 * Hashes the given addresses into the multicast table. 2723 **/ 2724 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2725 u32 mc_addr_count, ixgbe_mc_addr_itr next, 2726 bool clear) 2727 { 2728 u32 i; 2729 u32 vmdq; 2730 2731 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2732 2733 /* 2734 * Set the new number of MC addresses that we are being requested to 2735 * use. 2736 */ 2737 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2738 hw->addr_ctrl.mta_in_use = 0; 2739 2740 /* Clear mta_shadow */ 2741 if (clear) { 2742 DEBUGOUT(" Clearing MTA\n"); 2743 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2744 } 2745 2746 /* Update mta_shadow */ 2747 for (i = 0; i < mc_addr_count; i++) { 2748 DEBUGOUT(" Adding the multicast addresses:\n"); 2749 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2750 } 2751 2752 /* Enable mta */ 2753 for (i = 0; i < hw->mac.mcft_size; i++) 2754 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2755 hw->mac.mta_shadow[i]); 2756 2757 if (hw->addr_ctrl.mta_in_use > 0) 2758 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2759 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2760 2761 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2762 return IXGBE_SUCCESS; 2763 } 2764 2765 /** 2766 * ixgbe_enable_mc_generic - Enable multicast address in RAR 2767 * @hw: pointer to hardware structure 2768 * 2769 * Enables multicast address in RAR and the use of the multicast hash table. 2770 **/ 2771 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2772 { 2773 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2774 2775 DEBUGFUNC("ixgbe_enable_mc_generic"); 2776 2777 if (a->mta_in_use > 0) 2778 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2779 hw->mac.mc_filter_type); 2780 2781 return IXGBE_SUCCESS; 2782 } 2783 2784 /** 2785 * ixgbe_disable_mc_generic - Disable multicast address in RAR 2786 * @hw: pointer to hardware structure 2787 * 2788 * Disables multicast address in RAR and the use of the multicast hash table. 2789 **/ 2790 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2791 { 2792 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2793 2794 DEBUGFUNC("ixgbe_disable_mc_generic"); 2795 2796 if (a->mta_in_use > 0) 2797 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2798 2799 return IXGBE_SUCCESS; 2800 } 2801 2802 /** 2803 * ixgbe_fc_enable_generic - Enable flow control 2804 * @hw: pointer to hardware structure 2805 * 2806 * Enable flow control according to the current settings. 2807 **/ 2808 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2809 { 2810 s32 ret_val = IXGBE_SUCCESS; 2811 u32 mflcn_reg, fccfg_reg; 2812 u32 reg; 2813 u32 fcrtl, fcrth; 2814 int i; 2815 2816 DEBUGFUNC("ixgbe_fc_enable_generic"); 2817 2818 /* Validate the water mark configuration */ 2819 if (!hw->fc.pause_time) { 2820 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2821 goto out; 2822 } 2823 2824 /* Low water mark of zero causes XOFF floods */ 2825 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2826 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2827 hw->fc.high_water[i]) { 2828 if (!hw->fc.low_water[i] || 2829 hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2830 DEBUGOUT("Invalid water mark configuration\n"); 2831 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2832 goto out; 2833 } 2834 } 2835 } 2836 2837 /* Negotiate the fc mode to use */ 2838 hw->mac.ops.fc_autoneg(hw); 2839 2840 /* Disable any previous flow control settings */ 2841 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2842 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2843 2844 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2845 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2846 2847 /* 2848 * The possible values of fc.current_mode are: 2849 * 0: Flow control is completely disabled 2850 * 1: Rx flow control is enabled (we can receive pause frames, 2851 * but not send pause frames). 2852 * 2: Tx flow control is enabled (we can send pause frames but 2853 * we do not support receiving pause frames). 2854 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2855 * other: Invalid. 2856 */ 2857 switch (hw->fc.current_mode) { 2858 case ixgbe_fc_none: 2859 /* 2860 * Flow control is disabled by software override or autoneg. 2861 * The code below will actually disable it in the HW. 2862 */ 2863 break; 2864 case ixgbe_fc_rx_pause: 2865 /* 2866 * Rx Flow control is enabled and Tx Flow control is 2867 * disabled by software override. Since there really 2868 * isn't a way to advertise that we are capable of RX 2869 * Pause ONLY, we will advertise that we support both 2870 * symmetric and asymmetric Rx PAUSE. Later, we will 2871 * disable the adapter's ability to send PAUSE frames. 2872 */ 2873 mflcn_reg |= IXGBE_MFLCN_RFCE; 2874 break; 2875 case ixgbe_fc_tx_pause: 2876 /* 2877 * Tx Flow control is enabled, and Rx Flow control is 2878 * disabled by software override. 2879 */ 2880 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2881 break; 2882 case ixgbe_fc_full: 2883 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2884 mflcn_reg |= IXGBE_MFLCN_RFCE; 2885 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2886 break; 2887 default: 2888 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2889 "Flow control param set incorrectly\n"); 2890 ret_val = IXGBE_ERR_CONFIG; 2891 goto out; 2892 break; 2893 } 2894 2895 /* Set 802.3x based flow control settings. */ 2896 mflcn_reg |= IXGBE_MFLCN_DPF; 2897 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2898 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2899 2900 2901 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2902 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2903 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2904 hw->fc.high_water[i]) { 2905 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2906 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2907 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2908 } else { 2909 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2910 /* 2911 * In order to prevent Tx hangs when the internal Tx 2912 * switch is enabled we must set the high water mark 2913 * to the Rx packet buffer size - 24KB. This allows 2914 * the Tx switch to function even under heavy Rx 2915 * workloads. 2916 */ 2917 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; 2918 } 2919 2920 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2921 } 2922 2923 /* Configure pause time (2 TCs per register) */ 2924 reg = hw->fc.pause_time * 0x00010001; 2925 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2926 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2927 2928 /* Configure flow control refresh threshold value */ 2929 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2930 2931 out: 2932 return ret_val; 2933 } 2934 2935 /** 2936 * ixgbe_negotiate_fc - Negotiate flow control 2937 * @hw: pointer to hardware structure 2938 * @adv_reg: flow control advertised settings 2939 * @lp_reg: link partner's flow control settings 2940 * @adv_sym: symmetric pause bit in advertisement 2941 * @adv_asm: asymmetric pause bit in advertisement 2942 * @lp_sym: symmetric pause bit in link partner advertisement 2943 * @lp_asm: asymmetric pause bit in link partner advertisement 2944 * 2945 * Find the intersection between advertised settings and link partner's 2946 * advertised settings 2947 **/ 2948 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2949 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2950 { 2951 if ((!(adv_reg)) || (!(lp_reg))) { 2952 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2953 "Local or link partner's advertised flow control " 2954 "settings are NULL. Local: %x, link partner: %x\n", 2955 adv_reg, lp_reg); 2956 return IXGBE_ERR_FC_NOT_NEGOTIATED; 2957 } 2958 2959 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2960 /* 2961 * Now we need to check if the user selected Rx ONLY 2962 * of pause frames. In this case, we had to advertise 2963 * FULL flow control because we could not advertise RX 2964 * ONLY. Hence, we must now check to see if we need to 2965 * turn OFF the TRANSMISSION of PAUSE frames. 2966 */ 2967 if (hw->fc.requested_mode == ixgbe_fc_full) { 2968 hw->fc.current_mode = ixgbe_fc_full; 2969 DEBUGOUT("Flow Control = FULL.\n"); 2970 } else { 2971 hw->fc.current_mode = ixgbe_fc_rx_pause; 2972 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2973 } 2974 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2975 (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2976 hw->fc.current_mode = ixgbe_fc_tx_pause; 2977 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2978 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2979 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2980 hw->fc.current_mode = ixgbe_fc_rx_pause; 2981 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2982 } else { 2983 hw->fc.current_mode = ixgbe_fc_none; 2984 DEBUGOUT("Flow Control = NONE.\n"); 2985 } 2986 return IXGBE_SUCCESS; 2987 } 2988 2989 /** 2990 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2991 * @hw: pointer to hardware structure 2992 * 2993 * Enable flow control according on 1 gig fiber. 2994 **/ 2995 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2996 { 2997 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2998 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2999 3000 /* 3001 * On multispeed fiber at 1g, bail out if 3002 * - link is up but AN did not complete, or if 3003 * - link is up and AN completed but timed out 3004 */ 3005 3006 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 3007 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 3008 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 3009 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); 3010 goto out; 3011 } 3012 3013 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 3014 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 3015 3016 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 3017 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 3018 IXGBE_PCS1GANA_ASM_PAUSE, 3019 IXGBE_PCS1GANA_SYM_PAUSE, 3020 IXGBE_PCS1GANA_ASM_PAUSE); 3021 3022 out: 3023 return ret_val; 3024 } 3025 3026 /** 3027 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 3028 * @hw: pointer to hardware structure 3029 * 3030 * Enable flow control according to IEEE clause 37. 3031 **/ 3032 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 3033 { 3034 u32 links2, anlp1_reg, autoc_reg, links; 3035 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3036 3037 /* 3038 * On backplane, bail out if 3039 * - backplane autoneg was not completed, or if 3040 * - we are 82599 and link partner is not AN enabled 3041 */ 3042 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 3043 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 3044 DEBUGOUT("Auto-Negotiation did not complete\n"); 3045 goto out; 3046 } 3047 3048 if (hw->mac.type == ixgbe_mac_82599EB) { 3049 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 3050 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 3051 DEBUGOUT("Link partner is not AN enabled\n"); 3052 goto out; 3053 } 3054 } 3055 /* 3056 * Read the 10g AN autoc and LP ability registers and resolve 3057 * local flow control settings accordingly 3058 */ 3059 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3060 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 3061 3062 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 3063 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 3064 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 3065 3066 out: 3067 return ret_val; 3068 } 3069 3070 /** 3071 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 3072 * @hw: pointer to hardware structure 3073 * 3074 * Enable flow control according to IEEE clause 37. 3075 **/ 3076 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 3077 { 3078 u16 technology_ability_reg = 0; 3079 u16 lp_technology_ability_reg = 0; 3080 3081 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 3082 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3083 &technology_ability_reg); 3084 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 3085 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3086 &lp_technology_ability_reg); 3087 3088 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 3089 (u32)lp_technology_ability_reg, 3090 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 3091 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 3092 } 3093 3094 /** 3095 * ixgbe_fc_autoneg - Configure flow control 3096 * @hw: pointer to hardware structure 3097 * 3098 * Compares our advertised flow control capabilities to those advertised by 3099 * our link partner, and determines the proper flow control mode to use. 3100 **/ 3101 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) 3102 { 3103 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 3104 ixgbe_link_speed speed; 3105 bool link_up; 3106 3107 DEBUGFUNC("ixgbe_fc_autoneg"); 3108 3109 /* 3110 * AN should have completed when the cable was plugged in. 3111 * Look for reasons to bail out. Bail out if: 3112 * - FC autoneg is disabled, or if 3113 * - link is not up. 3114 */ 3115 if (hw->fc.disable_fc_autoneg) { 3116 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3117 "Flow control autoneg is disabled"); 3118 goto out; 3119 } 3120 3121 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3122 if (!link_up) { 3123 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3124 goto out; 3125 } 3126 3127 switch (hw->phy.media_type) { 3128 /* Autoneg flow control on fiber adapters */ 3129 case ixgbe_media_type_fiber_fixed: 3130 case ixgbe_media_type_fiber_qsfp: 3131 case ixgbe_media_type_fiber: 3132 if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3133 ret_val = ixgbe_fc_autoneg_fiber(hw); 3134 break; 3135 3136 /* Autoneg flow control on backplane adapters */ 3137 case ixgbe_media_type_backplane: 3138 ret_val = ixgbe_fc_autoneg_backplane(hw); 3139 break; 3140 3141 /* Autoneg flow control on copper adapters */ 3142 case ixgbe_media_type_copper: 3143 if (ixgbe_device_supports_autoneg_fc(hw)) 3144 ret_val = ixgbe_fc_autoneg_copper(hw); 3145 break; 3146 3147 default: 3148 break; 3149 } 3150 3151 out: 3152 if (ret_val == IXGBE_SUCCESS) { 3153 hw->fc.fc_was_autonegged = TRUE; 3154 } else { 3155 hw->fc.fc_was_autonegged = FALSE; 3156 hw->fc.current_mode = hw->fc.requested_mode; 3157 } 3158 } 3159 3160 /* 3161 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3162 * @hw: pointer to hardware structure 3163 * 3164 * System-wide timeout range is encoded in PCIe Device Control2 register. 3165 * 3166 * Add 10% to specified maximum and return the number of times to poll for 3167 * completion timeout, in units of 100 microsec. Never return less than 3168 * 800 = 80 millisec. 3169 */ 3170 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3171 { 3172 s16 devctl2; 3173 u32 pollcnt; 3174 3175 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3176 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3177 3178 switch (devctl2) { 3179 case IXGBE_PCIDEVCTRL2_65_130ms: 3180 pollcnt = 1300; /* 130 millisec */ 3181 break; 3182 case IXGBE_PCIDEVCTRL2_260_520ms: 3183 pollcnt = 5200; /* 520 millisec */ 3184 break; 3185 case IXGBE_PCIDEVCTRL2_1_2s: 3186 pollcnt = 20000; /* 2 sec */ 3187 break; 3188 case IXGBE_PCIDEVCTRL2_4_8s: 3189 pollcnt = 80000; /* 8 sec */ 3190 break; 3191 case IXGBE_PCIDEVCTRL2_17_34s: 3192 pollcnt = 34000; /* 34 sec */ 3193 break; 3194 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3195 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3196 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3197 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3198 default: 3199 pollcnt = 800; /* 80 millisec minimum */ 3200 break; 3201 } 3202 3203 /* add 10% to spec maximum */ 3204 return (pollcnt * 11) / 10; 3205 } 3206 3207 /** 3208 * ixgbe_disable_pcie_master - Disable PCI-express master access 3209 * @hw: pointer to hardware structure 3210 * 3211 * Disables PCI-Express master access and verifies there are no pending 3212 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3213 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3214 * is returned signifying master requests disabled. 3215 **/ 3216 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3217 { 3218 s32 status = IXGBE_SUCCESS; 3219 u32 i, poll; 3220 u16 value; 3221 3222 DEBUGFUNC("ixgbe_disable_pcie_master"); 3223 3224 /* Always set this bit to ensure any future transactions are blocked */ 3225 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3226 3227 /* Exit if master requests are blocked */ 3228 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || 3229 IXGBE_REMOVED(hw->hw_addr)) 3230 goto out; 3231 3232 /* Poll for master request bit to clear */ 3233 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3234 usec_delay(100); 3235 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3236 goto out; 3237 } 3238 3239 /* 3240 * Two consecutive resets are required via CTRL.RST per datasheet 3241 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3242 * of this need. The first reset prevents new master requests from 3243 * being issued by our device. We then must wait 1usec or more for any 3244 * remaining completions from the PCIe bus to trickle in, and then reset 3245 * again to clear out any effects they may have had on our device. 3246 */ 3247 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3248 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3249 3250 if (hw->mac.type >= ixgbe_mac_X550) 3251 goto out; 3252 3253 /* 3254 * Before proceeding, make sure that the PCIe block does not have 3255 * transactions pending. 3256 */ 3257 poll = ixgbe_pcie_timeout_poll(hw); 3258 for (i = 0; i < poll; i++) { 3259 usec_delay(100); 3260 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 3261 if (IXGBE_REMOVED(hw->hw_addr)) 3262 goto out; 3263 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3264 goto out; 3265 } 3266 3267 ERROR_REPORT1(IXGBE_ERROR_POLLING, 3268 "PCIe transaction pending bit also did not clear.\n"); 3269 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3270 3271 out: 3272 return status; 3273 } 3274 3275 /** 3276 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3277 * @hw: pointer to hardware structure 3278 * @mask: Mask to specify which semaphore to acquire 3279 * 3280 * Acquires the SWFW semaphore through the GSSR register for the specified 3281 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3282 **/ 3283 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3284 { 3285 u32 gssr = 0; 3286 u32 swmask = mask; 3287 u32 fwmask = mask << 5; 3288 u32 timeout = 200; 3289 u32 i; 3290 3291 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3292 3293 for (i = 0; i < timeout; i++) { 3294 /* 3295 * SW NVM semaphore bit is used for access to all 3296 * SW_FW_SYNC bits (not just NVM) 3297 */ 3298 if (ixgbe_get_eeprom_semaphore(hw)) 3299 return IXGBE_ERR_SWFW_SYNC; 3300 3301 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3302 if (!(gssr & (fwmask | swmask))) { 3303 gssr |= swmask; 3304 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3305 ixgbe_release_eeprom_semaphore(hw); 3306 return IXGBE_SUCCESS; 3307 } else { 3308 /* Resource is currently in use by FW or SW */ 3309 ixgbe_release_eeprom_semaphore(hw); 3310 msec_delay(5); 3311 } 3312 } 3313 3314 /* If time expired clear the bits holding the lock and retry */ 3315 if (gssr & (fwmask | swmask)) 3316 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3317 3318 msec_delay(5); 3319 return IXGBE_ERR_SWFW_SYNC; 3320 } 3321 3322 /** 3323 * ixgbe_release_swfw_sync - Release SWFW semaphore 3324 * @hw: pointer to hardware structure 3325 * @mask: Mask to specify which semaphore to release 3326 * 3327 * Releases the SWFW semaphore through the GSSR register for the specified 3328 * function (CSR, PHY0, PHY1, EEPROM, Flash) 3329 **/ 3330 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) 3331 { 3332 u32 gssr; 3333 u32 swmask = mask; 3334 3335 DEBUGFUNC("ixgbe_release_swfw_sync"); 3336 3337 ixgbe_get_eeprom_semaphore(hw); 3338 3339 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3340 gssr &= ~swmask; 3341 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3342 3343 ixgbe_release_eeprom_semaphore(hw); 3344 } 3345 3346 /** 3347 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3348 * @hw: pointer to hardware structure 3349 * 3350 * Stops the receive data path and waits for the HW to internally empty 3351 * the Rx security block 3352 **/ 3353 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3354 { 3355 #define IXGBE_MAX_SECRX_POLL 4000 3356 3357 int i; 3358 int secrxreg; 3359 3360 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3361 3362 3363 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3364 secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3365 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3366 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3367 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3368 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3369 break; 3370 else 3371 /* Use interrupt-safe sleep just in case */ 3372 usec_delay(10); 3373 } 3374 3375 /* For informational purposes only */ 3376 if (i >= IXGBE_MAX_SECRX_POLL) 3377 DEBUGOUT("Rx unit being enabled before security " 3378 "path fully disabled. Continuing with init.\n"); 3379 3380 return IXGBE_SUCCESS; 3381 } 3382 3383 /** 3384 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read 3385 * @hw: pointer to hardware structure 3386 * @reg_val: Value we read from AUTOC 3387 * 3388 * The default case requires no protection so just to the register read. 3389 */ 3390 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) 3391 { 3392 *locked = FALSE; 3393 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3394 return IXGBE_SUCCESS; 3395 } 3396 3397 /** 3398 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write 3399 * @hw: pointer to hardware structure 3400 * @reg_val: value to write to AUTOC 3401 * @locked: bool to indicate whether the SW/FW lock was already taken by 3402 * previous read. 3403 * 3404 * The default case requires no protection so just to the register write. 3405 */ 3406 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) 3407 { 3408 UNREFERENCED_1PARAMETER(locked); 3409 3410 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); 3411 return IXGBE_SUCCESS; 3412 } 3413 3414 /** 3415 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3416 * @hw: pointer to hardware structure 3417 * 3418 * Enables the receive data path. 3419 **/ 3420 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3421 { 3422 u32 secrxreg; 3423 3424 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3425 3426 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3427 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3428 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3429 IXGBE_WRITE_FLUSH(hw); 3430 3431 return IXGBE_SUCCESS; 3432 } 3433 3434 /** 3435 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3436 * @hw: pointer to hardware structure 3437 * @regval: register value to write to RXCTRL 3438 * 3439 * Enables the Rx DMA unit 3440 **/ 3441 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3442 { 3443 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3444 3445 if (regval & IXGBE_RXCTRL_RXEN) 3446 ixgbe_enable_rx(hw); 3447 else 3448 ixgbe_disable_rx(hw); 3449 3450 return IXGBE_SUCCESS; 3451 } 3452 3453 /** 3454 * ixgbe_blink_led_start_generic - Blink LED based on index. 3455 * @hw: pointer to hardware structure 3456 * @index: led number to blink 3457 **/ 3458 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3459 { 3460 ixgbe_link_speed speed = 0; 3461 bool link_up = 0; 3462 u32 autoc_reg = 0; 3463 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3464 s32 ret_val = IXGBE_SUCCESS; 3465 bool locked = FALSE; 3466 3467 DEBUGFUNC("ixgbe_blink_led_start_generic"); 3468 3469 if (index > 3) 3470 return IXGBE_ERR_PARAM; 3471 3472 /* 3473 * Link must be up to auto-blink the LEDs; 3474 * Force it if link is down. 3475 */ 3476 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3477 3478 if (!link_up) { 3479 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3480 if (ret_val != IXGBE_SUCCESS) 3481 goto out; 3482 3483 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3484 autoc_reg |= IXGBE_AUTOC_FLU; 3485 3486 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3487 if (ret_val != IXGBE_SUCCESS) 3488 goto out; 3489 3490 IXGBE_WRITE_FLUSH(hw); 3491 msec_delay(10); 3492 } 3493 3494 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3495 led_reg |= IXGBE_LED_BLINK(index); 3496 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3497 IXGBE_WRITE_FLUSH(hw); 3498 3499 out: 3500 return ret_val; 3501 } 3502 3503 /** 3504 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3505 * @hw: pointer to hardware structure 3506 * @index: led number to stop blinking 3507 **/ 3508 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3509 { 3510 u32 autoc_reg = 0; 3511 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3512 s32 ret_val = IXGBE_SUCCESS; 3513 bool locked = FALSE; 3514 3515 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3516 3517 if (index > 3) 3518 return IXGBE_ERR_PARAM; 3519 3520 3521 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); 3522 if (ret_val != IXGBE_SUCCESS) 3523 goto out; 3524 3525 autoc_reg &= ~IXGBE_AUTOC_FLU; 3526 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3527 3528 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); 3529 if (ret_val != IXGBE_SUCCESS) 3530 goto out; 3531 3532 led_reg &= ~IXGBE_LED_MODE_MASK(index); 3533 led_reg &= ~IXGBE_LED_BLINK(index); 3534 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3535 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3536 IXGBE_WRITE_FLUSH(hw); 3537 3538 out: 3539 return ret_val; 3540 } 3541 3542 /** 3543 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3544 * @hw: pointer to hardware structure 3545 * @san_mac_offset: SAN MAC address offset 3546 * 3547 * This function will read the EEPROM location for the SAN MAC address 3548 * pointer, and returns the value at that location. This is used in both 3549 * get and set mac_addr routines. 3550 **/ 3551 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3552 u16 *san_mac_offset) 3553 { 3554 s32 ret_val; 3555 3556 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3557 3558 /* 3559 * First read the EEPROM pointer to see if the MAC addresses are 3560 * available. 3561 */ 3562 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3563 san_mac_offset); 3564 if (ret_val) { 3565 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3566 "eeprom at offset %d failed", 3567 IXGBE_SAN_MAC_ADDR_PTR); 3568 } 3569 3570 return ret_val; 3571 } 3572 3573 /** 3574 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3575 * @hw: pointer to hardware structure 3576 * @san_mac_addr: SAN MAC address 3577 * 3578 * Reads the SAN MAC address from the EEPROM, if it's available. This is 3579 * per-port, so set_lan_id() must be called before reading the addresses. 3580 * set_lan_id() is called by identify_sfp(), but this cannot be relied 3581 * upon for non-SFP connections, so we must call it here. 3582 **/ 3583 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3584 { 3585 u16 san_mac_data, san_mac_offset; 3586 u8 i; 3587 s32 ret_val; 3588 3589 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3590 3591 /* 3592 * First read the EEPROM pointer to see if the MAC addresses are 3593 * available. If they're not, no point in calling set_lan_id() here. 3594 */ 3595 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3596 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3597 goto san_mac_addr_out; 3598 3599 /* make sure we know which port we need to program */ 3600 hw->mac.ops.set_lan_id(hw); 3601 /* apply the port offset to the address offset */ 3602 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3603 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3604 for (i = 0; i < 3; i++) { 3605 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3606 &san_mac_data); 3607 if (ret_val) { 3608 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3609 "eeprom read at offset %d failed", 3610 san_mac_offset); 3611 goto san_mac_addr_out; 3612 } 3613 san_mac_addr[i * 2] = (u8)(san_mac_data); 3614 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3615 san_mac_offset++; 3616 } 3617 return IXGBE_SUCCESS; 3618 3619 san_mac_addr_out: 3620 /* 3621 * No addresses available in this EEPROM. It's not an 3622 * error though, so just wipe the local address and return. 3623 */ 3624 for (i = 0; i < 6; i++) 3625 san_mac_addr[i] = 0xFF; 3626 return IXGBE_SUCCESS; 3627 } 3628 3629 /** 3630 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3631 * @hw: pointer to hardware structure 3632 * @san_mac_addr: SAN MAC address 3633 * 3634 * Write a SAN MAC address to the EEPROM. 3635 **/ 3636 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3637 { 3638 s32 ret_val; 3639 u16 san_mac_data, san_mac_offset; 3640 u8 i; 3641 3642 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3643 3644 /* Look for SAN mac address pointer. If not defined, return */ 3645 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3646 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3647 return IXGBE_ERR_NO_SAN_ADDR_PTR; 3648 3649 /* Make sure we know which port we need to write */ 3650 hw->mac.ops.set_lan_id(hw); 3651 /* Apply the port offset to the address offset */ 3652 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3653 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3654 3655 for (i = 0; i < 3; i++) { 3656 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3657 san_mac_data |= (u16)(san_mac_addr[i * 2]); 3658 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3659 san_mac_offset++; 3660 } 3661 3662 return IXGBE_SUCCESS; 3663 } 3664 3665 /** 3666 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3667 * @hw: pointer to hardware structure 3668 * 3669 * Read PCIe configuration space, and get the MSI-X vector count from 3670 * the capabilities table. 3671 **/ 3672 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3673 { 3674 u16 msix_count = 1; 3675 u16 max_msix_count; 3676 u16 pcie_offset; 3677 3678 switch (hw->mac.type) { 3679 case ixgbe_mac_82598EB: 3680 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3681 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3682 break; 3683 case ixgbe_mac_82599EB: 3684 case ixgbe_mac_X540: 3685 case ixgbe_mac_X550: 3686 case ixgbe_mac_X550EM_x: 3687 case ixgbe_mac_X550EM_a: 3688 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3689 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3690 break; 3691 default: 3692 return msix_count; 3693 } 3694 3695 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3696 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3697 if (IXGBE_REMOVED(hw->hw_addr)) 3698 msix_count = 0; 3699 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3700 3701 /* MSI-X count is zero-based in HW */ 3702 msix_count++; 3703 3704 if (msix_count > max_msix_count) 3705 msix_count = max_msix_count; 3706 3707 return msix_count; 3708 } 3709 3710 /** 3711 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3712 * @hw: pointer to hardware structure 3713 * @addr: Address to put into receive address register 3714 * @vmdq: VMDq pool to assign 3715 * 3716 * Puts an ethernet address into a receive address register, or 3717 * finds the rar that it is aleady in; adds to the pool list 3718 **/ 3719 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3720 { 3721 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3722 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3723 u32 rar; 3724 u32 rar_low, rar_high; 3725 u32 addr_low, addr_high; 3726 3727 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3728 3729 /* swap bytes for HW little endian */ 3730 addr_low = addr[0] | (addr[1] << 8) 3731 | (addr[2] << 16) 3732 | (addr[3] << 24); 3733 addr_high = addr[4] | (addr[5] << 8); 3734 3735 /* 3736 * Either find the mac_id in rar or find the first empty space. 3737 * rar_highwater points to just after the highest currently used 3738 * rar in order to shorten the search. It grows when we add a new 3739 * rar to the top. 3740 */ 3741 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3742 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3743 3744 if (((IXGBE_RAH_AV & rar_high) == 0) 3745 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3746 first_empty_rar = rar; 3747 } else if ((rar_high & 0xFFFF) == addr_high) { 3748 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3749 if (rar_low == addr_low) 3750 break; /* found it already in the rars */ 3751 } 3752 } 3753 3754 if (rar < hw->mac.rar_highwater) { 3755 /* already there so just add to the pool bits */ 3756 ixgbe_set_vmdq(hw, rar, vmdq); 3757 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3758 /* stick it into first empty RAR slot we found */ 3759 rar = first_empty_rar; 3760 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3761 } else if (rar == hw->mac.rar_highwater) { 3762 /* add it to the top of the list and inc the highwater mark */ 3763 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3764 hw->mac.rar_highwater++; 3765 } else if (rar >= hw->mac.num_rar_entries) { 3766 return IXGBE_ERR_INVALID_MAC_ADDR; 3767 } 3768 3769 /* 3770 * If we found rar[0], make sure the default pool bit (we use pool 0) 3771 * remains cleared to be sure default pool packets will get delivered 3772 */ 3773 if (rar == 0) 3774 ixgbe_clear_vmdq(hw, rar, 0); 3775 3776 return rar; 3777 } 3778 3779 /** 3780 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3781 * @hw: pointer to hardware struct 3782 * @rar: receive address register index to disassociate 3783 * @vmdq: VMDq pool index to remove from the rar 3784 **/ 3785 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3786 { 3787 u32 mpsar_lo, mpsar_hi; 3788 u32 rar_entries = hw->mac.num_rar_entries; 3789 3790 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3791 3792 /* Make sure we are using a valid rar index range */ 3793 if (rar >= rar_entries) { 3794 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3795 "RAR index %d is out of range.\n", rar); 3796 return IXGBE_ERR_INVALID_ARGUMENT; 3797 } 3798 3799 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3800 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3801 3802 if (IXGBE_REMOVED(hw->hw_addr)) 3803 goto done; 3804 3805 if (!mpsar_lo && !mpsar_hi) 3806 goto done; 3807 3808 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3809 if (mpsar_lo) { 3810 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3811 mpsar_lo = 0; 3812 } 3813 if (mpsar_hi) { 3814 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3815 mpsar_hi = 0; 3816 } 3817 } else if (vmdq < 32) { 3818 mpsar_lo &= ~(1 << vmdq); 3819 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3820 } else { 3821 mpsar_hi &= ~(1 << (vmdq - 32)); 3822 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3823 } 3824 3825 /* was that the last pool using this rar? */ 3826 if (mpsar_lo == 0 && mpsar_hi == 0 && 3827 rar != 0 && rar != hw->mac.san_mac_rar_index) 3828 hw->mac.ops.clear_rar(hw, rar); 3829 done: 3830 return IXGBE_SUCCESS; 3831 } 3832 3833 /** 3834 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3835 * @hw: pointer to hardware struct 3836 * @rar: receive address register index to associate with a VMDq index 3837 * @vmdq: VMDq pool index 3838 **/ 3839 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3840 { 3841 u32 mpsar; 3842 u32 rar_entries = hw->mac.num_rar_entries; 3843 3844 DEBUGFUNC("ixgbe_set_vmdq_generic"); 3845 3846 /* Make sure we are using a valid rar index range */ 3847 if (rar >= rar_entries) { 3848 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3849 "RAR index %d is out of range.\n", rar); 3850 return IXGBE_ERR_INVALID_ARGUMENT; 3851 } 3852 3853 if (vmdq < 32) { 3854 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3855 mpsar |= 1 << vmdq; 3856 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3857 } else { 3858 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3859 mpsar |= 1 << (vmdq - 32); 3860 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3861 } 3862 return IXGBE_SUCCESS; 3863 } 3864 3865 /** 3866 * This function should only be involved in the IOV mode. 3867 * In IOV mode, Default pool is next pool after the number of 3868 * VFs advertized and not 0. 3869 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3870 * 3871 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3872 * @hw: pointer to hardware struct 3873 * @vmdq: VMDq pool index 3874 **/ 3875 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3876 { 3877 u32 rar = hw->mac.san_mac_rar_index; 3878 3879 DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3880 3881 if (vmdq < 32) { 3882 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3883 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3884 } else { 3885 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3886 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3887 } 3888 3889 return IXGBE_SUCCESS; 3890 } 3891 3892 /** 3893 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3894 * @hw: pointer to hardware structure 3895 **/ 3896 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3897 { 3898 int i; 3899 3900 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3901 DEBUGOUT(" Clearing UTA\n"); 3902 3903 for (i = 0; i < 128; i++) 3904 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3905 3906 return IXGBE_SUCCESS; 3907 } 3908 3909 /** 3910 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3911 * @hw: pointer to hardware structure 3912 * @vlan: VLAN id to write to VLAN filter 3913 * 3914 * return the VLVF index where this VLAN id should be placed 3915 * 3916 **/ 3917 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) 3918 { 3919 s32 regindex, first_empty_slot; 3920 u32 bits; 3921 3922 /* short cut the special case */ 3923 if (vlan == 0) 3924 return 0; 3925 3926 /* if vlvf_bypass is set we don't want to use an empty slot, we 3927 * will simply bypass the VLVF if there are no entries present in the 3928 * VLVF that contain our VLAN 3929 */ 3930 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; 3931 3932 /* add VLAN enable bit for comparison */ 3933 vlan |= IXGBE_VLVF_VIEN; 3934 3935 /* Search for the vlan id in the VLVF entries. Save off the first empty 3936 * slot found along the way. 3937 * 3938 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 3939 */ 3940 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { 3941 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3942 if (bits == vlan) 3943 return regindex; 3944 if (!first_empty_slot && !bits) 3945 first_empty_slot = regindex; 3946 } 3947 3948 /* If we are here then we didn't find the VLAN. Return first empty 3949 * slot we found during our search, else error. 3950 */ 3951 if (!first_empty_slot) 3952 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "No space in VLVF.\n"); 3953 3954 return first_empty_slot ? first_empty_slot : IXGBE_ERR_NO_SPACE; 3955 } 3956 3957 /** 3958 * ixgbe_set_vfta_generic - Set VLAN filter table 3959 * @hw: pointer to hardware structure 3960 * @vlan: VLAN id to write to VLAN filter 3961 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 3962 * @vlan_on: boolean flag to turn on/off VLAN 3963 * @vlvf_bypass: boolean flag indicating updating default pool is okay 3964 * 3965 * Turn on/off specified VLAN in the VLAN filter table. 3966 **/ 3967 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3968 bool vlan_on, bool vlvf_bypass) 3969 { 3970 u32 regidx, vfta_delta, vfta; 3971 s32 ret_val; 3972 3973 DEBUGFUNC("ixgbe_set_vfta_generic"); 3974 3975 if (vlan > 4095 || vind > 63) 3976 return IXGBE_ERR_PARAM; 3977 3978 /* 3979 * this is a 2 part operation - first the VFTA, then the 3980 * VLVF and VLVFB if VT Mode is set 3981 * We don't write the VFTA until we know the VLVF part succeeded. 3982 */ 3983 3984 /* Part 1 3985 * The VFTA is a bitstring made up of 128 32-bit registers 3986 * that enable the particular VLAN id, much like the MTA: 3987 * bits[11-5]: which register 3988 * bits[4-0]: which bit in the register 3989 */ 3990 regidx = vlan / 32; 3991 vfta_delta = 1 << (vlan % 32); 3992 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); 3993 3994 /* 3995 * vfta_delta represents the difference between the current value 3996 * of vfta and the value we want in the register. Since the diff 3997 * is an XOR mask we can just update the vfta using an XOR 3998 */ 3999 vfta_delta &= vlan_on ? ~vfta : vfta; 4000 vfta ^= vfta_delta; 4001 4002 /* Part 2 4003 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 4004 */ 4005 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, 4006 vfta, vlvf_bypass); 4007 if (ret_val != IXGBE_SUCCESS) { 4008 if (vlvf_bypass) 4009 goto vfta_update; 4010 return ret_val; 4011 } 4012 4013 vfta_update: 4014 /* Update VFTA now that we are ready for traffic */ 4015 if (vfta_delta) 4016 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); 4017 4018 return IXGBE_SUCCESS; 4019 } 4020 4021 /** 4022 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 4023 * @hw: pointer to hardware structure 4024 * @vlan: VLAN id to write to VLAN filter 4025 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 4026 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 4027 * @vfta_delta: pointer to the difference between the current value of VFTA 4028 * and the desired value 4029 * @vfta: the desired value of the VFTA 4030 * @vlvf_bypass: boolean flag indicating updating default pool is okay 4031 * 4032 * Turn on/off specified bit in VLVF table. 4033 **/ 4034 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 4035 bool vlan_on, u32 *vfta_delta, u32 vfta, 4036 bool vlvf_bypass) 4037 { 4038 u32 bits; 4039 s32 vlvf_index; 4040 4041 DEBUGFUNC("ixgbe_set_vlvf_generic"); 4042 4043 if (vlan > 4095 || vind > 63) 4044 return IXGBE_ERR_PARAM; 4045 4046 /* If VT Mode is set 4047 * Either vlan_on 4048 * make sure the vlan is in VLVF 4049 * set the vind bit in the matching VLVFB 4050 * Or !vlan_on 4051 * clear the pool bit and possibly the vind 4052 */ 4053 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) 4054 return IXGBE_SUCCESS; 4055 4056 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); 4057 if (vlvf_index < 0) 4058 return vlvf_index; 4059 4060 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); 4061 4062 /* set the pool bit */ 4063 bits |= 1 << (vind % 32); 4064 if (vlan_on) 4065 goto vlvf_update; 4066 4067 /* clear the pool bit */ 4068 bits ^= 1 << (vind % 32); 4069 4070 if (!bits && 4071 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { 4072 /* Clear VFTA first, then disable VLVF. Otherwise 4073 * we run the risk of stray packets leaking into 4074 * the PF via the default pool 4075 */ 4076 if (*vfta_delta) 4077 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); 4078 4079 /* disable VLVF and clear remaining bit from pool */ 4080 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 4081 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); 4082 4083 return IXGBE_SUCCESS; 4084 } 4085 4086 /* If there are still bits set in the VLVFB registers 4087 * for the VLAN ID indicated we need to see if the 4088 * caller is requesting that we clear the VFTA entry bit. 4089 * If the caller has requested that we clear the VFTA 4090 * entry bit but there are still pools/VFs using this VLAN 4091 * ID entry then ignore the request. We're not worried 4092 * about the case where we're turning the VFTA VLAN ID 4093 * entry bit on, only when requested to turn it off as 4094 * there may be multiple pools and/or VFs using the 4095 * VLAN ID entry. In that case we cannot clear the 4096 * VFTA bit until all pools/VFs using that VLAN ID have also 4097 * been cleared. This will be indicated by "bits" being 4098 * zero. 4099 */ 4100 *vfta_delta = 0; 4101 4102 vlvf_update: 4103 /* record pool change and enable VLAN ID if not already enabled */ 4104 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); 4105 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); 4106 4107 return IXGBE_SUCCESS; 4108 } 4109 4110 /** 4111 * ixgbe_clear_vfta_generic - Clear VLAN filter table 4112 * @hw: pointer to hardware structure 4113 * 4114 * Clears the VLAN filer table, and the VMDq index associated with the filter 4115 **/ 4116 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 4117 { 4118 u32 offset; 4119 4120 DEBUGFUNC("ixgbe_clear_vfta_generic"); 4121 4122 for (offset = 0; offset < hw->mac.vft_size; offset++) 4123 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 4124 4125 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 4126 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 4127 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4128 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); 4129 } 4130 4131 return IXGBE_SUCCESS; 4132 } 4133 4134 /** 4135 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix 4136 * @hw: pointer to hardware structure 4137 * 4138 * Contains the logic to identify if we need to verify link for the 4139 * crosstalk fix 4140 **/ 4141 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) 4142 { 4143 4144 /* Does FW say we need the fix */ 4145 if (!hw->need_crosstalk_fix) 4146 return FALSE; 4147 4148 /* Only consider SFP+ PHYs i.e. media type fiber */ 4149 switch (hw->mac.ops.get_media_type(hw)) { 4150 case ixgbe_media_type_fiber: 4151 case ixgbe_media_type_fiber_qsfp: 4152 break; 4153 default: 4154 return FALSE; 4155 } 4156 4157 return TRUE; 4158 } 4159 4160 /** 4161 * ixgbe_check_mac_link_generic - Determine link and speed status 4162 * @hw: pointer to hardware structure 4163 * @speed: pointer to link speed 4164 * @link_up: TRUE when link is up 4165 * @link_up_wait_to_complete: bool used to wait for link up or not 4166 * 4167 * Reads the links register to determine if link is up and the current speed 4168 **/ 4169 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4170 bool *link_up, bool link_up_wait_to_complete) 4171 { 4172 u32 links_reg, links_orig; 4173 u32 i; 4174 4175 DEBUGFUNC("ixgbe_check_mac_link_generic"); 4176 4177 /* If Crosstalk fix enabled do the sanity check of making sure 4178 * the SFP+ cage is full. 4179 */ 4180 if (ixgbe_need_crosstalk_fix(hw)) { 4181 u32 sfp_cage_full; 4182 4183 switch (hw->mac.type) { 4184 case ixgbe_mac_82599EB: 4185 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4186 IXGBE_ESDP_SDP2; 4187 break; 4188 case ixgbe_mac_X550EM_x: 4189 case ixgbe_mac_X550EM_a: 4190 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & 4191 IXGBE_ESDP_SDP0; 4192 break; 4193 default: 4194 /* sanity check - No SFP+ devices here */ 4195 sfp_cage_full = FALSE; 4196 break; 4197 } 4198 4199 if (!sfp_cage_full) { 4200 *link_up = FALSE; 4201 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4202 return IXGBE_SUCCESS; 4203 } 4204 } 4205 4206 /* clear the old state */ 4207 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4208 4209 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4210 4211 if (links_orig != links_reg) { 4212 DEBUGOUT2("LINKS changed from %08X to %08X\n", 4213 links_orig, links_reg); 4214 } 4215 4216 if (link_up_wait_to_complete) { 4217 for (i = 0; i < hw->mac.max_link_up_time; i++) { 4218 if (links_reg & IXGBE_LINKS_UP) { 4219 *link_up = TRUE; 4220 break; 4221 } else { 4222 *link_up = FALSE; 4223 } 4224 msec_delay(100); 4225 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4226 } 4227 } else { 4228 if (links_reg & IXGBE_LINKS_UP) 4229 *link_up = TRUE; 4230 else 4231 *link_up = FALSE; 4232 } 4233 4234 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 4235 case IXGBE_LINKS_SPEED_10G_82599: 4236 *speed = IXGBE_LINK_SPEED_10GB_FULL; 4237 if (hw->mac.type >= ixgbe_mac_X550) { 4238 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4239 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 4240 } 4241 break; 4242 case IXGBE_LINKS_SPEED_1G_82599: 4243 *speed = IXGBE_LINK_SPEED_1GB_FULL; 4244 break; 4245 case IXGBE_LINKS_SPEED_100_82599: 4246 *speed = IXGBE_LINK_SPEED_100_FULL; 4247 if (hw->mac.type == ixgbe_mac_X550) { 4248 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 4249 *speed = IXGBE_LINK_SPEED_5GB_FULL; 4250 } 4251 break; 4252 case IXGBE_LINKS_SPEED_10_X550EM_A: 4253 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4254 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || 4255 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) 4256 *speed = IXGBE_LINK_SPEED_10_FULL; 4257 break; 4258 default: 4259 *speed = IXGBE_LINK_SPEED_UNKNOWN; 4260 } 4261 4262 return IXGBE_SUCCESS; 4263 } 4264 4265 /** 4266 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4267 * the EEPROM 4268 * @hw: pointer to hardware structure 4269 * @wwnn_prefix: the alternative WWNN prefix 4270 * @wwpn_prefix: the alternative WWPN prefix 4271 * 4272 * This function will read the EEPROM from the alternative SAN MAC address 4273 * block to check the support for the alternative WWNN/WWPN prefix support. 4274 **/ 4275 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4276 u16 *wwpn_prefix) 4277 { 4278 u16 offset, caps; 4279 u16 alt_san_mac_blk_offset; 4280 4281 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4282 4283 /* clear output first */ 4284 *wwnn_prefix = 0xFFFF; 4285 *wwpn_prefix = 0xFFFF; 4286 4287 /* check if alternative SAN MAC is supported */ 4288 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4289 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4290 goto wwn_prefix_err; 4291 4292 if ((alt_san_mac_blk_offset == 0) || 4293 (alt_san_mac_blk_offset == 0xFFFF)) 4294 goto wwn_prefix_out; 4295 4296 /* check capability in alternative san mac address block */ 4297 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4298 if (hw->eeprom.ops.read(hw, offset, &caps)) 4299 goto wwn_prefix_err; 4300 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4301 goto wwn_prefix_out; 4302 4303 /* get the corresponding prefix for WWNN/WWPN */ 4304 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4305 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4306 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4307 "eeprom read at offset %d failed", offset); 4308 } 4309 4310 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4311 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4312 goto wwn_prefix_err; 4313 4314 wwn_prefix_out: 4315 return IXGBE_SUCCESS; 4316 4317 wwn_prefix_err: 4318 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4319 "eeprom read at offset %d failed", offset); 4320 return IXGBE_SUCCESS; 4321 } 4322 4323 /** 4324 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4325 * @hw: pointer to hardware structure 4326 * @bs: the fcoe boot status 4327 * 4328 * This function will read the FCOE boot status from the iSCSI FCOE block 4329 **/ 4330 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4331 { 4332 u16 offset, caps, flags; 4333 s32 status; 4334 4335 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4336 4337 /* clear output first */ 4338 *bs = ixgbe_fcoe_bootstatus_unavailable; 4339 4340 /* check if FCOE IBA block is present */ 4341 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4342 status = hw->eeprom.ops.read(hw, offset, &caps); 4343 if (status != IXGBE_SUCCESS) 4344 goto out; 4345 4346 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4347 goto out; 4348 4349 /* check if iSCSI FCOE block is populated */ 4350 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4351 if (status != IXGBE_SUCCESS) 4352 goto out; 4353 4354 if ((offset == 0) || (offset == 0xFFFF)) 4355 goto out; 4356 4357 /* read fcoe flags in iSCSI FCOE block */ 4358 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4359 status = hw->eeprom.ops.read(hw, offset, &flags); 4360 if (status != IXGBE_SUCCESS) 4361 goto out; 4362 4363 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4364 *bs = ixgbe_fcoe_bootstatus_enabled; 4365 else 4366 *bs = ixgbe_fcoe_bootstatus_disabled; 4367 4368 out: 4369 return status; 4370 } 4371 4372 /** 4373 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4374 * @hw: pointer to hardware structure 4375 * @enable: enable or disable switch for MAC anti-spoofing 4376 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing 4377 * 4378 **/ 4379 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4380 { 4381 int vf_target_reg = vf >> 3; 4382 int vf_target_shift = vf % 8; 4383 u32 pfvfspoof; 4384 4385 if (hw->mac.type == ixgbe_mac_82598EB) 4386 return; 4387 4388 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4389 if (enable) 4390 pfvfspoof |= (1 << vf_target_shift); 4391 else 4392 pfvfspoof &= ~(1 << vf_target_shift); 4393 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4394 } 4395 4396 /** 4397 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4398 * @hw: pointer to hardware structure 4399 * @enable: enable or disable switch for VLAN anti-spoofing 4400 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4401 * 4402 **/ 4403 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4404 { 4405 int vf_target_reg = vf >> 3; 4406 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4407 u32 pfvfspoof; 4408 4409 if (hw->mac.type == ixgbe_mac_82598EB) 4410 return; 4411 4412 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4413 if (enable) 4414 pfvfspoof |= (1 << vf_target_shift); 4415 else 4416 pfvfspoof &= ~(1 << vf_target_shift); 4417 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4418 } 4419 4420 /** 4421 * ixgbe_get_device_caps_generic - Get additional device capabilities 4422 * @hw: pointer to hardware structure 4423 * @device_caps: the EEPROM word with the extra device capabilities 4424 * 4425 * This function will read the EEPROM location for the device capabilities, 4426 * and return the word through device_caps. 4427 **/ 4428 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4429 { 4430 DEBUGFUNC("ixgbe_get_device_caps_generic"); 4431 4432 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4433 4434 return IXGBE_SUCCESS; 4435 } 4436 4437 /** 4438 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4439 * @hw: pointer to hardware structure 4440 * 4441 **/ 4442 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4443 { 4444 u32 regval; 4445 u32 i; 4446 4447 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4448 4449 /* Enable relaxed ordering */ 4450 for (i = 0; i < hw->mac.max_tx_queues; i++) { 4451 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4452 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4453 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4454 } 4455 4456 for (i = 0; i < hw->mac.max_rx_queues; i++) { 4457 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4458 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4459 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4460 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4461 } 4462 4463 } 4464 4465 /** 4466 * ixgbe_calculate_checksum - Calculate checksum for buffer 4467 * @buffer: pointer to EEPROM 4468 * @length: size of EEPROM to calculate a checksum for 4469 * Calculates the checksum for some buffer on a specified length. The 4470 * checksum calculated is returned. 4471 **/ 4472 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4473 { 4474 u32 i; 4475 u8 sum = 0; 4476 4477 DEBUGFUNC("ixgbe_calculate_checksum"); 4478 4479 if (!buffer) 4480 return 0; 4481 4482 for (i = 0; i < length; i++) 4483 sum += buffer[i]; 4484 4485 return (u8) (0 - sum); 4486 } 4487 4488 /** 4489 * ixgbe_hic_unlocked - Issue command to manageability block unlocked 4490 * @hw: pointer to the HW structure 4491 * @buffer: command to write and where the return status will be placed 4492 * @length: length of buffer, must be multiple of 4 bytes 4493 * @timeout: time in ms to wait for command completion 4494 * 4495 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4496 * else returns semaphore error when encountering an error acquiring 4497 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4498 * 4499 * This function assumes that the IXGBE_GSSR_SW_MNG_SM semaphore is held 4500 * by the caller. 4501 **/ 4502 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, 4503 u32 timeout) 4504 { 4505 u32 hicr, i, fwsts; 4506 u16 dword_len; 4507 4508 DEBUGFUNC("ixgbe_hic_unlocked"); 4509 4510 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4511 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4512 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4513 } 4514 4515 /* Set bit 9 of FWSTS clearing FW reset indication */ 4516 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); 4517 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); 4518 4519 /* Check that the host interface is enabled. */ 4520 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4521 if (!(hicr & IXGBE_HICR_EN)) { 4522 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4523 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4524 } 4525 4526 /* Calculate length in DWORDs. We must be DWORD aligned */ 4527 if (length % sizeof(u32)) { 4528 DEBUGOUT("Buffer length failure, not aligned to dword"); 4529 return IXGBE_ERR_INVALID_ARGUMENT; 4530 } 4531 4532 dword_len = length >> 2; 4533 4534 /* The device driver writes the relevant command block 4535 * into the ram area. 4536 */ 4537 for (i = 0; i < dword_len; i++) 4538 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4539 i, IXGBE_CPU_TO_LE32(buffer[i])); 4540 4541 /* Setting this bit tells the ARC that a new command is pending. */ 4542 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4543 4544 for (i = 0; i < timeout; i++) { 4545 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4546 if (!(hicr & IXGBE_HICR_C)) 4547 break; 4548 msec_delay(1); 4549 } 4550 4551 /* Check command completion */ 4552 if ((timeout && i == timeout) || 4553 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { 4554 ERROR_REPORT1(IXGBE_ERROR_CAUTION, 4555 "Command has failed with no status valid.\n"); 4556 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4557 } 4558 4559 return IXGBE_SUCCESS; 4560 } 4561 4562 /** 4563 * ixgbe_host_interface_command - Issue command to manageability block 4564 * @hw: pointer to the HW structure 4565 * @buffer: contains the command to write and where the return status will 4566 * be placed 4567 * @length: length of buffer, must be multiple of 4 bytes 4568 * @timeout: time in ms to wait for command completion 4569 * @return_data: read and return data from the buffer (TRUE) or not (FALSE) 4570 * Needed because FW structures are big endian and decoding of 4571 * these fields can be 8 bit or 16 bit based on command. Decoding 4572 * is not easily understood without making a table of commands. 4573 * So we will leave this up to the caller to read back the data 4574 * in these cases. 4575 * 4576 * Communicates with the manageability block. On success return IXGBE_SUCCESS 4577 * else returns semaphore error when encountering an error acquiring 4578 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4579 **/ 4580 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4581 u32 length, u32 timeout, bool return_data) 4582 { 4583 u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4584 u16 dword_len; 4585 u16 buf_len; 4586 s32 status; 4587 u32 bi; 4588 4589 DEBUGFUNC("ixgbe_host_interface_command"); 4590 4591 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4592 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length); 4593 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 4594 } 4595 4596 /* Take management host interface semaphore */ 4597 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4598 if (status) 4599 return status; 4600 4601 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); 4602 if (status) 4603 goto rel_out; 4604 4605 if (!return_data) 4606 goto rel_out; 4607 4608 /* Calculate length in DWORDs */ 4609 dword_len = hdr_size >> 2; 4610 4611 /* first pull in the header so we know the buffer length */ 4612 for (bi = 0; bi < dword_len; bi++) { 4613 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4614 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4615 } 4616 4617 /* If there is any thing in data position pull it in */ 4618 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; 4619 if (!buf_len) 4620 goto rel_out; 4621 4622 if (length < buf_len + hdr_size) { 4623 DEBUGOUT("Buffer not large enough for reply message.\n"); 4624 status = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4625 goto rel_out; 4626 } 4627 4628 /* Calculate length in DWORDs, add 3 for odd lengths */ 4629 dword_len = (buf_len + 3) >> 2; 4630 4631 /* Pull in the rest of the buffer (bi is where we left off) */ 4632 for (; bi <= dword_len; bi++) { 4633 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4634 IXGBE_LE32_TO_CPUS(&buffer[bi]); 4635 } 4636 4637 rel_out: 4638 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4639 4640 return status; 4641 } 4642 4643 /** 4644 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4645 * @hw: pointer to the HW structure 4646 * @maj: driver version major number 4647 * @min: driver version minor number 4648 * @build: driver version build number 4649 * @sub: driver version sub build number 4650 * 4651 * Sends driver version number to firmware through the manageability 4652 * block. On success return IXGBE_SUCCESS 4653 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4654 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4655 **/ 4656 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 4657 u8 build, u8 sub, u16 len, 4658 const char *driver_ver) 4659 { 4660 struct ixgbe_hic_drv_info fw_cmd; 4661 int i; 4662 s32 ret_val = IXGBE_SUCCESS; 4663 4664 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4665 UNREFERENCED_2PARAMETER(len, driver_ver); 4666 4667 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4668 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4669 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4670 fw_cmd.port_num = (u8)hw->bus.func; 4671 fw_cmd.ver_maj = maj; 4672 fw_cmd.ver_min = min; 4673 fw_cmd.ver_build = build; 4674 fw_cmd.ver_sub = sub; 4675 fw_cmd.hdr.checksum = 0; 4676 fw_cmd.pad = 0; 4677 fw_cmd.pad2 = 0; 4678 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4679 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4680 4681 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4682 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4683 sizeof(fw_cmd), 4684 IXGBE_HI_COMMAND_TIMEOUT, 4685 TRUE); 4686 if (ret_val != IXGBE_SUCCESS) 4687 continue; 4688 4689 if (fw_cmd.hdr.cmd_or_resp.ret_status == 4690 FW_CEM_RESP_STATUS_SUCCESS) 4691 ret_val = IXGBE_SUCCESS; 4692 else 4693 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4694 4695 break; 4696 } 4697 4698 return ret_val; 4699 } 4700 4701 /** 4702 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4703 * @hw: pointer to hardware structure 4704 * @num_pb: number of packet buffers to allocate 4705 * @headroom: reserve n KB of headroom 4706 * @strategy: packet buffer allocation strategy 4707 **/ 4708 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4709 int strategy) 4710 { 4711 u32 pbsize = hw->mac.rx_pb_size; 4712 int i = 0; 4713 u32 rxpktsize, txpktsize, txpbthresh; 4714 4715 /* Reserve headroom */ 4716 pbsize -= headroom; 4717 4718 if (!num_pb) 4719 num_pb = 1; 4720 4721 /* Divide remaining packet buffer space amongst the number of packet 4722 * buffers requested using supplied strategy. 4723 */ 4724 switch (strategy) { 4725 case PBA_STRATEGY_WEIGHTED: 4726 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4727 * buffer with 5/8 of the packet buffer space. 4728 */ 4729 rxpktsize = (pbsize * 5) / (num_pb * 4); 4730 pbsize -= rxpktsize * (num_pb / 2); 4731 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4732 for (; i < (num_pb / 2); i++) 4733 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4734 /* fall through - configure remaining packet buffers */ 4735 case PBA_STRATEGY_EQUAL: 4736 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4737 for (; i < num_pb; i++) 4738 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4739 break; 4740 default: 4741 break; 4742 } 4743 4744 /* Only support an equally distributed Tx packet buffer strategy. */ 4745 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4746 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4747 for (i = 0; i < num_pb; i++) { 4748 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4749 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4750 } 4751 4752 /* Clear unused TCs, if any, to zero buffer size*/ 4753 for (; i < IXGBE_MAX_PB; i++) { 4754 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4755 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4756 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4757 } 4758 } 4759 4760 /** 4761 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4762 * @hw: pointer to the hardware structure 4763 * 4764 * The 82599 and x540 MACs can experience issues if TX work is still pending 4765 * when a reset occurs. This function prevents this by flushing the PCIe 4766 * buffers on the system. 4767 **/ 4768 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4769 { 4770 u32 gcr_ext, hlreg0, i, poll; 4771 u16 value; 4772 4773 /* 4774 * If double reset is not requested then all transactions should 4775 * already be clear and as such there is no work to do 4776 */ 4777 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4778 return; 4779 4780 /* 4781 * Set loopback enable to prevent any transmits from being sent 4782 * should the link come up. This assumes that the RXCTRL.RXEN bit 4783 * has already been cleared. 4784 */ 4785 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4786 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4787 4788 /* Wait for a last completion before clearing buffers */ 4789 IXGBE_WRITE_FLUSH(hw); 4790 msec_delay(3); 4791 4792 /* 4793 * Before proceeding, make sure that the PCIe block does not have 4794 * transactions pending. 4795 */ 4796 poll = ixgbe_pcie_timeout_poll(hw); 4797 for (i = 0; i < poll; i++) { 4798 usec_delay(100); 4799 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); 4800 if (IXGBE_REMOVED(hw->hw_addr)) 4801 goto out; 4802 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 4803 goto out; 4804 } 4805 4806 out: 4807 /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4808 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4809 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4810 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4811 4812 /* Flush all writes and allow 20usec for all transactions to clear */ 4813 IXGBE_WRITE_FLUSH(hw); 4814 usec_delay(20); 4815 4816 /* restore previous register values */ 4817 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4818 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4819 } 4820 4821 /** 4822 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW 4823 * 4824 * @hw: pointer to hardware structure 4825 * @cmd: Command we send to the FW 4826 * @status: The reply from the FW 4827 * 4828 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 4829 **/ 4830 #define IXGBE_BYPASS_BB_WAIT 1 4831 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) 4832 { 4833 int i; 4834 u32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo; 4835 u32 esdp; 4836 4837 if (!status) 4838 return IXGBE_ERR_PARAM; 4839 4840 *status = 0; 4841 4842 /* SDP vary by MAC type */ 4843 switch (hw->mac.type) { 4844 case ixgbe_mac_82599EB: 4845 sck = IXGBE_ESDP_SDP7; 4846 sdi = IXGBE_ESDP_SDP0; 4847 sdo = IXGBE_ESDP_SDP6; 4848 dir_sck = IXGBE_ESDP_SDP7_DIR; 4849 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4850 dir_sdo = IXGBE_ESDP_SDP6_DIR; 4851 break; 4852 case ixgbe_mac_X540: 4853 sck = IXGBE_ESDP_SDP2; 4854 sdi = IXGBE_ESDP_SDP0; 4855 sdo = IXGBE_ESDP_SDP1; 4856 dir_sck = IXGBE_ESDP_SDP2_DIR; 4857 dir_sdi = IXGBE_ESDP_SDP0_DIR; 4858 dir_sdo = IXGBE_ESDP_SDP1_DIR; 4859 break; 4860 default: 4861 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 4862 } 4863 4864 /* Set SDP pins direction */ 4865 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4866 esdp |= dir_sck; /* SCK as output */ 4867 esdp |= dir_sdi; /* SDI as output */ 4868 esdp &= ~dir_sdo; /* SDO as input */ 4869 esdp |= sck; 4870 esdp |= sdi; 4871 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4872 IXGBE_WRITE_FLUSH(hw); 4873 msec_delay(IXGBE_BYPASS_BB_WAIT); 4874 4875 /* Generate start condition */ 4876 esdp &= ~sdi; 4877 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4878 IXGBE_WRITE_FLUSH(hw); 4879 msec_delay(IXGBE_BYPASS_BB_WAIT); 4880 4881 esdp &= ~sck; 4882 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4883 IXGBE_WRITE_FLUSH(hw); 4884 msec_delay(IXGBE_BYPASS_BB_WAIT); 4885 4886 /* Clock out the new control word and clock in the status */ 4887 for (i = 0; i < 32; i++) { 4888 if ((cmd >> (31 - i)) & 0x01) { 4889 esdp |= sdi; 4890 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4891 } else { 4892 esdp &= ~sdi; 4893 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4894 } 4895 IXGBE_WRITE_FLUSH(hw); 4896 msec_delay(IXGBE_BYPASS_BB_WAIT); 4897 4898 esdp |= sck; 4899 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4900 IXGBE_WRITE_FLUSH(hw); 4901 msec_delay(IXGBE_BYPASS_BB_WAIT); 4902 4903 esdp &= ~sck; 4904 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4905 IXGBE_WRITE_FLUSH(hw); 4906 msec_delay(IXGBE_BYPASS_BB_WAIT); 4907 4908 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 4909 if (esdp & sdo) 4910 *status = (*status << 1) | 0x01; 4911 else 4912 *status = (*status << 1) | 0x00; 4913 msec_delay(IXGBE_BYPASS_BB_WAIT); 4914 } 4915 4916 /* stop condition */ 4917 esdp |= sck; 4918 esdp &= ~sdi; 4919 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4920 IXGBE_WRITE_FLUSH(hw); 4921 msec_delay(IXGBE_BYPASS_BB_WAIT); 4922 4923 esdp |= sdi; 4924 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 4925 IXGBE_WRITE_FLUSH(hw); 4926 4927 /* set the page bits to match the cmd that the status it belongs to */ 4928 *status = (*status & 0x3fffffff) | (cmd & 0xc0000000); 4929 4930 return IXGBE_SUCCESS; 4931 } 4932 4933 /** 4934 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang. 4935 * 4936 * If we send a write we can't be sure it took until we can read back 4937 * that same register. It can be a problem as some of the feilds may 4938 * for valid reasons change inbetween the time wrote the register and 4939 * we read it again to verify. So this function check everything we 4940 * can check and then assumes it worked. 4941 * 4942 * @u32 in_reg - The register cmd for the bit-bang read. 4943 * @u32 out_reg - The register returned from a bit-bang read. 4944 **/ 4945 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) 4946 { 4947 u32 mask; 4948 4949 /* Page must match for all control pages */ 4950 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) 4951 return FALSE; 4952 4953 switch (in_reg & BYPASS_PAGE_M) { 4954 case BYPASS_PAGE_CTL0: 4955 /* All the following can't change since the last write 4956 * - All the event actions 4957 * - The timeout value 4958 */ 4959 mask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M | 4960 BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M | 4961 BYPASS_WDTIMEOUT_M | 4962 BYPASS_WDT_VALUE_M; 4963 if ((out_reg & mask) != (in_reg & mask)) 4964 return FALSE; 4965 4966 /* 0x0 is never a valid value for bypass status */ 4967 if (!(out_reg & BYPASS_STATUS_OFF_M)) 4968 return FALSE; 4969 break; 4970 case BYPASS_PAGE_CTL1: 4971 /* All the following can't change since the last write 4972 * - time valid bit 4973 * - time we last sent 4974 */ 4975 mask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M; 4976 if ((out_reg & mask) != (in_reg & mask)) 4977 return FALSE; 4978 break; 4979 case BYPASS_PAGE_CTL2: 4980 /* All we can check in this page is control number 4981 * which is already done above. 4982 */ 4983 break; 4984 } 4985 4986 /* We are as sure as we can be return TRUE */ 4987 return TRUE; 4988 } 4989 4990 /** 4991 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter. 4992 * 4993 * @hw: pointer to hardware structure 4994 * @cmd: The control word we are setting. 4995 * @event: The event we are setting in the FW. This also happens to 4996 * be the mask for the event we are setting (handy) 4997 * @action: The action we set the event to in the FW. This is in a 4998 * bit field that happens to be what we want to put in 4999 * the event spot (also handy) 5000 **/ 5001 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, 5002 u32 action) 5003 { 5004 u32 by_ctl = 0; 5005 u32 cmd, verify; 5006 u32 count = 0; 5007 5008 /* Get current values */ 5009 cmd = ctrl; /* just reading only need control number */ 5010 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5011 return IXGBE_ERR_INVALID_ARGUMENT; 5012 5013 /* Set to new action */ 5014 cmd = (by_ctl & ~event) | BYPASS_WE | action; 5015 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) 5016 return IXGBE_ERR_INVALID_ARGUMENT; 5017 5018 /* Page 0 force a FW eeprom write which is slow so verify */ 5019 if ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) { 5020 verify = BYPASS_PAGE_CTL0; 5021 do { 5022 if (count++ > 5) 5023 return IXGBE_BYPASS_FW_WRITE_FAILURE; 5024 5025 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) 5026 return IXGBE_ERR_INVALID_ARGUMENT; 5027 } while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl)); 5028 } else { 5029 /* We have give the FW time for the write to stick */ 5030 msec_delay(100); 5031 } 5032 5033 return IXGBE_SUCCESS; 5034 } 5035 5036 /** 5037 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres. 5038 * 5039 * @hw: pointer to hardware structure 5040 * @addr: The bypass eeprom address to read. 5041 * @value: The 8b of data at the address above. 5042 **/ 5043 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) 5044 { 5045 u32 cmd; 5046 u32 status; 5047 5048 5049 /* send the request */ 5050 cmd = BYPASS_PAGE_CTL2 | BYPASS_WE; 5051 cmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M; 5052 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5053 return IXGBE_ERR_INVALID_ARGUMENT; 5054 5055 /* We have give the FW time for the write to stick */ 5056 msec_delay(100); 5057 5058 /* now read the results */ 5059 cmd &= ~BYPASS_WE; 5060 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) 5061 return IXGBE_ERR_INVALID_ARGUMENT; 5062 5063 *value = status & BYPASS_CTL2_DATA_M; 5064 5065 return IXGBE_SUCCESS; 5066 } 5067 5068 /** 5069 * ixgbe_get_orom_version - Return option ROM from EEPROM 5070 * 5071 * @hw: pointer to hardware structure 5072 * @nvm_ver: pointer to output structure 5073 * 5074 * if valid option ROM version, nvm_ver->or_valid set to TRUE 5075 * else nvm_ver->or_valid is FALSE. 5076 **/ 5077 void ixgbe_get_orom_version(struct ixgbe_hw *hw, 5078 struct ixgbe_nvm_version *nvm_ver) 5079 { 5080 u16 offset, eeprom_cfg_blkh, eeprom_cfg_blkl; 5081 5082 nvm_ver->or_valid = FALSE; 5083 /* Option Rom may or may not be present. Start with pointer */ 5084 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); 5085 5086 /* make sure offset is valid */ 5087 if ((offset == 0x0) || (offset == NVM_INVALID_PTR)) 5088 return; 5089 5090 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); 5091 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); 5092 5093 /* option rom exists and is valid */ 5094 if ((eeprom_cfg_blkl | eeprom_cfg_blkh) == 0x0 || 5095 eeprom_cfg_blkl == NVM_VER_INVALID || 5096 eeprom_cfg_blkh == NVM_VER_INVALID) 5097 return; 5098 5099 nvm_ver->or_valid = TRUE; 5100 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; 5101 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | 5102 (eeprom_cfg_blkh >> NVM_OROM_SHIFT); 5103 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; 5104 } 5105 5106 /** 5107 * ixgbe_get_oem_prod_version - Return OEM Product version 5108 * 5109 * @hw: pointer to hardware structure 5110 * @nvm_ver: pointer to output structure 5111 * 5112 * if valid OEM product version, nvm_ver->oem_valid set to TRUE 5113 * else nvm_ver->oem_valid is FALSE. 5114 **/ 5115 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, 5116 struct ixgbe_nvm_version *nvm_ver) 5117 { 5118 u16 rel_num, prod_ver, mod_len, cap, offset; 5119 5120 nvm_ver->oem_valid = FALSE; 5121 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); 5122 5123 /* Return is offset to OEM Product Version block is invalid */ 5124 if (offset == 0x0 && offset == NVM_INVALID_PTR) 5125 return; 5126 5127 /* Read product version block */ 5128 hw->eeprom.ops.read(hw, offset, &mod_len); 5129 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); 5130 5131 /* Return if OEM product version block is invalid */ 5132 if (mod_len != NVM_OEM_PROD_VER_MOD_LEN || 5133 (cap & NVM_OEM_PROD_VER_CAP_MASK) != 0x0) 5134 return; 5135 5136 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); 5137 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); 5138 5139 /* Return if version is invalid */ 5140 if ((rel_num | prod_ver) == 0x0 || 5141 rel_num == NVM_VER_INVALID || prod_ver == NVM_VER_INVALID) 5142 return; 5143 5144 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; 5145 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; 5146 nvm_ver->oem_release = rel_num; 5147 nvm_ver->oem_valid = TRUE; 5148 } 5149 5150 /** 5151 * ixgbe_get_etk_id - Return Etrack ID from EEPROM 5152 * 5153 * @hw: pointer to hardware structure 5154 * @nvm_ver: pointer to output structure 5155 * 5156 * word read errors will return 0xFFFF 5157 **/ 5158 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) 5159 { 5160 u16 etk_id_l, etk_id_h; 5161 5162 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) 5163 etk_id_l = NVM_VER_INVALID; 5164 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) 5165 etk_id_h = NVM_VER_INVALID; 5166 5167 /* The word order for the version format is determined by high order 5168 * word bit 15. 5169 */ 5170 if ((etk_id_h & NVM_ETK_VALID) == 0) { 5171 nvm_ver->etk_id = etk_id_h; 5172 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); 5173 } else { 5174 nvm_ver->etk_id = etk_id_l; 5175 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); 5176 } 5177 } 5178 5179 5180 /** 5181 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 5182 * @hw: pointer to hardware structure 5183 * @map: pointer to u8 arr for returning map 5184 * 5185 * Read the rtrup2tc HW register and resolve its content into map 5186 **/ 5187 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 5188 { 5189 u32 reg, i; 5190 5191 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 5192 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 5193 map[i] = IXGBE_RTRUP2TC_UP_MASK & 5194 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 5195 return; 5196 } 5197 5198 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) 5199 { 5200 u32 pfdtxgswc; 5201 u32 rxctrl; 5202 5203 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5204 if (rxctrl & IXGBE_RXCTRL_RXEN) { 5205 if (hw->mac.type != ixgbe_mac_82598EB) { 5206 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5207 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 5208 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 5209 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5210 hw->mac.set_lben = TRUE; 5211 } else { 5212 hw->mac.set_lben = FALSE; 5213 } 5214 } 5215 rxctrl &= ~IXGBE_RXCTRL_RXEN; 5216 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 5217 } 5218 } 5219 5220 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) 5221 { 5222 u32 pfdtxgswc; 5223 u32 rxctrl; 5224 5225 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 5226 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); 5227 5228 if (hw->mac.type != ixgbe_mac_82598EB) { 5229 if (hw->mac.set_lben) { 5230 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 5231 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; 5232 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 5233 hw->mac.set_lben = FALSE; 5234 } 5235 } 5236 } 5237 5238 /** 5239 * ixgbe_mng_present - returns TRUE when management capability is present 5240 * @hw: pointer to hardware structure 5241 */ 5242 bool ixgbe_mng_present(struct ixgbe_hw *hw) 5243 { 5244 u32 fwsm; 5245 5246 if (hw->mac.type < ixgbe_mac_82599EB) 5247 return FALSE; 5248 5249 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5250 5251 return !!(fwsm & IXGBE_FWSM_FW_MODE_PT); 5252 } 5253 5254 /** 5255 * ixgbe_mng_enabled - Is the manageability engine enabled? 5256 * @hw: pointer to hardware structure 5257 * 5258 * Returns TRUE if the manageability engine is enabled. 5259 **/ 5260 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) 5261 { 5262 u32 fwsm, manc, factps; 5263 5264 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); 5265 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) 5266 return FALSE; 5267 5268 manc = IXGBE_READ_REG(hw, IXGBE_MANC); 5269 if (!(manc & IXGBE_MANC_RCV_TCO_EN)) 5270 return FALSE; 5271 5272 if (hw->mac.type <= ixgbe_mac_X540) { 5273 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); 5274 if (factps & IXGBE_FACTPS_MNGCG) 5275 return FALSE; 5276 } 5277 5278 return TRUE; 5279 } 5280 5281 /** 5282 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed 5283 * @hw: pointer to hardware structure 5284 * @speed: new link speed 5285 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 5286 * 5287 * Set the link speed in the MAC and/or PHY register and restarts link. 5288 **/ 5289 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, 5290 ixgbe_link_speed speed, 5291 bool autoneg_wait_to_complete) 5292 { 5293 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5294 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; 5295 s32 status = IXGBE_SUCCESS; 5296 u32 speedcnt = 0; 5297 u32 i = 0; 5298 bool autoneg, link_up = FALSE; 5299 5300 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber"); 5301 5302 /* Mask off requested but non-supported speeds */ 5303 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); 5304 if (status != IXGBE_SUCCESS) 5305 return status; 5306 5307 speed &= link_speed; 5308 5309 /* Try each speed one by one, highest priority first. We do this in 5310 * software because 10Gb fiber doesn't support speed autonegotiation. 5311 */ 5312 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 5313 speedcnt++; 5314 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; 5315 5316 /* Set the module link speed */ 5317 switch (hw->phy.media_type) { 5318 case ixgbe_media_type_fiber_fixed: 5319 case ixgbe_media_type_fiber: 5320 ixgbe_set_rate_select_speed(hw, 5321 IXGBE_LINK_SPEED_10GB_FULL); 5322 break; 5323 case ixgbe_media_type_fiber_qsfp: 5324 /* QSFP module automatically detects MAC link speed */ 5325 break; 5326 default: 5327 DEBUGOUT("Unexpected media type.\n"); 5328 break; 5329 } 5330 5331 /* Allow module to change analog characteristics (1G->10G) */ 5332 msec_delay(40); 5333 5334 status = ixgbe_setup_mac_link(hw, 5335 IXGBE_LINK_SPEED_10GB_FULL, 5336 autoneg_wait_to_complete); 5337 if (status != IXGBE_SUCCESS) 5338 return status; 5339 5340 /* Flap the Tx laser if it has not already been done */ 5341 ixgbe_flap_tx_laser(hw); 5342 5343 /* Wait for the controller to acquire link. Per IEEE 802.3ap, 5344 * Section 73.10.2, we may have to wait up to 500ms if KR is 5345 * attempted. 82599 uses the same timing for 10g SFI. 5346 */ 5347 for (i = 0; i < 5; i++) { 5348 /* Wait for the link partner to also set speed */ 5349 msec_delay(100); 5350 5351 /* If we have link, just jump out */ 5352 status = ixgbe_check_link(hw, &link_speed, 5353 &link_up, FALSE); 5354 if (status != IXGBE_SUCCESS) 5355 return status; 5356 5357 if (link_up) 5358 goto out; 5359 } 5360 } 5361 5362 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 5363 speedcnt++; 5364 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) 5365 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; 5366 5367 /* Set the module link speed */ 5368 switch (hw->phy.media_type) { 5369 case ixgbe_media_type_fiber_fixed: 5370 case ixgbe_media_type_fiber: 5371 ixgbe_set_rate_select_speed(hw, 5372 IXGBE_LINK_SPEED_1GB_FULL); 5373 break; 5374 case ixgbe_media_type_fiber_qsfp: 5375 /* QSFP module automatically detects link speed */ 5376 break; 5377 default: 5378 DEBUGOUT("Unexpected media type.\n"); 5379 break; 5380 } 5381 5382 /* Allow module to change analog characteristics (10G->1G) */ 5383 msec_delay(40); 5384 5385 status = ixgbe_setup_mac_link(hw, 5386 IXGBE_LINK_SPEED_1GB_FULL, 5387 autoneg_wait_to_complete); 5388 if (status != IXGBE_SUCCESS) 5389 return status; 5390 5391 /* Flap the Tx laser if it has not already been done */ 5392 ixgbe_flap_tx_laser(hw); 5393 5394 /* Wait for the link partner to also set speed */ 5395 msec_delay(100); 5396 5397 /* If we have link, just jump out */ 5398 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 5399 if (status != IXGBE_SUCCESS) 5400 return status; 5401 5402 if (link_up) 5403 goto out; 5404 } 5405 5406 /* We didn't get link. Configure back to the highest speed we tried, 5407 * (if there was more than one). We call ourselves back with just the 5408 * single highest speed that the user requested. 5409 */ 5410 if (speedcnt > 1) 5411 status = ixgbe_setup_mac_link_multispeed_fiber(hw, 5412 highest_link_speed, 5413 autoneg_wait_to_complete); 5414 5415 out: 5416 /* Set autoneg_advertised value based on input link speed */ 5417 hw->phy.autoneg_advertised = 0; 5418 5419 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 5420 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 5421 5422 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 5423 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 5424 5425 return status; 5426 } 5427 5428 /** 5429 * ixgbe_set_soft_rate_select_speed - Set module link speed 5430 * @hw: pointer to hardware structure 5431 * @speed: link speed to set 5432 * 5433 * Set module link speed via the soft rate select. 5434 */ 5435 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, 5436 ixgbe_link_speed speed) 5437 { 5438 s32 status; 5439 u8 rs, eeprom_data; 5440 5441 switch (speed) { 5442 case IXGBE_LINK_SPEED_10GB_FULL: 5443 /* one bit mask same as setting on */ 5444 rs = IXGBE_SFF_SOFT_RS_SELECT_10G; 5445 break; 5446 case IXGBE_LINK_SPEED_1GB_FULL: 5447 rs = IXGBE_SFF_SOFT_RS_SELECT_1G; 5448 break; 5449 default: 5450 DEBUGOUT("Invalid fixed module speed\n"); 5451 return; 5452 } 5453 5454 /* Set RS0 */ 5455 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5456 IXGBE_I2C_EEPROM_DEV_ADDR2, 5457 &eeprom_data); 5458 if (status) { 5459 DEBUGOUT("Failed to read Rx Rate Select RS0\n"); 5460 goto out; 5461 } 5462 5463 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5464 5465 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, 5466 IXGBE_I2C_EEPROM_DEV_ADDR2, 5467 eeprom_data); 5468 if (status) { 5469 DEBUGOUT("Failed to write Rx Rate Select RS0\n"); 5470 goto out; 5471 } 5472 5473 /* Set RS1 */ 5474 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5475 IXGBE_I2C_EEPROM_DEV_ADDR2, 5476 &eeprom_data); 5477 if (status) { 5478 DEBUGOUT("Failed to read Rx Rate Select RS1\n"); 5479 goto out; 5480 } 5481 5482 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; 5483 5484 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, 5485 IXGBE_I2C_EEPROM_DEV_ADDR2, 5486 eeprom_data); 5487 if (status) { 5488 DEBUGOUT("Failed to write Rx Rate Select RS1\n"); 5489 goto out; 5490 } 5491 out: 5492 return; 5493 } 5494