1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 36 #include "ixgbe_type.h" 37 #include "ixgbe_dcb.h" 38 #include "ixgbe_dcb_82598.h" 39 #include "ixgbe_dcb_82599.h" 40 41 /** 42 * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class 43 * credits from the configured bandwidth percentages. Credits 44 * are the smallest unit programmable into the underlying 45 * hardware. The IEEE 802.1Qaz specification do not use bandwidth 46 * groups so this is much simplified from the CEE case. 47 */ 48 s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max, 49 int max_frame_size) 50 { 51 int min_percent = 100; 52 int min_credit, multiplier; 53 int i; 54 55 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) / 56 IXGBE_DCB_CREDIT_QUANTUM; 57 58 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 59 if (bw[i] < min_percent && bw[i]) 60 min_percent = bw[i]; 61 } 62 63 multiplier = (min_credit / min_percent) + 1; 64 65 /* Find out the hw credits for each TC */ 66 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 67 int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL); 68 69 if (val < min_credit) 70 val = min_credit; 71 refill[i] = (u16)val; 72 73 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit; 74 } 75 76 return 0; 77 } 78 79 /** 80 * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits 81 * @ixgbe_dcb_config: Struct containing DCB settings. 82 * @direction: Configuring either Tx or Rx. 83 * 84 * This function calculates the credits allocated to each traffic class. 85 * It should be called only after the rules are checked by 86 * ixgbe_dcb_check_config_cee(). 87 */ 88 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw, 89 struct ixgbe_dcb_config *dcb_config, 90 u32 max_frame_size, u8 direction) 91 { 92 struct ixgbe_dcb_tc_path *p; 93 u32 min_multiplier = 0; 94 u16 min_percent = 100; 95 s32 ret_val = IXGBE_SUCCESS; 96 /* Initialization values default for Tx settings */ 97 u32 min_credit = 0; 98 u32 credit_refill = 0; 99 u32 credit_max = 0; 100 u16 link_percentage = 0; 101 u8 bw_percent = 0; 102 u8 i; 103 104 if (dcb_config == NULL) { 105 ret_val = IXGBE_ERR_CONFIG; 106 goto out; 107 } 108 109 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) / 110 IXGBE_DCB_CREDIT_QUANTUM; 111 112 /* Find smallest link percentage */ 113 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 114 p = &dcb_config->tc_config[i].path[direction]; 115 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 116 link_percentage = p->bwg_percent; 117 118 link_percentage = (link_percentage * bw_percent) / 100; 119 120 if (link_percentage && link_percentage < min_percent) 121 min_percent = link_percentage; 122 } 123 124 /* 125 * The ratio between traffic classes will control the bandwidth 126 * percentages seen on the wire. To calculate this ratio we use 127 * a multiplier. It is required that the refill credits must be 128 * larger than the max frame size so here we find the smallest 129 * multiplier that will allow all bandwidth percentages to be 130 * greater than the max frame size. 131 */ 132 min_multiplier = (min_credit / min_percent) + 1; 133 134 /* Find out the link percentage for each TC first */ 135 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 136 p = &dcb_config->tc_config[i].path[direction]; 137 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 138 139 link_percentage = p->bwg_percent; 140 /* Must be careful of integer division for very small nums */ 141 link_percentage = (link_percentage * bw_percent) / 100; 142 if (p->bwg_percent > 0 && link_percentage == 0) 143 link_percentage = 1; 144 145 /* Save link_percentage for reference */ 146 p->link_percent = (u8)link_percentage; 147 148 /* Calculate credit refill ratio using multiplier */ 149 credit_refill = min(link_percentage * min_multiplier, 150 (u32)IXGBE_DCB_MAX_CREDIT_REFILL); 151 152 /* Refill at least minimum credit */ 153 if (credit_refill < min_credit) 154 credit_refill = min_credit; 155 156 p->data_credits_refill = (u16)credit_refill; 157 158 /* Calculate maximum credit for the TC */ 159 credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100; 160 161 /* 162 * Adjustment based on rule checking, if the percentage 163 * of a TC is too small, the maximum credit may not be 164 * enough to send out a jumbo frame in data plane arbitration. 165 */ 166 if (credit_max < min_credit) 167 credit_max = min_credit; 168 169 if (direction == IXGBE_DCB_TX_CONFIG) { 170 /* 171 * Adjustment based on rule checking, if the 172 * percentage of a TC is too small, the maximum 173 * credit may not be enough to send out a TSO 174 * packet in descriptor plane arbitration. 175 */ 176 if (credit_max && (credit_max < 177 IXGBE_DCB_MIN_TSO_CREDIT) 178 && (hw->mac.type == ixgbe_mac_82598EB)) 179 credit_max = IXGBE_DCB_MIN_TSO_CREDIT; 180 181 dcb_config->tc_config[i].desc_credits_max = 182 (u16)credit_max; 183 } 184 185 p->data_credits_max = (u16)credit_max; 186 } 187 188 out: 189 return ret_val; 190 } 191 192 /** 193 * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info 194 * @cfg: dcb configuration to unpack into hardware consumable fields 195 * @map: user priority to traffic class map 196 * @pfc_up: u8 to store user priority PFC bitmask 197 * 198 * This unpacks the dcb configuration PFC info which is stored per 199 * traffic class into a 8bit user priority bitmask that can be 200 * consumed by hardware routines. The priority to tc map must be 201 * updated before calling this routine to use current up-to maps. 202 */ 203 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up) 204 { 205 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 206 int up; 207 208 /* 209 * If the TC for this user priority has PFC enabled then set the 210 * matching bit in 'pfc_up' to reflect that PFC is enabled. 211 */ 212 for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) { 213 if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled) 214 *pfc_up |= 1 << up; 215 } 216 } 217 218 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction, 219 u16 *refill) 220 { 221 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 222 int tc; 223 224 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 225 refill[tc] = tc_config[tc].path[direction].data_credits_refill; 226 } 227 228 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max) 229 { 230 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 231 int tc; 232 233 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 234 max[tc] = tc_config[tc].desc_credits_max; 235 } 236 237 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction, 238 u8 *bwgid) 239 { 240 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 241 int tc; 242 243 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 244 bwgid[tc] = tc_config[tc].path[direction].bwg_id; 245 } 246 247 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction, 248 u8 *tsa) 249 { 250 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 251 int tc; 252 253 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 254 tsa[tc] = tc_config[tc].path[direction].tsa; 255 } 256 257 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up) 258 { 259 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 260 u8 prio_mask = 1 << up; 261 u8 tc = cfg->num_tcs.pg_tcs; 262 263 /* If tc is 0 then DCB is likely not enabled or supported */ 264 if (!tc) 265 goto out; 266 267 /* 268 * Test from maximum TC to 1 and report the first match we find. If 269 * we find no match we can assume that the TC is 0 since the TC must 270 * be set for all user priorities 271 */ 272 for (tc--; tc; tc--) { 273 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap) 274 break; 275 } 276 out: 277 return tc; 278 } 279 280 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction, 281 u8 *map) 282 { 283 u8 up; 284 285 for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) 286 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up); 287 } 288 289 /** 290 * ixgbe_dcb_config - Struct containing DCB settings. 291 * @dcb_config: Pointer to DCB config structure 292 * 293 * This function checks DCB rules for DCB settings. 294 * The following rules are checked: 295 * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%. 296 * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth 297 * Group must total 100. 298 * 3. A Traffic Class should not be set to both Link Strict Priority 299 * and Group Strict Priority. 300 * 4. Link strict Bandwidth Groups can only have link strict traffic classes 301 * with zero bandwidth. 302 */ 303 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config) 304 { 305 struct ixgbe_dcb_tc_path *p; 306 s32 ret_val = IXGBE_SUCCESS; 307 u8 i, j, bw = 0, bw_id; 308 u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP]; 309 bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP]; 310 311 memset(bw_sum, 0, sizeof(bw_sum)); 312 memset(link_strict, 0, sizeof(link_strict)); 313 314 /* First Tx, then Rx */ 315 for (i = 0; i < 2; i++) { 316 /* Check each traffic class for rule violation */ 317 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) { 318 p = &dcb_config->tc_config[j].path[i]; 319 320 bw = p->bwg_percent; 321 bw_id = p->bwg_id; 322 323 if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) { 324 ret_val = IXGBE_ERR_CONFIG; 325 goto err_config; 326 } 327 if (p->tsa == ixgbe_dcb_tsa_strict) { 328 link_strict[i][bw_id] = TRUE; 329 /* Link strict should have zero bandwidth */ 330 if (bw) { 331 ret_val = IXGBE_ERR_CONFIG; 332 goto err_config; 333 } 334 } else if (!bw) { 335 /* 336 * Traffic classes without link strict 337 * should have non-zero bandwidth. 338 */ 339 ret_val = IXGBE_ERR_CONFIG; 340 goto err_config; 341 } 342 bw_sum[i][bw_id] += bw; 343 } 344 345 bw = 0; 346 347 /* Check each bandwidth group for rule violation */ 348 for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) { 349 bw += dcb_config->bw_percentage[i][j]; 350 /* 351 * Sum of bandwidth percentages of all traffic classes 352 * within a Bandwidth Group must total 100 except for 353 * link strict group (zero bandwidth). 354 */ 355 if (link_strict[i][j]) { 356 if (bw_sum[i][j]) { 357 /* 358 * Link strict group should have zero 359 * bandwidth. 360 */ 361 ret_val = IXGBE_ERR_CONFIG; 362 goto err_config; 363 } 364 } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT && 365 bw_sum[i][j] != 0) { 366 ret_val = IXGBE_ERR_CONFIG; 367 goto err_config; 368 } 369 } 370 371 if (bw != IXGBE_DCB_BW_PERCENT) { 372 ret_val = IXGBE_ERR_CONFIG; 373 goto err_config; 374 } 375 } 376 377 err_config: 378 379 return ret_val; 380 } 381 382 /** 383 * ixgbe_dcb_get_tc_stats - Returns status of each traffic class 384 * @hw: pointer to hardware structure 385 * @stats: pointer to statistics structure 386 * @tc_count: Number of elements in bwg_array. 387 * 388 * This function returns the status data for each of the Traffic Classes in use. 389 */ 390 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, 391 u8 tc_count) 392 { 393 s32 ret = IXGBE_NOT_IMPLEMENTED; 394 switch (hw->mac.type) { 395 case ixgbe_mac_82598EB: 396 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count); 397 break; 398 case ixgbe_mac_82599EB: 399 case ixgbe_mac_X540: 400 case ixgbe_mac_X550: 401 case ixgbe_mac_X550EM_x: 402 case ixgbe_mac_X550EM_a: 403 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 404 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count); 405 break; 406 #endif 407 default: 408 break; 409 } 410 return ret; 411 } 412 413 /** 414 * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class 415 * @hw: pointer to hardware structure 416 * @stats: pointer to statistics structure 417 * @tc_count: Number of elements in bwg_array. 418 * 419 * This function returns the CBFC status data for each of the Traffic Classes. 420 */ 421 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, 422 u8 tc_count) 423 { 424 s32 ret = IXGBE_NOT_IMPLEMENTED; 425 switch (hw->mac.type) { 426 case ixgbe_mac_82598EB: 427 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count); 428 break; 429 case ixgbe_mac_82599EB: 430 case ixgbe_mac_X540: 431 case ixgbe_mac_X550: 432 case ixgbe_mac_X550EM_x: 433 case ixgbe_mac_X550EM_a: 434 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 435 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count); 436 break; 437 #endif 438 default: 439 break; 440 } 441 return ret; 442 } 443 444 /** 445 * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter 446 * @hw: pointer to hardware structure 447 * @dcb_config: pointer to ixgbe_dcb_config structure 448 * 449 * Configure Rx Data Arbiter and credits for each traffic class. 450 */ 451 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw, 452 struct ixgbe_dcb_config *dcb_config) 453 { 454 s32 ret = IXGBE_NOT_IMPLEMENTED; 455 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 456 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 457 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 458 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 459 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 460 461 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 462 ixgbe_dcb_unpack_max_cee(dcb_config, max); 463 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 464 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 465 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 466 467 switch (hw->mac.type) { 468 case ixgbe_mac_82598EB: 469 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 470 break; 471 case ixgbe_mac_82599EB: 472 case ixgbe_mac_X540: 473 case ixgbe_mac_X550: 474 case ixgbe_mac_X550EM_x: 475 case ixgbe_mac_X550EM_a: 476 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 477 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid, 478 tsa, map); 479 break; 480 #endif 481 default: 482 break; 483 } 484 return ret; 485 } 486 487 /** 488 * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter 489 * @hw: pointer to hardware structure 490 * @dcb_config: pointer to ixgbe_dcb_config structure 491 * 492 * Configure Tx Descriptor Arbiter and credits for each traffic class. 493 */ 494 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw, 495 struct ixgbe_dcb_config *dcb_config) 496 { 497 s32 ret = IXGBE_NOT_IMPLEMENTED; 498 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 499 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 500 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 501 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 502 503 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 504 ixgbe_dcb_unpack_max_cee(dcb_config, max); 505 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 506 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 507 508 switch (hw->mac.type) { 509 case ixgbe_mac_82598EB: 510 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 511 bwgid, tsa); 512 break; 513 case ixgbe_mac_82599EB: 514 case ixgbe_mac_X540: 515 case ixgbe_mac_X550: 516 case ixgbe_mac_X550EM_x: 517 case ixgbe_mac_X550EM_a: 518 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 519 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 520 bwgid, tsa); 521 break; 522 #endif 523 default: 524 break; 525 } 526 return ret; 527 } 528 529 /** 530 * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter 531 * @hw: pointer to hardware structure 532 * @dcb_config: pointer to ixgbe_dcb_config structure 533 * 534 * Configure Tx Data Arbiter and credits for each traffic class. 535 */ 536 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw, 537 struct ixgbe_dcb_config *dcb_config) 538 { 539 s32 ret = IXGBE_NOT_IMPLEMENTED; 540 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 541 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 542 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 543 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 544 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 545 546 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 547 ixgbe_dcb_unpack_max_cee(dcb_config, max); 548 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 549 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 550 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 551 552 switch (hw->mac.type) { 553 case ixgbe_mac_82598EB: 554 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 555 bwgid, tsa); 556 break; 557 case ixgbe_mac_82599EB: 558 case ixgbe_mac_X540: 559 case ixgbe_mac_X550: 560 case ixgbe_mac_X550EM_x: 561 case ixgbe_mac_X550EM_a: 562 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 563 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 564 bwgid, tsa, 565 map); 566 break; 567 #endif 568 default: 569 break; 570 } 571 return ret; 572 } 573 574 /** 575 * ixgbe_dcb_config_pfc_cee - Config priority flow control 576 * @hw: pointer to hardware structure 577 * @dcb_config: pointer to ixgbe_dcb_config structure 578 * 579 * Configure Priority Flow Control for each traffic class. 580 */ 581 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw, 582 struct ixgbe_dcb_config *dcb_config) 583 { 584 s32 ret = IXGBE_NOT_IMPLEMENTED; 585 u8 pfc_en; 586 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 587 588 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 589 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en); 590 591 switch (hw->mac.type) { 592 case ixgbe_mac_82598EB: 593 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en); 594 break; 595 case ixgbe_mac_82599EB: 596 case ixgbe_mac_X540: 597 case ixgbe_mac_X550: 598 case ixgbe_mac_X550EM_x: 599 case ixgbe_mac_X550EM_a: 600 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 601 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map); 602 break; 603 #endif 604 default: 605 break; 606 } 607 return ret; 608 } 609 610 /** 611 * ixgbe_dcb_config_tc_stats - Config traffic class statistics 612 * @hw: pointer to hardware structure 613 * 614 * Configure queue statistics registers, all queues belonging to same traffic 615 * class uses a single set of queue statistics counters. 616 */ 617 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw) 618 { 619 s32 ret = IXGBE_NOT_IMPLEMENTED; 620 switch (hw->mac.type) { 621 case ixgbe_mac_82598EB: 622 ret = ixgbe_dcb_config_tc_stats_82598(hw); 623 break; 624 case ixgbe_mac_82599EB: 625 case ixgbe_mac_X540: 626 case ixgbe_mac_X550: 627 case ixgbe_mac_X550EM_x: 628 case ixgbe_mac_X550EM_a: 629 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 630 ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL); 631 break; 632 #endif 633 default: 634 break; 635 } 636 return ret; 637 } 638 639 /** 640 * ixgbe_dcb_hw_config_cee - Config and enable DCB 641 * @hw: pointer to hardware structure 642 * @dcb_config: pointer to ixgbe_dcb_config structure 643 * 644 * Configure dcb settings and enable dcb mode. 645 */ 646 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw, 647 struct ixgbe_dcb_config *dcb_config) 648 { 649 s32 ret = IXGBE_NOT_IMPLEMENTED; 650 u8 pfc_en; 651 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 652 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 653 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 654 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 655 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 656 657 /* Unpack CEE standard containers */ 658 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 659 ixgbe_dcb_unpack_max_cee(dcb_config, max); 660 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 661 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 662 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 663 664 hw->mac.ops.setup_rxpba(hw, dcb_config->num_tcs.pg_tcs, 665 0, dcb_config->rx_pba_cfg); 666 667 switch (hw->mac.type) { 668 case ixgbe_mac_82598EB: 669 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed, 670 refill, max, bwgid, tsa); 671 break; 672 case ixgbe_mac_82599EB: 673 case ixgbe_mac_X540: 674 case ixgbe_mac_X550: 675 case ixgbe_mac_X550EM_x: 676 case ixgbe_mac_X550EM_a: 677 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 678 ixgbe_dcb_config_82599(hw, dcb_config); 679 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed, 680 refill, max, bwgid, 681 tsa, map); 682 683 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config); 684 break; 685 #endif 686 default: 687 break; 688 } 689 690 if (!ret && dcb_config->pfc_mode_enable) { 691 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en); 692 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map); 693 } 694 695 return ret; 696 } 697 698 /* Helper routines to abstract HW specifics from DCB netlink ops */ 699 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map) 700 { 701 int ret = IXGBE_ERR_PARAM; 702 703 switch (hw->mac.type) { 704 case ixgbe_mac_82598EB: 705 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en); 706 break; 707 case ixgbe_mac_82599EB: 708 case ixgbe_mac_X540: 709 case ixgbe_mac_X550: 710 case ixgbe_mac_X550EM_x: 711 case ixgbe_mac_X550EM_a: 712 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 713 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map); 714 break; 715 #endif 716 default: 717 break; 718 } 719 return ret; 720 } 721 722 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, 723 u8 *bwg_id, u8 *tsa, u8 *map) 724 { 725 switch (hw->mac.type) { 726 case ixgbe_mac_82598EB: 727 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 728 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, 729 tsa); 730 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, 731 tsa); 732 break; 733 case ixgbe_mac_82599EB: 734 case ixgbe_mac_X540: 735 case ixgbe_mac_X550: 736 case ixgbe_mac_X550EM_x: 737 case ixgbe_mac_X550EM_a: 738 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 739 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 740 tsa, map); 741 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, 742 tsa); 743 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, 744 tsa, map); 745 break; 746 #endif 747 default: 748 break; 749 } 750 return 0; 751 } 752