1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 36 #include "ixgbe_type.h" 37 #include "ixgbe_dcb.h" 38 #include "ixgbe_dcb_82598.h" 39 #include "ixgbe_dcb_82599.h" 40 41 /** 42 * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class 43 * credits from the configured bandwidth percentages. Credits 44 * are the smallest unit programmable into the underlying 45 * hardware. The IEEE 802.1Qaz specification do not use bandwidth 46 * groups so this is much simplified from the CEE case. 47 */ 48 s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max, 49 int max_frame_size) 50 { 51 int min_percent = 100; 52 int min_credit, multiplier; 53 int i; 54 55 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) / 56 IXGBE_DCB_CREDIT_QUANTUM; 57 58 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 59 if (bw[i] < min_percent && bw[i]) 60 min_percent = bw[i]; 61 } 62 63 multiplier = (min_credit / min_percent) + 1; 64 65 /* Find out the hw credits for each TC */ 66 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 67 int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL); 68 69 if (val < min_credit) 70 val = min_credit; 71 refill[i] = (u16)val; 72 73 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit; 74 } 75 76 return 0; 77 } 78 79 /** 80 * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits 81 * @ixgbe_dcb_config: Struct containing DCB settings. 82 * @direction: Configuring either Tx or Rx. 83 * 84 * This function calculates the credits allocated to each traffic class. 85 * It should be called only after the rules are checked by 86 * ixgbe_dcb_check_config_cee(). 87 */ 88 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw, 89 struct ixgbe_dcb_config *dcb_config, 90 u32 max_frame_size, u8 direction) 91 { 92 struct ixgbe_dcb_tc_path *p; 93 u32 min_multiplier = 0; 94 u16 min_percent = 100; 95 s32 ret_val = IXGBE_SUCCESS; 96 /* Initialization values default for Tx settings */ 97 u32 min_credit = 0; 98 u32 credit_refill = 0; 99 u32 credit_max = 0; 100 u16 link_percentage = 0; 101 u8 bw_percent = 0; 102 u8 i; 103 104 if (dcb_config == NULL) { 105 ret_val = IXGBE_ERR_CONFIG; 106 goto out; 107 } 108 109 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) / 110 IXGBE_DCB_CREDIT_QUANTUM; 111 112 /* Find smallest link percentage */ 113 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 114 p = &dcb_config->tc_config[i].path[direction]; 115 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 116 link_percentage = p->bwg_percent; 117 118 link_percentage = (link_percentage * bw_percent) / 100; 119 120 if (link_percentage && link_percentage < min_percent) 121 min_percent = link_percentage; 122 } 123 124 /* 125 * The ratio between traffic classes will control the bandwidth 126 * percentages seen on the wire. To calculate this ratio we use 127 * a multiplier. It is required that the refill credits must be 128 * larger than the max frame size so here we find the smallest 129 * multiplier that will allow all bandwidth percentages to be 130 * greater than the max frame size. 131 */ 132 min_multiplier = (min_credit / min_percent) + 1; 133 134 /* Find out the link percentage for each TC first */ 135 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 136 p = &dcb_config->tc_config[i].path[direction]; 137 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id]; 138 139 link_percentage = p->bwg_percent; 140 /* Must be careful of integer division for very small nums */ 141 link_percentage = (link_percentage * bw_percent) / 100; 142 if (p->bwg_percent > 0 && link_percentage == 0) 143 link_percentage = 1; 144 145 /* Save link_percentage for reference */ 146 p->link_percent = (u8)link_percentage; 147 148 /* Calculate credit refill ratio using multiplier */ 149 credit_refill = min(link_percentage * min_multiplier, 150 (u32)IXGBE_DCB_MAX_CREDIT_REFILL); 151 p->data_credits_refill = (u16)credit_refill; 152 153 /* Calculate maximum credit for the TC */ 154 credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100; 155 156 /* 157 * Adjustment based on rule checking, if the percentage 158 * of a TC is too small, the maximum credit may not be 159 * enough to send out a jumbo frame in data plane arbitration. 160 */ 161 if (credit_max && (credit_max < min_credit)) 162 credit_max = min_credit; 163 164 if (direction == IXGBE_DCB_TX_CONFIG) { 165 /* 166 * Adjustment based on rule checking, if the 167 * percentage of a TC is too small, the maximum 168 * credit may not be enough to send out a TSO 169 * packet in descriptor plane arbitration. 170 */ 171 if (credit_max && (credit_max < 172 IXGBE_DCB_MIN_TSO_CREDIT) 173 && (hw->mac.type == ixgbe_mac_82598EB)) 174 credit_max = IXGBE_DCB_MIN_TSO_CREDIT; 175 176 dcb_config->tc_config[i].desc_credits_max = 177 (u16)credit_max; 178 } 179 180 p->data_credits_max = (u16)credit_max; 181 } 182 183 out: 184 return ret_val; 185 } 186 187 /** 188 * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info 189 * @cfg: dcb configuration to unpack into hardware consumable fields 190 * @map: user priority to traffic class map 191 * @pfc_up: u8 to store user priority PFC bitmask 192 * 193 * This unpacks the dcb configuration PFC info which is stored per 194 * traffic class into a 8bit user priority bitmask that can be 195 * consumed by hardware routines. The priority to tc map must be 196 * updated before calling this routine to use current up-to maps. 197 */ 198 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up) 199 { 200 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 201 int up; 202 203 /* 204 * If the TC for this user priority has PFC enabled then set the 205 * matching bit in 'pfc_up' to reflect that PFC is enabled. 206 */ 207 for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) { 208 if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled) 209 *pfc_up |= 1 << up; 210 } 211 } 212 213 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction, 214 u16 *refill) 215 { 216 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 217 int tc; 218 219 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 220 refill[tc] = tc_config[tc].path[direction].data_credits_refill; 221 } 222 223 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max) 224 { 225 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 226 int tc; 227 228 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 229 max[tc] = tc_config[tc].desc_credits_max; 230 } 231 232 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction, 233 u8 *bwgid) 234 { 235 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 236 int tc; 237 238 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 239 bwgid[tc] = tc_config[tc].path[direction].bwg_id; 240 } 241 242 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction, 243 u8 *tsa) 244 { 245 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 246 int tc; 247 248 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) 249 tsa[tc] = tc_config[tc].path[direction].tsa; 250 } 251 252 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up) 253 { 254 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0]; 255 u8 prio_mask = 1 << up; 256 u8 tc = cfg->num_tcs.pg_tcs; 257 258 /* If tc is 0 then DCB is likely not enabled or supported */ 259 if (!tc) 260 goto out; 261 262 /* 263 * Test from maximum TC to 1 and report the first match we find. If 264 * we find no match we can assume that the TC is 0 since the TC must 265 * be set for all user priorities 266 */ 267 for (tc--; tc; tc--) { 268 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap) 269 break; 270 } 271 out: 272 return tc; 273 } 274 275 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction, 276 u8 *map) 277 { 278 u8 up; 279 280 for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) 281 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up); 282 } 283 284 /** 285 * ixgbe_dcb_config - Struct containing DCB settings. 286 * @dcb_config: Pointer to DCB config structure 287 * 288 * This function checks DCB rules for DCB settings. 289 * The following rules are checked: 290 * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%. 291 * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth 292 * Group must total 100. 293 * 3. A Traffic Class should not be set to both Link Strict Priority 294 * and Group Strict Priority. 295 * 4. Link strict Bandwidth Groups can only have link strict traffic classes 296 * with zero bandwidth. 297 */ 298 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config) 299 { 300 struct ixgbe_dcb_tc_path *p; 301 s32 ret_val = IXGBE_SUCCESS; 302 u8 i, j, bw = 0, bw_id; 303 u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP]; 304 bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP]; 305 306 memset(bw_sum, 0, sizeof(bw_sum)); 307 memset(link_strict, 0, sizeof(link_strict)); 308 309 /* First Tx, then Rx */ 310 for (i = 0; i < 2; i++) { 311 /* Check each traffic class for rule violation */ 312 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) { 313 p = &dcb_config->tc_config[j].path[i]; 314 315 bw = p->bwg_percent; 316 bw_id = p->bwg_id; 317 318 if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) { 319 ret_val = IXGBE_ERR_CONFIG; 320 goto err_config; 321 } 322 if (p->tsa == ixgbe_dcb_tsa_strict) { 323 link_strict[i][bw_id] = TRUE; 324 /* Link strict should have zero bandwidth */ 325 if (bw) { 326 ret_val = IXGBE_ERR_CONFIG; 327 goto err_config; 328 } 329 } else if (!bw) { 330 /* 331 * Traffic classes without link strict 332 * should have non-zero bandwidth. 333 */ 334 ret_val = IXGBE_ERR_CONFIG; 335 goto err_config; 336 } 337 bw_sum[i][bw_id] += bw; 338 } 339 340 bw = 0; 341 342 /* Check each bandwidth group for rule violation */ 343 for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) { 344 bw += dcb_config->bw_percentage[i][j]; 345 /* 346 * Sum of bandwidth percentages of all traffic classes 347 * within a Bandwidth Group must total 100 except for 348 * link strict group (zero bandwidth). 349 */ 350 if (link_strict[i][j]) { 351 if (bw_sum[i][j]) { 352 /* 353 * Link strict group should have zero 354 * bandwidth. 355 */ 356 ret_val = IXGBE_ERR_CONFIG; 357 goto err_config; 358 } 359 } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT && 360 bw_sum[i][j] != 0) { 361 ret_val = IXGBE_ERR_CONFIG; 362 goto err_config; 363 } 364 } 365 366 if (bw != IXGBE_DCB_BW_PERCENT) { 367 ret_val = IXGBE_ERR_CONFIG; 368 goto err_config; 369 } 370 } 371 372 err_config: 373 DEBUGOUT2("DCB error code %d while checking %s settings.\n", 374 ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx"); 375 376 return ret_val; 377 } 378 379 /** 380 * ixgbe_dcb_get_tc_stats - Returns status of each traffic class 381 * @hw: pointer to hardware structure 382 * @stats: pointer to statistics structure 383 * @tc_count: Number of elements in bwg_array. 384 * 385 * This function returns the status data for each of the Traffic Classes in use. 386 */ 387 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, 388 u8 tc_count) 389 { 390 s32 ret = IXGBE_NOT_IMPLEMENTED; 391 switch (hw->mac.type) { 392 case ixgbe_mac_82598EB: 393 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count); 394 break; 395 case ixgbe_mac_82599EB: 396 case ixgbe_mac_X540: 397 case ixgbe_mac_X550: 398 case ixgbe_mac_X550EM_x: 399 case ixgbe_mac_X550EM_a: 400 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 401 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count); 402 break; 403 #endif 404 default: 405 break; 406 } 407 return ret; 408 } 409 410 /** 411 * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class 412 * @hw: pointer to hardware structure 413 * @stats: pointer to statistics structure 414 * @tc_count: Number of elements in bwg_array. 415 * 416 * This function returns the CBFC status data for each of the Traffic Classes. 417 */ 418 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats, 419 u8 tc_count) 420 { 421 s32 ret = IXGBE_NOT_IMPLEMENTED; 422 switch (hw->mac.type) { 423 case ixgbe_mac_82598EB: 424 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count); 425 break; 426 case ixgbe_mac_82599EB: 427 case ixgbe_mac_X540: 428 case ixgbe_mac_X550: 429 case ixgbe_mac_X550EM_x: 430 case ixgbe_mac_X550EM_a: 431 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 432 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count); 433 break; 434 #endif 435 default: 436 break; 437 } 438 return ret; 439 } 440 441 /** 442 * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter 443 * @hw: pointer to hardware structure 444 * @dcb_config: pointer to ixgbe_dcb_config structure 445 * 446 * Configure Rx Data Arbiter and credits for each traffic class. 447 */ 448 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw, 449 struct ixgbe_dcb_config *dcb_config) 450 { 451 s32 ret = IXGBE_NOT_IMPLEMENTED; 452 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 453 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 454 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 455 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 456 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 }; 457 458 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 459 ixgbe_dcb_unpack_max_cee(dcb_config, max); 460 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 461 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 462 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 463 464 switch (hw->mac.type) { 465 case ixgbe_mac_82598EB: 466 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 467 break; 468 case ixgbe_mac_82599EB: 469 case ixgbe_mac_X540: 470 case ixgbe_mac_X550: 471 case ixgbe_mac_X550EM_x: 472 case ixgbe_mac_X550EM_a: 473 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 474 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid, 475 tsa, map); 476 break; 477 #endif 478 default: 479 break; 480 } 481 return ret; 482 } 483 484 /** 485 * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter 486 * @hw: pointer to hardware structure 487 * @dcb_config: pointer to ixgbe_dcb_config structure 488 * 489 * Configure Tx Descriptor Arbiter and credits for each traffic class. 490 */ 491 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw, 492 struct ixgbe_dcb_config *dcb_config) 493 { 494 s32 ret = IXGBE_NOT_IMPLEMENTED; 495 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 496 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 497 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 498 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 499 500 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 501 ixgbe_dcb_unpack_max_cee(dcb_config, max); 502 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 503 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 504 505 switch (hw->mac.type) { 506 case ixgbe_mac_82598EB: 507 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, 508 bwgid, tsa); 509 break; 510 case ixgbe_mac_82599EB: 511 case ixgbe_mac_X540: 512 case ixgbe_mac_X550: 513 case ixgbe_mac_X550EM_x: 514 case ixgbe_mac_X550EM_a: 515 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 516 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, 517 bwgid, tsa); 518 break; 519 #endif 520 default: 521 break; 522 } 523 return ret; 524 } 525 526 /** 527 * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter 528 * @hw: pointer to hardware structure 529 * @dcb_config: pointer to ixgbe_dcb_config structure 530 * 531 * Configure Tx Data Arbiter and credits for each traffic class. 532 */ 533 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw, 534 struct ixgbe_dcb_config *dcb_config) 535 { 536 s32 ret = IXGBE_NOT_IMPLEMENTED; 537 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 538 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 539 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 540 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 541 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 542 543 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 544 ixgbe_dcb_unpack_max_cee(dcb_config, max); 545 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 546 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 547 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 548 549 switch (hw->mac.type) { 550 case ixgbe_mac_82598EB: 551 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, 552 bwgid, tsa); 553 break; 554 case ixgbe_mac_82599EB: 555 case ixgbe_mac_X540: 556 case ixgbe_mac_X550: 557 case ixgbe_mac_X550EM_x: 558 case ixgbe_mac_X550EM_a: 559 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 560 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, 561 bwgid, tsa, 562 map); 563 break; 564 #endif 565 default: 566 break; 567 } 568 return ret; 569 } 570 571 /** 572 * ixgbe_dcb_config_pfc_cee - Config priority flow control 573 * @hw: pointer to hardware structure 574 * @dcb_config: pointer to ixgbe_dcb_config structure 575 * 576 * Configure Priority Flow Control for each traffic class. 577 */ 578 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw, 579 struct ixgbe_dcb_config *dcb_config) 580 { 581 s32 ret = IXGBE_NOT_IMPLEMENTED; 582 u8 pfc_en; 583 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 584 585 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 586 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en); 587 588 switch (hw->mac.type) { 589 case ixgbe_mac_82598EB: 590 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en); 591 break; 592 case ixgbe_mac_82599EB: 593 case ixgbe_mac_X540: 594 case ixgbe_mac_X550: 595 case ixgbe_mac_X550EM_x: 596 case ixgbe_mac_X550EM_a: 597 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 598 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map); 599 break; 600 #endif 601 default: 602 break; 603 } 604 return ret; 605 } 606 607 /** 608 * ixgbe_dcb_config_tc_stats - Config traffic class statistics 609 * @hw: pointer to hardware structure 610 * 611 * Configure queue statistics registers, all queues belonging to same traffic 612 * class uses a single set of queue statistics counters. 613 */ 614 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw) 615 { 616 s32 ret = IXGBE_NOT_IMPLEMENTED; 617 switch (hw->mac.type) { 618 case ixgbe_mac_82598EB: 619 ret = ixgbe_dcb_config_tc_stats_82598(hw); 620 break; 621 case ixgbe_mac_82599EB: 622 case ixgbe_mac_X540: 623 case ixgbe_mac_X550: 624 case ixgbe_mac_X550EM_x: 625 case ixgbe_mac_X550EM_a: 626 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 627 ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL); 628 break; 629 #endif 630 default: 631 break; 632 } 633 return ret; 634 } 635 636 /** 637 * ixgbe_dcb_hw_config_cee - Config and enable DCB 638 * @hw: pointer to hardware structure 639 * @dcb_config: pointer to ixgbe_dcb_config structure 640 * 641 * Configure dcb settings and enable dcb mode. 642 */ 643 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw, 644 struct ixgbe_dcb_config *dcb_config) 645 { 646 s32 ret = IXGBE_NOT_IMPLEMENTED; 647 u8 pfc_en; 648 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 649 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 650 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 651 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 652 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 653 654 /* Unpack CEE standard containers */ 655 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill); 656 ixgbe_dcb_unpack_max_cee(dcb_config, max); 657 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid); 658 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa); 659 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map); 660 661 hw->mac.ops.setup_rxpba(hw, dcb_config->num_tcs.pg_tcs, 662 0, dcb_config->rx_pba_cfg); 663 664 switch (hw->mac.type) { 665 case ixgbe_mac_82598EB: 666 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed, 667 refill, max, bwgid, tsa); 668 break; 669 case ixgbe_mac_82599EB: 670 case ixgbe_mac_X540: 671 case ixgbe_mac_X550: 672 case ixgbe_mac_X550EM_x: 673 case ixgbe_mac_X550EM_a: 674 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 675 ixgbe_dcb_config_82599(hw, dcb_config); 676 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed, 677 refill, max, bwgid, 678 tsa, map); 679 680 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config); 681 break; 682 #endif 683 default: 684 break; 685 } 686 687 if (!ret && dcb_config->pfc_mode_enable) { 688 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en); 689 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map); 690 } 691 692 return ret; 693 } 694 695 /* Helper routines to abstract HW specifics from DCB netlink ops */ 696 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map) 697 { 698 int ret = IXGBE_ERR_PARAM; 699 700 switch (hw->mac.type) { 701 case ixgbe_mac_82598EB: 702 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en); 703 break; 704 case ixgbe_mac_82599EB: 705 case ixgbe_mac_X540: 706 case ixgbe_mac_X550: 707 case ixgbe_mac_X550EM_x: 708 case ixgbe_mac_X550EM_a: 709 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 710 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map); 711 break; 712 #endif 713 default: 714 break; 715 } 716 return ret; 717 } 718 719 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max, 720 u8 *bwg_id, u8 *tsa, u8 *map) 721 { 722 switch (hw->mac.type) { 723 case ixgbe_mac_82598EB: 724 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa); 725 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id, 726 tsa); 727 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id, 728 tsa); 729 break; 730 case ixgbe_mac_82599EB: 731 case ixgbe_mac_X540: 732 case ixgbe_mac_X550: 733 case ixgbe_mac_X550EM_x: 734 case ixgbe_mac_X550EM_a: 735 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT) 736 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, 737 tsa, map); 738 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id, 739 tsa); 740 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id, 741 tsa, map); 742 break; 743 #endif 744 default: 745 break; 746 } 747 return 0; 748 } 749