1 /****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "ixgbe_api.h" 36 #include "ixgbe_common.h" 37 #include "ixgbe_phy.h" 38 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53 /** 54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55 * @hw: pointer to the hardware structure 56 * @byte: byte to send 57 * 58 * Returns an error code on error. 59 */ 60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61 { 62 s32 status; 63 64 status = ixgbe_clock_out_i2c_byte(hw, byte); 65 if (status) 66 return status; 67 return ixgbe_get_i2c_ack(hw); 68 } 69 70 /** 71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72 * @hw: pointer to the hardware structure 73 * @byte: pointer to a u8 to receive the byte 74 * 75 * Returns an error code on error. 76 */ 77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78 { 79 s32 status; 80 81 status = ixgbe_clock_in_i2c_byte(hw, byte); 82 if (status) 83 return status; 84 /* ACK */ 85 return ixgbe_clock_out_i2c_bit(hw, FALSE); 86 } 87 88 /** 89 * ixgbe_ones_comp_byte_add - Perform one's complement addition 90 * @add1: addend 1 91 * @add2: addend 2 92 * 93 * Returns one's complement 8-bit sum. 94 */ 95 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 96 { 97 u16 sum = add1 + add2; 98 99 sum = (sum & 0xFF) + (sum >> 8); 100 return sum & 0xFF; 101 } 102 103 /** 104 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 105 * @hw: pointer to the hardware structure 106 * @addr: I2C bus address to read from 107 * @reg: I2C device register to read from 108 * @val: pointer to location to receive read value 109 * @lock: TRUE if to take and release semaphore 110 * 111 * Returns an error code on error. 112 */ 113 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 114 u16 *val, bool lock) 115 { 116 u32 swfw_mask = hw->phy.phy_semaphore_mask; 117 int max_retry = 3; 118 int retry = 0; 119 u8 csum_byte; 120 u8 high_bits; 121 u8 low_bits; 122 u8 reg_high; 123 u8 csum; 124 125 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 126 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 127 csum = ~csum; 128 do { 129 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 130 return IXGBE_ERR_SWFW_SYNC; 131 ixgbe_i2c_start(hw); 132 /* Device Address and write indication */ 133 if (ixgbe_out_i2c_byte_ack(hw, addr)) 134 goto fail; 135 /* Write bits 14:8 */ 136 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 137 goto fail; 138 /* Write bits 7:0 */ 139 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 140 goto fail; 141 /* Write csum */ 142 if (ixgbe_out_i2c_byte_ack(hw, csum)) 143 goto fail; 144 /* Re-start condition */ 145 ixgbe_i2c_start(hw); 146 /* Device Address and read indication */ 147 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 148 goto fail; 149 /* Get upper bits */ 150 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 151 goto fail; 152 /* Get low bits */ 153 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 154 goto fail; 155 /* Get csum */ 156 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 157 goto fail; 158 /* NACK */ 159 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 160 goto fail; 161 ixgbe_i2c_stop(hw); 162 if (lock) 163 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 164 *val = (high_bits << 8) | low_bits; 165 return 0; 166 167 fail: 168 ixgbe_i2c_bus_clear(hw); 169 if (lock) 170 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 171 retry++; 172 if (retry < max_retry) 173 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 174 else 175 DEBUGOUT("I2C byte read combined error.\n"); 176 } while (retry < max_retry); 177 178 return IXGBE_ERR_I2C; 179 } 180 181 /** 182 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 183 * @hw: pointer to the hardware structure 184 * @addr: I2C bus address to write to 185 * @reg: I2C device register to write to 186 * @val: value to write 187 * @lock: TRUE if to take and release semaphore 188 * 189 * Returns an error code on error. 190 */ 191 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg, 192 u16 val, bool lock) 193 { 194 u32 swfw_mask = hw->phy.phy_semaphore_mask; 195 int max_retry = 1; 196 int retry = 0; 197 u8 reg_high; 198 u8 csum; 199 200 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 201 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 202 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 203 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 204 csum = ~csum; 205 do { 206 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 207 return IXGBE_ERR_SWFW_SYNC; 208 ixgbe_i2c_start(hw); 209 /* Device Address and write indication */ 210 if (ixgbe_out_i2c_byte_ack(hw, addr)) 211 goto fail; 212 /* Write bits 14:8 */ 213 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 214 goto fail; 215 /* Write bits 7:0 */ 216 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 217 goto fail; 218 /* Write data 15:8 */ 219 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 220 goto fail; 221 /* Write data 7:0 */ 222 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 223 goto fail; 224 /* Write csum */ 225 if (ixgbe_out_i2c_byte_ack(hw, csum)) 226 goto fail; 227 ixgbe_i2c_stop(hw); 228 if (lock) 229 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 230 return 0; 231 232 fail: 233 ixgbe_i2c_bus_clear(hw); 234 if (lock) 235 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 236 retry++; 237 if (retry < max_retry) 238 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 239 else 240 DEBUGOUT("I2C byte write combined error.\n"); 241 } while (retry < max_retry); 242 243 return IXGBE_ERR_I2C; 244 } 245 246 /** 247 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 248 * @hw: pointer to the hardware structure 249 * 250 * Initialize the function pointers. 251 **/ 252 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 253 { 254 struct ixgbe_phy_info *phy = &hw->phy; 255 256 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 257 258 /* PHY */ 259 phy->ops.identify = ixgbe_identify_phy_generic; 260 phy->ops.reset = ixgbe_reset_phy_generic; 261 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 262 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 263 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 264 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 265 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 266 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 267 phy->ops.check_link = NULL; 268 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 269 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 270 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 271 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 272 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 273 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 274 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 275 phy->ops.identify_sfp = ixgbe_identify_module_generic; 276 phy->sfp_type = ixgbe_sfp_type_unknown; 277 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 278 phy->ops.write_i2c_byte_unlocked = 279 ixgbe_write_i2c_byte_generic_unlocked; 280 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 281 return IXGBE_SUCCESS; 282 } 283 284 /** 285 * ixgbe_probe_phy - Probe a single address for a PHY 286 * @hw: pointer to hardware structure 287 * @phy_addr: PHY address to probe 288 * 289 * Returns TRUE if PHY found 290 */ 291 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr) 292 { 293 u16 ext_ability = 0; 294 295 if (!ixgbe_validate_phy_addr(hw, phy_addr)) { 296 DEBUGOUT1("Unable to validate PHY address 0x%04X\n", 297 phy_addr); 298 return FALSE; 299 } 300 301 if (ixgbe_get_phy_id(hw)) 302 return FALSE; 303 304 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id); 305 306 if (hw->phy.type == ixgbe_phy_unknown) { 307 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 308 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 309 if (ext_ability & 310 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 311 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 312 hw->phy.type = ixgbe_phy_cu_unknown; 313 else 314 hw->phy.type = ixgbe_phy_generic; 315 } 316 317 return TRUE; 318 } 319 320 /** 321 * ixgbe_identify_phy_generic - Get physical layer module 322 * @hw: pointer to hardware structure 323 * 324 * Determines the physical layer module found on the current adapter. 325 **/ 326 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 327 { 328 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 329 u16 phy_addr; 330 331 DEBUGFUNC("ixgbe_identify_phy_generic"); 332 333 if (!hw->phy.phy_semaphore_mask) { 334 if (hw->bus.lan_id) 335 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 336 else 337 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 338 } 339 340 if (hw->phy.type != ixgbe_phy_unknown) 341 return IXGBE_SUCCESS; 342 343 if (hw->phy.nw_mng_if_sel) { 344 phy_addr = (hw->phy.nw_mng_if_sel & 345 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 346 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 347 if (ixgbe_probe_phy(hw, phy_addr)) 348 return IXGBE_SUCCESS; 349 else 350 return IXGBE_ERR_PHY_ADDR_INVALID; 351 } 352 353 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 354 if (ixgbe_probe_phy(hw, phy_addr)) { 355 status = IXGBE_SUCCESS; 356 break; 357 } 358 } 359 360 /* Certain media types do not have a phy so an address will not 361 * be found and the code will take this path. Caller has to 362 * decide if it is an error or not. 363 */ 364 if (status != IXGBE_SUCCESS) 365 hw->phy.addr = 0; 366 367 return status; 368 } 369 370 /** 371 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 372 * @hw: pointer to the hardware structure 373 * 374 * This function checks the MMNGC.MNG_VETO bit to see if there are 375 * any constraints on link from manageability. For MAC's that don't 376 * have this bit just return faluse since the link can not be blocked 377 * via this method. 378 **/ 379 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 380 { 381 u32 mmngc; 382 383 DEBUGFUNC("ixgbe_check_reset_blocked"); 384 385 /* If we don't have this bit, it can't be blocking */ 386 if (hw->mac.type == ixgbe_mac_82598EB) 387 return FALSE; 388 389 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 390 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 391 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 392 "MNG_VETO bit detected.\n"); 393 return TRUE; 394 } 395 396 return FALSE; 397 } 398 399 /** 400 * ixgbe_validate_phy_addr - Determines phy address is valid 401 * @hw: pointer to hardware structure 402 * @phy_addr: PHY address 403 * 404 **/ 405 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 406 { 407 u16 phy_id = 0; 408 bool valid = FALSE; 409 410 DEBUGFUNC("ixgbe_validate_phy_addr"); 411 412 hw->phy.addr = phy_addr; 413 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 414 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 415 416 if (phy_id != 0xFFFF && phy_id != 0x0) 417 valid = TRUE; 418 419 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id); 420 421 return valid; 422 } 423 424 /** 425 * ixgbe_get_phy_id - Get the phy type 426 * @hw: pointer to hardware structure 427 * 428 **/ 429 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 430 { 431 u32 status; 432 u16 phy_id_high = 0; 433 u16 phy_id_low = 0; 434 435 DEBUGFUNC("ixgbe_get_phy_id"); 436 437 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 438 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 439 &phy_id_high); 440 441 if (status == IXGBE_SUCCESS) { 442 hw->phy.id = (u32)(phy_id_high << 16); 443 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 444 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 445 &phy_id_low); 446 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 447 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 448 } 449 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n", 450 phy_id_high, phy_id_low); 451 452 return status; 453 } 454 455 /** 456 * ixgbe_get_phy_type_from_id - Get the phy type 457 * @phy_id: PHY ID information 458 * 459 **/ 460 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 461 { 462 enum ixgbe_phy_type phy_type; 463 464 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 465 466 switch (phy_id) { 467 case TN1010_PHY_ID: 468 phy_type = ixgbe_phy_tn; 469 break; 470 case X550_PHY_ID2: 471 case X550_PHY_ID3: 472 case X540_PHY_ID: 473 phy_type = ixgbe_phy_aq; 474 break; 475 case QT2022_PHY_ID: 476 phy_type = ixgbe_phy_qt; 477 break; 478 case ATH_PHY_ID: 479 phy_type = ixgbe_phy_nl; 480 break; 481 case X557_PHY_ID: 482 case X557_PHY_ID2: 483 phy_type = ixgbe_phy_x550em_ext_t; 484 break; 485 case IXGBE_M88E1500_E_PHY_ID: 486 case IXGBE_M88E1543_E_PHY_ID: 487 phy_type = ixgbe_phy_ext_1g_t; 488 break; 489 default: 490 phy_type = ixgbe_phy_unknown; 491 break; 492 } 493 return phy_type; 494 } 495 496 /** 497 * ixgbe_reset_phy_generic - Performs a PHY reset 498 * @hw: pointer to hardware structure 499 **/ 500 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 501 { 502 u32 i; 503 u16 ctrl = 0; 504 s32 status = IXGBE_SUCCESS; 505 506 DEBUGFUNC("ixgbe_reset_phy_generic"); 507 508 if (hw->phy.type == ixgbe_phy_unknown) 509 status = ixgbe_identify_phy_generic(hw); 510 511 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 512 goto out; 513 514 /* Don't reset PHY if it's shut down due to overtemp. */ 515 if (!hw->phy.reset_if_overtemp && 516 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 517 goto out; 518 519 /* Blocked by MNG FW so bail */ 520 if (ixgbe_check_reset_blocked(hw)) 521 goto out; 522 523 /* 524 * Perform soft PHY reset to the PHY_XS. 525 * This will cause a soft reset to the PHY 526 */ 527 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 528 IXGBE_MDIO_PHY_XS_DEV_TYPE, 529 IXGBE_MDIO_PHY_XS_RESET); 530 531 /* 532 * Poll for reset bit to self-clear indicating reset is complete. 533 * Some PHYs could take up to 3 seconds to complete and need about 534 * 1.7 usec delay after the reset is complete. 535 */ 536 for (i = 0; i < 30; i++) { 537 msec_delay(100); 538 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 539 status = hw->phy.ops.read_reg(hw, 540 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 541 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 542 &ctrl); 543 if (status != IXGBE_SUCCESS) 544 return status; 545 546 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 547 usec_delay(2); 548 break; 549 } 550 } else { 551 status = hw->phy.ops.read_reg(hw, 552 IXGBE_MDIO_PHY_XS_CONTROL, 553 IXGBE_MDIO_PHY_XS_DEV_TYPE, 554 &ctrl); 555 if (status != IXGBE_SUCCESS) 556 return status; 557 558 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 559 usec_delay(2); 560 break; 561 } 562 } 563 } 564 565 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 566 status = IXGBE_ERR_RESET_FAILED; 567 ERROR_REPORT1(IXGBE_ERROR_POLLING, 568 "PHY reset polling failed to complete.\n"); 569 } 570 571 out: 572 return status; 573 } 574 575 /** 576 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 577 * the SWFW lock 578 * @hw: pointer to hardware structure 579 * @reg_addr: 32 bit address of PHY register to read 580 * @device_type: 5 bit device type 581 * @phy_data: Pointer to read data from PHY register 582 **/ 583 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 584 u16 *phy_data) 585 { 586 u32 i, data, command; 587 588 /* Setup and write the address cycle command */ 589 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 590 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 591 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 592 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 593 594 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 595 596 /* 597 * Check every 10 usec to see if the address cycle completed. 598 * The MDI Command bit will clear when the operation is 599 * complete 600 */ 601 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 602 usec_delay(10); 603 604 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 605 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 606 break; 607 } 608 609 610 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 611 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 612 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n"); 613 return IXGBE_ERR_PHY; 614 } 615 616 /* 617 * Address cycle complete, setup and write the read 618 * command 619 */ 620 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 621 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 622 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 623 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 624 625 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 626 627 /* 628 * Check every 10 usec to see if the address cycle 629 * completed. The MDI Command bit will clear when the 630 * operation is complete 631 */ 632 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 633 usec_delay(10); 634 635 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 636 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 637 break; 638 } 639 640 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 641 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 642 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n"); 643 return IXGBE_ERR_PHY; 644 } 645 646 /* 647 * Read operation is complete. Get the data 648 * from MSRWD 649 */ 650 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 651 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 652 *phy_data = (u16)(data); 653 654 return IXGBE_SUCCESS; 655 } 656 657 /** 658 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 659 * using the SWFW lock - this function is needed in most cases 660 * @hw: pointer to hardware structure 661 * @reg_addr: 32 bit address of PHY register to read 662 * @device_type: 5 bit device type 663 * @phy_data: Pointer to read data from PHY register 664 **/ 665 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 666 u32 device_type, u16 *phy_data) 667 { 668 s32 status; 669 u32 gssr = hw->phy.phy_semaphore_mask; 670 671 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 672 673 if (hw->mac.ops.acquire_swfw_sync(hw, gssr)) 674 return IXGBE_ERR_SWFW_SYNC; 675 676 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 677 678 hw->mac.ops.release_swfw_sync(hw, gssr); 679 680 return status; 681 } 682 683 /** 684 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 685 * without SWFW lock 686 * @hw: pointer to hardware structure 687 * @reg_addr: 32 bit PHY register to write 688 * @device_type: 5 bit device type 689 * @phy_data: Data to write to the PHY register 690 **/ 691 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 692 u32 device_type, u16 phy_data) 693 { 694 u32 i, command; 695 696 /* Put the data in the MDI single read and write data register*/ 697 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 698 699 /* Setup and write the address cycle command */ 700 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 701 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 702 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 703 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 704 705 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 706 707 /* 708 * Check every 10 usec to see if the address cycle completed. 709 * The MDI Command bit will clear when the operation is 710 * complete 711 */ 712 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 713 usec_delay(10); 714 715 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 716 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 717 break; 718 } 719 720 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 721 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 722 return IXGBE_ERR_PHY; 723 } 724 725 /* 726 * Address cycle complete, setup and write the write 727 * command 728 */ 729 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 730 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 731 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 732 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 733 734 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 735 736 /* 737 * Check every 10 usec to see if the address cycle 738 * completed. The MDI Command bit will clear when the 739 * operation is complete 740 */ 741 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 742 usec_delay(10); 743 744 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 745 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 746 break; 747 } 748 749 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 750 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 751 return IXGBE_ERR_PHY; 752 } 753 754 return IXGBE_SUCCESS; 755 } 756 757 /** 758 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 759 * using SWFW lock- this function is needed in most cases 760 * @hw: pointer to hardware structure 761 * @reg_addr: 32 bit PHY register to write 762 * @device_type: 5 bit device type 763 * @phy_data: Data to write to the PHY register 764 **/ 765 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 766 u32 device_type, u16 phy_data) 767 { 768 s32 status; 769 u32 gssr = hw->phy.phy_semaphore_mask; 770 771 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 772 773 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 774 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, 775 phy_data); 776 hw->mac.ops.release_swfw_sync(hw, gssr); 777 } else { 778 status = IXGBE_ERR_SWFW_SYNC; 779 } 780 781 return status; 782 } 783 784 /** 785 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 786 * @hw: pointer to hardware structure 787 * 788 * Restart auto-negotiation and PHY and waits for completion. 789 **/ 790 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 791 { 792 s32 status = IXGBE_SUCCESS; 793 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 794 bool autoneg = FALSE; 795 ixgbe_link_speed speed; 796 797 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 798 799 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 800 801 /* Set or unset auto-negotiation 10G advertisement */ 802 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 803 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 804 &autoneg_reg); 805 806 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 807 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) && 808 (speed & IXGBE_LINK_SPEED_10GB_FULL)) 809 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 810 811 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 812 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 813 autoneg_reg); 814 815 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 816 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 817 &autoneg_reg); 818 819 if (hw->mac.type == ixgbe_mac_X550) { 820 /* Set or unset auto-negotiation 5G advertisement */ 821 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 822 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) && 823 (speed & IXGBE_LINK_SPEED_5GB_FULL)) 824 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 825 826 /* Set or unset auto-negotiation 2.5G advertisement */ 827 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 828 if ((hw->phy.autoneg_advertised & 829 IXGBE_LINK_SPEED_2_5GB_FULL) && 830 (speed & IXGBE_LINK_SPEED_2_5GB_FULL)) 831 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 832 } 833 834 /* Set or unset auto-negotiation 1G advertisement */ 835 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 836 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) && 837 (speed & IXGBE_LINK_SPEED_1GB_FULL)) 838 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 839 840 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 841 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 842 autoneg_reg); 843 844 /* Set or unset auto-negotiation 100M advertisement */ 845 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 846 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 847 &autoneg_reg); 848 849 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 850 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 851 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) && 852 (speed & IXGBE_LINK_SPEED_100_FULL)) 853 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 854 855 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 856 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 857 autoneg_reg); 858 859 /* Blocked by MNG FW so don't reset PHY */ 860 if (ixgbe_check_reset_blocked(hw)) 861 return status; 862 863 /* Restart PHY auto-negotiation. */ 864 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 865 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 866 867 autoneg_reg |= IXGBE_MII_RESTART; 868 869 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 870 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 871 872 return status; 873 } 874 875 /** 876 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 877 * @hw: pointer to hardware structure 878 * @speed: new link speed 879 * @autoneg_wait_to_complete: unused 880 **/ 881 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 882 ixgbe_link_speed speed, 883 bool autoneg_wait_to_complete) 884 { 885 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 886 887 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 888 889 /* 890 * Clear autoneg_advertised and set new values based on input link 891 * speed. 892 */ 893 hw->phy.autoneg_advertised = 0; 894 895 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 896 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 897 898 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 899 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 900 901 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 902 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 903 904 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 905 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 906 907 if (speed & IXGBE_LINK_SPEED_100_FULL) 908 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 909 910 if (speed & IXGBE_LINK_SPEED_10_FULL) 911 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL; 912 913 /* Setup link based on the new speed settings */ 914 ixgbe_setup_phy_link(hw); 915 916 return IXGBE_SUCCESS; 917 } 918 919 /** 920 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 921 * @hw: pointer to hardware structure 922 * 923 * Determines the supported link capabilities by reading the PHY auto 924 * negotiation register. 925 **/ 926 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 927 { 928 s32 status; 929 u16 speed_ability; 930 931 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 932 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 933 &speed_ability); 934 if (status) 935 return status; 936 937 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 938 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 939 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 940 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 943 944 switch (hw->mac.type) { 945 case ixgbe_mac_X550: 946 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 947 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 948 break; 949 case ixgbe_mac_X550EM_x: 950 case ixgbe_mac_X550EM_a: 951 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 952 break; 953 default: 954 break; 955 } 956 957 return status; 958 } 959 960 /** 961 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 962 * @hw: pointer to hardware structure 963 * @speed: pointer to link speed 964 * @autoneg: boolean auto-negotiation value 965 **/ 966 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 967 ixgbe_link_speed *speed, 968 bool *autoneg) 969 { 970 s32 status = IXGBE_SUCCESS; 971 972 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 973 974 *autoneg = TRUE; 975 if (!hw->phy.speeds_supported) 976 status = ixgbe_get_copper_speeds_supported(hw); 977 978 *speed = hw->phy.speeds_supported; 979 return status; 980 } 981 982 /** 983 * ixgbe_check_phy_link_tnx - Determine link and speed status 984 * @hw: pointer to hardware structure 985 * @speed: current link speed 986 * @link_up: TRUE is link is up, FALSE otherwise 987 * 988 * Reads the VS1 register to determine if link is up and the current speed for 989 * the PHY. 990 **/ 991 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 992 bool *link_up) 993 { 994 s32 status = IXGBE_SUCCESS; 995 u32 time_out; 996 u32 max_time_out = 10; 997 u16 phy_link = 0; 998 u16 phy_speed = 0; 999 u16 phy_data = 0; 1000 1001 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1002 1003 /* Initialize speed and link to default case */ 1004 *link_up = FALSE; 1005 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1006 1007 /* 1008 * Check current speed and link status of the PHY register. 1009 * This is a vendor specific register and may have to 1010 * be changed for other copper PHYs. 1011 */ 1012 for (time_out = 0; time_out < max_time_out; time_out++) { 1013 usec_delay(10); 1014 status = hw->phy.ops.read_reg(hw, 1015 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1016 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1017 &phy_data); 1018 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1019 phy_speed = phy_data & 1020 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1021 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1022 *link_up = TRUE; 1023 if (phy_speed == 1024 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1025 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1026 break; 1027 } 1028 } 1029 1030 return status; 1031 } 1032 1033 /** 1034 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1035 * @hw: pointer to hardware structure 1036 * 1037 * Restart auto-negotiation and PHY and waits for completion. 1038 **/ 1039 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1040 { 1041 s32 status = IXGBE_SUCCESS; 1042 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1043 bool autoneg = FALSE; 1044 ixgbe_link_speed speed; 1045 1046 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1047 1048 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1049 1050 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1051 /* Set or unset auto-negotiation 10G advertisement */ 1052 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1053 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1054 &autoneg_reg); 1055 1056 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1057 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1058 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1059 1060 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1061 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1062 autoneg_reg); 1063 } 1064 1065 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1066 /* Set or unset auto-negotiation 1G advertisement */ 1067 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1068 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1069 &autoneg_reg); 1070 1071 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1072 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1073 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1074 1075 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1076 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1077 autoneg_reg); 1078 } 1079 1080 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1081 /* Set or unset auto-negotiation 100M advertisement */ 1082 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1083 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1084 &autoneg_reg); 1085 1086 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1087 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1088 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1089 1090 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1091 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1092 autoneg_reg); 1093 } 1094 1095 /* Blocked by MNG FW so don't reset PHY */ 1096 if (ixgbe_check_reset_blocked(hw)) 1097 return status; 1098 1099 /* Restart PHY auto-negotiation. */ 1100 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1101 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1102 1103 autoneg_reg |= IXGBE_MII_RESTART; 1104 1105 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1106 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1107 1108 return status; 1109 } 1110 1111 /** 1112 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1113 * @hw: pointer to hardware structure 1114 * @firmware_version: pointer to the PHY Firmware Version 1115 **/ 1116 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1117 u16 *firmware_version) 1118 { 1119 s32 status; 1120 1121 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1122 1123 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1124 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1125 firmware_version); 1126 1127 return status; 1128 } 1129 1130 /** 1131 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1132 * @hw: pointer to hardware structure 1133 * @firmware_version: pointer to the PHY Firmware Version 1134 **/ 1135 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1136 u16 *firmware_version) 1137 { 1138 s32 status; 1139 1140 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1141 1142 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1143 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1144 firmware_version); 1145 1146 return status; 1147 } 1148 1149 /** 1150 * ixgbe_reset_phy_nl - Performs a PHY reset 1151 * @hw: pointer to hardware structure 1152 **/ 1153 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1154 { 1155 u16 phy_offset, control, eword, edata, block_crc; 1156 bool end_data = FALSE; 1157 u16 list_offset, data_offset; 1158 u16 phy_data = 0; 1159 s32 ret_val = IXGBE_SUCCESS; 1160 u32 i; 1161 1162 DEBUGFUNC("ixgbe_reset_phy_nl"); 1163 1164 /* Blocked by MNG FW so bail */ 1165 if (ixgbe_check_reset_blocked(hw)) 1166 goto out; 1167 1168 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1169 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1170 1171 /* reset the PHY and poll for completion */ 1172 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1173 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1174 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1175 1176 for (i = 0; i < 100; i++) { 1177 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1178 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1179 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1180 break; 1181 msec_delay(10); 1182 } 1183 1184 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1185 DEBUGOUT("PHY reset did not complete.\n"); 1186 ret_val = IXGBE_ERR_PHY; 1187 goto out; 1188 } 1189 1190 /* Get init offsets */ 1191 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1192 &data_offset); 1193 if (ret_val != IXGBE_SUCCESS) 1194 goto out; 1195 1196 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1197 data_offset++; 1198 while (!end_data) { 1199 /* 1200 * Read control word from PHY init contents offset 1201 */ 1202 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1203 if (ret_val) 1204 goto err_eeprom; 1205 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1206 IXGBE_CONTROL_SHIFT_NL; 1207 edata = eword & IXGBE_DATA_MASK_NL; 1208 switch (control) { 1209 case IXGBE_DELAY_NL: 1210 data_offset++; 1211 DEBUGOUT1("DELAY: %d MS\n", edata); 1212 msec_delay(edata); 1213 break; 1214 case IXGBE_DATA_NL: 1215 DEBUGOUT("DATA:\n"); 1216 data_offset++; 1217 ret_val = hw->eeprom.ops.read(hw, data_offset, 1218 &phy_offset); 1219 if (ret_val) 1220 goto err_eeprom; 1221 data_offset++; 1222 for (i = 0; i < edata; i++) { 1223 ret_val = hw->eeprom.ops.read(hw, data_offset, 1224 &eword); 1225 if (ret_val) 1226 goto err_eeprom; 1227 hw->phy.ops.write_reg(hw, phy_offset, 1228 IXGBE_TWINAX_DEV, eword); 1229 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1230 phy_offset); 1231 data_offset++; 1232 phy_offset++; 1233 } 1234 break; 1235 case IXGBE_CONTROL_NL: 1236 data_offset++; 1237 DEBUGOUT("CONTROL:\n"); 1238 if (edata == IXGBE_CONTROL_EOL_NL) { 1239 DEBUGOUT("EOL\n"); 1240 end_data = TRUE; 1241 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1242 DEBUGOUT("SOL\n"); 1243 } else { 1244 DEBUGOUT("Bad control value\n"); 1245 ret_val = IXGBE_ERR_PHY; 1246 goto out; 1247 } 1248 break; 1249 default: 1250 DEBUGOUT("Bad control type\n"); 1251 ret_val = IXGBE_ERR_PHY; 1252 goto out; 1253 } 1254 } 1255 1256 out: 1257 return ret_val; 1258 1259 err_eeprom: 1260 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1261 "eeprom read at offset %d failed", data_offset); 1262 return IXGBE_ERR_PHY; 1263 } 1264 1265 /** 1266 * ixgbe_identify_module_generic - Identifies module type 1267 * @hw: pointer to hardware structure 1268 * 1269 * Determines HW type and calls appropriate function. 1270 **/ 1271 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1272 { 1273 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1274 1275 DEBUGFUNC("ixgbe_identify_module_generic"); 1276 1277 switch (hw->mac.ops.get_media_type(hw)) { 1278 case ixgbe_media_type_fiber: 1279 status = ixgbe_identify_sfp_module_generic(hw); 1280 break; 1281 1282 case ixgbe_media_type_fiber_qsfp: 1283 status = ixgbe_identify_qsfp_module_generic(hw); 1284 break; 1285 1286 default: 1287 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1288 status = IXGBE_ERR_SFP_NOT_PRESENT; 1289 break; 1290 } 1291 1292 return status; 1293 } 1294 1295 /** 1296 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1297 * @hw: pointer to hardware structure 1298 * 1299 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1300 **/ 1301 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1302 { 1303 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1304 u32 vendor_oui = 0; 1305 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1306 u8 identifier = 0; 1307 u8 comp_codes_1g = 0; 1308 u8 comp_codes_10g = 0; 1309 u8 oui_bytes[3] = {0, 0, 0}; 1310 u8 cable_tech = 0; 1311 u8 cable_spec = 0; 1312 u16 enforce_sfp = 0; 1313 1314 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1315 1316 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1317 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1318 status = IXGBE_ERR_SFP_NOT_PRESENT; 1319 goto out; 1320 } 1321 1322 /* LAN ID is needed for I2C access */ 1323 hw->mac.ops.set_lan_id(hw); 1324 1325 status = hw->phy.ops.read_i2c_eeprom(hw, 1326 IXGBE_SFF_IDENTIFIER, 1327 &identifier); 1328 1329 if (status != IXGBE_SUCCESS) 1330 goto err_read_i2c_eeprom; 1331 1332 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1333 hw->phy.type = ixgbe_phy_sfp_unsupported; 1334 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1335 } else { 1336 status = hw->phy.ops.read_i2c_eeprom(hw, 1337 IXGBE_SFF_1GBE_COMP_CODES, 1338 &comp_codes_1g); 1339 1340 if (status != IXGBE_SUCCESS) 1341 goto err_read_i2c_eeprom; 1342 1343 status = hw->phy.ops.read_i2c_eeprom(hw, 1344 IXGBE_SFF_10GBE_COMP_CODES, 1345 &comp_codes_10g); 1346 1347 if (status != IXGBE_SUCCESS) 1348 goto err_read_i2c_eeprom; 1349 status = hw->phy.ops.read_i2c_eeprom(hw, 1350 IXGBE_SFF_CABLE_TECHNOLOGY, 1351 &cable_tech); 1352 1353 if (status != IXGBE_SUCCESS) 1354 goto err_read_i2c_eeprom; 1355 1356 /* ID Module 1357 * ========= 1358 * 0 SFP_DA_CU 1359 * 1 SFP_SR 1360 * 2 SFP_LR 1361 * 3 SFP_DA_CORE0 - 82599-specific 1362 * 4 SFP_DA_CORE1 - 82599-specific 1363 * 5 SFP_SR/LR_CORE0 - 82599-specific 1364 * 6 SFP_SR/LR_CORE1 - 82599-specific 1365 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1366 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1367 * 9 SFP_1g_cu_CORE0 - 82599-specific 1368 * 10 SFP_1g_cu_CORE1 - 82599-specific 1369 * 11 SFP_1g_sx_CORE0 - 82599-specific 1370 * 12 SFP_1g_sx_CORE1 - 82599-specific 1371 */ 1372 if (hw->mac.type == ixgbe_mac_82598EB) { 1373 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1374 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1375 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1376 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1377 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1378 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1379 else 1380 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1381 } else { 1382 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1383 if (hw->bus.lan_id == 0) 1384 hw->phy.sfp_type = 1385 ixgbe_sfp_type_da_cu_core0; 1386 else 1387 hw->phy.sfp_type = 1388 ixgbe_sfp_type_da_cu_core1; 1389 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1390 hw->phy.ops.read_i2c_eeprom( 1391 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1392 &cable_spec); 1393 if (cable_spec & 1394 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1395 if (hw->bus.lan_id == 0) 1396 hw->phy.sfp_type = 1397 ixgbe_sfp_type_da_act_lmt_core0; 1398 else 1399 hw->phy.sfp_type = 1400 ixgbe_sfp_type_da_act_lmt_core1; 1401 } else { 1402 hw->phy.sfp_type = 1403 ixgbe_sfp_type_unknown; 1404 } 1405 } else if (comp_codes_10g & 1406 (IXGBE_SFF_10GBASESR_CAPABLE | 1407 IXGBE_SFF_10GBASELR_CAPABLE)) { 1408 if (hw->bus.lan_id == 0) 1409 hw->phy.sfp_type = 1410 ixgbe_sfp_type_srlr_core0; 1411 else 1412 hw->phy.sfp_type = 1413 ixgbe_sfp_type_srlr_core1; 1414 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1415 if (hw->bus.lan_id == 0) 1416 hw->phy.sfp_type = 1417 ixgbe_sfp_type_1g_cu_core0; 1418 else 1419 hw->phy.sfp_type = 1420 ixgbe_sfp_type_1g_cu_core1; 1421 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1422 if (hw->bus.lan_id == 0) 1423 hw->phy.sfp_type = 1424 ixgbe_sfp_type_1g_sx_core0; 1425 else 1426 hw->phy.sfp_type = 1427 ixgbe_sfp_type_1g_sx_core1; 1428 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1429 if (hw->bus.lan_id == 0) 1430 hw->phy.sfp_type = 1431 ixgbe_sfp_type_1g_lx_core0; 1432 else 1433 hw->phy.sfp_type = 1434 ixgbe_sfp_type_1g_lx_core1; 1435 } else { 1436 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1437 } 1438 } 1439 1440 if (hw->phy.sfp_type != stored_sfp_type) 1441 hw->phy.sfp_setup_needed = TRUE; 1442 1443 /* Determine if the SFP+ PHY is dual speed or not. */ 1444 hw->phy.multispeed_fiber = FALSE; 1445 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1446 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1447 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1448 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1449 hw->phy.multispeed_fiber = TRUE; 1450 1451 /* Determine PHY vendor */ 1452 if (hw->phy.type != ixgbe_phy_nl) { 1453 hw->phy.id = identifier; 1454 status = hw->phy.ops.read_i2c_eeprom(hw, 1455 IXGBE_SFF_VENDOR_OUI_BYTE0, 1456 &oui_bytes[0]); 1457 1458 if (status != IXGBE_SUCCESS) 1459 goto err_read_i2c_eeprom; 1460 1461 status = hw->phy.ops.read_i2c_eeprom(hw, 1462 IXGBE_SFF_VENDOR_OUI_BYTE1, 1463 &oui_bytes[1]); 1464 1465 if (status != IXGBE_SUCCESS) 1466 goto err_read_i2c_eeprom; 1467 1468 status = hw->phy.ops.read_i2c_eeprom(hw, 1469 IXGBE_SFF_VENDOR_OUI_BYTE2, 1470 &oui_bytes[2]); 1471 1472 if (status != IXGBE_SUCCESS) 1473 goto err_read_i2c_eeprom; 1474 1475 vendor_oui = 1476 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1477 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1478 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1479 1480 switch (vendor_oui) { 1481 case IXGBE_SFF_VENDOR_OUI_TYCO: 1482 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1483 hw->phy.type = 1484 ixgbe_phy_sfp_passive_tyco; 1485 break; 1486 case IXGBE_SFF_VENDOR_OUI_FTL: 1487 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1488 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1489 else 1490 hw->phy.type = ixgbe_phy_sfp_ftl; 1491 break; 1492 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1493 hw->phy.type = ixgbe_phy_sfp_avago; 1494 break; 1495 case IXGBE_SFF_VENDOR_OUI_INTEL: 1496 hw->phy.type = ixgbe_phy_sfp_intel; 1497 break; 1498 default: 1499 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1500 hw->phy.type = 1501 ixgbe_phy_sfp_passive_unknown; 1502 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1503 hw->phy.type = 1504 ixgbe_phy_sfp_active_unknown; 1505 else 1506 hw->phy.type = ixgbe_phy_sfp_unknown; 1507 break; 1508 } 1509 } 1510 1511 /* Allow any DA cable vendor */ 1512 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1513 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1514 status = IXGBE_SUCCESS; 1515 goto out; 1516 } 1517 1518 /* Verify supported 1G SFP modules */ 1519 if (comp_codes_10g == 0 && 1520 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1521 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1522 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1523 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1524 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1525 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1526 hw->phy.type = ixgbe_phy_sfp_unsupported; 1527 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1528 goto out; 1529 } 1530 1531 /* Anything else 82598-based is supported */ 1532 if (hw->mac.type == ixgbe_mac_82598EB) { 1533 status = IXGBE_SUCCESS; 1534 goto out; 1535 } 1536 1537 ixgbe_get_device_caps(hw, &enforce_sfp); 1538 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1539 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1540 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1541 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1543 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1544 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1545 /* Make sure we're a supported PHY type */ 1546 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1547 status = IXGBE_SUCCESS; 1548 } else { 1549 if (hw->allow_unsupported_sfp == TRUE) { 1550 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1551 status = IXGBE_SUCCESS; 1552 } else { 1553 DEBUGOUT("SFP+ module not supported\n"); 1554 hw->phy.type = 1555 ixgbe_phy_sfp_unsupported; 1556 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1557 } 1558 } 1559 } else { 1560 status = IXGBE_SUCCESS; 1561 } 1562 } 1563 1564 out: 1565 return status; 1566 1567 err_read_i2c_eeprom: 1568 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1569 if (hw->phy.type != ixgbe_phy_nl) { 1570 hw->phy.id = 0; 1571 hw->phy.type = ixgbe_phy_unknown; 1572 } 1573 return IXGBE_ERR_SFP_NOT_PRESENT; 1574 } 1575 1576 /** 1577 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1578 * @hw: pointer to hardware structure 1579 * 1580 * Determines physical layer capabilities of the current SFP. 1581 */ 1582 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1583 { 1584 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1585 u8 comp_codes_10g = 0; 1586 u8 comp_codes_1g = 0; 1587 1588 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1589 1590 hw->phy.ops.identify_sfp(hw); 1591 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1592 return physical_layer; 1593 1594 switch (hw->phy.type) { 1595 case ixgbe_phy_sfp_passive_tyco: 1596 case ixgbe_phy_sfp_passive_unknown: 1597 case ixgbe_phy_qsfp_passive_unknown: 1598 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1599 break; 1600 case ixgbe_phy_sfp_ftl_active: 1601 case ixgbe_phy_sfp_active_unknown: 1602 case ixgbe_phy_qsfp_active_unknown: 1603 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1604 break; 1605 case ixgbe_phy_sfp_avago: 1606 case ixgbe_phy_sfp_ftl: 1607 case ixgbe_phy_sfp_intel: 1608 case ixgbe_phy_sfp_unknown: 1609 hw->phy.ops.read_i2c_eeprom(hw, 1610 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1611 hw->phy.ops.read_i2c_eeprom(hw, 1612 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1613 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1614 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1615 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1616 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1617 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1618 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1619 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1620 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1621 break; 1622 case ixgbe_phy_qsfp_intel: 1623 case ixgbe_phy_qsfp_unknown: 1624 hw->phy.ops.read_i2c_eeprom(hw, 1625 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1626 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1627 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1628 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1629 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1630 break; 1631 default: 1632 break; 1633 } 1634 1635 return physical_layer; 1636 } 1637 1638 /** 1639 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1640 * @hw: pointer to hardware structure 1641 * 1642 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1643 **/ 1644 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1645 { 1646 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1647 u32 vendor_oui = 0; 1648 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1649 u8 identifier = 0; 1650 u8 comp_codes_1g = 0; 1651 u8 comp_codes_10g = 0; 1652 u8 oui_bytes[3] = {0, 0, 0}; 1653 u16 enforce_sfp = 0; 1654 u8 connector = 0; 1655 u8 cable_length = 0; 1656 u8 device_tech = 0; 1657 bool active_cable = FALSE; 1658 1659 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1660 1661 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1662 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1663 status = IXGBE_ERR_SFP_NOT_PRESENT; 1664 goto out; 1665 } 1666 1667 /* LAN ID is needed for I2C access */ 1668 hw->mac.ops.set_lan_id(hw); 1669 1670 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1671 &identifier); 1672 1673 if (status != IXGBE_SUCCESS) 1674 goto err_read_i2c_eeprom; 1675 1676 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1677 hw->phy.type = ixgbe_phy_sfp_unsupported; 1678 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1679 goto out; 1680 } 1681 1682 hw->phy.id = identifier; 1683 1684 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1685 &comp_codes_10g); 1686 1687 if (status != IXGBE_SUCCESS) 1688 goto err_read_i2c_eeprom; 1689 1690 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1691 &comp_codes_1g); 1692 1693 if (status != IXGBE_SUCCESS) 1694 goto err_read_i2c_eeprom; 1695 1696 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1697 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1698 if (hw->bus.lan_id == 0) 1699 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1700 else 1701 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1702 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1703 IXGBE_SFF_10GBASELR_CAPABLE)) { 1704 if (hw->bus.lan_id == 0) 1705 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1706 else 1707 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1708 } else { 1709 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1710 active_cable = TRUE; 1711 1712 if (!active_cable) { 1713 /* check for active DA cables that pre-date 1714 * SFF-8436 v3.6 */ 1715 hw->phy.ops.read_i2c_eeprom(hw, 1716 IXGBE_SFF_QSFP_CONNECTOR, 1717 &connector); 1718 1719 hw->phy.ops.read_i2c_eeprom(hw, 1720 IXGBE_SFF_QSFP_CABLE_LENGTH, 1721 &cable_length); 1722 1723 hw->phy.ops.read_i2c_eeprom(hw, 1724 IXGBE_SFF_QSFP_DEVICE_TECH, 1725 &device_tech); 1726 1727 if ((connector == 1728 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1729 (cable_length > 0) && 1730 ((device_tech >> 4) == 1731 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1732 active_cable = TRUE; 1733 } 1734 1735 if (active_cable) { 1736 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1737 if (hw->bus.lan_id == 0) 1738 hw->phy.sfp_type = 1739 ixgbe_sfp_type_da_act_lmt_core0; 1740 else 1741 hw->phy.sfp_type = 1742 ixgbe_sfp_type_da_act_lmt_core1; 1743 } else { 1744 /* unsupported module type */ 1745 hw->phy.type = ixgbe_phy_sfp_unsupported; 1746 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1747 goto out; 1748 } 1749 } 1750 1751 if (hw->phy.sfp_type != stored_sfp_type) 1752 hw->phy.sfp_setup_needed = TRUE; 1753 1754 /* Determine if the QSFP+ PHY is dual speed or not. */ 1755 hw->phy.multispeed_fiber = FALSE; 1756 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1757 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1758 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1759 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1760 hw->phy.multispeed_fiber = TRUE; 1761 1762 /* Determine PHY vendor for optical modules */ 1763 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1764 IXGBE_SFF_10GBASELR_CAPABLE)) { 1765 status = hw->phy.ops.read_i2c_eeprom(hw, 1766 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1767 &oui_bytes[0]); 1768 1769 if (status != IXGBE_SUCCESS) 1770 goto err_read_i2c_eeprom; 1771 1772 status = hw->phy.ops.read_i2c_eeprom(hw, 1773 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1774 &oui_bytes[1]); 1775 1776 if (status != IXGBE_SUCCESS) 1777 goto err_read_i2c_eeprom; 1778 1779 status = hw->phy.ops.read_i2c_eeprom(hw, 1780 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1781 &oui_bytes[2]); 1782 1783 if (status != IXGBE_SUCCESS) 1784 goto err_read_i2c_eeprom; 1785 1786 vendor_oui = 1787 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1788 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1789 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1790 1791 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1792 hw->phy.type = ixgbe_phy_qsfp_intel; 1793 else 1794 hw->phy.type = ixgbe_phy_qsfp_unknown; 1795 1796 ixgbe_get_device_caps(hw, &enforce_sfp); 1797 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1798 /* Make sure we're a supported PHY type */ 1799 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1800 status = IXGBE_SUCCESS; 1801 } else { 1802 if (hw->allow_unsupported_sfp == TRUE) { 1803 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n"); 1804 status = IXGBE_SUCCESS; 1805 } else { 1806 DEBUGOUT("QSFP module not supported\n"); 1807 hw->phy.type = 1808 ixgbe_phy_sfp_unsupported; 1809 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1810 } 1811 } 1812 } else { 1813 status = IXGBE_SUCCESS; 1814 } 1815 } 1816 1817 out: 1818 return status; 1819 1820 err_read_i2c_eeprom: 1821 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1822 hw->phy.id = 0; 1823 hw->phy.type = ixgbe_phy_unknown; 1824 1825 return IXGBE_ERR_SFP_NOT_PRESENT; 1826 } 1827 1828 /** 1829 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1830 * @hw: pointer to hardware structure 1831 * @list_offset: offset to the SFP ID list 1832 * @data_offset: offset to the SFP data block 1833 * 1834 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1835 * so it returns the offsets to the phy init sequence block. 1836 **/ 1837 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1838 u16 *list_offset, 1839 u16 *data_offset) 1840 { 1841 u16 sfp_id; 1842 u16 sfp_type = hw->phy.sfp_type; 1843 1844 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1845 1846 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1847 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1848 1849 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1850 return IXGBE_ERR_SFP_NOT_PRESENT; 1851 1852 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1853 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1854 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1855 1856 /* 1857 * Limiting active cables and 1G Phys must be initialized as 1858 * SR modules 1859 */ 1860 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1861 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1862 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1863 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1864 sfp_type = ixgbe_sfp_type_srlr_core0; 1865 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1866 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1867 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1868 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1869 sfp_type = ixgbe_sfp_type_srlr_core1; 1870 1871 /* Read offset to PHY init contents */ 1872 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1873 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1874 "eeprom read at offset %d failed", 1875 IXGBE_PHY_INIT_OFFSET_NL); 1876 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1877 } 1878 1879 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1880 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1881 1882 /* Shift offset to first ID word */ 1883 (*list_offset)++; 1884 1885 /* 1886 * Find the matching SFP ID in the EEPROM 1887 * and program the init sequence 1888 */ 1889 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1890 goto err_phy; 1891 1892 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1893 if (sfp_id == sfp_type) { 1894 (*list_offset)++; 1895 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1896 goto err_phy; 1897 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1898 DEBUGOUT("SFP+ module not supported\n"); 1899 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1900 } else { 1901 break; 1902 } 1903 } else { 1904 (*list_offset) += 2; 1905 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1906 goto err_phy; 1907 } 1908 } 1909 1910 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1911 DEBUGOUT("No matching SFP+ module found\n"); 1912 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1913 } 1914 1915 return IXGBE_SUCCESS; 1916 1917 err_phy: 1918 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1919 "eeprom read at offset %d failed", *list_offset); 1920 return IXGBE_ERR_PHY; 1921 } 1922 1923 /** 1924 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1925 * @hw: pointer to hardware structure 1926 * @byte_offset: EEPROM byte offset to read 1927 * @eeprom_data: value read 1928 * 1929 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1930 **/ 1931 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1932 u8 *eeprom_data) 1933 { 1934 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1935 1936 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1937 IXGBE_I2C_EEPROM_DEV_ADDR, 1938 eeprom_data); 1939 } 1940 1941 /** 1942 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 1943 * @hw: pointer to hardware structure 1944 * @byte_offset: byte offset at address 0xA2 1945 * @sff8472_data: value read 1946 * 1947 * Performs byte read operation to SFP module's SFF-8472 data over I2C 1948 **/ 1949 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 1950 u8 *sff8472_data) 1951 { 1952 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1953 IXGBE_I2C_EEPROM_DEV_ADDR2, 1954 sff8472_data); 1955 } 1956 1957 /** 1958 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 1959 * @hw: pointer to hardware structure 1960 * @byte_offset: EEPROM byte offset to write 1961 * @eeprom_data: value to write 1962 * 1963 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1964 **/ 1965 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1966 u8 eeprom_data) 1967 { 1968 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 1969 1970 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 1971 IXGBE_I2C_EEPROM_DEV_ADDR, 1972 eeprom_data); 1973 } 1974 1975 /** 1976 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 1977 * @hw: pointer to hardware structure 1978 * @offset: eeprom offset to be read 1979 * @addr: I2C address to be read 1980 */ 1981 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 1982 { 1983 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 1984 offset == IXGBE_SFF_IDENTIFIER && 1985 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1986 return TRUE; 1987 return FALSE; 1988 } 1989 1990 /** 1991 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 1992 * @hw: pointer to hardware structure 1993 * @byte_offset: byte offset to read 1994 * @dev_addr: address to read from 1995 * @data: value read 1996 * @lock: TRUE if to take and release semaphore 1997 * 1998 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1999 * a specified device address. 2000 **/ 2001 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2002 u8 dev_addr, u8 *data, bool lock) 2003 { 2004 s32 status; 2005 u32 max_retry = 10; 2006 u32 retry = 0; 2007 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2008 bool nack = 1; 2009 *data = 0; 2010 2011 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2012 2013 if (hw->mac.type >= ixgbe_mac_X550) 2014 max_retry = 3; 2015 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2016 max_retry = IXGBE_SFP_DETECT_RETRIES; 2017 2018 do { 2019 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2020 return IXGBE_ERR_SWFW_SYNC; 2021 2022 ixgbe_i2c_start(hw); 2023 2024 /* Device Address and write indication */ 2025 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2026 if (status != IXGBE_SUCCESS) 2027 goto fail; 2028 2029 status = ixgbe_get_i2c_ack(hw); 2030 if (status != IXGBE_SUCCESS) 2031 goto fail; 2032 2033 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2034 if (status != IXGBE_SUCCESS) 2035 goto fail; 2036 2037 status = ixgbe_get_i2c_ack(hw); 2038 if (status != IXGBE_SUCCESS) 2039 goto fail; 2040 2041 ixgbe_i2c_start(hw); 2042 2043 /* Device Address and read indication */ 2044 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2045 if (status != IXGBE_SUCCESS) 2046 goto fail; 2047 2048 status = ixgbe_get_i2c_ack(hw); 2049 if (status != IXGBE_SUCCESS) 2050 goto fail; 2051 2052 status = ixgbe_clock_in_i2c_byte(hw, data); 2053 if (status != IXGBE_SUCCESS) 2054 goto fail; 2055 2056 status = ixgbe_clock_out_i2c_bit(hw, nack); 2057 if (status != IXGBE_SUCCESS) 2058 goto fail; 2059 2060 ixgbe_i2c_stop(hw); 2061 if (lock) 2062 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2063 return IXGBE_SUCCESS; 2064 2065 fail: 2066 ixgbe_i2c_bus_clear(hw); 2067 if (lock) { 2068 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2069 msec_delay(100); 2070 } 2071 retry++; 2072 if (retry < max_retry) 2073 DEBUGOUT("I2C byte read error - Retrying.\n"); 2074 else 2075 DEBUGOUT("I2C byte read error.\n"); 2076 2077 } while (retry < max_retry); 2078 2079 return status; 2080 } 2081 2082 /** 2083 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2084 * @hw: pointer to hardware structure 2085 * @byte_offset: byte offset to read 2086 * @dev_addr: address to read from 2087 * @data: value read 2088 * 2089 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2090 * a specified device address. 2091 **/ 2092 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2093 u8 dev_addr, u8 *data) 2094 { 2095 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2096 data, TRUE); 2097 } 2098 2099 /** 2100 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2101 * @hw: pointer to hardware structure 2102 * @byte_offset: byte offset to read 2103 * @dev_addr: address to read from 2104 * @data: value read 2105 * 2106 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2107 * a specified device address. 2108 **/ 2109 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2110 u8 dev_addr, u8 *data) 2111 { 2112 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2113 data, FALSE); 2114 } 2115 2116 /** 2117 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2118 * @hw: pointer to hardware structure 2119 * @byte_offset: byte offset to write 2120 * @dev_addr: address to write to 2121 * @data: value to write 2122 * @lock: TRUE if to take and release semaphore 2123 * 2124 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2125 * a specified device address. 2126 **/ 2127 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2128 u8 dev_addr, u8 data, bool lock) 2129 { 2130 s32 status; 2131 u32 max_retry = 1; 2132 u32 retry = 0; 2133 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2134 2135 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2136 2137 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2138 IXGBE_SUCCESS) 2139 return IXGBE_ERR_SWFW_SYNC; 2140 2141 do { 2142 ixgbe_i2c_start(hw); 2143 2144 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2145 if (status != IXGBE_SUCCESS) 2146 goto fail; 2147 2148 status = ixgbe_get_i2c_ack(hw); 2149 if (status != IXGBE_SUCCESS) 2150 goto fail; 2151 2152 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2153 if (status != IXGBE_SUCCESS) 2154 goto fail; 2155 2156 status = ixgbe_get_i2c_ack(hw); 2157 if (status != IXGBE_SUCCESS) 2158 goto fail; 2159 2160 status = ixgbe_clock_out_i2c_byte(hw, data); 2161 if (status != IXGBE_SUCCESS) 2162 goto fail; 2163 2164 status = ixgbe_get_i2c_ack(hw); 2165 if (status != IXGBE_SUCCESS) 2166 goto fail; 2167 2168 ixgbe_i2c_stop(hw); 2169 if (lock) 2170 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2171 return IXGBE_SUCCESS; 2172 2173 fail: 2174 ixgbe_i2c_bus_clear(hw); 2175 retry++; 2176 if (retry < max_retry) 2177 DEBUGOUT("I2C byte write error - Retrying.\n"); 2178 else 2179 DEBUGOUT("I2C byte write error.\n"); 2180 } while (retry < max_retry); 2181 2182 if (lock) 2183 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2184 2185 return status; 2186 } 2187 2188 /** 2189 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2190 * @hw: pointer to hardware structure 2191 * @byte_offset: byte offset to write 2192 * @dev_addr: address to write to 2193 * @data: value to write 2194 * 2195 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2196 * a specified device address. 2197 **/ 2198 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2199 u8 dev_addr, u8 data) 2200 { 2201 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2202 data, TRUE); 2203 } 2204 2205 /** 2206 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2207 * @hw: pointer to hardware structure 2208 * @byte_offset: byte offset to write 2209 * @dev_addr: address to write to 2210 * @data: value to write 2211 * 2212 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2213 * a specified device address. 2214 **/ 2215 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2216 u8 dev_addr, u8 data) 2217 { 2218 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2219 data, FALSE); 2220 } 2221 2222 /** 2223 * ixgbe_i2c_start - Sets I2C start condition 2224 * @hw: pointer to hardware structure 2225 * 2226 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2227 * Set bit-bang mode on X550 hardware. 2228 **/ 2229 static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2230 { 2231 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2232 2233 DEBUGFUNC("ixgbe_i2c_start"); 2234 2235 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2236 2237 /* Start condition must begin with data and clock high */ 2238 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2239 ixgbe_raise_i2c_clk(hw, &i2cctl); 2240 2241 /* Setup time for start condition (4.7us) */ 2242 usec_delay(IXGBE_I2C_T_SU_STA); 2243 2244 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2245 2246 /* Hold time for start condition (4us) */ 2247 usec_delay(IXGBE_I2C_T_HD_STA); 2248 2249 ixgbe_lower_i2c_clk(hw, &i2cctl); 2250 2251 /* Minimum low period of clock is 4.7 us */ 2252 usec_delay(IXGBE_I2C_T_LOW); 2253 2254 } 2255 2256 /** 2257 * ixgbe_i2c_stop - Sets I2C stop condition 2258 * @hw: pointer to hardware structure 2259 * 2260 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2261 * Disables bit-bang mode and negates data output enable on X550 2262 * hardware. 2263 **/ 2264 static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2265 { 2266 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2267 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2268 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2269 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2270 2271 DEBUGFUNC("ixgbe_i2c_stop"); 2272 2273 /* Stop condition must begin with data low and clock high */ 2274 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2275 ixgbe_raise_i2c_clk(hw, &i2cctl); 2276 2277 /* Setup time for stop condition (4us) */ 2278 usec_delay(IXGBE_I2C_T_SU_STO); 2279 2280 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2281 2282 /* bus free time between stop and start (4.7us)*/ 2283 usec_delay(IXGBE_I2C_T_BUF); 2284 2285 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2286 i2cctl &= ~bb_en_bit; 2287 i2cctl |= data_oe_bit | clk_oe_bit; 2288 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2289 IXGBE_WRITE_FLUSH(hw); 2290 } 2291 } 2292 2293 /** 2294 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2295 * @hw: pointer to hardware structure 2296 * @data: data byte to clock in 2297 * 2298 * Clocks in one byte data via I2C data/clock 2299 **/ 2300 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2301 { 2302 s32 i; 2303 bool bit = 0; 2304 2305 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2306 2307 *data = 0; 2308 for (i = 7; i >= 0; i--) { 2309 ixgbe_clock_in_i2c_bit(hw, &bit); 2310 *data |= bit << i; 2311 } 2312 2313 return IXGBE_SUCCESS; 2314 } 2315 2316 /** 2317 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2318 * @hw: pointer to hardware structure 2319 * @data: data byte clocked out 2320 * 2321 * Clocks out one byte data via I2C data/clock 2322 **/ 2323 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2324 { 2325 s32 status = IXGBE_SUCCESS; 2326 s32 i; 2327 u32 i2cctl; 2328 bool bit; 2329 2330 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2331 2332 for (i = 7; i >= 0; i--) { 2333 bit = (data >> i) & 0x1; 2334 status = ixgbe_clock_out_i2c_bit(hw, bit); 2335 2336 if (status != IXGBE_SUCCESS) 2337 break; 2338 } 2339 2340 /* Release SDA line (set high) */ 2341 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2342 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2343 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2344 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2345 IXGBE_WRITE_FLUSH(hw); 2346 2347 return status; 2348 } 2349 2350 /** 2351 * ixgbe_get_i2c_ack - Polls for I2C ACK 2352 * @hw: pointer to hardware structure 2353 * 2354 * Clocks in/out one bit via I2C data/clock 2355 **/ 2356 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2357 { 2358 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2359 s32 status = IXGBE_SUCCESS; 2360 u32 i = 0; 2361 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2362 u32 timeout = 10; 2363 bool ack = 1; 2364 2365 DEBUGFUNC("ixgbe_get_i2c_ack"); 2366 2367 if (data_oe_bit) { 2368 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2369 i2cctl |= data_oe_bit; 2370 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2371 IXGBE_WRITE_FLUSH(hw); 2372 } 2373 ixgbe_raise_i2c_clk(hw, &i2cctl); 2374 2375 /* Minimum high period of clock is 4us */ 2376 usec_delay(IXGBE_I2C_T_HIGH); 2377 2378 /* Poll for ACK. Note that ACK in I2C spec is 2379 * transition from 1 to 0 */ 2380 for (i = 0; i < timeout; i++) { 2381 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2382 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2383 2384 usec_delay(1); 2385 if (!ack) 2386 break; 2387 } 2388 2389 if (ack) { 2390 DEBUGOUT("I2C ack was not received.\n"); 2391 status = IXGBE_ERR_I2C; 2392 } 2393 2394 ixgbe_lower_i2c_clk(hw, &i2cctl); 2395 2396 /* Minimum low period of clock is 4.7 us */ 2397 usec_delay(IXGBE_I2C_T_LOW); 2398 2399 return status; 2400 } 2401 2402 /** 2403 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2404 * @hw: pointer to hardware structure 2405 * @data: read data value 2406 * 2407 * Clocks in one bit via I2C data/clock 2408 **/ 2409 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2410 { 2411 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2412 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2413 2414 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2415 2416 if (data_oe_bit) { 2417 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2418 i2cctl |= data_oe_bit; 2419 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2420 IXGBE_WRITE_FLUSH(hw); 2421 } 2422 ixgbe_raise_i2c_clk(hw, &i2cctl); 2423 2424 /* Minimum high period of clock is 4us */ 2425 usec_delay(IXGBE_I2C_T_HIGH); 2426 2427 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2428 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2429 2430 ixgbe_lower_i2c_clk(hw, &i2cctl); 2431 2432 /* Minimum low period of clock is 4.7 us */ 2433 usec_delay(IXGBE_I2C_T_LOW); 2434 2435 return IXGBE_SUCCESS; 2436 } 2437 2438 /** 2439 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2440 * @hw: pointer to hardware structure 2441 * @data: data value to write 2442 * 2443 * Clocks out one bit via I2C data/clock 2444 **/ 2445 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2446 { 2447 s32 status; 2448 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2449 2450 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2451 2452 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2453 if (status == IXGBE_SUCCESS) { 2454 ixgbe_raise_i2c_clk(hw, &i2cctl); 2455 2456 /* Minimum high period of clock is 4us */ 2457 usec_delay(IXGBE_I2C_T_HIGH); 2458 2459 ixgbe_lower_i2c_clk(hw, &i2cctl); 2460 2461 /* Minimum low period of clock is 4.7 us. 2462 * This also takes care of the data hold time. 2463 */ 2464 usec_delay(IXGBE_I2C_T_LOW); 2465 } else { 2466 status = IXGBE_ERR_I2C; 2467 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2468 "I2C data was not set to %X\n", data); 2469 } 2470 2471 return status; 2472 } 2473 2474 /** 2475 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2476 * @hw: pointer to hardware structure 2477 * @i2cctl: Current value of I2CCTL register 2478 * 2479 * Raises the I2C clock line '0'->'1' 2480 * Negates the I2C clock output enable on X550 hardware. 2481 **/ 2482 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2483 { 2484 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2485 u32 i = 0; 2486 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2487 u32 i2cctl_r = 0; 2488 2489 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2490 2491 if (clk_oe_bit) { 2492 *i2cctl |= clk_oe_bit; 2493 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2494 } 2495 2496 for (i = 0; i < timeout; i++) { 2497 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2498 2499 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2500 IXGBE_WRITE_FLUSH(hw); 2501 /* SCL rise time (1000ns) */ 2502 usec_delay(IXGBE_I2C_T_RISE); 2503 2504 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2505 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2506 break; 2507 } 2508 } 2509 2510 /** 2511 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2512 * @hw: pointer to hardware structure 2513 * @i2cctl: Current value of I2CCTL register 2514 * 2515 * Lowers the I2C clock line '1'->'0' 2516 * Asserts the I2C clock output enable on X550 hardware. 2517 **/ 2518 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2519 { 2520 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2521 2522 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2523 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2524 2525 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2526 IXGBE_WRITE_FLUSH(hw); 2527 2528 /* SCL fall time (300ns) */ 2529 usec_delay(IXGBE_I2C_T_FALL); 2530 } 2531 2532 /** 2533 * ixgbe_set_i2c_data - Sets the I2C data bit 2534 * @hw: pointer to hardware structure 2535 * @i2cctl: Current value of I2CCTL register 2536 * @data: I2C data value (0 or 1) to set 2537 * 2538 * Sets the I2C data bit 2539 * Asserts the I2C data output enable on X550 hardware. 2540 **/ 2541 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2542 { 2543 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2544 s32 status = IXGBE_SUCCESS; 2545 2546 DEBUGFUNC("ixgbe_set_i2c_data"); 2547 2548 if (data) 2549 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2550 else 2551 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2552 *i2cctl &= ~data_oe_bit; 2553 2554 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2555 IXGBE_WRITE_FLUSH(hw); 2556 2557 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2558 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2559 2560 if (!data) /* Can't verify data in this case */ 2561 return IXGBE_SUCCESS; 2562 if (data_oe_bit) { 2563 *i2cctl |= data_oe_bit; 2564 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2565 IXGBE_WRITE_FLUSH(hw); 2566 } 2567 2568 /* Verify data was set correctly */ 2569 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2570 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2571 status = IXGBE_ERR_I2C; 2572 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2573 "Error - I2C data was not set to %X.\n", 2574 data); 2575 } 2576 2577 return status; 2578 } 2579 2580 /** 2581 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2582 * @hw: pointer to hardware structure 2583 * @i2cctl: Current value of I2CCTL register 2584 * 2585 * Returns the I2C data bit value 2586 * Negates the I2C data output enable on X550 hardware. 2587 **/ 2588 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2589 { 2590 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2591 bool data; 2592 2593 DEBUGFUNC("ixgbe_get_i2c_data"); 2594 2595 if (data_oe_bit) { 2596 *i2cctl |= data_oe_bit; 2597 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2598 IXGBE_WRITE_FLUSH(hw); 2599 usec_delay(IXGBE_I2C_T_FALL); 2600 } 2601 2602 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2603 data = 1; 2604 else 2605 data = 0; 2606 2607 return data; 2608 } 2609 2610 /** 2611 * ixgbe_i2c_bus_clear - Clears the I2C bus 2612 * @hw: pointer to hardware structure 2613 * 2614 * Clears the I2C bus by sending nine clock pulses. 2615 * Used when data line is stuck low. 2616 **/ 2617 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2618 { 2619 u32 i2cctl; 2620 u32 i; 2621 2622 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2623 2624 ixgbe_i2c_start(hw); 2625 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2626 2627 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2628 2629 for (i = 0; i < 9; i++) { 2630 ixgbe_raise_i2c_clk(hw, &i2cctl); 2631 2632 /* Min high period of clock is 4us */ 2633 usec_delay(IXGBE_I2C_T_HIGH); 2634 2635 ixgbe_lower_i2c_clk(hw, &i2cctl); 2636 2637 /* Min low period of clock is 4.7us*/ 2638 usec_delay(IXGBE_I2C_T_LOW); 2639 } 2640 2641 ixgbe_i2c_start(hw); 2642 2643 /* Put the i2c bus back to default state */ 2644 ixgbe_i2c_stop(hw); 2645 } 2646 2647 /** 2648 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2649 * @hw: pointer to hardware structure 2650 * 2651 * Checks if the LASI temp alarm status was triggered due to overtemp 2652 **/ 2653 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2654 { 2655 s32 status = IXGBE_SUCCESS; 2656 u16 phy_data = 0; 2657 2658 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2659 2660 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2661 goto out; 2662 2663 /* Check that the LASI temp alarm status was triggered */ 2664 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2665 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2666 2667 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2668 goto out; 2669 2670 status = IXGBE_ERR_OVERTEMP; 2671 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2672 out: 2673 return status; 2674 } 2675 2676 /** 2677 * ixgbe_set_copper_phy_power - Control power for copper phy 2678 * @hw: pointer to hardware structure 2679 * @on: TRUE for on, FALSE for off 2680 */ 2681 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2682 { 2683 u32 status; 2684 u16 reg; 2685 2686 if (!on && ixgbe_mng_present(hw)) 2687 return 0; 2688 2689 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2690 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2691 ®); 2692 if (status) 2693 return status; 2694 2695 if (on) { 2696 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2697 } else { 2698 if (ixgbe_check_reset_blocked(hw)) 2699 return 0; 2700 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2701 } 2702 2703 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2704 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2705 reg); 2706 return status; 2707 } 2708