1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $ 28 */ 29 30 #include "opt_ifpoll.h" 31 #include "opt_jme.h" 32 33 #include <sys/param.h> 34 #include <sys/endian.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/interrupt.h> 38 #include <sys/malloc.h> 39 #include <sys/proc.h> 40 #include <sys/rman.h> 41 #include <sys/serialize.h> 42 #include <sys/serialize2.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 47 #include <net/ethernet.h> 48 #include <net/if.h> 49 #include <net/bpf.h> 50 #include <net/if_arp.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_poll.h> 54 #include <net/ifq_var.h> 55 #include <net/toeplitz.h> 56 #include <net/toeplitz2.h> 57 #include <net/vlan/if_vlan_var.h> 58 #include <net/vlan/if_vlan_ether.h> 59 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/netif/mii_layer/mii.h> 64 #include <dev/netif/mii_layer/miivar.h> 65 #include <dev/netif/mii_layer/jmphyreg.h> 66 67 #include <bus/pci/pcireg.h> 68 #include <bus/pci/pcivar.h> 69 #include "pcidevs.h" 70 71 #include <dev/netif/jme/if_jmereg.h> 72 #include <dev/netif/jme/if_jmevar.h> 73 74 #include "miibus_if.h" 75 76 #define JME_TICK_CPUID 0 /* DO NOT CHANGE THIS */ 77 78 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 79 80 #ifdef JME_RSS_DEBUG 81 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \ 82 do { \ 83 if ((sc)->jme_rss_debug >= (lvl)) \ 84 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \ 85 } while (0) 86 #else /* !JME_RSS_DEBUG */ 87 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0) 88 #endif /* JME_RSS_DEBUG */ 89 90 static int jme_probe(device_t); 91 static int jme_attach(device_t); 92 static int jme_detach(device_t); 93 static int jme_shutdown(device_t); 94 static int jme_suspend(device_t); 95 static int jme_resume(device_t); 96 97 static int jme_miibus_readreg(device_t, int, int); 98 static int jme_miibus_writereg(device_t, int, int, int); 99 static void jme_miibus_statchg(device_t); 100 101 static void jme_init(void *); 102 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 103 static void jme_start(struct ifnet *, struct ifaltq_subque *); 104 static void jme_watchdog(struct ifnet *); 105 static void jme_mediastatus(struct ifnet *, struct ifmediareq *); 106 static int jme_mediachange(struct ifnet *); 107 #ifdef IFPOLL_ENABLE 108 static void jme_npoll(struct ifnet *, struct ifpoll_info *); 109 static void jme_npoll_status(struct ifnet *); 110 static void jme_npoll_rx(struct ifnet *, void *, int); 111 static void jme_npoll_tx(struct ifnet *, void *, int); 112 #endif 113 static void jme_serialize(struct ifnet *, enum ifnet_serialize); 114 static void jme_deserialize(struct ifnet *, enum ifnet_serialize); 115 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize); 116 #ifdef INVARIANTS 117 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize, 118 boolean_t); 119 #endif 120 121 static void jme_intr(void *); 122 static void jme_msix_tx(void *); 123 static void jme_msix_rx(void *); 124 static void jme_msix_status(void *); 125 static void jme_txeof(struct jme_txdata *); 126 static void jme_rxeof(struct jme_rxdata *, int, int); 127 static void jme_rx_intr(struct jme_softc *, uint32_t); 128 static void jme_enable_intr(struct jme_softc *); 129 static void jme_disable_intr(struct jme_softc *); 130 static void jme_rx_restart(struct jme_softc *, uint32_t); 131 132 static int jme_msix_setup(device_t); 133 static void jme_msix_teardown(device_t, int); 134 static int jme_intr_setup(device_t); 135 static void jme_intr_teardown(device_t); 136 static void jme_msix_try_alloc(device_t); 137 static void jme_msix_free(device_t); 138 static int jme_intr_alloc(device_t); 139 static void jme_intr_free(device_t); 140 static int jme_dma_alloc(struct jme_softc *); 141 static void jme_dma_free(struct jme_softc *); 142 static int jme_init_rx_ring(struct jme_rxdata *); 143 static void jme_init_tx_ring(struct jme_txdata *); 144 static void jme_init_ssb(struct jme_softc *); 145 static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int); 146 static int jme_encap(struct jme_txdata *, struct mbuf **, int *); 147 static void jme_rxpkt(struct jme_rxdata *, int); 148 static int jme_rxring_dma_alloc(struct jme_rxdata *); 149 static int jme_rxbuf_dma_alloc(struct jme_rxdata *); 150 static int jme_rxbuf_dma_filter(void *, bus_addr_t); 151 152 static void jme_tick(void *); 153 static void jme_stop(struct jme_softc *); 154 static void jme_reset(struct jme_softc *); 155 static void jme_set_msinum(struct jme_softc *); 156 static void jme_set_vlan(struct jme_softc *); 157 static void jme_set_filter(struct jme_softc *); 158 static void jme_stop_tx(struct jme_softc *); 159 static void jme_stop_rx(struct jme_softc *); 160 static void jme_mac_config(struct jme_softc *); 161 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]); 162 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]); 163 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 164 #ifdef notyet 165 static void jme_setwol(struct jme_softc *); 166 static void jme_setlinkspeed(struct jme_softc *); 167 #endif 168 static void jme_set_tx_coal(struct jme_softc *); 169 static void jme_set_rx_coal(struct jme_softc *); 170 static void jme_enable_rss(struct jme_softc *); 171 static void jme_disable_rss(struct jme_softc *); 172 static void jme_serialize_skipmain(struct jme_softc *); 173 static void jme_deserialize_skipmain(struct jme_softc *); 174 static void jme_phy_poweron(struct jme_softc *); 175 static void jme_phy_poweroff(struct jme_softc *); 176 static int jme_miiext_read(struct jme_softc *, int); 177 static void jme_miiext_write(struct jme_softc *, int, int); 178 static void jme_phy_init(struct jme_softc *); 179 180 static void jme_sysctl_node(struct jme_softc *); 181 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS); 182 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 183 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS); 184 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 185 #ifdef IFPOLL_ENABLE 186 static int jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS); 187 static int jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS); 188 #endif 189 190 /* 191 * Devices supported by this driver. 192 */ 193 static const struct jme_dev { 194 uint16_t jme_vendorid; 195 uint16_t jme_deviceid; 196 uint32_t jme_caps; 197 const char *jme_name; 198 } jme_devs[] = { 199 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250, 200 JME_CAP_JUMBO, 201 "JMicron Inc, JMC250 Gigabit Ethernet" }, 202 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260, 203 JME_CAP_FASTETH, 204 "JMicron Inc, JMC260 Fast Ethernet" }, 205 { 0, 0, 0, NULL } 206 }; 207 208 static device_method_t jme_methods[] = { 209 /* Device interface. */ 210 DEVMETHOD(device_probe, jme_probe), 211 DEVMETHOD(device_attach, jme_attach), 212 DEVMETHOD(device_detach, jme_detach), 213 DEVMETHOD(device_shutdown, jme_shutdown), 214 DEVMETHOD(device_suspend, jme_suspend), 215 DEVMETHOD(device_resume, jme_resume), 216 217 /* Bus interface. */ 218 DEVMETHOD(bus_print_child, bus_generic_print_child), 219 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 220 221 /* MII interface. */ 222 DEVMETHOD(miibus_readreg, jme_miibus_readreg), 223 DEVMETHOD(miibus_writereg, jme_miibus_writereg), 224 DEVMETHOD(miibus_statchg, jme_miibus_statchg), 225 226 { NULL, NULL } 227 }; 228 229 static driver_t jme_driver = { 230 "jme", 231 jme_methods, 232 sizeof(struct jme_softc) 233 }; 234 235 static devclass_t jme_devclass; 236 237 DECLARE_DUMMY_MODULE(if_jme); 238 MODULE_DEPEND(if_jme, miibus, 1, 1, 1); 239 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL); 240 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL); 241 242 static const struct { 243 uint32_t jme_coal; 244 uint32_t jme_comp; 245 uint32_t jme_empty; 246 } jme_rx_status[JME_NRXRING_MAX] = { 247 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP, 248 INTR_RXQ0_DESC_EMPTY }, 249 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP, 250 INTR_RXQ1_DESC_EMPTY }, 251 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP, 252 INTR_RXQ2_DESC_EMPTY }, 253 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP, 254 INTR_RXQ3_DESC_EMPTY } 255 }; 256 257 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF; 258 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF; 259 static int jme_rx_ring_count = 0; 260 static int jme_msi_enable = 1; 261 static int jme_msix_enable = 1; 262 263 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count); 264 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count); 265 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count); 266 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable); 267 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable); 268 269 static __inline void 270 jme_setup_rxdesc(struct jme_rxdesc *rxd) 271 { 272 struct jme_desc *desc; 273 274 desc = rxd->rx_desc; 275 desc->buflen = htole32(MCLBYTES); 276 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr)); 277 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr)); 278 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 279 } 280 281 /* 282 * Read a PHY register on the MII of the JMC250. 283 */ 284 static int 285 jme_miibus_readreg(device_t dev, int phy, int reg) 286 { 287 struct jme_softc *sc = device_get_softc(dev); 288 uint32_t val; 289 int i; 290 291 /* For FPGA version, PHY address 0 should be ignored. */ 292 if (sc->jme_caps & JME_CAP_FPGA) { 293 if (phy == 0) 294 return (0); 295 } else { 296 if (sc->jme_phyaddr != phy) 297 return (0); 298 } 299 300 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 301 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 302 303 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 304 DELAY(1); 305 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 306 break; 307 } 308 if (i == 0) { 309 device_printf(sc->jme_dev, "phy read timeout: " 310 "phy %d, reg %d\n", phy, reg); 311 return (0); 312 } 313 314 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 315 } 316 317 /* 318 * Write a PHY register on the MII of the JMC250. 319 */ 320 static int 321 jme_miibus_writereg(device_t dev, int phy, int reg, int val) 322 { 323 struct jme_softc *sc = device_get_softc(dev); 324 int i; 325 326 /* For FPGA version, PHY address 0 should be ignored. */ 327 if (sc->jme_caps & JME_CAP_FPGA) { 328 if (phy == 0) 329 return (0); 330 } else { 331 if (sc->jme_phyaddr != phy) 332 return (0); 333 } 334 335 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 336 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 337 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 338 339 for (i = JME_PHY_TIMEOUT; i > 0; i--) { 340 DELAY(1); 341 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 342 break; 343 } 344 if (i == 0) { 345 device_printf(sc->jme_dev, "phy write timeout: " 346 "phy %d, reg %d\n", phy, reg); 347 } 348 349 return (0); 350 } 351 352 /* 353 * Callback from MII layer when media changes. 354 */ 355 static void 356 jme_miibus_statchg(device_t dev) 357 { 358 struct jme_softc *sc = device_get_softc(dev); 359 struct ifnet *ifp = &sc->arpcom.ac_if; 360 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 361 struct mii_data *mii; 362 struct jme_txdesc *txd; 363 bus_addr_t paddr; 364 int i, r; 365 366 if (sc->jme_in_tick) 367 jme_serialize_skipmain(sc); 368 ASSERT_IFNET_SERIALIZED_ALL(ifp); 369 370 if ((ifp->if_flags & IFF_RUNNING) == 0) 371 goto done; 372 373 mii = device_get_softc(sc->jme_miibus); 374 375 sc->jme_has_link = FALSE; 376 if ((mii->mii_media_status & IFM_AVALID) != 0) { 377 switch (IFM_SUBTYPE(mii->mii_media_active)) { 378 case IFM_10_T: 379 case IFM_100_TX: 380 sc->jme_has_link = TRUE; 381 break; 382 case IFM_1000_T: 383 if (sc->jme_caps & JME_CAP_FASTETH) 384 break; 385 sc->jme_has_link = TRUE; 386 break; 387 default: 388 break; 389 } 390 } 391 392 /* 393 * Disabling Rx/Tx MACs have a side-effect of resetting 394 * JME_TXNDA/JME_RXNDA register to the first address of 395 * Tx/Rx descriptor address. So driver should reset its 396 * internal procucer/consumer pointer and reclaim any 397 * allocated resources. Note, just saving the value of 398 * JME_TXNDA and JME_RXNDA registers before stopping MAC 399 * and restoring JME_TXNDA/JME_RXNDA register is not 400 * sufficient to make sure correct MAC state because 401 * stopping MAC operation can take a while and hardware 402 * might have updated JME_TXNDA/JME_RXNDA registers 403 * during the stop operation. 404 */ 405 406 /* Disable interrupts */ 407 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 408 409 /* Stop driver */ 410 ifp->if_flags &= ~IFF_RUNNING; 411 ifq_clr_oactive(&ifp->if_snd); 412 ifp->if_timer = 0; 413 callout_stop(&sc->jme_tick_ch); 414 415 /* Stop receiver/transmitter. */ 416 jme_stop_rx(sc); 417 jme_stop_tx(sc); 418 419 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 420 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 421 422 jme_rxeof(rdata, -1, -1); 423 if (rdata->jme_rxhead != NULL) 424 m_freem(rdata->jme_rxhead); 425 JME_RXCHAIN_RESET(rdata); 426 427 /* 428 * Reuse configured Rx descriptors and reset 429 * procuder/consumer index. 430 */ 431 rdata->jme_rx_cons = 0; 432 } 433 if (JME_ENABLE_HWRSS(sc)) 434 jme_enable_rss(sc); 435 else 436 jme_disable_rss(sc); 437 438 jme_txeof(tdata); 439 if (tdata->jme_tx_cnt != 0) { 440 /* Remove queued packets for transmit. */ 441 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 442 txd = &tdata->jme_txdesc[i]; 443 if (txd->tx_m != NULL) { 444 bus_dmamap_unload( tdata->jme_tx_tag, 445 txd->tx_dmamap); 446 m_freem(txd->tx_m); 447 txd->tx_m = NULL; 448 txd->tx_ndesc = 0; 449 IFNET_STAT_INC(ifp, oerrors, 1); 450 } 451 } 452 } 453 jme_init_tx_ring(tdata); 454 455 /* Initialize shadow status block. */ 456 jme_init_ssb(sc); 457 458 /* Program MAC with resolved speed/duplex/flow-control. */ 459 if (sc->jme_has_link) { 460 jme_mac_config(sc); 461 462 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 463 464 /* Set Tx ring address to the hardware. */ 465 paddr = tdata->jme_tx_ring_paddr; 466 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 467 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 468 469 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 470 CSR_WRITE_4(sc, JME_RXCSR, 471 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r)); 472 473 /* Set Rx ring address to the hardware. */ 474 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr; 475 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 476 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 477 } 478 479 /* Restart receiver/transmitter. */ 480 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 481 RXCSR_RXQ_START); 482 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 483 } 484 485 ifp->if_flags |= IFF_RUNNING; 486 ifq_clr_oactive(&ifp->if_snd); 487 callout_reset_bycpu(&sc->jme_tick_ch, hz, jme_tick, sc, 488 JME_TICK_CPUID); 489 490 #ifdef IFPOLL_ENABLE 491 if (!(ifp->if_flags & IFF_NPOLLING)) 492 #endif 493 /* Reenable interrupts. */ 494 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 495 496 done: 497 if (sc->jme_in_tick) 498 jme_deserialize_skipmain(sc); 499 } 500 501 /* 502 * Get the current interface media status. 503 */ 504 static void 505 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 506 { 507 struct jme_softc *sc = ifp->if_softc; 508 struct mii_data *mii = device_get_softc(sc->jme_miibus); 509 510 ASSERT_IFNET_SERIALIZED_ALL(ifp); 511 512 mii_pollstat(mii); 513 ifmr->ifm_status = mii->mii_media_status; 514 ifmr->ifm_active = mii->mii_media_active; 515 } 516 517 /* 518 * Set hardware to newly-selected media. 519 */ 520 static int 521 jme_mediachange(struct ifnet *ifp) 522 { 523 struct jme_softc *sc = ifp->if_softc; 524 struct mii_data *mii = device_get_softc(sc->jme_miibus); 525 int error; 526 527 ASSERT_IFNET_SERIALIZED_ALL(ifp); 528 529 if (mii->mii_instance != 0) { 530 struct mii_softc *miisc; 531 532 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 533 mii_phy_reset(miisc); 534 } 535 error = mii_mediachg(mii); 536 537 return (error); 538 } 539 540 static int 541 jme_probe(device_t dev) 542 { 543 const struct jme_dev *sp; 544 uint16_t vid, did; 545 546 vid = pci_get_vendor(dev); 547 did = pci_get_device(dev); 548 for (sp = jme_devs; sp->jme_name != NULL; ++sp) { 549 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) { 550 struct jme_softc *sc = device_get_softc(dev); 551 552 sc->jme_caps = sp->jme_caps; 553 device_set_desc(dev, sp->jme_name); 554 return (0); 555 } 556 } 557 return (ENXIO); 558 } 559 560 static int 561 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 562 { 563 uint32_t reg; 564 int i; 565 566 *val = 0; 567 for (i = JME_TIMEOUT; i > 0; i--) { 568 reg = CSR_READ_4(sc, JME_SMBCSR); 569 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 570 break; 571 DELAY(1); 572 } 573 574 if (i == 0) { 575 device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 576 return (ETIMEDOUT); 577 } 578 579 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 580 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 581 for (i = JME_TIMEOUT; i > 0; i--) { 582 DELAY(1); 583 reg = CSR_READ_4(sc, JME_SMBINTF); 584 if ((reg & SMBINTF_CMD_TRIGGER) == 0) 585 break; 586 } 587 588 if (i == 0) { 589 device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 590 return (ETIMEDOUT); 591 } 592 593 reg = CSR_READ_4(sc, JME_SMBINTF); 594 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 595 596 return (0); 597 } 598 599 static int 600 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[]) 601 { 602 uint8_t fup, reg, val; 603 uint32_t offset; 604 int match; 605 606 offset = 0; 607 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 608 fup != JME_EEPROM_SIG0) 609 return (ENOENT); 610 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 611 fup != JME_EEPROM_SIG1) 612 return (ENOENT); 613 match = 0; 614 do { 615 if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 616 break; 617 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 618 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 619 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 620 break; 621 if (reg >= JME_PAR0 && 622 reg < JME_PAR0 + ETHER_ADDR_LEN) { 623 if (jme_eeprom_read_byte(sc, offset + 2, 624 &val) != 0) 625 break; 626 eaddr[reg - JME_PAR0] = val; 627 match++; 628 } 629 } 630 /* Check for the end of EEPROM descriptor. */ 631 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 632 break; 633 /* Try next eeprom descriptor. */ 634 offset += JME_EEPROM_DESC_BYTES; 635 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 636 637 if (match == ETHER_ADDR_LEN) 638 return (0); 639 640 return (ENOENT); 641 } 642 643 static void 644 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[]) 645 { 646 uint32_t par0, par1; 647 648 /* Read station address. */ 649 par0 = CSR_READ_4(sc, JME_PAR0); 650 par1 = CSR_READ_4(sc, JME_PAR1); 651 par1 &= 0xFFFF; 652 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) { 653 device_printf(sc->jme_dev, 654 "generating fake ethernet address.\n"); 655 par0 = karc4random(); 656 /* Set OUI to JMicron. */ 657 eaddr[0] = 0x00; 658 eaddr[1] = 0x1B; 659 eaddr[2] = 0x8C; 660 eaddr[3] = (par0 >> 16) & 0xff; 661 eaddr[4] = (par0 >> 8) & 0xff; 662 eaddr[5] = par0 & 0xff; 663 } else { 664 eaddr[0] = (par0 >> 0) & 0xFF; 665 eaddr[1] = (par0 >> 8) & 0xFF; 666 eaddr[2] = (par0 >> 16) & 0xFF; 667 eaddr[3] = (par0 >> 24) & 0xFF; 668 eaddr[4] = (par1 >> 0) & 0xFF; 669 eaddr[5] = (par1 >> 8) & 0xFF; 670 } 671 } 672 673 static int 674 jme_attach(device_t dev) 675 { 676 struct jme_softc *sc = device_get_softc(dev); 677 struct ifnet *ifp = &sc->arpcom.ac_if; 678 uint32_t reg; 679 uint16_t did; 680 uint8_t pcie_ptr, rev; 681 int error = 0, i, j, rx_desc_cnt, coal_max; 682 uint8_t eaddr[ETHER_ADDR_LEN]; 683 #ifdef IFPOLL_ENABLE 684 int offset, offset_def; 685 #endif 686 687 /* 688 * Initialize serializers 689 */ 690 lwkt_serialize_init(&sc->jme_serialize); 691 lwkt_serialize_init(&sc->jme_cdata.jme_tx_data.jme_tx_serialize); 692 for (i = 0; i < JME_NRXRING_MAX; ++i) { 693 lwkt_serialize_init( 694 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize); 695 } 696 697 /* 698 * Get # of RX ring descriptors 699 */ 700 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count", 701 jme_rx_desc_count); 702 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN); 703 if (rx_desc_cnt > JME_NDESC_MAX) 704 rx_desc_cnt = JME_NDESC_MAX; 705 706 /* 707 * Get # of TX ring descriptors 708 */ 709 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = 710 device_getenv_int(dev, "tx_desc_count", jme_tx_desc_count); 711 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = 712 roundup(sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt, JME_NDESC_ALIGN); 713 if (sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt > JME_NDESC_MAX) 714 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt = JME_NDESC_MAX; 715 716 /* 717 * Get # of RX rings 718 */ 719 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count", 720 jme_rx_ring_count); 721 sc->jme_cdata.jme_rx_ring_cnt = 722 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX); 723 724 /* 725 * Initialize serializer array 726 */ 727 i = 0; 728 729 KKASSERT(i < JME_NSERIALIZE); 730 sc->jme_serialize_arr[i++] = &sc->jme_serialize; 731 732 KKASSERT(i < JME_NSERIALIZE); 733 sc->jme_serialize_arr[i++] = 734 &sc->jme_cdata.jme_tx_data.jme_tx_serialize; 735 736 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) { 737 KKASSERT(i < JME_NSERIALIZE); 738 sc->jme_serialize_arr[i++] = 739 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize; 740 } 741 742 KKASSERT(i <= JME_NSERIALIZE); 743 sc->jme_serialize_cnt = i; 744 745 /* 746 * Setup TX ring specific data 747 */ 748 sc->jme_cdata.jme_tx_data.jme_sc = sc; 749 750 /* 751 * Setup RX rings specific data 752 */ 753 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 754 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 755 756 rdata->jme_sc = sc; 757 rdata->jme_rx_coal = jme_rx_status[i].jme_coal; 758 rdata->jme_rx_comp = jme_rx_status[i].jme_comp; 759 rdata->jme_rx_empty = jme_rx_status[i].jme_empty; 760 rdata->jme_rx_idx = i; 761 rdata->jme_rx_desc_cnt = rx_desc_cnt; 762 } 763 764 sc->jme_dev = dev; 765 sc->jme_lowaddr = BUS_SPACE_MAXADDR; 766 767 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 768 769 callout_init(&sc->jme_tick_ch); 770 771 #ifndef BURN_BRIDGES 772 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 773 uint32_t irq, mem; 774 775 irq = pci_read_config(dev, PCIR_INTLINE, 4); 776 mem = pci_read_config(dev, JME_PCIR_BAR, 4); 777 778 device_printf(dev, "chip is in D%d power mode " 779 "-- setting to D0\n", pci_get_powerstate(dev)); 780 781 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 782 783 pci_write_config(dev, PCIR_INTLINE, irq, 4); 784 pci_write_config(dev, JME_PCIR_BAR, mem, 4); 785 } 786 #endif /* !BURN_BRIDGE */ 787 788 /* Enable bus mastering */ 789 pci_enable_busmaster(dev); 790 791 /* 792 * Allocate IO memory 793 * 794 * JMC250 supports both memory mapped and I/O register space 795 * access. Because I/O register access should use different 796 * BARs to access registers it's waste of time to use I/O 797 * register spce access. JMC250 uses 16K to map entire memory 798 * space. 799 */ 800 sc->jme_mem_rid = JME_PCIR_BAR; 801 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 802 &sc->jme_mem_rid, RF_ACTIVE); 803 if (sc->jme_mem_res == NULL) { 804 device_printf(dev, "can't allocate IO memory\n"); 805 return ENXIO; 806 } 807 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res); 808 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res); 809 810 /* 811 * Allocate IRQ 812 */ 813 error = jme_intr_alloc(dev); 814 if (error) 815 goto fail; 816 817 /* 818 * Extract revisions 819 */ 820 reg = CSR_READ_4(sc, JME_CHIPMODE); 821 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 822 CHIPMODE_NOT_FPGA) { 823 sc->jme_caps |= JME_CAP_FPGA; 824 if (bootverbose) { 825 device_printf(dev, "FPGA revision: 0x%04x\n", 826 (reg & CHIPMODE_FPGA_REV_MASK) >> 827 CHIPMODE_FPGA_REV_SHIFT); 828 } 829 } 830 831 /* NOTE: FM revision is put in the upper 4 bits */ 832 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4; 833 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT; 834 if (bootverbose) 835 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev); 836 837 did = pci_get_device(dev); 838 switch (did) { 839 case PCI_PRODUCT_JMICRON_JMC250: 840 if (rev == JME_REV1_A2) 841 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX; 842 break; 843 844 case PCI_PRODUCT_JMICRON_JMC260: 845 if (rev == JME_REV2) { 846 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT; 847 sc->jme_phycom0 = 0x608a; 848 } else if (rev == JME_REV2_2) { 849 sc->jme_phycom0 = 0x408a; 850 } 851 break; 852 853 default: 854 panic("unknown device id 0x%04x", did); 855 } 856 if (rev >= JME_REV2) { 857 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC; 858 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 | 859 GHC_TXMAC_CLKSRC_1000; 860 } 861 if (rev >= JME_REV5) 862 sc->jme_caps |= JME_CAP_PHYPWR; 863 if (rev >= JME_REV6 || rev == JME_REV5 || rev == JME_REV5_1 || 864 rev == JME_REV5_3) { 865 sc->jme_phycom0 = 0x008a; 866 sc->jme_phycom1 = 0x4109; 867 } else if (rev == JME_REV3_1 || rev == JME_REV3_2) { 868 sc->jme_phycom0 = 0xe088; 869 } 870 871 if (rev >= JME_REV2) { 872 reg = pci_read_config(dev, JME_PCI_SSCTRL, 4); 873 if ((reg & SSCTRL_PHYMASK) == SSCTRL_PHYEA) { 874 sc->jme_phycom0 = 0; 875 sc->jme_phycom1 = 0; 876 } 877 } 878 879 /* Reset the ethernet controller. */ 880 jme_reset(sc); 881 882 /* Map MSI/MSI-X vectors */ 883 jme_set_msinum(sc); 884 885 /* Get station address. */ 886 reg = CSR_READ_4(sc, JME_SMBCSR); 887 if (reg & SMBCSR_EEPROM_PRESENT) 888 error = jme_eeprom_macaddr(sc, eaddr); 889 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) { 890 if (error != 0 && (bootverbose)) { 891 device_printf(dev, "ethernet hardware address " 892 "not found in EEPROM.\n"); 893 } 894 jme_reg_macaddr(sc, eaddr); 895 } 896 897 /* 898 * Save PHY address. 899 * Integrated JR0211 has fixed PHY address whereas FPGA version 900 * requires PHY probing to get correct PHY address. 901 */ 902 if ((sc->jme_caps & JME_CAP_FPGA) == 0) { 903 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 904 GPREG0_PHY_ADDR_MASK; 905 if (bootverbose) { 906 device_printf(dev, "PHY is at address %d.\n", 907 sc->jme_phyaddr); 908 } 909 } else { 910 sc->jme_phyaddr = 0; 911 } 912 913 /* Set max allowable DMA size. */ 914 pcie_ptr = pci_get_pciecap_ptr(dev); 915 if (pcie_ptr != 0) { 916 uint16_t ctrl; 917 918 sc->jme_caps |= JME_CAP_PCIE; 919 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2); 920 if (bootverbose) { 921 device_printf(dev, "Read request size : %d bytes.\n", 922 128 << ((ctrl >> 12) & 0x07)); 923 device_printf(dev, "TLP payload size : %d bytes.\n", 924 128 << ((ctrl >> 5) & 0x07)); 925 } 926 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) { 927 case PCIEM_DEVCTL_MAX_READRQ_128: 928 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 929 break; 930 case PCIEM_DEVCTL_MAX_READRQ_256: 931 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 932 break; 933 default: 934 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 935 break; 936 } 937 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 938 } else { 939 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 940 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 941 } 942 943 #ifdef notyet 944 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) 945 sc->jme_caps |= JME_CAP_PMCAP; 946 #endif 947 948 #ifdef IFPOLL_ENABLE 949 /* 950 * NPOLLING RX CPU offset 951 */ 952 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) { 953 offset = 0; 954 } else { 955 offset_def = (sc->jme_cdata.jme_rx_ring_cnt * 956 device_get_unit(dev)) % ncpus2; 957 offset = device_getenv_int(dev, "npoll.rxoff", offset_def); 958 if (offset >= ncpus2 || 959 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) { 960 device_printf(dev, "invalid npoll.rxoff %d, use %d\n", 961 offset, offset_def); 962 offset = offset_def; 963 } 964 } 965 sc->jme_npoll_rxoff = offset; 966 967 /* 968 * NPOLLING TX CPU offset 969 */ 970 offset_def = sc->jme_npoll_rxoff; 971 offset = device_getenv_int(dev, "npoll.txoff", offset_def); 972 if (offset >= ncpus2) { 973 device_printf(dev, "invalid npoll.txoff %d, use %d\n", 974 offset, offset_def); 975 offset = offset_def; 976 } 977 sc->jme_npoll_txoff = offset; 978 #endif 979 980 /* 981 * Set default coalesce valves 982 */ 983 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 984 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 985 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 986 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 987 988 /* 989 * Adjust coalesce valves, in case that the number of TX/RX 990 * descs are set to small values by users. 991 * 992 * NOTE: coal_max will not be zero, since number of descs 993 * must aligned by JME_NDESC_ALIGN (16 currently) 994 */ 995 coal_max = sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt / 2; 996 if (coal_max < sc->jme_tx_coal_pkt) 997 sc->jme_tx_coal_pkt = coal_max; 998 999 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 2; 1000 if (coal_max < sc->jme_rx_coal_pkt) 1001 sc->jme_rx_coal_pkt = coal_max; 1002 1003 sc->jme_cdata.jme_tx_data.jme_tx_wreg = JME_TXWREG_NSEGS; 1004 1005 /* 1006 * Create sysctl tree 1007 */ 1008 jme_sysctl_node(sc); 1009 1010 /* Allocate DMA stuffs */ 1011 error = jme_dma_alloc(sc); 1012 if (error) 1013 goto fail; 1014 1015 ifp->if_softc = sc; 1016 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1017 ifp->if_init = jme_init; 1018 ifp->if_ioctl = jme_ioctl; 1019 ifp->if_start = jme_start; 1020 #ifdef IFPOLL_ENABLE 1021 ifp->if_npoll = jme_npoll; 1022 #endif 1023 ifp->if_watchdog = jme_watchdog; 1024 ifp->if_serialize = jme_serialize; 1025 ifp->if_deserialize = jme_deserialize; 1026 ifp->if_tryserialize = jme_tryserialize; 1027 #ifdef INVARIANTS 1028 ifp->if_serialize_assert = jme_serialize_assert; 1029 #endif 1030 ifq_set_maxlen(&ifp->if_snd, 1031 sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt - JME_TXD_RSVD); 1032 ifq_set_ready(&ifp->if_snd); 1033 1034 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */ 1035 ifp->if_capabilities = IFCAP_HWCSUM | 1036 IFCAP_TSO | 1037 IFCAP_VLAN_MTU | 1038 IFCAP_VLAN_HWTAGGING; 1039 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN) 1040 ifp->if_capabilities |= IFCAP_RSS; 1041 ifp->if_capenable = ifp->if_capabilities; 1042 1043 /* 1044 * Disable TXCSUM by default to improve bulk data 1045 * transmit performance (+20Mbps improvement). 1046 */ 1047 ifp->if_capenable &= ~IFCAP_TXCSUM; 1048 1049 if (ifp->if_capenable & IFCAP_TXCSUM) 1050 ifp->if_hwassist |= JME_CSUM_FEATURES; 1051 ifp->if_hwassist |= CSUM_TSO; 1052 1053 /* Set up MII bus. */ 1054 error = mii_phy_probe(dev, &sc->jme_miibus, 1055 jme_mediachange, jme_mediastatus); 1056 if (error) { 1057 device_printf(dev, "no PHY found!\n"); 1058 goto fail; 1059 } 1060 1061 /* 1062 * Save PHYADDR for FPGA mode PHY. 1063 */ 1064 if (sc->jme_caps & JME_CAP_FPGA) { 1065 struct mii_data *mii = device_get_softc(sc->jme_miibus); 1066 1067 if (mii->mii_instance != 0) { 1068 struct mii_softc *miisc; 1069 1070 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1071 if (miisc->mii_phy != 0) { 1072 sc->jme_phyaddr = miisc->mii_phy; 1073 break; 1074 } 1075 } 1076 if (sc->jme_phyaddr != 0) { 1077 device_printf(sc->jme_dev, 1078 "FPGA PHY is at %d\n", sc->jme_phyaddr); 1079 /* vendor magic. */ 1080 jme_miibus_writereg(dev, sc->jme_phyaddr, 1081 JMPHY_CONF, JMPHY_CONF_DEFFIFO); 1082 1083 /* XXX should we clear JME_WA_EXTFIFO */ 1084 } 1085 } 1086 } 1087 1088 ether_ifattach(ifp, eaddr, NULL); 1089 1090 /* Tell the upper layer(s) we support long frames. */ 1091 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1092 1093 /* Setup the TX ring's CPUID */ 1094 ifq_set_cpuid(&ifp->if_snd, sc->jme_tx_cpuid); 1095 ifq_set_hw_serialize(&ifp->if_snd, 1096 &sc->jme_cdata.jme_tx_data.jme_tx_serialize); 1097 1098 error = jme_intr_setup(dev); 1099 if (error) { 1100 ether_ifdetach(ifp); 1101 goto fail; 1102 } 1103 1104 return 0; 1105 fail: 1106 jme_detach(dev); 1107 return (error); 1108 } 1109 1110 static int 1111 jme_detach(device_t dev) 1112 { 1113 struct jme_softc *sc = device_get_softc(dev); 1114 1115 if (device_is_attached(dev)) { 1116 struct ifnet *ifp = &sc->arpcom.ac_if; 1117 1118 ifnet_serialize_all(ifp); 1119 jme_stop(sc); 1120 jme_intr_teardown(dev); 1121 ifnet_deserialize_all(ifp); 1122 1123 ether_ifdetach(ifp); 1124 } 1125 1126 if (sc->jme_miibus != NULL) 1127 device_delete_child(dev, sc->jme_miibus); 1128 bus_generic_detach(dev); 1129 1130 jme_intr_free(dev); 1131 1132 if (sc->jme_mem_res != NULL) { 1133 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid, 1134 sc->jme_mem_res); 1135 } 1136 1137 jme_dma_free(sc); 1138 1139 return (0); 1140 } 1141 1142 static void 1143 jme_sysctl_node(struct jme_softc *sc) 1144 { 1145 struct sysctl_ctx_list *ctx; 1146 struct sysctl_oid *tree; 1147 #ifdef JME_RSS_DEBUG 1148 int r; 1149 #endif 1150 1151 ctx = device_get_sysctl_ctx(sc->jme_dev); 1152 tree = device_get_sysctl_tree(sc->jme_dev); 1153 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1154 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW, 1155 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout"); 1156 1157 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1158 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, 1159 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet"); 1160 1161 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1162 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW, 1163 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout"); 1164 1165 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1166 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW, 1167 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet"); 1168 1169 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1170 "rx_desc_count", CTLFLAG_RD, 1171 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt, 1172 0, "RX desc count"); 1173 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1174 "tx_desc_count", CTLFLAG_RD, 1175 &sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt, 1176 0, "TX desc count"); 1177 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1178 "rx_ring_count", CTLFLAG_RD, 1179 &sc->jme_cdata.jme_rx_ring_cnt, 1180 0, "RX ring count"); 1181 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1182 "tx_wreg", CTLFLAG_RW, 1183 &sc->jme_cdata.jme_tx_data.jme_tx_wreg, 0, 1184 "# of segments before writing to hardware register"); 1185 1186 #ifdef JME_RSS_DEBUG 1187 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1188 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug, 1189 0, "RSS debug level"); 1190 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1191 char rx_ring_desc[32]; 1192 1193 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc), 1194 "rx_ring%d_pkt", r); 1195 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1196 rx_ring_desc, CTLFLAG_RW, 1197 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets"); 1198 1199 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc), 1200 "rx_ring%d_emp", r); 1201 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1202 rx_ring_desc, CTLFLAG_RW, 1203 &sc->jme_cdata.jme_rx_data[r].jme_rx_emp, 1204 "# of time RX ring empty"); 1205 } 1206 #endif 1207 1208 #ifdef IFPOLL_ENABLE 1209 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1210 "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 1211 jme_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset"); 1212 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 1213 "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW, sc, 0, 1214 jme_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset"); 1215 #endif 1216 } 1217 1218 static int 1219 jme_dma_alloc(struct jme_softc *sc) 1220 { 1221 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1222 struct jme_txdesc *txd; 1223 bus_dmamem_t dmem; 1224 int error, i, asize; 1225 1226 asize = __VM_CACHELINE_ALIGN( 1227 tdata->jme_tx_desc_cnt * sizeof(struct jme_txdesc)); 1228 tdata->jme_txdesc = kmalloc_cachealign(asize, M_DEVBUF, 1229 M_WAITOK | M_ZERO); 1230 1231 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1232 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 1233 1234 asize = __VM_CACHELINE_ALIGN( 1235 rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc)); 1236 rdata->jme_rxdesc = kmalloc_cachealign(asize, M_DEVBUF, 1237 M_WAITOK | M_ZERO); 1238 } 1239 1240 /* Create parent ring tag. */ 1241 error = bus_dma_tag_create(NULL,/* parent */ 1242 1, JME_RING_BOUNDARY, /* algnmnt, boundary */ 1243 sc->jme_lowaddr, /* lowaddr */ 1244 BUS_SPACE_MAXADDR, /* highaddr */ 1245 NULL, NULL, /* filter, filterarg */ 1246 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1247 0, /* nsegments */ 1248 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1249 0, /* flags */ 1250 &sc->jme_cdata.jme_ring_tag); 1251 if (error) { 1252 device_printf(sc->jme_dev, 1253 "could not create parent ring DMA tag.\n"); 1254 return error; 1255 } 1256 1257 /* 1258 * Create DMA stuffs for TX ring 1259 */ 1260 asize = roundup2(JME_TX_RING_SIZE(tdata), JME_TX_RING_ALIGN); 1261 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag, 1262 JME_TX_RING_ALIGN, 0, 1263 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1264 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1265 if (error) { 1266 device_printf(sc->jme_dev, "could not allocate Tx ring.\n"); 1267 return error; 1268 } 1269 tdata->jme_tx_ring_tag = dmem.dmem_tag; 1270 tdata->jme_tx_ring_map = dmem.dmem_map; 1271 tdata->jme_tx_ring = dmem.dmem_addr; 1272 tdata->jme_tx_ring_paddr = dmem.dmem_busaddr; 1273 1274 /* 1275 * Create DMA stuffs for RX rings 1276 */ 1277 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1278 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]); 1279 if (error) 1280 return error; 1281 } 1282 1283 /* Create parent buffer tag. */ 1284 error = bus_dma_tag_create(NULL,/* parent */ 1285 1, 0, /* algnmnt, boundary */ 1286 sc->jme_lowaddr, /* lowaddr */ 1287 BUS_SPACE_MAXADDR, /* highaddr */ 1288 NULL, NULL, /* filter, filterarg */ 1289 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1290 0, /* nsegments */ 1291 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1292 0, /* flags */ 1293 &sc->jme_cdata.jme_buffer_tag); 1294 if (error) { 1295 device_printf(sc->jme_dev, 1296 "could not create parent buffer DMA tag.\n"); 1297 return error; 1298 } 1299 1300 /* 1301 * Create DMA stuffs for shadow status block 1302 */ 1303 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN); 1304 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag, 1305 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1306 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 1307 if (error) { 1308 device_printf(sc->jme_dev, 1309 "could not create shadow status block.\n"); 1310 return error; 1311 } 1312 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag; 1313 sc->jme_cdata.jme_ssb_map = dmem.dmem_map; 1314 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr; 1315 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr; 1316 1317 /* 1318 * Create DMA stuffs for TX buffers 1319 */ 1320 1321 /* Create tag for Tx buffers. */ 1322 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1323 1, 0, /* algnmnt, boundary */ 1324 BUS_SPACE_MAXADDR, /* lowaddr */ 1325 BUS_SPACE_MAXADDR, /* highaddr */ 1326 NULL, NULL, /* filter, filterarg */ 1327 JME_TSO_MAXSIZE, /* maxsize */ 1328 JME_MAXTXSEGS, /* nsegments */ 1329 JME_MAXSEGSIZE, /* maxsegsize */ 1330 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */ 1331 &tdata->jme_tx_tag); 1332 if (error != 0) { 1333 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1334 return error; 1335 } 1336 1337 /* Create DMA maps for Tx buffers. */ 1338 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 1339 txd = &tdata->jme_txdesc[i]; 1340 error = bus_dmamap_create(tdata->jme_tx_tag, 1341 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, 1342 &txd->tx_dmamap); 1343 if (error) { 1344 int j; 1345 1346 device_printf(sc->jme_dev, 1347 "could not create %dth Tx dmamap.\n", i); 1348 1349 for (j = 0; j < i; ++j) { 1350 txd = &tdata->jme_txdesc[j]; 1351 bus_dmamap_destroy(tdata->jme_tx_tag, 1352 txd->tx_dmamap); 1353 } 1354 bus_dma_tag_destroy(tdata->jme_tx_tag); 1355 tdata->jme_tx_tag = NULL; 1356 return error; 1357 } 1358 } 1359 1360 /* 1361 * Create DMA stuffs for RX buffers 1362 */ 1363 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 1364 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]); 1365 if (error) 1366 return error; 1367 } 1368 return 0; 1369 } 1370 1371 static void 1372 jme_dma_free(struct jme_softc *sc) 1373 { 1374 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1375 struct jme_txdesc *txd; 1376 struct jme_rxdesc *rxd; 1377 struct jme_rxdata *rdata; 1378 int i, r; 1379 1380 /* Tx ring */ 1381 if (tdata->jme_tx_ring_tag != NULL) { 1382 bus_dmamap_unload(tdata->jme_tx_ring_tag, 1383 tdata->jme_tx_ring_map); 1384 bus_dmamem_free(tdata->jme_tx_ring_tag, 1385 tdata->jme_tx_ring, tdata->jme_tx_ring_map); 1386 bus_dma_tag_destroy(tdata->jme_tx_ring_tag); 1387 tdata->jme_tx_ring_tag = NULL; 1388 } 1389 1390 /* Rx ring */ 1391 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1392 rdata = &sc->jme_cdata.jme_rx_data[r]; 1393 if (rdata->jme_rx_ring_tag != NULL) { 1394 bus_dmamap_unload(rdata->jme_rx_ring_tag, 1395 rdata->jme_rx_ring_map); 1396 bus_dmamem_free(rdata->jme_rx_ring_tag, 1397 rdata->jme_rx_ring, 1398 rdata->jme_rx_ring_map); 1399 bus_dma_tag_destroy(rdata->jme_rx_ring_tag); 1400 rdata->jme_rx_ring_tag = NULL; 1401 } 1402 } 1403 1404 /* Tx buffers */ 1405 if (tdata->jme_tx_tag != NULL) { 1406 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 1407 txd = &tdata->jme_txdesc[i]; 1408 bus_dmamap_destroy(tdata->jme_tx_tag, txd->tx_dmamap); 1409 } 1410 bus_dma_tag_destroy(tdata->jme_tx_tag); 1411 tdata->jme_tx_tag = NULL; 1412 } 1413 1414 /* Rx buffers */ 1415 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1416 rdata = &sc->jme_cdata.jme_rx_data[r]; 1417 if (rdata->jme_rx_tag != NULL) { 1418 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 1419 rxd = &rdata->jme_rxdesc[i]; 1420 bus_dmamap_destroy(rdata->jme_rx_tag, 1421 rxd->rx_dmamap); 1422 } 1423 bus_dmamap_destroy(rdata->jme_rx_tag, 1424 rdata->jme_rx_sparemap); 1425 bus_dma_tag_destroy(rdata->jme_rx_tag); 1426 rdata->jme_rx_tag = NULL; 1427 } 1428 } 1429 1430 /* Shadow status block. */ 1431 if (sc->jme_cdata.jme_ssb_tag != NULL) { 1432 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1433 sc->jme_cdata.jme_ssb_map); 1434 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1435 sc->jme_cdata.jme_ssb_block, 1436 sc->jme_cdata.jme_ssb_map); 1437 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1438 sc->jme_cdata.jme_ssb_tag = NULL; 1439 } 1440 1441 if (sc->jme_cdata.jme_buffer_tag != NULL) { 1442 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1443 sc->jme_cdata.jme_buffer_tag = NULL; 1444 } 1445 if (sc->jme_cdata.jme_ring_tag != NULL) { 1446 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1447 sc->jme_cdata.jme_ring_tag = NULL; 1448 } 1449 1450 if (tdata->jme_txdesc != NULL) { 1451 kfree(tdata->jme_txdesc, M_DEVBUF); 1452 tdata->jme_txdesc = NULL; 1453 } 1454 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 1455 rdata = &sc->jme_cdata.jme_rx_data[r]; 1456 if (rdata->jme_rxdesc != NULL) { 1457 kfree(rdata->jme_rxdesc, M_DEVBUF); 1458 rdata->jme_rxdesc = NULL; 1459 } 1460 } 1461 } 1462 1463 /* 1464 * Make sure the interface is stopped at reboot time. 1465 */ 1466 static int 1467 jme_shutdown(device_t dev) 1468 { 1469 return jme_suspend(dev); 1470 } 1471 1472 #ifdef notyet 1473 /* 1474 * Unlike other ethernet controllers, JMC250 requires 1475 * explicit resetting link speed to 10/100Mbps as gigabit 1476 * link will cunsume more power than 375mA. 1477 * Note, we reset the link speed to 10/100Mbps with 1478 * auto-negotiation but we don't know whether that operation 1479 * would succeed or not as we have no control after powering 1480 * off. If the renegotiation fail WOL may not work. Running 1481 * at 1Gbps draws more power than 375mA at 3.3V which is 1482 * specified in PCI specification and that would result in 1483 * complete shutdowning power to ethernet controller. 1484 * 1485 * TODO 1486 * Save current negotiated media speed/duplex/flow-control 1487 * to softc and restore the same link again after resuming. 1488 * PHY handling such as power down/resetting to 100Mbps 1489 * may be better handled in suspend method in phy driver. 1490 */ 1491 static void 1492 jme_setlinkspeed(struct jme_softc *sc) 1493 { 1494 struct mii_data *mii; 1495 int aneg, i; 1496 1497 JME_LOCK_ASSERT(sc); 1498 1499 mii = device_get_softc(sc->jme_miibus); 1500 mii_pollstat(mii); 1501 aneg = 0; 1502 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1503 switch IFM_SUBTYPE(mii->mii_media_active) { 1504 case IFM_10_T: 1505 case IFM_100_TX: 1506 return; 1507 case IFM_1000_T: 1508 aneg++; 1509 default: 1510 break; 1511 } 1512 } 1513 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1514 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1515 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1516 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1517 BMCR_AUTOEN | BMCR_STARTNEG); 1518 DELAY(1000); 1519 if (aneg != 0) { 1520 /* Poll link state until jme(4) get a 10/100 link. */ 1521 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1522 mii_pollstat(mii); 1523 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1524 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1525 case IFM_10_T: 1526 case IFM_100_TX: 1527 jme_mac_config(sc); 1528 return; 1529 default: 1530 break; 1531 } 1532 } 1533 JME_UNLOCK(sc); 1534 pause("jmelnk", hz); 1535 JME_LOCK(sc); 1536 } 1537 if (i == MII_ANEGTICKS_GIGE) 1538 device_printf(sc->jme_dev, "establishing link failed, " 1539 "WOL may not work!"); 1540 } 1541 /* 1542 * No link, force MAC to have 100Mbps, full-duplex link. 1543 * This is the last resort and may/may not work. 1544 */ 1545 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1546 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1547 jme_mac_config(sc); 1548 } 1549 1550 static void 1551 jme_setwol(struct jme_softc *sc) 1552 { 1553 struct ifnet *ifp = &sc->arpcom.ac_if; 1554 uint32_t gpr, pmcs; 1555 uint16_t pmstat; 1556 int pmc; 1557 1558 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1559 /* No PME capability, PHY power down. */ 1560 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1561 MII_BMCR, BMCR_PDOWN); 1562 return; 1563 } 1564 1565 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1566 pmcs = CSR_READ_4(sc, JME_PMCS); 1567 pmcs &= ~PMCS_WOL_ENB_MASK; 1568 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1569 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1570 /* Enable PME message. */ 1571 gpr |= GPREG0_PME_ENB; 1572 /* For gigabit controllers, reset link speed to 10/100. */ 1573 if ((sc->jme_caps & JME_CAP_FASTETH) == 0) 1574 jme_setlinkspeed(sc); 1575 } 1576 1577 CSR_WRITE_4(sc, JME_PMCS, pmcs); 1578 CSR_WRITE_4(sc, JME_GPREG0, gpr); 1579 1580 /* Request PME. */ 1581 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1582 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1583 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1584 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1585 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1586 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1587 /* No WOL, PHY power down. */ 1588 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 1589 MII_BMCR, BMCR_PDOWN); 1590 } 1591 } 1592 #endif 1593 1594 static int 1595 jme_suspend(device_t dev) 1596 { 1597 struct jme_softc *sc = device_get_softc(dev); 1598 struct ifnet *ifp = &sc->arpcom.ac_if; 1599 1600 ifnet_serialize_all(ifp); 1601 jme_stop(sc); 1602 #ifdef notyet 1603 jme_setwol(sc); 1604 #endif 1605 ifnet_deserialize_all(ifp); 1606 1607 return (0); 1608 } 1609 1610 static int 1611 jme_resume(device_t dev) 1612 { 1613 struct jme_softc *sc = device_get_softc(dev); 1614 struct ifnet *ifp = &sc->arpcom.ac_if; 1615 #ifdef notyet 1616 int pmc; 1617 #endif 1618 1619 ifnet_serialize_all(ifp); 1620 1621 #ifdef notyet 1622 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1623 uint16_t pmstat; 1624 1625 pmstat = pci_read_config(sc->jme_dev, 1626 pmc + PCIR_POWER_STATUS, 2); 1627 /* Disable PME clear PME status. */ 1628 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1629 pci_write_config(sc->jme_dev, 1630 pmc + PCIR_POWER_STATUS, pmstat, 2); 1631 } 1632 #endif 1633 1634 if (ifp->if_flags & IFF_UP) 1635 jme_init(sc); 1636 1637 ifnet_deserialize_all(ifp); 1638 1639 return (0); 1640 } 1641 1642 static __inline int 1643 jme_tso_pullup(struct mbuf **mp) 1644 { 1645 int hoff, iphlen, thoff; 1646 struct mbuf *m; 1647 1648 m = *mp; 1649 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable")); 1650 1651 iphlen = m->m_pkthdr.csum_iphlen; 1652 thoff = m->m_pkthdr.csum_thlen; 1653 hoff = m->m_pkthdr.csum_lhlen; 1654 1655 KASSERT(iphlen > 0, ("invalid ip hlen")); 1656 KASSERT(thoff > 0, ("invalid tcp hlen")); 1657 KASSERT(hoff > 0, ("invalid ether hlen")); 1658 1659 if (__predict_false(m->m_len < hoff + iphlen + thoff)) { 1660 m = m_pullup(m, hoff + iphlen + thoff); 1661 if (m == NULL) { 1662 *mp = NULL; 1663 return ENOBUFS; 1664 } 1665 *mp = m; 1666 } 1667 return 0; 1668 } 1669 1670 static int 1671 jme_encap(struct jme_txdata *tdata, struct mbuf **m_head, int *segs_used) 1672 { 1673 struct jme_txdesc *txd; 1674 struct jme_desc *desc; 1675 struct mbuf *m; 1676 bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1677 int maxsegs, nsegs; 1678 int error, i, prod, symbol_desc; 1679 uint32_t cflags, flag64, mss; 1680 1681 M_ASSERTPKTHDR((*m_head)); 1682 1683 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) { 1684 /* XXX Is this necessary? */ 1685 error = jme_tso_pullup(m_head); 1686 if (error) 1687 return error; 1688 } 1689 1690 prod = tdata->jme_tx_prod; 1691 txd = &tdata->jme_txdesc[prod]; 1692 1693 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) 1694 symbol_desc = 1; 1695 else 1696 symbol_desc = 0; 1697 1698 maxsegs = (tdata->jme_tx_desc_cnt - tdata->jme_tx_cnt) - 1699 (JME_TXD_RSVD + symbol_desc); 1700 if (maxsegs > JME_MAXTXSEGS) 1701 maxsegs = JME_MAXTXSEGS; 1702 KASSERT(maxsegs >= (JME_TXD_SPARE - symbol_desc), 1703 ("not enough segments %d", maxsegs)); 1704 1705 error = bus_dmamap_load_mbuf_defrag(tdata->jme_tx_tag, 1706 txd->tx_dmamap, m_head, 1707 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT); 1708 if (error) 1709 goto fail; 1710 *segs_used += nsegs; 1711 1712 bus_dmamap_sync(tdata->jme_tx_tag, txd->tx_dmamap, 1713 BUS_DMASYNC_PREWRITE); 1714 1715 m = *m_head; 1716 cflags = 0; 1717 mss = 0; 1718 1719 /* Configure checksum offload. */ 1720 if (m->m_pkthdr.csum_flags & CSUM_TSO) { 1721 mss = (uint32_t)m->m_pkthdr.tso_segsz << JME_TD_MSS_SHIFT; 1722 cflags |= JME_TD_TSO; 1723 } else if (m->m_pkthdr.csum_flags & JME_CSUM_FEATURES) { 1724 if (m->m_pkthdr.csum_flags & CSUM_IP) 1725 cflags |= JME_TD_IPCSUM; 1726 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1727 cflags |= JME_TD_TCPCSUM; 1728 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1729 cflags |= JME_TD_UDPCSUM; 1730 } 1731 1732 /* Configure VLAN. */ 1733 if (m->m_flags & M_VLANTAG) { 1734 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK); 1735 cflags |= JME_TD_VLAN_TAG; 1736 } 1737 1738 desc = &tdata->jme_tx_ring[prod]; 1739 desc->flags = htole32(cflags); 1740 desc->addr_hi = htole32(m->m_pkthdr.len); 1741 if (tdata->jme_sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1742 /* 1743 * Use 64bits TX desc chain format. 1744 * 1745 * The first TX desc of the chain, which is setup here, 1746 * is just a symbol TX desc carrying no payload. 1747 */ 1748 flag64 = JME_TD_64BIT; 1749 desc->buflen = htole32(mss); 1750 desc->addr_lo = 0; 1751 1752 *segs_used += 1; 1753 1754 /* No effective TX desc is consumed */ 1755 i = 0; 1756 } else { 1757 /* 1758 * Use 32bits TX desc chain format. 1759 * 1760 * The first TX desc of the chain, which is setup here, 1761 * is an effective TX desc carrying the first segment of 1762 * the mbuf chain. 1763 */ 1764 flag64 = 0; 1765 desc->buflen = htole32(mss | txsegs[0].ds_len); 1766 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr)); 1767 1768 /* One effective TX desc is consumed */ 1769 i = 1; 1770 } 1771 tdata->jme_tx_cnt++; 1772 KKASSERT(tdata->jme_tx_cnt - i < tdata->jme_tx_desc_cnt - JME_TXD_RSVD); 1773 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt); 1774 1775 txd->tx_ndesc = 1 - i; 1776 for (; i < nsegs; i++) { 1777 desc = &tdata->jme_tx_ring[prod]; 1778 desc->buflen = htole32(txsegs[i].ds_len); 1779 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1780 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1781 desc->flags = htole32(JME_TD_OWN | flag64); 1782 1783 tdata->jme_tx_cnt++; 1784 KKASSERT(tdata->jme_tx_cnt <= 1785 tdata->jme_tx_desc_cnt - JME_TXD_RSVD); 1786 JME_DESC_INC(prod, tdata->jme_tx_desc_cnt); 1787 } 1788 1789 /* Update producer index. */ 1790 tdata->jme_tx_prod = prod; 1791 /* 1792 * Finally request interrupt and give the first descriptor 1793 * owenership to hardware. 1794 */ 1795 desc = txd->tx_desc; 1796 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1797 1798 txd->tx_m = m; 1799 txd->tx_ndesc += nsegs; 1800 1801 return 0; 1802 fail: 1803 m_freem(*m_head); 1804 *m_head = NULL; 1805 return error; 1806 } 1807 1808 static void 1809 jme_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1810 { 1811 struct jme_softc *sc = ifp->if_softc; 1812 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1813 struct mbuf *m_head; 1814 int enq = 0; 1815 1816 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1817 ASSERT_SERIALIZED(&tdata->jme_tx_serialize); 1818 1819 if (!sc->jme_has_link) { 1820 ifq_purge(&ifp->if_snd); 1821 return; 1822 } 1823 1824 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1825 return; 1826 1827 if (tdata->jme_tx_cnt >= JME_TX_DESC_HIWAT(tdata)) 1828 jme_txeof(tdata); 1829 1830 while (!ifq_is_empty(&ifp->if_snd)) { 1831 /* 1832 * Check number of available TX descs, always 1833 * leave JME_TXD_RSVD free TX descs. 1834 */ 1835 if (tdata->jme_tx_cnt + JME_TXD_SPARE > 1836 tdata->jme_tx_desc_cnt - JME_TXD_RSVD) { 1837 ifq_set_oactive(&ifp->if_snd); 1838 break; 1839 } 1840 1841 m_head = ifq_dequeue(&ifp->if_snd); 1842 if (m_head == NULL) 1843 break; 1844 1845 /* 1846 * Pack the data into the transmit ring. If we 1847 * don't have room, set the OACTIVE flag and wait 1848 * for the NIC to drain the ring. 1849 */ 1850 if (jme_encap(tdata, &m_head, &enq)) { 1851 KKASSERT(m_head == NULL); 1852 IFNET_STAT_INC(ifp, oerrors, 1); 1853 ifq_set_oactive(&ifp->if_snd); 1854 break; 1855 } 1856 1857 if (enq >= tdata->jme_tx_wreg) { 1858 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | 1859 TXCSR_TX_ENB | TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1860 enq = 0; 1861 } 1862 1863 /* 1864 * If there's a BPF listener, bounce a copy of this frame 1865 * to him. 1866 */ 1867 ETHER_BPF_MTAP(ifp, m_head); 1868 1869 /* Set a timeout in case the chip goes out to lunch. */ 1870 ifp->if_timer = JME_TX_TIMEOUT; 1871 } 1872 1873 if (enq > 0) { 1874 /* 1875 * Reading TXCSR takes very long time under heavy load 1876 * so cache TXCSR value and writes the ORed value with 1877 * the kick command to the TXCSR. This saves one register 1878 * access cycle. 1879 */ 1880 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1881 TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1882 } 1883 } 1884 1885 static void 1886 jme_watchdog(struct ifnet *ifp) 1887 { 1888 struct jme_softc *sc = ifp->if_softc; 1889 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 1890 1891 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1892 1893 if (!sc->jme_has_link) { 1894 if_printf(ifp, "watchdog timeout (missed link)\n"); 1895 IFNET_STAT_INC(ifp, oerrors, 1); 1896 jme_init(sc); 1897 return; 1898 } 1899 1900 jme_txeof(tdata); 1901 if (tdata->jme_tx_cnt == 0) { 1902 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 1903 "-- recovering\n"); 1904 if (!ifq_is_empty(&ifp->if_snd)) 1905 if_devstart(ifp); 1906 return; 1907 } 1908 1909 if_printf(ifp, "watchdog timeout\n"); 1910 IFNET_STAT_INC(ifp, oerrors, 1); 1911 jme_init(sc); 1912 if (!ifq_is_empty(&ifp->if_snd)) 1913 if_devstart(ifp); 1914 } 1915 1916 static int 1917 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1918 { 1919 struct jme_softc *sc = ifp->if_softc; 1920 struct mii_data *mii = device_get_softc(sc->jme_miibus); 1921 struct ifreq *ifr = (struct ifreq *)data; 1922 int error = 0, mask; 1923 1924 ASSERT_IFNET_SERIALIZED_ALL(ifp); 1925 1926 switch (cmd) { 1927 case SIOCSIFMTU: 1928 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1929 (!(sc->jme_caps & JME_CAP_JUMBO) && 1930 ifr->ifr_mtu > JME_MAX_MTU)) { 1931 error = EINVAL; 1932 break; 1933 } 1934 1935 if (ifp->if_mtu != ifr->ifr_mtu) { 1936 /* 1937 * No special configuration is required when interface 1938 * MTU is changed but availability of Tx checksum 1939 * offload should be chcked against new MTU size as 1940 * FIFO size is just 2K. 1941 */ 1942 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 1943 ifp->if_capenable &= 1944 ~(IFCAP_TXCSUM | IFCAP_TSO); 1945 ifp->if_hwassist &= 1946 ~(JME_CSUM_FEATURES | CSUM_TSO); 1947 } 1948 ifp->if_mtu = ifr->ifr_mtu; 1949 if (ifp->if_flags & IFF_RUNNING) 1950 jme_init(sc); 1951 } 1952 break; 1953 1954 case SIOCSIFFLAGS: 1955 if (ifp->if_flags & IFF_UP) { 1956 if (ifp->if_flags & IFF_RUNNING) { 1957 if ((ifp->if_flags ^ sc->jme_if_flags) & 1958 (IFF_PROMISC | IFF_ALLMULTI)) 1959 jme_set_filter(sc); 1960 } else { 1961 jme_init(sc); 1962 } 1963 } else { 1964 if (ifp->if_flags & IFF_RUNNING) 1965 jme_stop(sc); 1966 } 1967 sc->jme_if_flags = ifp->if_flags; 1968 break; 1969 1970 case SIOCADDMULTI: 1971 case SIOCDELMULTI: 1972 if (ifp->if_flags & IFF_RUNNING) 1973 jme_set_filter(sc); 1974 break; 1975 1976 case SIOCSIFMEDIA: 1977 case SIOCGIFMEDIA: 1978 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1979 break; 1980 1981 case SIOCSIFCAP: 1982 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1983 1984 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) { 1985 ifp->if_capenable ^= IFCAP_TXCSUM; 1986 if (ifp->if_capenable & IFCAP_TXCSUM) 1987 ifp->if_hwassist |= JME_CSUM_FEATURES; 1988 else 1989 ifp->if_hwassist &= ~JME_CSUM_FEATURES; 1990 } 1991 if (mask & IFCAP_RXCSUM) { 1992 uint32_t reg; 1993 1994 ifp->if_capenable ^= IFCAP_RXCSUM; 1995 reg = CSR_READ_4(sc, JME_RXMAC); 1996 reg &= ~RXMAC_CSUM_ENB; 1997 if (ifp->if_capenable & IFCAP_RXCSUM) 1998 reg |= RXMAC_CSUM_ENB; 1999 CSR_WRITE_4(sc, JME_RXMAC, reg); 2000 } 2001 2002 if (mask & IFCAP_VLAN_HWTAGGING) { 2003 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2004 jme_set_vlan(sc); 2005 } 2006 2007 if ((mask & IFCAP_TSO) && ifp->if_mtu < JME_TX_FIFO_SIZE) { 2008 ifp->if_capenable ^= IFCAP_TSO; 2009 if (ifp->if_capenable & IFCAP_TSO) 2010 ifp->if_hwassist |= CSUM_TSO; 2011 else 2012 ifp->if_hwassist &= ~CSUM_TSO; 2013 } 2014 2015 if (mask & IFCAP_RSS) 2016 ifp->if_capenable ^= IFCAP_RSS; 2017 break; 2018 2019 default: 2020 error = ether_ioctl(ifp, cmd, data); 2021 break; 2022 } 2023 return (error); 2024 } 2025 2026 static void 2027 jme_mac_config(struct jme_softc *sc) 2028 { 2029 struct mii_data *mii; 2030 uint32_t ghc, rxmac, txmac, txpause, gp1; 2031 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0; 2032 2033 mii = device_get_softc(sc->jme_miibus); 2034 2035 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2036 DELAY(10); 2037 CSR_WRITE_4(sc, JME_GHC, 0); 2038 ghc = 0; 2039 rxmac = CSR_READ_4(sc, JME_RXMAC); 2040 rxmac &= ~RXMAC_FC_ENB; 2041 txmac = CSR_READ_4(sc, JME_TXMAC); 2042 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2043 txpause = CSR_READ_4(sc, JME_TXPFC); 2044 txpause &= ~TXPFC_PAUSE_ENB; 2045 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2046 ghc |= GHC_FULL_DUPLEX; 2047 rxmac &= ~RXMAC_COLL_DET_ENB; 2048 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2049 TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2050 TXMAC_FRAME_BURST); 2051 #ifdef notyet 2052 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2053 txpause |= TXPFC_PAUSE_ENB; 2054 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2055 rxmac |= RXMAC_FC_ENB; 2056 #endif 2057 /* Disable retry transmit timer/retry limit. */ 2058 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2059 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2060 } else { 2061 rxmac |= RXMAC_COLL_DET_ENB; 2062 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2063 /* Enable retry transmit timer/retry limit. */ 2064 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2065 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2066 } 2067 2068 /* 2069 * Reprogram Tx/Rx MACs with resolved speed/duplex. 2070 */ 2071 gp1 = CSR_READ_4(sc, JME_GPREG1); 2072 gp1 &= ~GPREG1_WA_HDX; 2073 2074 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2075 hdx = 1; 2076 2077 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2078 case IFM_10_T: 2079 ghc |= GHC_SPEED_10 | sc->jme_clksrc; 2080 if (hdx) 2081 gp1 |= GPREG1_WA_HDX; 2082 break; 2083 2084 case IFM_100_TX: 2085 ghc |= GHC_SPEED_100 | sc->jme_clksrc; 2086 if (hdx) 2087 gp1 |= GPREG1_WA_HDX; 2088 2089 /* 2090 * Use extended FIFO depth to workaround CRC errors 2091 * emitted by chips before JMC250B 2092 */ 2093 phyconf = JMPHY_CONF_EXTFIFO; 2094 break; 2095 2096 case IFM_1000_T: 2097 if (sc->jme_caps & JME_CAP_FASTETH) 2098 break; 2099 2100 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000; 2101 if (hdx) 2102 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2103 break; 2104 2105 default: 2106 break; 2107 } 2108 CSR_WRITE_4(sc, JME_GHC, ghc); 2109 CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2110 CSR_WRITE_4(sc, JME_TXMAC, txmac); 2111 CSR_WRITE_4(sc, JME_TXPFC, txpause); 2112 2113 if (sc->jme_workaround & JME_WA_EXTFIFO) { 2114 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2115 JMPHY_CONF, phyconf); 2116 } 2117 if (sc->jme_workaround & JME_WA_HDX) 2118 CSR_WRITE_4(sc, JME_GPREG1, gp1); 2119 } 2120 2121 static void 2122 jme_intr(void *xsc) 2123 { 2124 struct jme_softc *sc = xsc; 2125 struct ifnet *ifp = &sc->arpcom.ac_if; 2126 uint32_t status; 2127 int r; 2128 2129 ASSERT_SERIALIZED(&sc->jme_serialize); 2130 2131 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2132 if (status == 0 || status == 0xFFFFFFFF) 2133 return; 2134 2135 /* Disable interrupts. */ 2136 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2137 2138 status = CSR_READ_4(sc, JME_INTR_STATUS); 2139 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2140 goto back; 2141 2142 /* Reset PCC counter/timer and Ack interrupts. */ 2143 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2144 2145 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) 2146 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2147 2148 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2149 if (status & jme_rx_status[r].jme_coal) { 2150 status |= jme_rx_status[r].jme_coal | 2151 jme_rx_status[r].jme_comp; 2152 } 2153 } 2154 2155 CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2156 2157 if (ifp->if_flags & IFF_RUNNING) { 2158 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 2159 2160 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) 2161 jme_rx_intr(sc, status); 2162 2163 if (status & INTR_RXQ_DESC_EMPTY) { 2164 /* 2165 * Notify hardware availability of new Rx buffers. 2166 * Reading RXCSR takes very long time under heavy 2167 * load so cache RXCSR value and writes the ORed 2168 * value with the kick command to the RXCSR. This 2169 * saves one register access cycle. 2170 */ 2171 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2172 RXCSR_RX_ENB | RXCSR_RXQ_START); 2173 } 2174 2175 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) { 2176 lwkt_serialize_enter(&tdata->jme_tx_serialize); 2177 jme_txeof(tdata); 2178 if (!ifq_is_empty(&ifp->if_snd)) 2179 if_devstart(ifp); 2180 lwkt_serialize_exit(&tdata->jme_tx_serialize); 2181 } 2182 } 2183 back: 2184 /* Reenable interrupts. */ 2185 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2186 } 2187 2188 static void 2189 jme_txeof(struct jme_txdata *tdata) 2190 { 2191 struct ifnet *ifp = &tdata->jme_sc->arpcom.ac_if; 2192 int cons; 2193 2194 cons = tdata->jme_tx_cons; 2195 if (cons == tdata->jme_tx_prod) 2196 return; 2197 2198 /* 2199 * Go through our Tx list and free mbufs for those 2200 * frames which have been transmitted. 2201 */ 2202 while (cons != tdata->jme_tx_prod) { 2203 struct jme_txdesc *txd, *next_txd; 2204 uint32_t status, next_status; 2205 int next_cons, nsegs; 2206 2207 txd = &tdata->jme_txdesc[cons]; 2208 KASSERT(txd->tx_m != NULL, 2209 ("%s: freeing NULL mbuf!", __func__)); 2210 2211 status = le32toh(txd->tx_desc->flags); 2212 if ((status & JME_TD_OWN) == JME_TD_OWN) 2213 break; 2214 2215 /* 2216 * NOTE: 2217 * This chip will always update the TX descriptor's 2218 * buflen field and this updating always happens 2219 * after clearing the OWN bit, so even if the OWN 2220 * bit is cleared by the chip, we still don't sure 2221 * about whether the buflen field has been updated 2222 * by the chip or not. To avoid this race, we wait 2223 * for the next TX descriptor's OWN bit to be cleared 2224 * by the chip before reusing this TX descriptor. 2225 */ 2226 next_cons = cons; 2227 JME_DESC_ADD(next_cons, txd->tx_ndesc, tdata->jme_tx_desc_cnt); 2228 next_txd = &tdata->jme_txdesc[next_cons]; 2229 if (next_txd->tx_m == NULL) 2230 break; 2231 next_status = le32toh(next_txd->tx_desc->flags); 2232 if ((next_status & JME_TD_OWN) == JME_TD_OWN) 2233 break; 2234 2235 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) { 2236 IFNET_STAT_INC(ifp, oerrors, 1); 2237 } else { 2238 IFNET_STAT_INC(ifp, opackets, 1); 2239 if (status & JME_TD_COLLISION) { 2240 IFNET_STAT_INC(ifp, collisions, 2241 le32toh(txd->tx_desc->buflen) & 2242 JME_TD_BUF_LEN_MASK); 2243 } 2244 } 2245 2246 /* 2247 * Only the first descriptor of multi-descriptor 2248 * transmission is updated so driver have to skip entire 2249 * chained buffers for the transmiited frame. In other 2250 * words, JME_TD_OWN bit is valid only at the first 2251 * descriptor of a multi-descriptor transmission. 2252 */ 2253 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2254 tdata->jme_tx_ring[cons].flags = 0; 2255 JME_DESC_INC(cons, tdata->jme_tx_desc_cnt); 2256 } 2257 2258 /* Reclaim transferred mbufs. */ 2259 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap); 2260 m_freem(txd->tx_m); 2261 txd->tx_m = NULL; 2262 tdata->jme_tx_cnt -= txd->tx_ndesc; 2263 KASSERT(tdata->jme_tx_cnt >= 0, 2264 ("%s: Active Tx desc counter was garbled", __func__)); 2265 txd->tx_ndesc = 0; 2266 } 2267 tdata->jme_tx_cons = cons; 2268 2269 /* 1 for symbol TX descriptor */ 2270 if (tdata->jme_tx_cnt <= JME_MAXTXSEGS + 1) 2271 ifp->if_timer = 0; 2272 2273 if (tdata->jme_tx_cnt + JME_TXD_SPARE <= 2274 tdata->jme_tx_desc_cnt - JME_TXD_RSVD) 2275 ifq_clr_oactive(&ifp->if_snd); 2276 } 2277 2278 static __inline void 2279 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count) 2280 { 2281 int i; 2282 2283 for (i = 0; i < count; ++i) { 2284 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]); 2285 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt); 2286 } 2287 } 2288 2289 static __inline struct pktinfo * 2290 jme_pktinfo(struct pktinfo *pi, uint32_t flags) 2291 { 2292 if (flags & JME_RD_IPV4) 2293 pi->pi_netisr = NETISR_IP; 2294 else if (flags & JME_RD_IPV6) 2295 pi->pi_netisr = NETISR_IPV6; 2296 else 2297 return NULL; 2298 2299 pi->pi_flags = 0; 2300 pi->pi_l3proto = IPPROTO_UNKNOWN; 2301 2302 if (flags & JME_RD_MORE_FRAG) 2303 pi->pi_flags |= PKTINFO_FLAG_FRAG; 2304 else if (flags & JME_RD_TCP) 2305 pi->pi_l3proto = IPPROTO_TCP; 2306 else if (flags & JME_RD_UDP) 2307 pi->pi_l3proto = IPPROTO_UDP; 2308 else 2309 pi = NULL; 2310 return pi; 2311 } 2312 2313 /* Receive a frame. */ 2314 static void 2315 jme_rxpkt(struct jme_rxdata *rdata, int cpuid) 2316 { 2317 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if; 2318 struct jme_desc *desc; 2319 struct jme_rxdesc *rxd; 2320 struct mbuf *mp, *m; 2321 uint32_t flags, status, hash, hashinfo; 2322 int cons, count, nsegs; 2323 2324 cons = rdata->jme_rx_cons; 2325 desc = &rdata->jme_rx_ring[cons]; 2326 2327 flags = le32toh(desc->flags); 2328 status = le32toh(desc->buflen); 2329 hash = le32toh(desc->addr_hi); 2330 hashinfo = le32toh(desc->addr_lo); 2331 nsegs = JME_RX_NSEGS(status); 2332 2333 if (nsegs > 1) { 2334 /* Skip the first descriptor. */ 2335 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt); 2336 2337 /* 2338 * Clear the OWN bit of the following RX descriptors; 2339 * hardware will not clear the OWN bit except the first 2340 * RX descriptor. 2341 * 2342 * Since the first RX descriptor is setup, i.e. OWN bit 2343 * on, before its followins RX descriptors, leaving the 2344 * OWN bit on the following RX descriptors will trick 2345 * the hardware into thinking that the following RX 2346 * descriptors are ready to be used too. 2347 */ 2348 for (count = 1; count < nsegs; count++, 2349 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) 2350 rdata->jme_rx_ring[cons].flags = 0; 2351 2352 cons = rdata->jme_rx_cons; 2353 } 2354 2355 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, " 2356 "hash 0x%08x, hash info 0x%08x\n", 2357 rdata->jme_rx_idx, flags, hash, hashinfo); 2358 2359 if (status & JME_RX_ERR_STAT) { 2360 IFNET_STAT_INC(ifp, ierrors, 1); 2361 jme_discard_rxbufs(rdata, cons, nsegs); 2362 #ifdef JME_SHOW_ERRORS 2363 if_printf(ifp, "%s : receive error = 0x%b\n", 2364 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2365 #endif 2366 rdata->jme_rx_cons += nsegs; 2367 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt; 2368 return; 2369 } 2370 2371 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2372 for (count = 0; count < nsegs; count++, 2373 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) { 2374 rxd = &rdata->jme_rxdesc[cons]; 2375 mp = rxd->rx_m; 2376 2377 /* Add a new receive buffer to the ring. */ 2378 if (jme_newbuf(rdata, rxd, 0) != 0) { 2379 IFNET_STAT_INC(ifp, iqdrops, 1); 2380 /* Reuse buffer. */ 2381 jme_discard_rxbufs(rdata, cons, nsegs - count); 2382 if (rdata->jme_rxhead != NULL) { 2383 m_freem(rdata->jme_rxhead); 2384 JME_RXCHAIN_RESET(rdata); 2385 } 2386 break; 2387 } 2388 2389 /* 2390 * Assume we've received a full sized frame. 2391 * Actual size is fixed when we encounter the end of 2392 * multi-segmented frame. 2393 */ 2394 mp->m_len = MCLBYTES; 2395 2396 /* Chain received mbufs. */ 2397 if (rdata->jme_rxhead == NULL) { 2398 rdata->jme_rxhead = mp; 2399 rdata->jme_rxtail = mp; 2400 } else { 2401 /* 2402 * Receive processor can receive a maximum frame 2403 * size of 65535 bytes. 2404 */ 2405 rdata->jme_rxtail->m_next = mp; 2406 rdata->jme_rxtail = mp; 2407 } 2408 2409 if (count == nsegs - 1) { 2410 struct pktinfo pi0, *pi; 2411 2412 /* Last desc. for this frame. */ 2413 m = rdata->jme_rxhead; 2414 m->m_pkthdr.len = rdata->jme_rxlen; 2415 if (nsegs > 1) { 2416 /* Set first mbuf size. */ 2417 m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2418 /* Set last mbuf size. */ 2419 mp->m_len = rdata->jme_rxlen - 2420 ((MCLBYTES - JME_RX_PAD_BYTES) + 2421 (MCLBYTES * (nsegs - 2))); 2422 } else { 2423 m->m_len = rdata->jme_rxlen; 2424 } 2425 m->m_pkthdr.rcvif = ifp; 2426 2427 /* 2428 * Account for 10bytes auto padding which is used 2429 * to align IP header on 32bit boundary. Also note, 2430 * CRC bytes is automatically removed by the 2431 * hardware. 2432 */ 2433 m->m_data += JME_RX_PAD_BYTES; 2434 2435 /* Set checksum information. */ 2436 if ((ifp->if_capenable & IFCAP_RXCSUM) && 2437 (flags & JME_RD_IPV4)) { 2438 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2439 if (flags & JME_RD_IPCSUM) 2440 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2441 if ((flags & JME_RD_MORE_FRAG) == 0 && 2442 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2443 (JME_RD_TCP | JME_RD_TCPCSUM) || 2444 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2445 (JME_RD_UDP | JME_RD_UDPCSUM))) { 2446 m->m_pkthdr.csum_flags |= 2447 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2448 m->m_pkthdr.csum_data = 0xffff; 2449 } 2450 } 2451 2452 /* Check for VLAN tagged packets. */ 2453 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) && 2454 (flags & JME_RD_VLAN_TAG)) { 2455 m->m_pkthdr.ether_vlantag = 2456 flags & JME_RD_VLAN_MASK; 2457 m->m_flags |= M_VLANTAG; 2458 } 2459 2460 IFNET_STAT_INC(ifp, ipackets, 1); 2461 2462 if (ifp->if_capenable & IFCAP_RSS) 2463 pi = jme_pktinfo(&pi0, flags); 2464 else 2465 pi = NULL; 2466 2467 if (pi != NULL && 2468 (hashinfo & JME_RD_HASH_FN_MASK) == 2469 JME_RD_HASH_FN_TOEPLITZ) { 2470 m->m_flags |= (M_HASH | M_CKHASH); 2471 m->m_pkthdr.hash = toeplitz_hash(hash); 2472 } 2473 2474 #ifdef JME_RSS_DEBUG 2475 if (pi != NULL) { 2476 JME_RSS_DPRINTF(rdata->jme_sc, 10, 2477 "isr %d flags %08x, l3 %d %s\n", 2478 pi->pi_netisr, pi->pi_flags, 2479 pi->pi_l3proto, 2480 (m->m_flags & M_HASH) ? "hash" : ""); 2481 } 2482 #endif 2483 2484 /* Pass it on. */ 2485 ifp->if_input(ifp, m, pi, cpuid); 2486 2487 /* Reset mbuf chains. */ 2488 JME_RXCHAIN_RESET(rdata); 2489 #ifdef JME_RSS_DEBUG 2490 rdata->jme_rx_pkt++; 2491 #endif 2492 } 2493 } 2494 2495 rdata->jme_rx_cons += nsegs; 2496 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt; 2497 } 2498 2499 static void 2500 jme_rxeof(struct jme_rxdata *rdata, int count, int cpuid) 2501 { 2502 struct jme_desc *desc; 2503 int nsegs, pktlen; 2504 2505 for (;;) { 2506 #ifdef IFPOLL_ENABLE 2507 if (count >= 0 && count-- == 0) 2508 break; 2509 #endif 2510 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons]; 2511 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2512 break; 2513 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2514 break; 2515 2516 /* 2517 * Check number of segments against received bytes. 2518 * Non-matching value would indicate that hardware 2519 * is still trying to update Rx descriptors. I'm not 2520 * sure whether this check is needed. 2521 */ 2522 nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2523 pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2524 if (nsegs != howmany(pktlen, MCLBYTES)) { 2525 if_printf(&rdata->jme_sc->arpcom.ac_if, 2526 "RX fragment count(%d) and " 2527 "packet size(%d) mismach\n", nsegs, pktlen); 2528 break; 2529 } 2530 2531 /* 2532 * NOTE: 2533 * RSS hash and hash information may _not_ be set by the 2534 * hardware even if the OWN bit is cleared and VALID bit 2535 * is set. 2536 * 2537 * If the RSS information is not delivered by the hardware 2538 * yet, we MUST NOT accept this packet, let alone reusing 2539 * its RX descriptor. If this packet was accepted and its 2540 * RX descriptor was reused before hardware delivering the 2541 * RSS information, the RX buffer's address would be trashed 2542 * by the RSS information delivered by the hardware. 2543 */ 2544 if (JME_ENABLE_HWRSS(rdata->jme_sc)) { 2545 struct jme_rxdesc *rxd; 2546 uint32_t hashinfo; 2547 2548 hashinfo = le32toh(desc->addr_lo); 2549 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons]; 2550 2551 /* 2552 * This test should be enough to detect the pending 2553 * RSS information delivery, given: 2554 * - If RSS hash is not calculated, the hashinfo 2555 * will be 0. Howvever, the lower 32bits of RX 2556 * buffers' physical address will never be 0. 2557 * (see jme_rxbuf_dma_filter) 2558 * - If RSS hash is calculated, the lowest 4 bits 2559 * of hashinfo will be set, while the RX buffers 2560 * are at least 2K aligned. 2561 */ 2562 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) { 2563 #ifdef JME_SHOW_RSSWB 2564 if_printf(&rdata->jme_sc->arpcom.ac_if, 2565 "RSS is not written back yet\n"); 2566 #endif 2567 break; 2568 } 2569 } 2570 2571 /* Received a frame. */ 2572 jme_rxpkt(rdata, cpuid); 2573 } 2574 } 2575 2576 static void 2577 jme_tick(void *xsc) 2578 { 2579 struct jme_softc *sc = xsc; 2580 struct mii_data *mii = device_get_softc(sc->jme_miibus); 2581 2582 lwkt_serialize_enter(&sc->jme_serialize); 2583 2584 KKASSERT(mycpuid == JME_TICK_CPUID); 2585 2586 sc->jme_in_tick = TRUE; 2587 mii_tick(mii); 2588 sc->jme_in_tick = FALSE; 2589 2590 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2591 2592 lwkt_serialize_exit(&sc->jme_serialize); 2593 } 2594 2595 static void 2596 jme_reset(struct jme_softc *sc) 2597 { 2598 uint32_t val; 2599 2600 /* Make sure that TX and RX are stopped */ 2601 jme_stop_tx(sc); 2602 jme_stop_rx(sc); 2603 2604 /* Start reset */ 2605 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2606 DELAY(20); 2607 2608 /* 2609 * Hold reset bit before stop reset 2610 */ 2611 2612 /* Disable TXMAC and TXOFL clock sources */ 2613 CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2614 /* Disable RXMAC clock source */ 2615 val = CSR_READ_4(sc, JME_GPREG1); 2616 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC); 2617 /* Flush */ 2618 CSR_READ_4(sc, JME_GHC); 2619 2620 /* Stop reset */ 2621 CSR_WRITE_4(sc, JME_GHC, 0); 2622 /* Flush */ 2623 CSR_READ_4(sc, JME_GHC); 2624 2625 /* 2626 * Clear reset bit after stop reset 2627 */ 2628 2629 /* Enable TXMAC and TXOFL clock sources */ 2630 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC); 2631 /* Enable RXMAC clock source */ 2632 val = CSR_READ_4(sc, JME_GPREG1); 2633 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC); 2634 /* Flush */ 2635 CSR_READ_4(sc, JME_GHC); 2636 2637 /* Disable TXMAC and TXOFL clock sources */ 2638 CSR_WRITE_4(sc, JME_GHC, 0); 2639 /* Disable RXMAC clock source */ 2640 val = CSR_READ_4(sc, JME_GPREG1); 2641 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC); 2642 /* Flush */ 2643 CSR_READ_4(sc, JME_GHC); 2644 2645 /* Enable TX and RX */ 2646 val = CSR_READ_4(sc, JME_TXCSR); 2647 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB); 2648 val = CSR_READ_4(sc, JME_RXCSR); 2649 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB); 2650 /* Flush */ 2651 CSR_READ_4(sc, JME_TXCSR); 2652 CSR_READ_4(sc, JME_RXCSR); 2653 2654 /* Enable TXMAC and TXOFL clock sources */ 2655 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC); 2656 /* Disable RXMAC clock source */ 2657 val = CSR_READ_4(sc, JME_GPREG1); 2658 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC); 2659 /* Flush */ 2660 CSR_READ_4(sc, JME_GHC); 2661 2662 /* Stop TX and RX */ 2663 jme_stop_tx(sc); 2664 jme_stop_rx(sc); 2665 } 2666 2667 static void 2668 jme_init(void *xsc) 2669 { 2670 struct jme_softc *sc = xsc; 2671 struct ifnet *ifp = &sc->arpcom.ac_if; 2672 struct mii_data *mii; 2673 uint8_t eaddr[ETHER_ADDR_LEN]; 2674 bus_addr_t paddr; 2675 uint32_t reg; 2676 int error, r; 2677 2678 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2679 2680 /* 2681 * Cancel any pending I/O. 2682 */ 2683 jme_stop(sc); 2684 2685 /* 2686 * Reset the chip to a known state. 2687 */ 2688 jme_reset(sc); 2689 2690 /* 2691 * Setup MSI/MSI-X vectors to interrupts mapping 2692 */ 2693 jme_set_msinum(sc); 2694 2695 if (JME_ENABLE_HWRSS(sc)) 2696 jme_enable_rss(sc); 2697 else 2698 jme_disable_rss(sc); 2699 2700 /* Init RX descriptors */ 2701 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2702 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]); 2703 if (error) { 2704 if_printf(ifp, "initialization failed: " 2705 "no memory for %dth RX ring.\n", r); 2706 jme_stop(sc); 2707 return; 2708 } 2709 } 2710 2711 /* Init TX descriptors */ 2712 jme_init_tx_ring(&sc->jme_cdata.jme_tx_data); 2713 2714 /* Initialize shadow status block. */ 2715 jme_init_ssb(sc); 2716 2717 /* Reprogram the station address. */ 2718 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2719 CSR_WRITE_4(sc, JME_PAR0, 2720 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 2721 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 2722 2723 /* 2724 * Configure Tx queue. 2725 * Tx priority queue weight value : 0 2726 * Tx FIFO threshold for processing next packet : 16QW 2727 * Maximum Tx DMA length : 512 2728 * Allow Tx DMA burst. 2729 */ 2730 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2731 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2732 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2733 sc->jme_txcsr |= sc->jme_tx_dma_size; 2734 sc->jme_txcsr |= TXCSR_DMA_BURST; 2735 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2736 2737 /* Set Tx descriptor counter. */ 2738 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_data.jme_tx_desc_cnt); 2739 2740 /* Set Tx ring address to the hardware. */ 2741 paddr = sc->jme_cdata.jme_tx_data.jme_tx_ring_paddr; 2742 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2743 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2744 2745 /* Configure TxMAC parameters. */ 2746 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2747 reg |= TXMAC_THRESH_1_PKT; 2748 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2749 CSR_WRITE_4(sc, JME_TXMAC, reg); 2750 2751 /* 2752 * Configure Rx queue. 2753 * FIFO full threshold for transmitting Tx pause packet : 128T 2754 * FIFO threshold for processing next packet : 128QW 2755 * Rx queue 0 select 2756 * Max Rx DMA length : 128 2757 * Rx descriptor retry : 32 2758 * Rx descriptor retry time gap : 256ns 2759 * Don't receive runt/bad frame. 2760 */ 2761 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2762 #if 0 2763 /* 2764 * Since Rx FIFO size is 4K bytes, receiving frames larger 2765 * than 4K bytes will suffer from Rx FIFO overruns. So 2766 * decrease FIFO threshold to reduce the FIFO overruns for 2767 * frames larger than 4000 bytes. 2768 * For best performance of standard MTU sized frames use 2769 * maximum allowable FIFO threshold, 128QW. 2770 */ 2771 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) > 2772 JME_RX_FIFO_SIZE) 2773 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2774 else 2775 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2776 #else 2777 /* Improve PCI Express compatibility */ 2778 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2779 #endif 2780 sc->jme_rxcsr |= sc->jme_rx_dma_size; 2781 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2782 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2783 /* XXX TODO DROP_BAD */ 2784 2785 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2786 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 2787 2788 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r)); 2789 2790 /* Set Rx descriptor counter. */ 2791 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt); 2792 2793 /* Set Rx ring address to the hardware. */ 2794 paddr = rdata->jme_rx_ring_paddr; 2795 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2796 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2797 } 2798 2799 /* Clear receive filter. */ 2800 CSR_WRITE_4(sc, JME_RXMAC, 0); 2801 2802 /* Set up the receive filter. */ 2803 jme_set_filter(sc); 2804 jme_set_vlan(sc); 2805 2806 /* 2807 * Disable all WOL bits as WOL can interfere normal Rx 2808 * operation. Also clear WOL detection status bits. 2809 */ 2810 reg = CSR_READ_4(sc, JME_PMCS); 2811 reg &= ~PMCS_WOL_ENB_MASK; 2812 CSR_WRITE_4(sc, JME_PMCS, reg); 2813 2814 /* 2815 * Pad 10bytes right before received frame. This will greatly 2816 * help Rx performance on strict-alignment architectures as 2817 * it does not need to copy the frame to align the payload. 2818 */ 2819 reg = CSR_READ_4(sc, JME_RXMAC); 2820 reg |= RXMAC_PAD_10BYTES; 2821 2822 if (ifp->if_capenable & IFCAP_RXCSUM) 2823 reg |= RXMAC_CSUM_ENB; 2824 CSR_WRITE_4(sc, JME_RXMAC, reg); 2825 2826 /* Configure general purpose reg0 */ 2827 reg = CSR_READ_4(sc, JME_GPREG0); 2828 reg &= ~GPREG0_PCC_UNIT_MASK; 2829 /* Set PCC timer resolution to micro-seconds unit. */ 2830 reg |= GPREG0_PCC_UNIT_US; 2831 /* 2832 * Disable all shadow register posting as we have to read 2833 * JME_INTR_STATUS register in jme_intr. Also it seems 2834 * that it's hard to synchronize interrupt status between 2835 * hardware and software with shadow posting due to 2836 * requirements of bus_dmamap_sync(9). 2837 */ 2838 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2839 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2840 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2841 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2842 /* Disable posting of DW0. */ 2843 reg &= ~GPREG0_POST_DW0_ENB; 2844 /* Clear PME message. */ 2845 reg &= ~GPREG0_PME_ENB; 2846 /* Set PHY address. */ 2847 reg &= ~GPREG0_PHY_ADDR_MASK; 2848 reg |= sc->jme_phyaddr; 2849 CSR_WRITE_4(sc, JME_GPREG0, reg); 2850 2851 /* Configure Tx queue 0 packet completion coalescing. */ 2852 jme_set_tx_coal(sc); 2853 2854 /* Configure Rx queues packet completion coalescing. */ 2855 jme_set_rx_coal(sc); 2856 2857 /* Configure shadow status block but don't enable posting. */ 2858 paddr = sc->jme_cdata.jme_ssb_block_paddr; 2859 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2860 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2861 2862 /* Disable Timer 1 and Timer 2. */ 2863 CSR_WRITE_4(sc, JME_TIMER1, 0); 2864 CSR_WRITE_4(sc, JME_TIMER2, 0); 2865 2866 /* Configure retry transmit period, retry limit value. */ 2867 CSR_WRITE_4(sc, JME_TXTRHD, 2868 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2869 TXTRHD_RT_PERIOD_MASK) | 2870 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2871 TXTRHD_RT_LIMIT_SHIFT)); 2872 2873 #ifdef IFPOLL_ENABLE 2874 if (!(ifp->if_flags & IFF_NPOLLING)) 2875 #endif 2876 /* Initialize the interrupt mask. */ 2877 jme_enable_intr(sc); 2878 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2879 2880 /* 2881 * Enabling Tx/Rx DMA engines and Rx queue processing is 2882 * done after detection of valid link in jme_miibus_statchg. 2883 */ 2884 sc->jme_has_link = FALSE; 2885 2886 jme_phy_init(sc); 2887 2888 /* Set the current media. */ 2889 mii = device_get_softc(sc->jme_miibus); 2890 mii_mediachg(mii); 2891 2892 callout_reset_bycpu(&sc->jme_tick_ch, hz, jme_tick, sc, 2893 JME_TICK_CPUID); 2894 2895 ifp->if_flags |= IFF_RUNNING; 2896 ifq_clr_oactive(&ifp->if_snd); 2897 } 2898 2899 static void 2900 jme_stop(struct jme_softc *sc) 2901 { 2902 struct ifnet *ifp = &sc->arpcom.ac_if; 2903 struct jme_txdata *tdata = &sc->jme_cdata.jme_tx_data; 2904 struct jme_txdesc *txd; 2905 struct jme_rxdesc *rxd; 2906 struct jme_rxdata *rdata; 2907 int i, r; 2908 2909 ASSERT_IFNET_SERIALIZED_ALL(ifp); 2910 2911 /* 2912 * Mark the interface down and cancel the watchdog timer. 2913 */ 2914 ifp->if_flags &= ~IFF_RUNNING; 2915 ifq_clr_oactive(&ifp->if_snd); 2916 ifp->if_timer = 0; 2917 2918 callout_stop(&sc->jme_tick_ch); 2919 sc->jme_has_link = FALSE; 2920 2921 /* 2922 * Disable interrupts. 2923 */ 2924 jme_disable_intr(sc); 2925 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2926 2927 /* Disable updating shadow status block. */ 2928 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 2929 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 2930 2931 /* Stop receiver, transmitter. */ 2932 jme_stop_rx(sc); 2933 jme_stop_tx(sc); 2934 2935 /* 2936 * Free partial finished RX segments 2937 */ 2938 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2939 rdata = &sc->jme_cdata.jme_rx_data[r]; 2940 if (rdata->jme_rxhead != NULL) 2941 m_freem(rdata->jme_rxhead); 2942 JME_RXCHAIN_RESET(rdata); 2943 } 2944 2945 /* 2946 * Free RX and TX mbufs still in the queues. 2947 */ 2948 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 2949 rdata = &sc->jme_cdata.jme_rx_data[r]; 2950 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 2951 rxd = &rdata->jme_rxdesc[i]; 2952 if (rxd->rx_m != NULL) { 2953 bus_dmamap_unload(rdata->jme_rx_tag, 2954 rxd->rx_dmamap); 2955 m_freem(rxd->rx_m); 2956 rxd->rx_m = NULL; 2957 } 2958 } 2959 } 2960 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 2961 txd = &tdata->jme_txdesc[i]; 2962 if (txd->tx_m != NULL) { 2963 bus_dmamap_unload(tdata->jme_tx_tag, txd->tx_dmamap); 2964 m_freem(txd->tx_m); 2965 txd->tx_m = NULL; 2966 txd->tx_ndesc = 0; 2967 } 2968 } 2969 } 2970 2971 static void 2972 jme_stop_tx(struct jme_softc *sc) 2973 { 2974 uint32_t reg; 2975 int i; 2976 2977 reg = CSR_READ_4(sc, JME_TXCSR); 2978 if ((reg & TXCSR_TX_ENB) == 0) 2979 return; 2980 reg &= ~TXCSR_TX_ENB; 2981 CSR_WRITE_4(sc, JME_TXCSR, reg); 2982 for (i = JME_TIMEOUT; i > 0; i--) { 2983 DELAY(1); 2984 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 2985 break; 2986 } 2987 if (i == 0) 2988 device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 2989 } 2990 2991 static void 2992 jme_stop_rx(struct jme_softc *sc) 2993 { 2994 uint32_t reg; 2995 int i; 2996 2997 reg = CSR_READ_4(sc, JME_RXCSR); 2998 if ((reg & RXCSR_RX_ENB) == 0) 2999 return; 3000 reg &= ~RXCSR_RX_ENB; 3001 CSR_WRITE_4(sc, JME_RXCSR, reg); 3002 for (i = JME_TIMEOUT; i > 0; i--) { 3003 DELAY(1); 3004 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 3005 break; 3006 } 3007 if (i == 0) 3008 device_printf(sc->jme_dev, "stopping receiver timeout!\n"); 3009 } 3010 3011 static void 3012 jme_init_tx_ring(struct jme_txdata *tdata) 3013 { 3014 struct jme_txdesc *txd; 3015 int i; 3016 3017 tdata->jme_tx_prod = 0; 3018 tdata->jme_tx_cons = 0; 3019 tdata->jme_tx_cnt = 0; 3020 3021 bzero(tdata->jme_tx_ring, JME_TX_RING_SIZE(tdata)); 3022 for (i = 0; i < tdata->jme_tx_desc_cnt; i++) { 3023 txd = &tdata->jme_txdesc[i]; 3024 txd->tx_m = NULL; 3025 txd->tx_desc = &tdata->jme_tx_ring[i]; 3026 txd->tx_ndesc = 0; 3027 } 3028 } 3029 3030 static void 3031 jme_init_ssb(struct jme_softc *sc) 3032 { 3033 struct jme_chain_data *cd; 3034 3035 cd = &sc->jme_cdata; 3036 bzero(cd->jme_ssb_block, JME_SSB_SIZE); 3037 } 3038 3039 static int 3040 jme_init_rx_ring(struct jme_rxdata *rdata) 3041 { 3042 struct jme_rxdesc *rxd; 3043 int i; 3044 3045 KKASSERT(rdata->jme_rxhead == NULL && 3046 rdata->jme_rxtail == NULL && 3047 rdata->jme_rxlen == 0); 3048 rdata->jme_rx_cons = 0; 3049 3050 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata)); 3051 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 3052 int error; 3053 3054 rxd = &rdata->jme_rxdesc[i]; 3055 rxd->rx_m = NULL; 3056 rxd->rx_desc = &rdata->jme_rx_ring[i]; 3057 error = jme_newbuf(rdata, rxd, 1); 3058 if (error) 3059 return error; 3060 } 3061 return 0; 3062 } 3063 3064 static int 3065 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init) 3066 { 3067 struct mbuf *m; 3068 bus_dma_segment_t segs; 3069 bus_dmamap_t map; 3070 int error, nsegs; 3071 3072 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR); 3073 if (m == NULL) 3074 return ENOBUFS; 3075 /* 3076 * JMC250 has 64bit boundary alignment limitation so jme(4) 3077 * takes advantage of 10 bytes padding feature of hardware 3078 * in order not to copy entire frame to align IP header on 3079 * 32bit boundary. 3080 */ 3081 m->m_len = m->m_pkthdr.len = MCLBYTES; 3082 3083 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag, 3084 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs, 3085 BUS_DMA_NOWAIT); 3086 if (error) { 3087 m_freem(m); 3088 if (init) { 3089 if_printf(&rdata->jme_sc->arpcom.ac_if, 3090 "can't load RX mbuf\n"); 3091 } 3092 return error; 3093 } 3094 3095 if (rxd->rx_m != NULL) { 3096 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap, 3097 BUS_DMASYNC_POSTREAD); 3098 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap); 3099 } 3100 map = rxd->rx_dmamap; 3101 rxd->rx_dmamap = rdata->jme_rx_sparemap; 3102 rdata->jme_rx_sparemap = map; 3103 rxd->rx_m = m; 3104 rxd->rx_paddr = segs.ds_addr; 3105 3106 jme_setup_rxdesc(rxd); 3107 return 0; 3108 } 3109 3110 static void 3111 jme_set_vlan(struct jme_softc *sc) 3112 { 3113 struct ifnet *ifp = &sc->arpcom.ac_if; 3114 uint32_t reg; 3115 3116 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3117 3118 reg = CSR_READ_4(sc, JME_RXMAC); 3119 reg &= ~RXMAC_VLAN_ENB; 3120 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 3121 reg |= RXMAC_VLAN_ENB; 3122 CSR_WRITE_4(sc, JME_RXMAC, reg); 3123 } 3124 3125 static void 3126 jme_set_filter(struct jme_softc *sc) 3127 { 3128 struct ifnet *ifp = &sc->arpcom.ac_if; 3129 struct ifmultiaddr *ifma; 3130 uint32_t crc; 3131 uint32_t mchash[2]; 3132 uint32_t rxcfg; 3133 3134 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3135 3136 rxcfg = CSR_READ_4(sc, JME_RXMAC); 3137 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3138 RXMAC_ALLMULTI); 3139 3140 /* 3141 * Always accept frames destined to our station address. 3142 * Always accept broadcast frames. 3143 */ 3144 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST; 3145 3146 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 3147 if (ifp->if_flags & IFF_PROMISC) 3148 rxcfg |= RXMAC_PROMISC; 3149 if (ifp->if_flags & IFF_ALLMULTI) 3150 rxcfg |= RXMAC_ALLMULTI; 3151 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3152 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3153 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3154 return; 3155 } 3156 3157 /* 3158 * Set up the multicast address filter by passing all multicast 3159 * addresses through a CRC generator, and then using the low-order 3160 * 6 bits as an index into the 64 bit multicast hash table. The 3161 * high order bits select the register, while the rest of the bits 3162 * select the bit within the register. 3163 */ 3164 rxcfg |= RXMAC_MULTICAST; 3165 bzero(mchash, sizeof(mchash)); 3166 3167 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 3168 if (ifma->ifma_addr->sa_family != AF_LINK) 3169 continue; 3170 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3171 ifma->ifma_addr), ETHER_ADDR_LEN); 3172 3173 /* Just want the 6 least significant bits. */ 3174 crc &= 0x3f; 3175 3176 /* Set the corresponding bit in the hash table. */ 3177 mchash[crc >> 5] |= 1 << (crc & 0x1f); 3178 } 3179 3180 CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3181 CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3182 CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3183 } 3184 3185 static int 3186 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS) 3187 { 3188 struct jme_softc *sc = arg1; 3189 struct ifnet *ifp = &sc->arpcom.ac_if; 3190 int error, v; 3191 3192 ifnet_serialize_all(ifp); 3193 3194 v = sc->jme_tx_coal_to; 3195 error = sysctl_handle_int(oidp, &v, 0, req); 3196 if (error || req->newptr == NULL) 3197 goto back; 3198 3199 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) { 3200 error = EINVAL; 3201 goto back; 3202 } 3203 3204 if (v != sc->jme_tx_coal_to) { 3205 sc->jme_tx_coal_to = v; 3206 if (ifp->if_flags & IFF_RUNNING) 3207 jme_set_tx_coal(sc); 3208 } 3209 back: 3210 ifnet_deserialize_all(ifp); 3211 return error; 3212 } 3213 3214 static int 3215 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3216 { 3217 struct jme_softc *sc = arg1; 3218 struct ifnet *ifp = &sc->arpcom.ac_if; 3219 int error, v; 3220 3221 ifnet_serialize_all(ifp); 3222 3223 v = sc->jme_tx_coal_pkt; 3224 error = sysctl_handle_int(oidp, &v, 0, req); 3225 if (error || req->newptr == NULL) 3226 goto back; 3227 3228 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) { 3229 error = EINVAL; 3230 goto back; 3231 } 3232 3233 if (v != sc->jme_tx_coal_pkt) { 3234 sc->jme_tx_coal_pkt = v; 3235 if (ifp->if_flags & IFF_RUNNING) 3236 jme_set_tx_coal(sc); 3237 } 3238 back: 3239 ifnet_deserialize_all(ifp); 3240 return error; 3241 } 3242 3243 static int 3244 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS) 3245 { 3246 struct jme_softc *sc = arg1; 3247 struct ifnet *ifp = &sc->arpcom.ac_if; 3248 int error, v; 3249 3250 ifnet_serialize_all(ifp); 3251 3252 v = sc->jme_rx_coal_to; 3253 error = sysctl_handle_int(oidp, &v, 0, req); 3254 if (error || req->newptr == NULL) 3255 goto back; 3256 3257 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) { 3258 error = EINVAL; 3259 goto back; 3260 } 3261 3262 if (v != sc->jme_rx_coal_to) { 3263 sc->jme_rx_coal_to = v; 3264 if (ifp->if_flags & IFF_RUNNING) 3265 jme_set_rx_coal(sc); 3266 } 3267 back: 3268 ifnet_deserialize_all(ifp); 3269 return error; 3270 } 3271 3272 static int 3273 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3274 { 3275 struct jme_softc *sc = arg1; 3276 struct ifnet *ifp = &sc->arpcom.ac_if; 3277 int error, v; 3278 3279 ifnet_serialize_all(ifp); 3280 3281 v = sc->jme_rx_coal_pkt; 3282 error = sysctl_handle_int(oidp, &v, 0, req); 3283 if (error || req->newptr == NULL) 3284 goto back; 3285 3286 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) { 3287 error = EINVAL; 3288 goto back; 3289 } 3290 3291 if (v != sc->jme_rx_coal_pkt) { 3292 sc->jme_rx_coal_pkt = v; 3293 if (ifp->if_flags & IFF_RUNNING) 3294 jme_set_rx_coal(sc); 3295 } 3296 back: 3297 ifnet_deserialize_all(ifp); 3298 return error; 3299 } 3300 3301 static void 3302 jme_set_tx_coal(struct jme_softc *sc) 3303 { 3304 uint32_t reg; 3305 3306 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 3307 PCCTX_COAL_TO_MASK; 3308 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 3309 PCCTX_COAL_PKT_MASK; 3310 reg |= PCCTX_COAL_TXQ0; 3311 CSR_WRITE_4(sc, JME_PCCTX, reg); 3312 } 3313 3314 static void 3315 jme_set_rx_coal(struct jme_softc *sc) 3316 { 3317 uint32_t reg; 3318 int r; 3319 3320 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 3321 PCCRX_COAL_TO_MASK; 3322 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 3323 PCCRX_COAL_PKT_MASK; 3324 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) 3325 CSR_WRITE_4(sc, JME_PCCRX(r), reg); 3326 } 3327 3328 #ifdef IFPOLL_ENABLE 3329 3330 static void 3331 jme_npoll_status(struct ifnet *ifp) 3332 { 3333 struct jme_softc *sc = ifp->if_softc; 3334 uint32_t status; 3335 3336 ASSERT_SERIALIZED(&sc->jme_serialize); 3337 3338 status = CSR_READ_4(sc, JME_INTR_STATUS); 3339 if (status & INTR_RXQ_DESC_EMPTY) { 3340 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY); 3341 jme_rx_restart(sc, status); 3342 } 3343 } 3344 3345 static void 3346 jme_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle) 3347 { 3348 struct jme_rxdata *rdata = arg; 3349 3350 ASSERT_SERIALIZED(&rdata->jme_rx_serialize); 3351 3352 jme_rxeof(rdata, cycle, mycpuid); 3353 } 3354 3355 static void 3356 jme_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused) 3357 { 3358 struct jme_txdata *tdata = arg; 3359 3360 ASSERT_SERIALIZED(&tdata->jme_tx_serialize); 3361 3362 jme_txeof(tdata); 3363 if (!ifq_is_empty(&ifp->if_snd)) 3364 if_devstart(ifp); 3365 } 3366 3367 static void 3368 jme_npoll(struct ifnet *ifp, struct ifpoll_info *info) 3369 { 3370 struct jme_softc *sc = ifp->if_softc; 3371 3372 ASSERT_IFNET_SERIALIZED_ALL(ifp); 3373 3374 if (info) { 3375 int i, off; 3376 3377 info->ifpi_status.status_func = jme_npoll_status; 3378 info->ifpi_status.serializer = &sc->jme_serialize; 3379 3380 off = sc->jme_npoll_txoff; 3381 KKASSERT(off <= ncpus2); 3382 info->ifpi_tx[off].poll_func = jme_npoll_tx; 3383 info->ifpi_tx[off].arg = &sc->jme_cdata.jme_tx_data; 3384 info->ifpi_tx[off].serializer = 3385 &sc->jme_cdata.jme_tx_data.jme_tx_serialize; 3386 ifq_set_cpuid(&ifp->if_snd, sc->jme_npoll_txoff); 3387 3388 off = sc->jme_npoll_rxoff; 3389 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 3390 struct jme_rxdata *rdata = 3391 &sc->jme_cdata.jme_rx_data[i]; 3392 int idx = i + off; 3393 3394 info->ifpi_rx[idx].poll_func = jme_npoll_rx; 3395 info->ifpi_rx[idx].arg = rdata; 3396 info->ifpi_rx[idx].serializer = 3397 &rdata->jme_rx_serialize; 3398 } 3399 3400 if (ifp->if_flags & IFF_RUNNING) 3401 jme_disable_intr(sc); 3402 } else { 3403 ifq_set_cpuid(&ifp->if_snd, sc->jme_tx_cpuid); 3404 if (ifp->if_flags & IFF_RUNNING) 3405 jme_enable_intr(sc); 3406 } 3407 } 3408 3409 static int 3410 jme_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS) 3411 { 3412 struct jme_softc *sc = (void *)arg1; 3413 struct ifnet *ifp = &sc->arpcom.ac_if; 3414 int error, off; 3415 3416 off = sc->jme_npoll_rxoff; 3417 error = sysctl_handle_int(oidp, &off, 0, req); 3418 if (error || req->newptr == NULL) 3419 return error; 3420 if (off < 0) 3421 return EINVAL; 3422 3423 ifnet_serialize_all(ifp); 3424 if (off >= ncpus2 || off % sc->jme_cdata.jme_rx_ring_cnt != 0) { 3425 error = EINVAL; 3426 } else { 3427 error = 0; 3428 sc->jme_npoll_rxoff = off; 3429 } 3430 ifnet_deserialize_all(ifp); 3431 3432 return error; 3433 } 3434 3435 static int 3436 jme_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS) 3437 { 3438 struct jme_softc *sc = (void *)arg1; 3439 struct ifnet *ifp = &sc->arpcom.ac_if; 3440 int error, off; 3441 3442 off = sc->jme_npoll_txoff; 3443 error = sysctl_handle_int(oidp, &off, 0, req); 3444 if (error || req->newptr == NULL) 3445 return error; 3446 if (off < 0) 3447 return EINVAL; 3448 3449 ifnet_serialize_all(ifp); 3450 if (off >= ncpus2) { 3451 error = EINVAL; 3452 } else { 3453 error = 0; 3454 sc->jme_npoll_txoff = off; 3455 } 3456 ifnet_deserialize_all(ifp); 3457 3458 return error; 3459 } 3460 3461 #endif /* IFPOLL_ENABLE */ 3462 3463 static int 3464 jme_rxring_dma_alloc(struct jme_rxdata *rdata) 3465 { 3466 bus_dmamem_t dmem; 3467 int error, asize; 3468 3469 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN); 3470 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag, 3471 JME_RX_RING_ALIGN, 0, 3472 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 3473 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem); 3474 if (error) { 3475 device_printf(rdata->jme_sc->jme_dev, 3476 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx); 3477 return error; 3478 } 3479 rdata->jme_rx_ring_tag = dmem.dmem_tag; 3480 rdata->jme_rx_ring_map = dmem.dmem_map; 3481 rdata->jme_rx_ring = dmem.dmem_addr; 3482 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr; 3483 3484 return 0; 3485 } 3486 3487 static int 3488 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr) 3489 { 3490 if ((paddr & 0xffffffff) == 0) { 3491 /* 3492 * Don't allow lower 32bits of the RX buffer's 3493 * physical address to be 0, else it will break 3494 * hardware pending RSS information delivery 3495 * detection on RX path. 3496 */ 3497 return 1; 3498 } 3499 return 0; 3500 } 3501 3502 static int 3503 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata) 3504 { 3505 bus_addr_t lowaddr; 3506 int i, error; 3507 3508 lowaddr = BUS_SPACE_MAXADDR; 3509 if (JME_ENABLE_HWRSS(rdata->jme_sc)) { 3510 /* jme_rxbuf_dma_filter will be called */ 3511 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3512 } 3513 3514 /* Create tag for Rx buffers. */ 3515 error = bus_dma_tag_create( 3516 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */ 3517 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 3518 lowaddr, /* lowaddr */ 3519 BUS_SPACE_MAXADDR, /* highaddr */ 3520 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */ 3521 MCLBYTES, /* maxsize */ 3522 1, /* nsegments */ 3523 MCLBYTES, /* maxsegsize */ 3524 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */ 3525 &rdata->jme_rx_tag); 3526 if (error) { 3527 device_printf(rdata->jme_sc->jme_dev, 3528 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx); 3529 return error; 3530 } 3531 3532 /* Create DMA maps for Rx buffers. */ 3533 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK, 3534 &rdata->jme_rx_sparemap); 3535 if (error) { 3536 device_printf(rdata->jme_sc->jme_dev, 3537 "could not create %dth spare Rx dmamap.\n", 3538 rdata->jme_rx_idx); 3539 bus_dma_tag_destroy(rdata->jme_rx_tag); 3540 rdata->jme_rx_tag = NULL; 3541 return error; 3542 } 3543 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) { 3544 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i]; 3545 3546 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK, 3547 &rxd->rx_dmamap); 3548 if (error) { 3549 int j; 3550 3551 device_printf(rdata->jme_sc->jme_dev, 3552 "could not create %dth Rx dmamap " 3553 "for %dth RX ring.\n", i, rdata->jme_rx_idx); 3554 3555 for (j = 0; j < i; ++j) { 3556 rxd = &rdata->jme_rxdesc[j]; 3557 bus_dmamap_destroy(rdata->jme_rx_tag, 3558 rxd->rx_dmamap); 3559 } 3560 bus_dmamap_destroy(rdata->jme_rx_tag, 3561 rdata->jme_rx_sparemap); 3562 bus_dma_tag_destroy(rdata->jme_rx_tag); 3563 rdata->jme_rx_tag = NULL; 3564 return error; 3565 } 3566 } 3567 return 0; 3568 } 3569 3570 static void 3571 jme_rx_intr(struct jme_softc *sc, uint32_t status) 3572 { 3573 int r, cpuid = mycpuid; 3574 3575 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3576 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 3577 3578 if (status & rdata->jme_rx_coal) { 3579 lwkt_serialize_enter(&rdata->jme_rx_serialize); 3580 jme_rxeof(rdata, -1, cpuid); 3581 lwkt_serialize_exit(&rdata->jme_rx_serialize); 3582 } 3583 } 3584 } 3585 3586 static void 3587 jme_enable_rss(struct jme_softc *sc) 3588 { 3589 uint32_t rssc, ind; 3590 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE]; 3591 int i; 3592 3593 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 || 3594 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4, 3595 ("%s: invalid # of RX rings (%d)", 3596 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt)); 3597 3598 rssc = RSSC_HASH_64_ENTRY; 3599 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP; 3600 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1; 3601 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc); 3602 CSR_WRITE_4(sc, JME_RSSC, rssc); 3603 3604 toeplitz_get_key(key, sizeof(key)); 3605 for (i = 0; i < RSSKEY_NREGS; ++i) { 3606 uint32_t keyreg; 3607 3608 keyreg = RSSKEY_REGVAL(key, i); 3609 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x, reg 0x%08x\n", 3610 i, keyreg, RSSKEY_REG(RSSKEY_NREGS - 1 - i)); 3611 3612 CSR_WRITE_4(sc, RSSKEY_REG(RSSKEY_NREGS - 1 - i), keyreg); 3613 } 3614 3615 /* 3616 * Create redirect table in following fashion: 3617 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)] 3618 */ 3619 ind = 0; 3620 for (i = 0; i < RSSTBL_REGSIZE; ++i) { 3621 int q; 3622 3623 q = i % sc->jme_cdata.jme_rx_ring_cnt; 3624 ind |= q << (i * 8); 3625 } 3626 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind); 3627 3628 for (i = 0; i < RSSTBL_NREGS; ++i) 3629 CSR_WRITE_4(sc, RSSTBL_REG(i), ind); 3630 } 3631 3632 static void 3633 jme_disable_rss(struct jme_softc *sc) 3634 { 3635 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 3636 } 3637 3638 static void 3639 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz) 3640 { 3641 struct jme_softc *sc = ifp->if_softc; 3642 3643 ifnet_serialize_array_enter(sc->jme_serialize_arr, 3644 sc->jme_serialize_cnt, slz); 3645 } 3646 3647 static void 3648 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3649 { 3650 struct jme_softc *sc = ifp->if_softc; 3651 3652 ifnet_serialize_array_exit(sc->jme_serialize_arr, 3653 sc->jme_serialize_cnt, slz); 3654 } 3655 3656 static int 3657 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz) 3658 { 3659 struct jme_softc *sc = ifp->if_softc; 3660 3661 return ifnet_serialize_array_try(sc->jme_serialize_arr, 3662 sc->jme_serialize_cnt, slz); 3663 } 3664 3665 #ifdef INVARIANTS 3666 3667 static void 3668 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz, 3669 boolean_t serialized) 3670 { 3671 struct jme_softc *sc = ifp->if_softc; 3672 3673 ifnet_serialize_array_assert(sc->jme_serialize_arr, 3674 sc->jme_serialize_cnt, slz, serialized); 3675 } 3676 3677 #endif /* INVARIANTS */ 3678 3679 static void 3680 jme_msix_try_alloc(device_t dev) 3681 { 3682 struct jme_softc *sc = device_get_softc(dev); 3683 struct jme_msix_data *msix; 3684 int error, i, r, msix_enable, msix_count; 3685 int offset, offset_def; 3686 3687 msix_count = JME_MSIXCNT(sc->jme_cdata.jme_rx_ring_cnt); 3688 KKASSERT(msix_count <= JME_NMSIX); 3689 3690 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable); 3691 3692 /* 3693 * We leave the 1st MSI-X vector unused, so we 3694 * actually need msix_count + 1 MSI-X vectors. 3695 */ 3696 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1)) 3697 return; 3698 3699 for (i = 0; i < msix_count; ++i) 3700 sc->jme_msix[i].jme_msix_rid = -1; 3701 3702 i = 0; 3703 3704 /* 3705 * Setup status MSI-X 3706 */ 3707 3708 msix = &sc->jme_msix[i++]; 3709 msix->jme_msix_cpuid = 0; 3710 msix->jme_msix_arg = sc; 3711 msix->jme_msix_func = jme_msix_status; 3712 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3713 msix->jme_msix_intrs |= 3714 sc->jme_cdata.jme_rx_data[r].jme_rx_empty; 3715 } 3716 msix->jme_msix_serialize = &sc->jme_serialize; 3717 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s sts", 3718 device_get_nameunit(dev)); 3719 3720 /* 3721 * Setup TX MSI-X 3722 */ 3723 3724 offset_def = device_get_unit(dev) % ncpus2; 3725 offset = device_getenv_int(dev, "msix.txoff", offset_def); 3726 if (offset >= ncpus2) { 3727 device_printf(dev, "invalid msix.txoff %d, use %d\n", 3728 offset, offset_def); 3729 offset = offset_def; 3730 } 3731 3732 msix = &sc->jme_msix[i++]; 3733 msix->jme_msix_cpuid = offset; 3734 sc->jme_tx_cpuid = msix->jme_msix_cpuid; 3735 msix->jme_msix_arg = &sc->jme_cdata.jme_tx_data; 3736 msix->jme_msix_func = jme_msix_tx; 3737 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO; 3738 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_data.jme_tx_serialize; 3739 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx", 3740 device_get_nameunit(dev)); 3741 3742 /* 3743 * Setup RX MSI-X 3744 */ 3745 3746 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) { 3747 offset = 0; 3748 } else { 3749 offset_def = (sc->jme_cdata.jme_rx_ring_cnt * 3750 device_get_unit(dev)) % ncpus2; 3751 3752 offset = device_getenv_int(dev, "msix.rxoff", offset_def); 3753 if (offset >= ncpus2 || 3754 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) { 3755 device_printf(dev, "invalid msix.rxoff %d, use %d\n", 3756 offset, offset_def); 3757 offset = offset_def; 3758 } 3759 } 3760 3761 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) { 3762 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r]; 3763 3764 msix = &sc->jme_msix[i++]; 3765 msix->jme_msix_cpuid = r + offset; 3766 KKASSERT(msix->jme_msix_cpuid < ncpus2); 3767 msix->jme_msix_arg = rdata; 3768 msix->jme_msix_func = jme_msix_rx; 3769 msix->jme_msix_intrs = rdata->jme_rx_coal; 3770 msix->jme_msix_serialize = &rdata->jme_rx_serialize; 3771 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), 3772 "%s rx%d", device_get_nameunit(dev), r); 3773 } 3774 3775 KKASSERT(i == msix_count); 3776 3777 error = pci_setup_msix(dev); 3778 if (error) 3779 return; 3780 3781 /* Setup jme_msix_cnt early, so we could cleanup */ 3782 sc->jme_msix_cnt = msix_count; 3783 3784 for (i = 0; i < msix_count; ++i) { 3785 msix = &sc->jme_msix[i]; 3786 3787 msix->jme_msix_vector = i + 1; 3788 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector, 3789 &msix->jme_msix_rid, msix->jme_msix_cpuid); 3790 if (error) 3791 goto back; 3792 3793 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 3794 &msix->jme_msix_rid, RF_ACTIVE); 3795 if (msix->jme_msix_res == NULL) { 3796 error = ENOMEM; 3797 goto back; 3798 } 3799 } 3800 3801 for (i = 0; i < JME_INTR_CNT; ++i) { 3802 uint32_t intr_mask = (1 << i); 3803 int x; 3804 3805 if ((JME_INTRS & intr_mask) == 0) 3806 continue; 3807 3808 for (x = 0; x < msix_count; ++x) { 3809 msix = &sc->jme_msix[x]; 3810 if (msix->jme_msix_intrs & intr_mask) { 3811 int reg, shift; 3812 3813 reg = i / JME_MSINUM_FACTOR; 3814 KKASSERT(reg < JME_MSINUM_CNT); 3815 3816 shift = (i % JME_MSINUM_FACTOR) * 4; 3817 3818 sc->jme_msinum[reg] |= 3819 (msix->jme_msix_vector << shift); 3820 3821 break; 3822 } 3823 } 3824 } 3825 3826 if (bootverbose) { 3827 for (i = 0; i < JME_MSINUM_CNT; ++i) { 3828 device_printf(dev, "MSINUM%d: %#x\n", i, 3829 sc->jme_msinum[i]); 3830 } 3831 } 3832 3833 pci_enable_msix(dev); 3834 sc->jme_irq_type = PCI_INTR_TYPE_MSIX; 3835 3836 back: 3837 if (error) 3838 jme_msix_free(dev); 3839 } 3840 3841 static int 3842 jme_intr_alloc(device_t dev) 3843 { 3844 struct jme_softc *sc = device_get_softc(dev); 3845 u_int irq_flags; 3846 3847 jme_msix_try_alloc(dev); 3848 3849 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) { 3850 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable, 3851 &sc->jme_irq_rid, &irq_flags); 3852 3853 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 3854 &sc->jme_irq_rid, irq_flags); 3855 if (sc->jme_irq_res == NULL) { 3856 device_printf(dev, "can't allocate irq\n"); 3857 return ENXIO; 3858 } 3859 sc->jme_tx_cpuid = rman_get_cpuid(sc->jme_irq_res); 3860 } 3861 return 0; 3862 } 3863 3864 static void 3865 jme_msix_free(device_t dev) 3866 { 3867 struct jme_softc *sc = device_get_softc(dev); 3868 int i; 3869 3870 KKASSERT(sc->jme_msix_cnt > 1); 3871 3872 for (i = 0; i < sc->jme_msix_cnt; ++i) { 3873 struct jme_msix_data *msix = &sc->jme_msix[i]; 3874 3875 if (msix->jme_msix_res != NULL) { 3876 bus_release_resource(dev, SYS_RES_IRQ, 3877 msix->jme_msix_rid, msix->jme_msix_res); 3878 msix->jme_msix_res = NULL; 3879 } 3880 if (msix->jme_msix_rid >= 0) { 3881 pci_release_msix_vector(dev, msix->jme_msix_rid); 3882 msix->jme_msix_rid = -1; 3883 } 3884 } 3885 pci_teardown_msix(dev); 3886 } 3887 3888 static void 3889 jme_intr_free(device_t dev) 3890 { 3891 struct jme_softc *sc = device_get_softc(dev); 3892 3893 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) { 3894 if (sc->jme_irq_res != NULL) { 3895 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid, 3896 sc->jme_irq_res); 3897 } 3898 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI) 3899 pci_release_msi(dev); 3900 } else { 3901 jme_msix_free(dev); 3902 } 3903 } 3904 3905 static void 3906 jme_msix_tx(void *xtdata) 3907 { 3908 struct jme_txdata *tdata = xtdata; 3909 struct jme_softc *sc = tdata->jme_sc; 3910 struct ifnet *ifp = &sc->arpcom.ac_if; 3911 3912 ASSERT_SERIALIZED(&tdata->jme_tx_serialize); 3913 3914 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO); 3915 3916 CSR_WRITE_4(sc, JME_INTR_STATUS, 3917 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP); 3918 3919 if (ifp->if_flags & IFF_RUNNING) { 3920 jme_txeof(tdata); 3921 if (!ifq_is_empty(&ifp->if_snd)) 3922 if_devstart(ifp); 3923 } 3924 3925 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO); 3926 } 3927 3928 static void 3929 jme_msix_rx(void *xrdata) 3930 { 3931 struct jme_rxdata *rdata = xrdata; 3932 struct jme_softc *sc = rdata->jme_sc; 3933 struct ifnet *ifp = &sc->arpcom.ac_if; 3934 3935 ASSERT_SERIALIZED(&rdata->jme_rx_serialize); 3936 3937 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, rdata->jme_rx_coal); 3938 3939 CSR_WRITE_4(sc, JME_INTR_STATUS, 3940 rdata->jme_rx_coal | rdata->jme_rx_comp); 3941 3942 if (ifp->if_flags & IFF_RUNNING) 3943 jme_rxeof(rdata, -1, mycpuid); 3944 3945 CSR_WRITE_4(sc, JME_INTR_MASK_SET, rdata->jme_rx_coal); 3946 } 3947 3948 static void 3949 jme_msix_status(void *xsc) 3950 { 3951 struct jme_softc *sc = xsc; 3952 struct ifnet *ifp = &sc->arpcom.ac_if; 3953 uint32_t status; 3954 3955 ASSERT_SERIALIZED(&sc->jme_serialize); 3956 3957 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_RXQ_DESC_EMPTY); 3958 3959 status = CSR_READ_4(sc, JME_INTR_STATUS); 3960 3961 if (status & INTR_RXQ_DESC_EMPTY) { 3962 CSR_WRITE_4(sc, JME_INTR_STATUS, status & INTR_RXQ_DESC_EMPTY); 3963 if (ifp->if_flags & IFF_RUNNING) 3964 jme_rx_restart(sc, status); 3965 } 3966 3967 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_RXQ_DESC_EMPTY); 3968 } 3969 3970 static void 3971 jme_rx_restart(struct jme_softc *sc, uint32_t status) 3972 { 3973 int i, cpuid = mycpuid; 3974 3975 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) { 3976 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i]; 3977 3978 if (status & rdata->jme_rx_empty) { 3979 lwkt_serialize_enter(&rdata->jme_rx_serialize); 3980 jme_rxeof(rdata, -1, cpuid); 3981 #ifdef JME_RSS_DEBUG 3982 rdata->jme_rx_emp++; 3983 #endif 3984 lwkt_serialize_exit(&rdata->jme_rx_serialize); 3985 } 3986 } 3987 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 3988 RXCSR_RXQ_START); 3989 } 3990 3991 static void 3992 jme_set_msinum(struct jme_softc *sc) 3993 { 3994 int i; 3995 3996 for (i = 0; i < JME_MSINUM_CNT; ++i) 3997 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]); 3998 } 3999 4000 static int 4001 jme_intr_setup(device_t dev) 4002 { 4003 struct jme_softc *sc = device_get_softc(dev); 4004 int error; 4005 4006 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX) 4007 return jme_msix_setup(dev); 4008 4009 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, 4010 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize); 4011 if (error) { 4012 device_printf(dev, "could not set up interrupt handler.\n"); 4013 return error; 4014 } 4015 4016 return 0; 4017 } 4018 4019 static void 4020 jme_intr_teardown(device_t dev) 4021 { 4022 struct jme_softc *sc = device_get_softc(dev); 4023 4024 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX) 4025 jme_msix_teardown(dev, sc->jme_msix_cnt); 4026 else 4027 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle); 4028 } 4029 4030 static int 4031 jme_msix_setup(device_t dev) 4032 { 4033 struct jme_softc *sc = device_get_softc(dev); 4034 int x; 4035 4036 for (x = 0; x < sc->jme_msix_cnt; ++x) { 4037 struct jme_msix_data *msix = &sc->jme_msix[x]; 4038 int error; 4039 4040 error = bus_setup_intr_descr(dev, msix->jme_msix_res, 4041 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg, 4042 &msix->jme_msix_handle, msix->jme_msix_serialize, 4043 msix->jme_msix_desc); 4044 if (error) { 4045 device_printf(dev, "could not set up %s " 4046 "interrupt handler.\n", msix->jme_msix_desc); 4047 jme_msix_teardown(dev, x); 4048 return error; 4049 } 4050 } 4051 return 0; 4052 } 4053 4054 static void 4055 jme_msix_teardown(device_t dev, int msix_count) 4056 { 4057 struct jme_softc *sc = device_get_softc(dev); 4058 int x; 4059 4060 for (x = 0; x < msix_count; ++x) { 4061 struct jme_msix_data *msix = &sc->jme_msix[x]; 4062 4063 bus_teardown_intr(dev, msix->jme_msix_res, 4064 msix->jme_msix_handle); 4065 } 4066 } 4067 4068 static void 4069 jme_serialize_skipmain(struct jme_softc *sc) 4070 { 4071 lwkt_serialize_array_enter(sc->jme_serialize_arr, 4072 sc->jme_serialize_cnt, 1); 4073 } 4074 4075 static void 4076 jme_deserialize_skipmain(struct jme_softc *sc) 4077 { 4078 lwkt_serialize_array_exit(sc->jme_serialize_arr, 4079 sc->jme_serialize_cnt, 1); 4080 } 4081 4082 static void 4083 jme_enable_intr(struct jme_softc *sc) 4084 { 4085 int i; 4086 4087 for (i = 0; i < sc->jme_serialize_cnt; ++i) 4088 lwkt_serialize_handler_enable(sc->jme_serialize_arr[i]); 4089 4090 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 4091 } 4092 4093 static void 4094 jme_disable_intr(struct jme_softc *sc) 4095 { 4096 int i; 4097 4098 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 4099 4100 for (i = 0; i < sc->jme_serialize_cnt; ++i) 4101 lwkt_serialize_handler_disable(sc->jme_serialize_arr[i]); 4102 } 4103 4104 static void 4105 jme_phy_poweron(struct jme_softc *sc) 4106 { 4107 uint16_t bmcr; 4108 4109 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR); 4110 bmcr &= ~BMCR_PDOWN; 4111 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr); 4112 4113 if (sc->jme_caps & JME_CAP_PHYPWR) { 4114 uint32_t val; 4115 4116 val = CSR_READ_4(sc, JME_PHYPWR); 4117 val &= ~(PHYPWR_DOWN1SEL | PHYPWR_DOWN1SW | 4118 PHYPWR_DOWN2 | PHYPWR_CLKSEL); 4119 CSR_WRITE_4(sc, JME_PHYPWR, val); 4120 4121 val = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 4122 val &= ~PE1_GPREG0_PHYBG; 4123 val |= PE1_GPREG0_ENBG; 4124 pci_write_config(sc->jme_dev, JME_PCI_PE1, val, 4); 4125 } 4126 } 4127 4128 static void 4129 jme_phy_poweroff(struct jme_softc *sc) 4130 { 4131 uint16_t bmcr; 4132 4133 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR); 4134 bmcr |= BMCR_PDOWN; 4135 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr); 4136 4137 if (sc->jme_caps & JME_CAP_PHYPWR) { 4138 uint32_t val; 4139 4140 val = CSR_READ_4(sc, JME_PHYPWR); 4141 val |= PHYPWR_DOWN1SEL | PHYPWR_DOWN1SW | 4142 PHYPWR_DOWN2 | PHYPWR_CLKSEL; 4143 CSR_WRITE_4(sc, JME_PHYPWR, val); 4144 4145 val = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 4146 val &= ~PE1_GPREG0_PHYBG; 4147 val |= PE1_GPREG0_PDD3COLD; 4148 pci_write_config(sc->jme_dev, JME_PCI_PE1, val, 4); 4149 } 4150 } 4151 4152 static int 4153 jme_miiext_read(struct jme_softc *sc, int reg) 4154 { 4155 int addr; 4156 4157 addr = JME_MII_EXT_ADDR_RD | reg; 4158 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 4159 JME_MII_EXT_ADDR, addr); 4160 return jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, 4161 JME_MII_EXT_DATA); 4162 } 4163 4164 static void 4165 jme_miiext_write(struct jme_softc *sc, int reg, int val) 4166 { 4167 int addr; 4168 4169 addr = JME_MII_EXT_ADDR_WR | reg; 4170 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 4171 JME_MII_EXT_DATA, val); 4172 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 4173 JME_MII_EXT_ADDR, addr); 4174 } 4175 4176 static void 4177 jme_phy_init(struct jme_softc *sc) 4178 { 4179 uint16_t gtcr; 4180 int val; 4181 4182 jme_phy_poweroff(sc); 4183 jme_phy_poweron(sc); 4184 4185 /* Enable PHY test 1 */ 4186 gtcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR); 4187 gtcr &= ~GTCR_TEST_MASK; 4188 gtcr |= GTCR_TEST_1; 4189 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, gtcr); 4190 4191 val = jme_miiext_read(sc, JME_MII_EXT_COM2); 4192 val &= ~JME_MII_EXT_COM2_CALIB_MODE0; 4193 val |= JME_MII_EXT_COM2_CALIB_LATCH | JME_MII_EXT_COM2_CALIB_EN; 4194 jme_miiext_write(sc, JME_MII_EXT_COM2, val); 4195 4196 DELAY(20000); 4197 4198 val = jme_miiext_read(sc, JME_MII_EXT_COM2); 4199 val &= ~(JME_MII_EXT_COM2_CALIB_MODE0 | 4200 JME_MII_EXT_COM2_CALIB_LATCH | JME_MII_EXT_COM2_CALIB_EN); 4201 jme_miiext_write(sc, JME_MII_EXT_COM2, val); 4202 4203 /* Disable PHY test */ 4204 gtcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR); 4205 gtcr &= ~GTCR_TEST_MASK; 4206 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, gtcr); 4207 4208 if (sc->jme_phycom0 != 0) 4209 jme_miiext_write(sc, JME_MII_EXT_COM0, sc->jme_phycom0); 4210 if (sc->jme_phycom1 != 0) 4211 jme_miiext_write(sc, JME_MII_EXT_COM1, sc->jme_phycom1); 4212 } 4213