1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.1 2008/05/27 01:42:01 yongari Exp $ 28 * $DragonFly: src/sys/dev/netif/jme/if_jmereg.h,v 1.1 2008/07/26 14:00:31 sephe Exp $ 29 */ 30 31 #ifndef _IF_JMEREG_H 32 #define _IF_JMEREG_H 33 34 /* 35 * JMicron Inc. PCI vendor ID 36 */ 37 #define VENDORID_JMICRON 0x197B 38 39 /* 40 * JMC250 PCI device ID 41 */ 42 #define DEVICEID_JMC250 0x0250 43 #define DEVICEREVID_JMC250 0x10 44 45 /* 46 * JMC260 PCI device ID 47 */ 48 #define DEVICEID_JMC260 0x0260 49 #define DEVICEREVID_JMC260 0x20 50 51 /* JMC250 PCI configuration register. */ 52 #define JME_PCIR_BAR PCIR_BAR(0) 53 54 #define JME_PCI_EROM 0x30 55 56 #define JME_PCI_DBG 0x9C 57 58 #define JME_PCI_SPI 0xB0 59 60 #define SPI_ENB 0x00000010 61 #define SPI_SO_STATUS 0x00000008 62 #define SPI_SI_CTRL 0x00000004 63 #define SPI_SCK_CTRL 0x00000002 64 #define SPI_CS_N_CTRL 0x00000001 65 66 #define JME_PCI_PHYCFG0 0xC0 67 68 #define JME_PCI_PHYCFG1 0xC4 69 70 #define JME_PCI_PHYCFG2 0xC8 71 72 #define JME_PCI_PHYCFG3 0xCC 73 74 #define JME_PCI_PIPECTL1 0xD0 75 76 #define JME_PCI_PIPECTL2 0xD4 77 78 /* PCIe link error/status. */ 79 #define JME_PCI_LES 0xD8 80 81 /* propeietary register 0. */ 82 #define JME_PCI_PE0 0xE0 83 #define PE0_SPI_EXIST 0x00200000 84 #define PE0_PME_D0 0x00100000 85 #define PE0_PME_D3H 0x00080000 86 #define PE0_PME_SPI_PAD 0x00040000 87 #define PE0_MASK_ASPM 0x00020000 88 #define PE0_EEPROM_RW_DIS 0x00008000 89 #define PE0_PCI_INTA 0x00001000 90 #define PE0_PCI_INTB 0x00002000 91 #define PE0_PCI_INTC 0x00003000 92 #define PE0_PCI_INTD 0x00004000 93 #define PE0_PCI_SVSSID_WR_ENB 0x00000800 94 #define PE0_MSIX_SIZE_8 0x00000700 95 #define PE0_MSIX_SIZE_7 0x00000600 96 #define PE0_MSIX_SIZE_6 0x00000500 97 #define PE0_MSIX_SIZE_5 0x00000400 98 #define PE0_MSIX_SIZE_4 0x00000300 99 #define PE0_MSIX_SIZE_3 0x00000200 100 #define PE0_MSIX_SIZE_2 0x00000100 101 #define PE0_MSIX_SIZE_1 0x00000000 102 #define PE0_MSIX_SIZE_DEF 0x00000700 103 #define PE0_MSIX_CAP_DIS 0x00000080 104 #define PE0_MSI_PVMC_ENB 0x00000040 105 #define PE0_LCAP_EXIT_LAT_MASK 0x00000038 106 #define PE0_LCAP_EXIT_LAT_DEF 0x00000038 107 #define PE0_PM_AUXC_MASK 0x00000007 108 #define PE0_PM_AUXC_DEF 0x00000007 109 110 #define JME_PCI_PE1 0xE4 111 112 #define JME_PCI_PHYTEST 0xF8 113 114 #define JME_PCI_GPR 0xFC 115 116 /* 117 * JMC Register Map. 118 * ----------------------------------------------------------------------- 119 * Register Size IO space Memory space 120 * ----------------------------------------------------------------------- 121 * Tx/Rx MAC registers 128 bytes BAR1 + 0x00 ~ BAR0 + 0x00 ~ 122 * BAR1 + 0x7F BAR0 + 0x7F 123 * ----------------------------------------------------------------------- 124 * PHY registers 128 bytes BAR2 + 0x00 ~ BAR0 + 0x400 ~ 125 * BAR2 + 0x7F BAR0 + 0x47F 126 * ----------------------------------------------------------------------- 127 * Misc registers 128 bytes BAR2 + 0x80 ~ BAR0 + 0x800 ~ 128 * BAR2 + 0x7F BAR0 + 0x87F 129 * ----------------------------------------------------------------------- 130 * To simplify register access fuctions and to get better performance 131 * this driver doesn't support IO space access. It could be implemented 132 * as a function which selects appropriate BARs to access requested 133 * register. 134 */ 135 136 /* Tx control and status. */ 137 #define JME_TXCSR 0x0000 138 #define TXCSR_QWEIGHT_MASK 0x0F000000 139 #define TXCSR_QWEIGHT_SHIFT 24 140 #define TXCSR_TXQ_SEL_MASK 0x00070000 141 #define TXCSR_TXQ_SEL_SHIFT 16 142 #define TXCSR_TXQ_START 0x00000001 143 #define TXCSR_TXQ_START_SHIFT 8 144 #define TXCSR_FIFO_THRESH_4QW 0x00000000 145 #define TXCSR_FIFO_THRESH_8QW 0x00000040 146 #define TXCSR_FIFO_THRESH_12QW 0x00000080 147 #define TXCSR_FIFO_THRESH_16QW 0x000000C0 148 #define TXCSR_DMA_SIZE_64 0x00000000 149 #define TXCSR_DMA_SIZE_128 0x00000010 150 #define TXCSR_DMA_SIZE_256 0x00000020 151 #define TXCSR_DMA_SIZE_512 0x00000030 152 #define TXCSR_DMA_BURST 0x00000004 153 #define TXCSR_TX_SUSPEND 0x00000002 154 #define TXCSR_TX_ENB 0x00000001 155 #define TXCSR_TXQ0 0 156 #define TXCSR_TXQ1 1 157 #define TXCSR_TXQ2 2 158 #define TXCSR_TXQ3 3 159 #define TXCSR_TXQ4 4 160 #define TXCSR_TXQ5 5 161 #define TXCSR_TXQ6 6 162 #define TXCSR_TXQ7 7 163 #define TXCSR_TXQ_WEIGHT(x) \ 164 (((x) << TXCSR_QWEIGHT_SHIFT) & TXCSR_QWEIGHT_MASK) 165 #define TXCSR_TXQ_WEIGHT_MIN 0 166 #define TXCSR_TXQ_WEIGHT_MAX 15 167 #define TXCSR_TXQ_N_SEL(x) \ 168 (((x) << TXCSR_TXQ_SEL_SHIFT) & TXCSR_TXQ_SEL_MASK) 169 #define TXCSR_TXQ_N_START(x) \ 170 (TXCSR_TXQ_START << (TXCSR_TXQ_START_SHIFT + (x))) 171 172 /* Tx queue descriptor base address. 16bytes alignment required. */ 173 #define JME_TXDBA_LO 0x0004 174 #define JME_TXDBA_HI 0x0008 175 176 /* Tx queue descriptor count. multiple of 16(max = 1024). */ 177 #define JME_TXQDC 0x000C 178 #define TXQDC_MASK 0x0000007F0 179 180 /* Tx queue next descriptor address. */ 181 #define JME_TXNDA 0x0010 182 #define TXNDA_ADDR_MASK 0xFFFFFFF0 183 #define TXNDA_DESC_EMPTY 0x00000008 184 #define TXNDA_DESC_VALID 0x00000004 185 #define TXNDA_DESC_WAIT 0x00000002 186 #define TXNDA_DESC_FETCH 0x00000001 187 188 /* Tx MAC control ans status. */ 189 #define JME_TXMAC 0x0014 190 #define TXMAC_IFG2_MASK 0xC0000000 191 #define TXMAC_IFG2_DEFAULT 0x40000000 192 #define TXMAC_IFG1_MASK 0x30000000 193 #define TXMAC_IFG1_DEFAULT 0x20000000 194 #define TXMAC_THRESH_1_PKT 0x00000300 195 #define TXMAC_THRESH_1_2_PKT 0x00000200 196 #define TXMAC_THRESH_1_4_PKT 0x00000100 197 #define TXMAC_THRESH_1_8_PKT 0x00000000 198 #define TXMAC_FRAME_BURST 0x00000080 199 #define TXMAC_CARRIER_EXT 0x00000040 200 #define TXMAC_IFG_ENB 0x00000020 201 #define TXMAC_BACKOFF 0x00000010 202 #define TXMAC_CARRIER_SENSE 0x00000008 203 #define TXMAC_COLL_ENB 0x00000004 204 #define TXMAC_CRC_ENB 0x00000002 205 #define TXMAC_PAD_ENB 0x00000001 206 207 /* Tx pause frame control. */ 208 #define JME_TXPFC 0x0018 209 #define TXPFC_VLAN_TAG_MASK 0xFFFF0000 210 #define TXPFC_VLAN_TAG_SHIFT 16 211 #define TXPFC_VLAN_ENB 0x00008000 212 #define TXPFC_PAUSE_ENB 0x00000001 213 214 /* Tx timer/retry at half duplex. */ 215 #define JME_TXTRHD 0x001C 216 #define TXTRHD_RT_PERIOD_ENB 0x80000000 217 #define TXTRHD_RT_PERIOD_MASK 0x7FFFFF00 218 #define TXTRHD_RT_PERIOD_SHIFT 8 219 #define TXTRHD_RT_LIMIT_ENB 0x00000080 220 #define TXTRHD_RT_LIMIT_MASK 0x0000007F 221 #define TXTRHD_RT_LIMIT_SHIFT 0 222 #define TXTRHD_RT_PERIOD_DEFAULT 8192 223 #define TXTRHD_RT_LIMIT_DEFAULT 8 224 225 /* Rx control & status. */ 226 #define JME_RXCSR 0x0020 227 #define RXCSR_FIFO_FTHRESH_16T 0x00000000 228 #define RXCSR_FIFO_FTHRESH_32T 0x10000000 229 #define RXCSR_FIFO_FTHRESH_64T 0x20000000 230 #define RXCSR_FIFO_FTHRESH_128T 0x30000000 231 #define RXCSR_FIFO_FTHRESH_MASK 0x30000000 232 #define RXCSR_FIFO_THRESH_16QW 0x00000000 233 #define RXCSR_FIFO_THRESH_32QW 0x04000000 234 #define RXCSR_FIFO_THRESH_64QW 0x08000000 235 #define RXCSR_FIFO_THRESH_128QW 0x0C000000 236 #define RXCSR_FIFO_THRESH_MASK 0x0C000000 237 #define RXCSR_DMA_SIZE_16 0x00000000 238 #define RXCSR_DMA_SIZE_32 0x01000000 239 #define RXCSR_DMA_SIZE_64 0x02000000 240 #define RXCSR_DMA_SIZE_128 0x03000000 241 #define RXCSR_RXQ_SEL_MASK 0x00030000 242 #define RXCSR_RXQ_SEL_SHIFT 16 243 #define RXCSR_DESC_RT_GAP_MASK 0x0000F000 244 #define RXCSR_DESC_RT_GAP_SHIFT 12 245 #define RXCSR_DESC_RT_GAP_256 0x00000000 246 #define RXCSR_DESC_RT_GAP_512 0x00001000 247 #define RXCSR_DESC_RT_GAP_1024 0x00002000 248 #define RXCSR_DESC_RT_GAP_2048 0x00003000 249 #define RXCSR_DESC_RT_GAP_4096 0x00004000 250 #define RXCSR_DESC_RT_GAP_8192 0x00005000 251 #define RXCSR_DESC_RT_GAP_16384 0x00006000 252 #define RXCSR_DESC_RT_GAP_32768 0x00007000 253 #define RXCSR_DESC_RT_CNT_MASK 0x00000F00 254 #define RXCSR_DESC_RT_CNT_SHIFT 8 255 #define RXCSR_PASS_WAKEUP_PKT 0x00000040 256 #define RXCSR_PASS_MAGIC_PKT 0x00000020 257 #define RXCSR_PASS_RUNT_PKT 0x00000010 258 #define RXCSR_PASS_BAD_PKT 0x00000008 259 #define RXCSR_RXQ_START 0x00000004 260 #define RXCSR_RX_SUSPEND 0x00000002 261 #define RXCSR_RX_ENB 0x00000001 262 263 #define RXCSR_RXQ_N_SEL(x) ((x) << RXCSR_RXQ_SEL_SHIFT) 264 #define RXCSR_RXQ0 0 265 #define RXCSR_RXQ1 1 266 #define RXCSR_RXQ2 2 267 #define RXCSR_RXQ3 3 268 #define RXCSR_DESC_RT_CNT(x) \ 269 ((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK) 270 #define RXCSR_DESC_RT_CNT_DEFAULT 32 271 272 /* Rx queue descriptor base address. 16bytes alignment needed. */ 273 #define JME_RXDBA_LO 0x0024 274 #define JME_RXDBA_HI 0x0028 275 276 /* Rx queue descriptor count. multiple of 16(max = 1024). */ 277 #define JME_RXQDC 0x002C 278 #define RXQDC_MASK 0x0000007F0 279 280 /* Rx queue next descriptor address. */ 281 #define JME_RXNDA 0x0030 282 #define RXNDA_ADDR_MASK 0xFFFFFFF0 283 #define RXNDA_DESC_EMPTY 0x00000008 284 #define RXNDA_DESC_VALID 0x00000004 285 #define RXNDA_DESC_WAIT 0x00000002 286 #define RXNDA_DESC_FETCH 0x00000001 287 288 /* Rx MAC control and status. */ 289 #define JME_RXMAC 0x0034 290 #define RXMAC_RSS_UNICAST 0x00000000 291 #define RXMAC_RSS_UNI_MULTICAST 0x00010000 292 #define RXMAC_RSS_UNI_MULTI_BROADCAST 0x00020000 293 #define RXMAC_RSS_ALLFRAME 0x00030000 294 #define RXMAC_PROMISC 0x00000800 295 #define RXMAC_BROADCAST 0x00000400 296 #define RXMAC_MULTICAST 0x00000200 297 #define RXMAC_UNICAST 0x00000100 298 #define RXMAC_ALLMULTI 0x00000080 299 #define RXMAC_MULTICAST_FILTER 0x00000040 300 #define RXMAC_COLL_DET_ENB 0x00000020 301 #define RXMAC_FC_ENB 0x00000008 302 #define RXMAC_VLAN_ENB 0x00000004 303 #define RXMAC_PAD_10BYTES 0x00000002 304 #define RXMAC_CSUM_ENB 0x00000001 305 306 /* Rx unicast MAC address. */ 307 #define JME_PAR0 0x0038 308 #define JME_PAR1 0x003C 309 310 /* Rx multicast address hash table. */ 311 #define JME_MAR0 0x0040 312 #define JME_MAR1 0x0044 313 314 /* Wakeup frame output data port. */ 315 #define JME_WFODP 0x0048 316 317 /* Wakeup frame output interface. */ 318 #define JME_WFOI 0x004C 319 #define WFOI_MASK_0_31 0x00000000 320 #define WFOI_MASK_31_63 0x00000010 321 #define WFOI_MASK_64_95 0x00000020 322 #define WFOI_MASK_96_127 0x00000030 323 #define WFOI_MASK_SEL 0x00000008 324 #define WFOI_CRC_SEL 0x00000000 325 #define WFOI_WAKEUP_FRAME_MASK 0x00000007 326 #define WFOI_WAKEUP_FRAME_SEL(x) ((x) & WFOI_WAKEUP_FRAME_MASK) 327 328 /* Station management interface. */ 329 #define JME_SMI 0x0050 330 #define SMI_DATA_MASK 0xFFFF0000 331 #define SMI_DATA_SHIFT 16 332 #define SMI_REG_ADDR_MASK 0x0000F800 333 #define SMI_REG_ADDR_SHIFT 11 334 #define SMI_PHY_ADDR_MASK 0x000007C0 335 #define SMI_PHY_ADDR_SHIFT 6 336 #define SMI_OP_WRITE 0x00000020 337 #define SMI_OP_READ 0x00000000 338 #define SMI_OP_EXECUTE 0x00000010 339 #define SMI_MDIO 0x00000008 340 #define SMI_MDOE 0x00000004 341 #define SMI_MDC 0x00000002 342 #define SMI_MDEN 0x00000001 343 #define SMI_REG_ADDR(x) \ 344 (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK) 345 #define SMI_PHY_ADDR(x) \ 346 (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK) 347 348 /* Global host control. */ 349 #define JME_GHC 0x0054 350 #define GHC_LOOPBACK 0x80000000 351 #define GHC_RESET 0x40000000 352 #define GHC_FULL_DUPLEX 0x00000040 353 #define GHC_SPEED_UNKNOWN 0x00000000 354 #define GHC_SPEED_10 0x00000010 355 #define GHC_SPEED_100 0x00000020 356 #define GHC_SPEED_1000 0x00000030 357 #define GHC_SPEED_MASK 0x00000030 358 #define GHC_LINK_OFF 0x00000004 359 #define GHC_LINK_ON 0x00000002 360 #define GHC_LINK_STAT_POLLING 0x00000001 361 362 /* Power management control and status. */ 363 #define JME_PMCS 0x0060 364 #define PMCS_WAKEUP_FRAME_7 0x80000000 365 #define PMCS_WAKEUP_FRAME_6 0x40000000 366 #define PMCS_WAKEUP_FRAME_5 0x20000000 367 #define PMCS_WAKEUP_FRAME_4 0x10000000 368 #define PMCS_WAKEUP_FRAME_3 0x08000000 369 #define PMCS_WAKEUP_FRAME_2 0x04000000 370 #define PMCS_WAKEUP_FRAME_1 0x02000000 371 #define PMCS_WAKEUP_FRAME_0 0x01000000 372 #define PMCS_LINK_FAIL 0x00040000 373 #define PMCS_LINK_RISING 0x00020000 374 #define PMCS_MAGIC_FRAME 0x00010000 375 #define PMCS_WAKEUP_FRAME_7_ENB 0x00008000 376 #define PMCS_WAKEUP_FRAME_6_ENB 0x00004000 377 #define PMCS_WAKEUP_FRAME_5_ENB 0x00002000 378 #define PMCS_WAKEUP_FRAME_4_ENB 0x00001000 379 #define PMCS_WAKEUP_FRAME_3_ENB 0x00000800 380 #define PMCS_WAKEUP_FRAME_2_ENB 0x00000400 381 #define PMCS_WAKEUP_FRAME_1_ENB 0x00000200 382 #define PMCS_WAKEUP_FRAME_0_ENB 0x00000100 383 #define PMCS_LINK_FAIL_ENB 0x00000004 384 #define PMCS_LINK_RISING_ENB 0x00000002 385 #define PMCS_MAGIC_FRAME_ENB 0x00000001 386 #define PMCS_WOL_ENB_MASK 0x0000FFFF 387 388 /* Giga PHY & EEPROM registers. */ 389 #define JME_PHY_EEPROM_BASE_ADDR 0x0400 390 391 #define JME_GIGAR0LO 0x0400 392 #define JME_GIGAR0HI 0x0404 393 #define JME_GIGARALO 0x0408 394 #define JME_GIGARAHI 0x040C 395 #define JME_GIGARBLO 0x0410 396 #define JME_GIGARBHI 0x0414 397 #define JME_GIGARCLO 0x0418 398 #define JME_GIGARCHI 0x041C 399 #define JME_GIGARDLO 0x0420 400 #define JME_GIGARDHI 0x0424 401 402 /* BIST status and control. */ 403 #define JME_GIGACSR 0x0428 404 #define GIGACSR_STATUS 0x40000000 405 #define GIGACSR_CTRL_MASK 0x30000000 406 #define GIGACSR_CTRL_DEFAULT 0x30000000 407 #define GIGACSR_TX_CLK_MASK 0x0F000000 408 #define GIGACSR_RX_CLK_MASK 0x00F00000 409 #define GIGACSR_TX_CLK_INV 0x00080000 410 #define GIGACSR_RX_CLK_INV 0x00040000 411 #define GIGACSR_PHY_RST 0x00010000 412 #define GIGACSR_IRQ_N_O 0x00001000 413 #define GIGACSR_BIST_OK 0x00000200 414 #define GIGACSR_BIST_DONE 0x00000100 415 #define GIGACSR_BIST_LED_ENB 0x00000010 416 #define GIGACSR_BIST_MASK 0x00000003 417 418 /* PHY Link Status. */ 419 #define JME_LNKSTS 0x0430 420 #define LINKSTS_SPEED_10 0x00000000 421 #define LINKSTS_SPEED_100 0x00004000 422 #define LINKSTS_SPEED_1000 0x00008000 423 #define LINKSTS_FULL_DUPLEX 0x00002000 424 #define LINKSTS_PAGE_RCVD 0x00001000 425 #define LINKSTS_SPDDPX_RESOLVED 0x00000800 426 #define LINKSTS_UP 0x00000400 427 #define LINKSTS_ANEG_COMP 0x00000200 428 #define LINKSTS_MDI_CROSSOVR 0x00000040 429 #define LINKSTS_LPAR_PAUSE_ASYM 0x00000002 430 #define LINKSTS_LPAR_PAUSE 0x00000001 431 432 /* SMB control and status. */ 433 #define JME_SMBCSR 0x0440 434 #define SMBCSR_SLAVE_ADDR_MASK 0x7F000000 435 #define SMBCSR_WR_DATA_NACK 0x00040000 436 #define SMBCSR_CMD_NACK 0x00020000 437 #define SMBCSR_RELOAD 0x00010000 438 #define SMBCSR_CMD_ADDR_MASK 0x0000FF00 439 #define SMBCSR_SCL_STAT 0x00000080 440 #define SMBCSR_SDA_STAT 0x00000040 441 #define SMBCSR_EEPROM_PRESENT 0x00000020 442 #define SMBCSR_INIT_LD_DONE 0x00000010 443 #define SMBCSR_HW_BUSY_MASK 0x0000000F 444 #define SMBCSR_HW_IDLE 0x00000000 445 446 /* SMB interface. */ 447 #define JME_SMBINTF 0x0444 448 #define SMBINTF_RD_DATA_MASK 0xFF000000 449 #define SMBINTF_RD_DATA_SHIFT 24 450 #define SMBINTF_WR_DATA_MASK 0x00FF0000 451 #define SMBINTF_WR_DATA_SHIFT 16 452 #define SMBINTF_ADDR_MASK 0x0000FF00 453 #define SMBINTF_ADDR_SHIFT 8 454 #define SMBINTF_RD 0x00000020 455 #define SMBINTF_WR 0x00000000 456 #define SMBINTF_CMD_TRIGGER 0x00000010 457 #define SMBINTF_BUSY 0x00000010 458 #define SMBINTF_FAST_MODE 0x00000008 459 #define SMBINTF_GPIO_SCL 0x00000004 460 #define SMBINTF_GPIO_SDA 0x00000002 461 #define SMBINTF_GPIO_ENB 0x00000001 462 463 #define JME_EEPROM_SIG0 0x55 464 #define JME_EEPROM_SIG1 0xAA 465 #define JME_EEPROM_DESC_BYTES 3 466 #define JME_EEPROM_DESC_END 0x80 467 #define JME_EEPROM_FUNC_MASK 0x70 468 #define JME_EEPROM_FUNC_SHIFT 4 469 #define JME_EEPROM_PAGE_MASK 0x0F 470 #define JME_EEPROM_PAGE_SHIFT 0 471 472 #define JME_EEPROM_FUNC0 0 473 /* PCI configuration space. */ 474 #define JME_EEPROM_PAGE_BAR0 0 475 /* 128 bytes I/O window. */ 476 #define JME_EEPROM_PAGE_BAR1 1 477 /* 256 bytes I/O window. */ 478 #define JME_EEPROM_PAGE_BAR2 2 479 480 #define JME_EEPROM_END 0xFF 481 482 #define JME_EEPROM_MKDESC(f, p) \ 483 ((((f) & JME_EEPROM_FUNC_MASK) << JME_EEPROM_FUNC_SHIFT) | \ 484 (((p) & JME_EEPROM_PAGE_MASK) << JME_EEPROM_PAGE_SHIFT)) 485 486 /* 3-wire EEPROM interface. Obsolete interface, use SMBCSR. */ 487 #define JME_EEPINTF 0x0448 488 #define EEPINTF_DATA_MASK 0xFFFF0000 489 #define EEPINTF_DATA_SHIFT 16 490 #define EEPINTF_ADDR_MASK 0x0000FC00 491 #define EEPINTF_ADDR_SHIFT 10 492 #define EEPRINTF_OP_MASK 0x00000300 493 #define EEPINTF_OP_EXECUTE 0x00000080 494 #define EEPINTF_DATA_OUT 0x00000008 495 #define EEPINTF_DATA_IN 0x00000004 496 #define EEPINTF_CLK 0x00000002 497 #define EEPINTF_SEL 0x00000001 498 499 /* 3-wire EEPROM control and status. Obsolete interface, use SMBCSR. */ 500 #define JME_EEPCSR 0x044C 501 #define EEPCSR_EEPROM_RELOAD 0x00000002 502 #define EEPCSR_EEPROM_PRESENT 0x00000001 503 504 /* Misc registers. */ 505 #define JME_MISC_BASE_ADDR 0x800 506 507 /* Timer control and status. */ 508 #define JME_TMCSR 0x0800 509 #define TMCSR_SW_INTR 0x80000000 510 #define TMCSR_TIMER_INTR 0x10000000 511 #define TMCSR_TIMER_ENB 0x01000000 512 #define TMCSR_TIMER_COUNT_MASK 0x00FFFFFF 513 514 /* GPIO control and status. */ 515 #define JME_GPIO 0x0804 516 #define GPIO_4_SPI_IN 0x80000000 517 #define GPIO_3_SPI_IN 0x40000000 518 #define GPIO_4_SPI_OUT 0x20000000 519 #define GPIO_4_SPI_OUT_ENB 0x10000000 520 #define GPIO_3_SPI_OUT 0x08000000 521 #define GPIO_3_SPI_OUT_ENB 0x04000000 522 #define GPIO_3_4_LED 0x00000000 523 #define GPIO_3_4_GPIO 0x02000000 524 #define GPIO_2_CLKREQN_IN 0x00100000 525 #define GPIO_2_CLKREQN_OUT 0x00040000 526 #define GPIO_2_CLKREQN_OUT_ENB 0x00020000 527 #define GPIO_1_LED42_IN 0x00001000 528 #define GPIO_1_LED42_OUT 0x00000400 529 #define GPIO_1_LED42_OUT_ENB 0x00000200 530 #define GPIO_1_LED42_ENB 0x00000100 531 #define GPIO_0_SDA_IN 0x00000010 532 #define GPIO_0_SDA_OUT 0x00000004 533 #define GPIO_0_SDA_OUT_ENB 0x00000002 534 #define GPIO_0_SDA_ENB 0x00000001 535 536 /* General purpose register 0. */ 537 #define JME_GPREG0 0x0808 538 #define GPREG0_SH_POST_DW7_DIS 0x80000000 539 #define GPREG0_SH_POST_DW6_DIS 0x40000000 540 #define GPREG0_SH_POST_DW5_DIS 0x20000000 541 #define GPREG0_SH_POST_DW4_DIS 0x10000000 542 #define GPREG0_SH_POST_DW3_DIS 0x08000000 543 #define GPREG0_SH_POST_DW2_DIS 0x04000000 544 #define GPREG0_SH_POST_DW1_DIS 0x02000000 545 #define GPREG0_SH_POST_DW0_DIS 0x01000000 546 #define GPREG0_DMA_RD_REQ_8 0x00000000 547 #define GPREG0_DMA_RD_REQ_6 0x00100000 548 #define GPREG0_DMA_RD_REQ_5 0x00200000 549 #define GPREG0_DMA_RD_REQ_4 0x00300000 550 #define GPREG0_POST_DW0_ENB 0x00040000 551 #define GPREG0_PCC_CLR_DIS 0x00020000 552 #define GPREG0_FORCE_SCL_OUT 0x00010000 553 #define GPREG0_DL_RSTB_DIS 0x00008000 554 #define GPREG0_STICKY_RESET 0x00004000 555 #define GPREG0_DL_RSTB_CFG_DIS 0x00002000 556 #define GPREG0_LINK_CHG_POLL 0x00001000 557 #define GPREG0_LINK_CHG_DIRECT 0x00000000 558 #define GPREG0_MSI_GEN_SEL 0x00000800 559 #define GPREG0_SMB_PAD_PU_DIS 0x00000400 560 #define GPREG0_PCC_UNIT_16US 0x00000000 561 #define GPREG0_PCC_UNIT_256US 0x00000100 562 #define GPREG0_PCC_UNIT_US 0x00000200 563 #define GPREG0_PCC_UNIT_MS 0x00000300 564 #define GPREG0_PCC_UNIT_MASK 0x00000300 565 #define GPREG0_INTR_EVENT_ENB 0x00000080 566 #define GPREG0_PME_ENB 0x00000020 567 #define GPREG0_PHY_ADDR_MASK 0x0000001F 568 #define GPREG0_PHY_ADDR_SHIFT 0 569 #define GPREG0_PHY_ADDR 1 570 571 /* General purpose register 1. reserved for future use. */ 572 #define JME_GPREG1 0x080C 573 574 /* MSIX entry number of interrupt source. */ 575 #define JME_MSINUM_BASE 0x0810 576 #define JME_MSINUM_END 0x081F 577 #define MSINUM_MASK 0x7FFFFFFF 578 #define MSINUM_ENTRY_MASK 7 579 #define MSINUM_REG_INDEX(x) ((x) / 8) 580 #define MSINUM_INTR_SOURCE(x, y) \ 581 (((x) & MSINUM_ENTRY_MASK) << (((y) & 7) * 4)) 582 #define MSINUM_NUM_INTR_SOURCE 32 583 584 /* Interrupt event status. */ 585 #define JME_INTR_STATUS 0x0820 586 #define INTR_SW 0x80000000 587 #define INTR_TIMER 0x40000000 588 #define INTR_LINKCHG 0x20000000 589 #define INTR_PAUSE 0x10000000 590 #define INTR_MAGIC_PKT 0x08000000 591 #define INTR_WAKEUP_PKT 0x04000000 592 #define INTR_RXQ0_COAL_TO 0x02000000 593 #define INTR_RXQ1_COAL_TO 0x01000000 594 #define INTR_RXQ2_COAL_TO 0x00800000 595 #define INTR_RXQ3_COAL_TO 0x00400000 596 #define INTR_TXQ_COAL_TO 0x00200000 597 #define INTR_RXQ0_COAL 0x00100000 598 #define INTR_RXQ1_COAL 0x00080000 599 #define INTR_RXQ2_COAL 0x00040000 600 #define INTR_RXQ3_COAL 0x00020000 601 #define INTR_TXQ_COAL 0x00010000 602 #define INTR_RXQ3_DESC_EMPTY 0x00008000 603 #define INTR_RXQ2_DESC_EMPTY 0x00004000 604 #define INTR_RXQ1_DESC_EMPTY 0x00002000 605 #define INTR_RXQ0_DESC_EMPTY 0x00001000 606 #define INTR_RXQ3_COMP 0x00000800 607 #define INTR_RXQ2_COMP 0x00000400 608 #define INTR_RXQ1_COMP 0x00000200 609 #define INTR_RXQ0_COMP 0x00000100 610 #define INTR_TXQ7_COMP 0x00000080 611 #define INTR_TXQ6_COMP 0x00000040 612 #define INTR_TXQ5_COMP 0x00000020 613 #define INTR_TXQ4_COMP 0x00000010 614 #define INTR_TXQ3_COMP 0x00000008 615 #define INTR_TXQ2_COMP 0x00000004 616 #define INTR_TXQ1_COMP 0x00000002 617 #define INTR_TXQ0_COMP 0x00000001 618 619 #define INTR_RXQ_COAL_TO \ 620 (INTR_RXQ0_COAL_TO | INTR_RXQ1_COAL_TO | \ 621 INTR_RXQ2_COAL_TO | INTR_RXQ3_COAL_TO) 622 623 #define INTR_RXQ_COAL \ 624 (INTR_RXQ0_COAL | INTR_RXQ1_COAL | INTR_RXQ2_COAL | \ 625 INTR_RXQ3_COAL) 626 627 #define INTR_RXQ_COMP \ 628 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 629 INTR_RXQ3_COMP) 630 631 #define INTR_RXQ_DESC_EMPTY \ 632 (INTR_RXQ0_DESC_EMPTY | INTR_RXQ1_DESC_EMPTY | \ 633 INTR_RXQ2_DESC_EMPTY | INTR_RXQ3_DESC_EMPTY) 634 635 #define INTR_RXQ_COMP \ 636 (INTR_RXQ0_COMP | INTR_RXQ1_COMP | INTR_RXQ2_COMP | \ 637 INTR_RXQ3_COMP) 638 639 #define INTR_TXQ_COMP \ 640 (INTR_TXQ0_COMP | INTR_TXQ1_COMP | INTR_TXQ2_COMP | \ 641 INTR_TXQ3_COMP | INTR_TXQ4_COMP | INTR_TXQ5_COMP | \ 642 INTR_TXQ6_COMP | INTR_TXQ7_COMP) 643 644 #define JME_INTRS \ 645 (INTR_RXQ_COAL_TO | INTR_TXQ_COAL_TO | INTR_RXQ_COAL | \ 646 INTR_TXQ_COAL | INTR_RXQ_DESC_EMPTY) 647 648 #define N_INTR_SW 31 649 #define N_INTR_TIMER 30 650 #define N_INTR_LINKCHG 29 651 #define N_INTR_PAUSE 28 652 #define N_INTR_MAGIC_PKT 27 653 #define N_INTR_WAKEUP_PKT 26 654 #define N_INTR_RXQ0_COAL_TO 25 655 #define N_INTR_RXQ1_COAL_TO 24 656 #define N_INTR_RXQ2_COAL_TO 23 657 #define N_INTR_RXQ3_COAL_TO 22 658 #define N_INTR_TXQ_COAL_TO 21 659 #define N_INTR_RXQ0_COAL 20 660 #define N_INTR_RXQ1_COAL 19 661 #define N_INTR_RXQ2_COAL 18 662 #define N_INTR_RXQ3_COAL 17 663 #define N_INTR_TXQ_COAL 16 664 #define N_INTR_RXQ3_DESC_EMPTY 15 665 #define N_INTR_RXQ2_DESC_EMPTY 14 666 #define N_INTR_RXQ1_DESC_EMPTY 13 667 #define N_INTR_RXQ0_DESC_EMPTY 12 668 #define N_INTR_RXQ3_COMP 11 669 #define N_INTR_RXQ2_COMP 10 670 #define N_INTR_RXQ1_COMP 9 671 #define N_INTR_RXQ0_COMP 8 672 #define N_INTR_TXQ7_COMP 7 673 #define N_INTR_TXQ6_COMP 6 674 #define N_INTR_TXQ5_COMP 5 675 #define N_INTR_TXQ4_COMP 4 676 #define N_INTR_TXQ3_COMP 3 677 #define N_INTR_TXQ2_COMP 2 678 #define N_INTR_TXQ1_COMP 1 679 #define N_INTR_TXQ0_COMP 0 680 681 /* Interrupt request status. */ 682 #define JME_INTR_REQ_STATUS 0x0824 683 684 /* Interrupt enable - setting port. */ 685 #define JME_INTR_MASK_SET 0x0828 686 687 /* Interrupt enable - clearing port. */ 688 #define JME_INTR_MASK_CLR 0x082C 689 690 /* Packet completion coalescing control of Rx queue 0, 1, 2 and 3. */ 691 #define JME_PCCRX0 0x0830 692 #define JME_PCCRX1 0x0834 693 #define JME_PCCRX2 0x0838 694 #define JME_PCCRX3 0x083C 695 #define PCCRX_COAL_TO_MASK 0xFFFF0000 696 #define PCCRX_COAL_TO_SHIFT 16 697 #define PCCRX_COAL_PKT_MASK 0x0000FF00 698 #define PCCRX_COAL_PKT_SHIFT 8 699 700 #define PCCRX_COAL_TO_MIN 1 701 #define PCCRX_COAL_TO_DEFAULT 100 702 #define PCCRX_COAL_TO_MAX 65535 703 704 #define PCCRX_COAL_PKT_MIN 1 705 #define PCCRX_COAL_PKT_DEFAULT 2 706 #define PCCRX_COAL_PKT_MAX 255 707 708 /* Packet completion coalescing control of Tx queue. */ 709 #define JME_PCCTX 0x0840 710 #define PCCTX_COAL_TO_MASK 0xFFFF0000 711 #define PCCTX_COAL_TO_SHIFT 16 712 #define PCCTX_COAL_PKT_MASK 0x0000FF00 713 #define PCCTX_COAL_PKT_SHIFT 8 714 #define PCCTX_COAL_TXQ7 0x00000080 715 #define PCCTX_COAL_TXQ6 0x00000040 716 #define PCCTX_COAL_TXQ5 0x00000020 717 #define PCCTX_COAL_TXQ4 0x00000010 718 #define PCCTX_COAL_TXQ3 0x00000008 719 #define PCCTX_COAL_TXQ2 0x00000004 720 #define PCCTX_COAL_TXQ1 0x00000002 721 #define PCCTX_COAL_TXQ0 0x00000001 722 723 #define PCCTX_COAL_TO_MIN 1 724 #define PCCTX_COAL_TO_DEFAULT 100 725 #define PCCTX_COAL_TO_MAX 65535 726 727 #define PCCTX_COAL_PKT_MIN 1 728 #define PCCTX_COAL_PKT_DEFAULT 8 729 #define PCCTX_COAL_PKT_MAX 255 730 731 /* Chip mode and FPGA version. */ 732 #define JME_CHIPMODE 0x0844 733 #define CHIPMODE_FPGA_REV_MASK 0xFFFF0000 734 #define CHIPMODE_FPGA_REV_SHIFT 16 735 #define CHIPMODE_NOT_FPGA 0 736 #define CHIPMODE_REV_MASK 0x0000FF00 737 #define CHIPMODE_REV_SHIFT 8 738 #define CHIPMODE_MODE_48P 0x0000000C 739 #define CHIPMODE_MODE_64P 0x00000004 740 #define CHIPMODE_MODE_128P_MAC 0x00000003 741 #define CHIPMODE_MODE_128P_DBG 0x00000002 742 #define CHIPMODE_MODE_128P_PHY 0x00000000 743 744 /* Shadow status base address high/low. */ 745 #define JME_SHBASE_ADDR_HI 0x0848 746 #define JME_SHBASE_ADDR_LO 0x084C 747 #define SHBASE_ADDR_LO_MASK 0xFFFFFFE0 748 #define SHBASE_POST_FORCE 0x00000002 749 #define SHBASE_POST_ENB 0x00000001 750 751 /* Timer 1 and 2. */ 752 #define JME_TIMER1 0x0870 753 #define JME_TIMER2 0x0874 754 #define TIMER_ENB 0x01000000 755 #define TIMER_CNT_MASK 0x00FFFFFF 756 #define TIMER_CNT_SHIFT 0 757 #define TIMER_UNIT 1024 /* 1024us */ 758 759 /* Aggresive power mode control. */ 760 #define JME_APMC 0x087C 761 #define APMC_PCIE_SDOWN_STAT 0x80000000 762 #define APMC_PCIE_SDOWN_ENB 0x40000000 763 #define APMC_PSEUDO_HOT_PLUG 0x20000000 764 #define APMC_EXT_PLUGIN_ENB 0x04000000 765 #define APMC_EXT_PLUGIN_CTL_MSK 0x03000000 766 #define APMC_DIS_SRAM 0x00000004 767 #define APMC_DIS_CLKPM 0x00000002 768 #define APMC_DIS_CLKTX 0x00000001 769 770 /* Packet completion coalesing status of Rx queue 0, 1, 2 and 3. */ 771 #define JME_PCCSRX_BASE 0x0880 772 #define JME_PCCSRX_END 0x088F 773 #define PCCSRX_REG(x) (JME_PCCSRX_BASE + ((x) * 4)) 774 #define PCCSRX_TO_MASK 0xFFFF0000 775 #define PCCSRX_TO_SHIFT 16 776 #define PCCSRX_PKT_CNT_MASK 0x0000FF00 777 #define PCCSRX_PKT_CNT_SHIFT 8 778 779 /* Packet completion coalesing status of Tx queue. */ 780 #define JME_PCCSTX 0x0890 781 #define PCCSTX_TO_MASK 0xFFFF0000 782 #define PCCSTX_TO_SHIFT 16 783 #define PCCSTX_PKT_CNT_MASK 0x0000FF00 784 #define PCCSTX_PKT_CNT_SHIFT 8 785 786 /* Tx queues empty indicator. */ 787 #define JME_TXQEMPTY 0x0894 788 #define TXQEMPTY_TXQ7 0x00000080 789 #define TXQEMPTY_TXQ6 0x00000040 790 #define TXQEMPTY_TXQ5 0x00000020 791 #define TXQEMPTY_TXQ4 0x00000010 792 #define TXQEMPTY_TXQ3 0x00000008 793 #define TXQEMPTY_TXQ2 0x00000004 794 #define TXQEMPTY_TXQ1 0x00000002 795 #define TXQEMPTY_TXQ0 0x00000001 796 #define TXQEMPTY_N_TXQ(x, y) ((x) & (0x01 << (y))) 797 798 /* RSS control registers. */ 799 #define JME_RSS_BASE 0x0C00 800 801 #define JME_RSSC 0x0C00 802 #define RSSC_HASH_LEN_MASK 0x0000E000 803 #define RSSC_HASH_64_ENTRY 0x0000A000 804 #define RSSC_HASH_128_ENTRY 0x0000E000 805 #define RSSC_HASH_NONE 0x00001000 806 #define RSSC_HASH_IPV6 0x00000800 807 #define RSSC_HASH_IPV4 0x00000400 808 #define RSSC_HASH_IPV6_TCP 0x00000200 809 #define RSSC_HASH_IPV4_TCP 0x00000100 810 #define RSSC_NCPU_MASK 0x000000F8 811 #define RSSC_NCPU_SHIFT 3 812 #define RSSC_DIS_RSS 0x00000000 813 #define RSSC_2RXQ_ENB 0x00000001 814 #define RSSS_4RXQ_ENB 0x00000002 815 816 /* CPU vector. */ 817 #define JME_RSSCPU 0x0C04 818 #define RSSCPU_N_SEL(x) ((1 << (x)) 819 820 /* RSS Hash value. */ 821 #define JME_RSSHASH 0x0C10 822 823 #define JME_RSSHASH_STAT 0x0C14 824 825 #define JME_RSS_RDATA0 0x0C18 826 827 #define JME_RSS_RDATA1 0x0C1C 828 829 /* RSS secret key. */ 830 #define JME_RSSKEY_BASE 0x0C40 831 #define JME_RSSKEY_LAST 0x0C64 832 #define JME_RSSKEY_END 0x0C67 833 #define HASHKEY_NBYTES 40 834 #define RSSKEY_REG(x) (JME_RSSKEY_LAST - (4 * ((x) / 4))) 835 #define RSSKEY_VALUE(x, y) ((x) << (24 - 8 * ((y) % 4))) 836 837 /* RSS indirection table entries. */ 838 #define JME_RSSTBL_BASE 0x0C80 839 #define JME_RSSTBL_END 0x0CFF 840 #define RSSTBL_NENTRY 128 841 #define RSSTBL_REG(x) (JME_RSSTBL_BASE + ((x) / 4)) 842 #define RSSTBL_VALUE(x, y) ((x) << (8 * ((y) % 4))) 843 844 /* MSI-X table. */ 845 #define JME_MSIX_BASE_ADDR 0x2000 846 847 #define JME_MSIX_BASE 0x2000 848 #define JME_MSIX_END 0x207F 849 #define JME_MSIX_NENTRY 8 850 #define MSIX_REG(x) (JME_MSIX_BASE + ((x) * 0x10)) 851 #define MSIX_ADDR_HI_OFF 0x00 852 #define MSIX_ADDR_LO_OFF 0x04 853 #define MSIX_ADDR_LO_MASK 0xFFFFFFFC 854 #define MSIX_DATA_OFF 0x08 855 #define MSIX_VECTOR_OFF 0x0C 856 #define MSIX_VECTOR_RSVD 0x80000000 857 #define MSIX_VECTOR_DIS 0x00000001 858 859 /* MSI-X PBA. */ 860 #define JME_MSIX_PBA_BASE_ADDR 0x3000 861 862 #define JME_MSIX_PBA 0x3000 863 #define MSIX_PBA_RSVD_MASK 0xFFFFFF00 864 #define MSIX_PBA_RSVD_SHIFT 8 865 #define MSIX_PBA_PEND_MASK 0x000000FF 866 #define MSIX_PBA_PEND_SHIFT 0 867 #define MSIX_PBA_PEND_ENTRY7 0x00000080 868 #define MSIX_PBA_PEND_ENTRY6 0x00000040 869 #define MSIX_PBA_PEND_ENTRY5 0x00000020 870 #define MSIX_PBA_PEND_ENTRY4 0x00000010 871 #define MSIX_PBA_PEND_ENTRY3 0x00000008 872 #define MSIX_PBA_PEND_ENTRY2 0x00000004 873 #define MSIX_PBA_PEND_ENTRY1 0x00000002 874 #define MSIX_PBA_PEND_ENTRY0 0x00000001 875 876 #define JME_PHY_OUI 0x001B8C 877 #define JME_PHY_MODEL 0x21 878 #define JME_PHY_REV 0x01 879 #define JME_PHY_ADDR 1 880 881 /* JMC250 shadow status block. */ 882 struct jme_ssb { 883 uint32_t dw0; 884 uint32_t dw1; 885 uint32_t dw2; 886 uint32_t dw3; 887 uint32_t dw4; 888 uint32_t dw5; 889 uint32_t dw6; 890 uint32_t dw7; 891 }; 892 893 /* JMC250 descriptor structures. */ 894 struct jme_desc { 895 uint32_t flags; 896 uint32_t buflen; 897 uint32_t addr_hi; 898 uint32_t addr_lo; 899 }; 900 901 #define JME_TD_OWN 0x80000000 902 #define JME_TD_INTR 0x40000000 903 #define JME_TD_64BIT 0x20000000 904 #define JME_TD_TCPCSUM 0x10000000 905 #define JME_TD_UDPCSUM 0x08000000 906 #define JME_TD_IPCSUM 0x04000000 907 #define JME_TD_TSO 0x02000000 908 #define JME_TD_VLAN_TAG 0x01000000 909 #define JME_TD_VLAN_MASK 0x0000FFFF 910 911 #define JME_TD_MSS_MASK 0xFFFC0000 912 #define JME_TD_MSS_SHIFT 18 913 #define JME_TD_BUF_LEN_MASK 0x0000FFFF 914 #define JME_TD_BUF_LEN_SHIFT 0 915 916 #define JME_TD_FRAME_LEN_MASK 0x0000FFFF 917 #define JME_TD_FRAME_LEN_SHIFT 0 918 919 /* 920 * Only the first Tx descriptor of a packet is updated 921 * after packet transmission. 922 */ 923 #define JME_TD_TMOUT 0x20000000 924 #define JME_TD_RETRY_EXP 0x10000000 925 #define JME_TD_COLLISION 0x08000000 926 #define JME_TD_UNDERRUN 0x04000000 927 #define JME_TD_EHDR_SIZE_MASK 0x000000FF 928 #define JME_TD_EHDR_SIZE_SHIFT 0 929 930 #define JME_TD_SEG_CNT_MASK 0xFFFF0000 931 #define JME_TD_SEG_CNT_SHIFT 16 932 #define JME_TD_RETRY_CNT_MASK 0x0000FFFF 933 #define JME_TD_RETRY_CNT_SHIFT 0 934 935 #define JME_RD_OWN 0x80000000 936 #define JME_RD_INTR 0x40000000 937 #define JME_RD_64BIT 0x20000000 938 939 #define JME_RD_BUF_LEN_MASK 0x0000FFFF 940 #define JME_RD_BUF_LEN_SHIFT 0 941 942 /* 943 * Only the first Rx descriptor of a packet is updated 944 * after packet reception. 945 */ 946 #define JME_RD_MORE_FRAG 0x20000000 947 #define JME_RD_TCP 0x10000000 948 #define JME_RD_UDP 0x08000000 949 #define JME_RD_IPCSUM 0x04000000 950 #define JME_RD_TCPCSUM 0x02000000 951 #define JME_RD_UDPCSUM 0x01000000 952 #define JME_RD_VLAN_TAG 0x00800000 953 #define JME_RD_IPV4 0x00400000 954 #define JME_RD_IPV6 0x00200000 955 #define JME_RD_PAUSE 0x00100000 956 #define JME_RD_MAGIC 0x00080000 957 #define JME_RD_WAKEUP 0x00040000 958 #define JME_RD_BCAST 0x00030000 959 #define JME_RD_MCAST 0x00020000 960 #define JME_RD_UCAST 0x00010000 961 #define JME_RD_VLAN_MASK 0x0000FFFF 962 #define JME_RD_VLAN_SHIFT 0 963 964 #define JME_RD_VALID 0x80000000 965 #define JME_RD_CNT_MASK 0x7F000000 966 #define JME_RD_CNT_SHIFT 24 967 #define JME_RD_GIANT 0x00800000 968 #define JME_RD_GMII_ERR 0x00400000 969 #define JME_RD_NBL_RCVD 0x00200000 970 #define JME_RD_COLL 0x00100000 971 #define JME_RD_ABORT 0x00080000 972 #define JME_RD_RUNT 0x00040000 973 #define JME_RD_FIFO_OVRN 0x00020000 974 #define JME_RD_CRC_ERR 0x00010000 975 #define JME_RD_FRAME_LEN_MASK 0x0000FFFF 976 977 #define JME_RX_ERR_STAT \ 978 (JME_RD_GIANT | JME_RD_GMII_ERR | JME_RD_NBL_RCVD | \ 979 JME_RD_COLL | JME_RD_ABORT | JME_RD_RUNT | \ 980 JME_RD_FIFO_OVRN | JME_RD_CRC_ERR) 981 982 #define JME_RD_ERR_MASK 0x00FF0000 983 #define JME_RD_ERR_SHIFT 16 984 #define JME_RX_ERR(x) (((x) & JME_RD_ERR_MASK) >> JME_RD_ERR_SHIFT) 985 #define JME_RX_ERR_BITS "\20" \ 986 "\1CRCERR\2FIFOOVRN\3RUNT\4ABORT" \ 987 "\5COLL\6NBLRCVD\7GMIIERR\10" 988 989 #define JME_RX_NSEGS(x) (((x) & JME_RD_CNT_MASK) >> JME_RD_CNT_SHIFT) 990 #define JME_RX_BYTES(x) ((x) & JME_RD_FRAME_LEN_MASK) 991 #define JME_RX_PAD_BYTES 10 992 993 #define JME_RD_RSS_HASH_VALUE 0xFFFFFFFF 994 995 #define JME_RD_RSS_HASH_MASK 0x00003F00 996 #define JME_RD_RSS_HASH_SHIFT 8 997 #define JME_RD_RSS_HASH_NONE 0x00000000 998 #define JME_RD_RSS_HASH_IPV4 0x00000100 999 #define JME_RD_RSS_HASH_IPV4TCP 0x00000200 1000 #define JME_RD_RSS_HASH_IPV6 0x00000400 1001 #define JME_RD_RSS_HASH_IPV6TCP 0x00001000 1002 #define JME_RD_HASH_FN_NONE 0x00000000 1003 #define JME_RD_HASH_FN_TOEPLITZ 0x00000001 1004 1005 #endif 1006