xref: /dragonfly/sys/dev/netif/jme/if_jmevar.h (revision 9a92bb4c)
1 /*-
2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD: src/sys/dev/jme/if_jmevar.h,v 1.1 2008/05/27 01:42:01 yongari Exp $
28  * $DragonFly: src/sys/dev/netif/jme/if_jmevar.h,v 1.7 2008/10/25 10:46:55 sephe Exp $
29  */
30 
31 #ifndef	_IF_JMEVAR_H
32 #define	_IF_JMEVAR_H
33 
34 #include <sys/queue.h>
35 #include <sys/callout.h>
36 #include <sys/taskqueue.h>
37 
38 /*
39  * JMC250 supports upto 1024 descriptors and the number of
40  * descriptors should be multiple of 16.
41  */
42 #define	JME_TX_RING_CNT		384
43 #define	JME_RX_RING_CNT		256
44 /*
45  * Tx/Rx descriptor queue base should be 16bytes aligned and
46  * should not cross 4G bytes boundary on the 64bits address
47  * mode.
48  */
49 #define	JME_TX_RING_ALIGN	16
50 #define	JME_RX_RING_ALIGN	16
51 #define	JME_TSO_MAXSEGSIZE	4096
52 #define	JME_TSO_MAXSIZE		(65535 + sizeof(struct ether_vlan_header))
53 #define	JME_MAXTXSEGS		32
54 #define	JME_RX_BUF_ALIGN	sizeof(uint64_t)
55 #define	JME_SSB_ALIGN		16
56 
57 #define	JME_ADDR_LO(x)		((uint64_t) (x) & 0xFFFFFFFF)
58 #define	JME_ADDR_HI(x)		((uint64_t) (x) >> 32)
59 
60 #define	JME_MSI_MESSAGES	8
61 #define	JME_MSIX_MESSAGES	8
62 
63 /* Water mark to kick reclaiming Tx buffers. */
64 #define	JME_TX_DESC_HIWAT	(JME_TX_RING_CNT - (((JME_TX_RING_CNT) * 3) / 10))
65 
66 /*
67  * JMC250 can send 9K jumbo frame on Tx path and can receive
68  * 65535 bytes.
69  */
70 #define JME_JUMBO_FRAMELEN	9216
71 #define JME_JUMBO_MTU							\
72 	(JME_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) -	\
73 	 ETHER_HDR_LEN - ETHER_CRC_LEN)
74 #define	JME_MAX_MTU							\
75 	(ETHER_MAX_LEN + sizeof(struct ether_vlan_header) -		\
76 	 ETHER_HDR_LEN - ETHER_CRC_LEN)
77 /*
78  * JMC250 can't handle Tx checksum offload/TSO if frame length
79  * is larger than its FIFO size(2K). It's also good idea to not
80  * use jumbo frame if hardware is running at half-duplex media.
81  * Because the jumbo frame may not fit into the Tx FIFO,
82  * collisions make hardware fetch frame from host memory with
83  * DMA again which in turn slows down Tx performance
84  * significantly.
85  */
86 #define	JME_TX_FIFO_SIZE	2000
87 /*
88  * JMC250 has just 4K Rx FIFO. To support jumbo frame that is
89  * larger than 4K bytes in length, Rx FIFO threshold should be
90  * adjusted to minimize Rx FIFO overrun.
91  */
92 #define	JME_RX_FIFO_SIZE	4000
93 
94 #define	JME_DESC_INC(x, y)	((x) = ((x) + 1) % (y))
95 
96 #define	JME_PROC_MIN		10
97 #define	JME_PROC_DEFAULT	(JME_RX_RING_CNT / 2)
98 #define	JME_PROC_MAX		(JME_RX_RING_CNT - 1)
99 
100 struct jme_txdesc {
101 	struct mbuf		*tx_m;
102 	bus_dmamap_t		tx_dmamap;
103 	int			tx_ndesc;
104 	struct jme_desc		*tx_desc;
105 };
106 
107 struct jme_rxdesc {
108 	struct mbuf 		*rx_m;
109 	bus_dmamap_t		rx_dmamap;
110 	struct jme_desc		*rx_desc;
111 };
112 
113 struct jme_chain_data{
114 	bus_dma_tag_t		jme_ring_tag;
115 	bus_dma_tag_t		jme_buffer_tag;
116 	bus_dma_tag_t		jme_ssb_tag;
117 	bus_dmamap_t		jme_ssb_map;
118 	bus_dma_tag_t		jme_tx_tag;
119 	struct jme_txdesc	jme_txdesc[JME_TX_RING_CNT];
120 	bus_dma_tag_t		jme_rx_tag;
121 	struct jme_rxdesc	jme_rxdesc[JME_RX_RING_CNT];
122 	bus_dma_tag_t		jme_tx_ring_tag;
123 	bus_dmamap_t		jme_tx_ring_map;
124 	bus_dma_tag_t		jme_rx_ring_tag;
125 	bus_dmamap_t		jme_rx_ring_map;
126 	bus_dmamap_t		jme_rx_sparemap;
127 
128 	int			jme_tx_prod;
129 	int			jme_tx_cons;
130 	int			jme_tx_cnt;
131 
132 	int			jme_rx_cons;
133 	int			jme_rxlen;
134 	struct mbuf		*jme_rxhead;
135 	struct mbuf		*jme_rxtail;
136 };
137 
138 struct jme_ring_data {
139 	struct jme_desc		*jme_tx_ring;
140 	bus_addr_t		jme_tx_ring_paddr;
141 	struct jme_desc		*jme_rx_ring;
142 	bus_addr_t		jme_rx_ring_paddr;
143 	struct jme_ssb		*jme_ssb_block;
144 	bus_addr_t		jme_ssb_block_paddr;
145 };
146 
147 #define JME_TX_RING_ADDR(sc, i)	\
148     ((sc)->jme_rdata.jme_tx_ring_paddr + sizeof(struct jme_desc) * (i))
149 #define JME_RX_RING_ADDR(sc, i)	\
150     ((sc)->jme_rdata.jme_rx_ring_paddr + sizeof(struct jme_desc) * (i))
151 
152 #define JME_TX_RING_SIZE	\
153     (sizeof(struct jme_desc) * JME_TX_RING_CNT)
154 #define JME_RX_RING_SIZE	\
155     (sizeof(struct jme_desc) * JME_RX_RING_CNT)
156 #define	JME_SSB_SIZE		sizeof(struct jme_ssb)
157 
158 struct jme_dmamap_ctx {
159 	int			nsegs;
160 	bus_dma_segment_t	*segs;
161 };
162 
163 /*
164  * Software state per device.
165  */
166 struct jme_softc {
167 	struct arpcom		arpcom;
168 	device_t		jme_dev;
169 
170 	int			jme_mem_rid;
171 	struct resource		*jme_mem_res;
172 	bus_space_tag_t		jme_mem_bt;
173 	bus_space_handle_t	jme_mem_bh;
174 
175 	int			jme_irq_rid;
176 	struct resource		*jme_irq_res;
177 	void			*jme_irq_handle;
178 
179 	device_t		jme_miibus;
180 	int			jme_phyaddr;
181 
182 	uint32_t		jme_tx_dma_size;
183 	uint32_t		jme_rx_dma_size;
184 
185 	uint32_t		jme_caps;
186 #define	JME_CAP_FPGA		0x0001
187 #define	JME_CAP_PCIE		0x0002
188 #define	JME_CAP_PMCAP		0x0004
189 #define	JME_CAP_FASTETH		0x0008
190 #define	JME_CAP_JUMBO		0x0010
191 
192 	uint32_t		jme_workaround;
193 #define JME_WA_EXTFIFO		0x0001
194 #define JME_WA_HDX		0x0002
195 
196 	uint32_t		jme_flags;
197 #define	JME_FLAG_MSI		0x0001
198 #define	JME_FLAG_MSIX		0x0002
199 #define	JME_FLAG_DETACH		0x0004
200 #define	JME_FLAG_LINK		0x0008
201 
202 	struct callout		jme_tick_ch;
203 	struct jme_chain_data	jme_cdata;
204 	struct jme_ring_data	jme_rdata;
205 	int			jme_if_flags;
206 	uint32_t		jme_txcsr;
207 	uint32_t		jme_rxcsr;
208 
209 	int			jme_txd_spare;
210 
211 	struct sysctl_ctx_list	jme_sysctl_ctx;
212 	struct sysctl_oid	*jme_sysctl_tree;
213 
214 	/*
215 	 * Sysctl variables
216 	 */
217 	int			jme_tx_coal_to;
218 	int			jme_tx_coal_pkt;
219 	int			jme_rx_coal_to;
220 	int			jme_rx_coal_pkt;
221 };
222 
223 /* Register access macros. */
224 #define CSR_WRITE_4(_sc, reg, val)	\
225 	bus_space_write_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg), (val))
226 #define CSR_READ_4(_sc, reg)		\
227 	bus_space_read_4((_sc)->jme_mem_bt, (_sc)->jme_mem_bh, (reg))
228 
229 #define	JME_MAXERR	5
230 
231 #define	JME_RXCHAIN_RESET(_sc)						\
232 do {									\
233 	(_sc)->jme_cdata.jme_rxhead = NULL;				\
234 	(_sc)->jme_cdata.jme_rxtail = NULL;				\
235 	(_sc)->jme_cdata.jme_rxlen = 0;					\
236 } while (0)
237 
238 #define	JME_TX_TIMEOUT		5
239 #define JME_TIMEOUT		1000
240 #define JME_PHY_TIMEOUT		1000
241 #define JME_EEPROM_TIMEOUT	1000
242 
243 #define JME_TXD_RSVD		1
244 
245 #endif
246