1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.38 2006/12/22 23:26:20 swildner Exp $ 35 */ 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * Written by Bill Paul <william.paul@windriver.com> 42 * Wind River Systems 43 */ 44 45 /* 46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 47 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 49 * are three supported methods for data transfer between host and 50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 51 * Propulsion Technology (tm) DMA. The latter mechanism is a form 52 * of double buffer DMA where the packet data is copied to a 53 * pre-allocated DMA buffer who's physical address has been loaded 54 * into a table at device initialization time. The rationale is that 55 * the virtual to physical address translation needed for normal 56 * scatter/gather DMA is more expensive than the data copy needed 57 * for double buffering. This may be true in Windows NT and the like, 58 * but it isn't true for us, at least on the x86 arch. This driver 59 * uses the scatter/gather I/O method for both TX and RX. 60 * 61 * The LXT1001 only supports TCP/IP checksum offload on receive. 62 * Also, the VLAN tagging is done using a 16-entry table which allows 63 * the chip to perform hardware filtering based on VLAN tags. Sadly, 64 * our vlan support doesn't currently play well with this kind of 65 * hardware support. 66 * 67 * Special thanks to: 68 * - Jeff James at Intel, for arranging to have the LXT1001 manual 69 * released (at long last) 70 * - Beny Chen at D-Link, for actually sending it to me 71 * - Brad Short and Keith Alexis at SMC, for sending me sample 72 * SMC9462SX and SMC9462TX adapters for testing 73 * - Paul Saab at Y!, for not killing me (though it remains to be seen 74 * if in fact he did me much of a favor) 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/sockio.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/socket.h> 84 #include <sys/serialize.h> 85 #include <sys/thread2.h> 86 87 #include <net/if.h> 88 #include <net/ifq_var.h> 89 #include <net/if_arp.h> 90 #include <net/ethernet.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 94 #include <net/bpf.h> 95 96 #include <vm/vm.h> /* for vtophys */ 97 #include <vm/pmap.h> /* for vtophys */ 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 101 #include <dev/netif/mii_layer/mii.h> 102 #include <dev/netif/mii_layer/miivar.h> 103 104 #include <bus/pci/pcidevs.h> 105 #include <bus/pci/pcireg.h> 106 #include <bus/pci/pcivar.h> 107 108 #define LGE_USEIOSPACE 109 110 #include "if_lgereg.h" 111 112 /* "controller miibus0" required. See GENERIC if you get errors here. */ 113 #include "miibus_if.h" 114 115 /* 116 * Various supported device vendors/types and their names. 117 */ 118 static struct lge_type lge_devs[] = { 119 { PCI_VENDOR_LEVELONE, PCI_PRODUCT_LEVELONE_LXT1001, 120 "Level 1 Gigabit Ethernet" }, 121 { 0, 0, NULL } 122 }; 123 124 static int lge_probe(device_t); 125 static int lge_attach(device_t); 126 static int lge_detach(device_t); 127 128 static int lge_alloc_jumbo_mem(struct lge_softc *); 129 static void lge_free_jumbo_mem(struct lge_softc *); 130 static struct lge_jslot 131 *lge_jalloc(struct lge_softc *); 132 static void lge_jfree(void *); 133 static void lge_jref(void *); 134 135 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 136 struct mbuf *); 137 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *); 138 static void lge_rxeof(struct lge_softc *, int); 139 static void lge_rxeoc(struct lge_softc *); 140 static void lge_txeof(struct lge_softc *); 141 static void lge_intr(void *); 142 static void lge_tick(void *); 143 static void lge_tick_serialized(void *); 144 static void lge_start(struct ifnet *); 145 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 146 static void lge_init(void *); 147 static void lge_stop(struct lge_softc *); 148 static void lge_watchdog(struct ifnet *); 149 static void lge_shutdown(device_t); 150 static int lge_ifmedia_upd(struct ifnet *); 151 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 152 153 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *); 154 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int); 155 156 static int lge_miibus_readreg(device_t, int, int); 157 static int lge_miibus_writereg(device_t, int, int, int); 158 static void lge_miibus_statchg(device_t); 159 160 static void lge_setmulti(struct lge_softc *); 161 static void lge_reset(struct lge_softc *); 162 static int lge_list_rx_init(struct lge_softc *); 163 static int lge_list_tx_init(struct lge_softc *); 164 165 #ifdef LGE_USEIOSPACE 166 #define LGE_RES SYS_RES_IOPORT 167 #define LGE_RID LGE_PCI_LOIO 168 #else 169 #define LGE_RES SYS_RES_MEMORY 170 #define LGE_RID LGE_PCI_LOMEM 171 #endif 172 173 static device_method_t lge_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, lge_probe), 176 DEVMETHOD(device_attach, lge_attach), 177 DEVMETHOD(device_detach, lge_detach), 178 DEVMETHOD(device_shutdown, lge_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 186 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 187 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 188 189 { 0, 0 } 190 }; 191 192 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc)); 193 static devclass_t lge_devclass; 194 195 DECLARE_DUMMY_MODULE(if_lge); 196 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 197 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 198 199 #define LGE_SETBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 201 202 #define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 204 205 #define SIO_SET(x) \ 206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x)) 207 208 #define SIO_CLR(x) \ 209 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x)) 210 211 /* 212 * Read a word of data stored in the EEPROM at address 'addr.' 213 */ 214 static void 215 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest) 216 { 217 int i; 218 uint32_t val; 219 220 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 221 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8)); 222 223 for (i = 0; i < LGE_TIMEOUT; i++) { 224 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0) 225 break; 226 } 227 228 if (i == LGE_TIMEOUT) { 229 kprintf("lge%d: EEPROM read timed out\n", sc->lge_unit); 230 return; 231 } 232 233 val = CSR_READ_4(sc, LGE_EEDATA); 234 235 if (addr & 1) 236 *dest = (val >> 16) & 0xFFFF; 237 else 238 *dest = val & 0xFFFF; 239 } 240 241 /* 242 * Read a sequence of words from the EEPROM. 243 */ 244 static void 245 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt) 246 { 247 int i; 248 uint16_t word = 0, *ptr; 249 250 for (i = 0; i < cnt; i++) { 251 lge_eeprom_getword(sc, off + i, &word); 252 ptr = (uint16_t *)(dest + (i * 2)); 253 *ptr = ntohs(word); 254 } 255 } 256 257 static int 258 lge_miibus_readreg(device_t dev, int phy, int reg) 259 { 260 struct lge_softc *sc = device_get_softc(dev); 261 int i; 262 263 /* 264 * If we have a non-PCS PHY, pretend that the internal 265 * autoneg stuff at PHY address 0 isn't there so that 266 * the miibus code will find only the GMII PHY. 267 */ 268 if (sc->lge_pcs == 0 && phy == 0) 269 return(0); 270 271 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 272 273 for (i = 0; i < LGE_TIMEOUT; i++) { 274 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 275 break; 276 } 277 278 if (i == LGE_TIMEOUT) { 279 kprintf("lge%d: PHY read timed out\n", sc->lge_unit); 280 return(0); 281 } 282 283 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 284 } 285 286 static int 287 lge_miibus_writereg(device_t dev, int phy, int reg, int data) 288 { 289 struct lge_softc *sc = device_get_softc(dev); 290 int i; 291 292 CSR_WRITE_4(sc, LGE_GMIICTL, 293 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 294 295 for (i = 0; i < LGE_TIMEOUT; i++) { 296 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 297 break; 298 } 299 300 if (i == LGE_TIMEOUT) { 301 kprintf("lge%d: PHY write timed out\n", sc->lge_unit); 302 return(0); 303 } 304 305 return(0); 306 } 307 308 static void 309 lge_miibus_statchg(device_t dev) 310 { 311 struct lge_softc *sc = device_get_softc(dev); 312 struct mii_data *mii = device_get_softc(sc->lge_miibus); 313 314 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_1000_T: 317 case IFM_1000_SX: 318 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 319 break; 320 case IFM_100_TX: 321 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 322 break; 323 case IFM_10_T: 324 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 325 break; 326 default: 327 /* 328 * Choose something, even if it's wrong. Clearing 329 * all the bits will hose autoneg on the internal 330 * PHY. 331 */ 332 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 333 break; 334 } 335 336 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 337 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 338 else 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 340 } 341 342 static void 343 lge_setmulti(struct lge_softc *sc) 344 { 345 struct ifnet *ifp = &sc->arpcom.ac_if; 346 struct ifmultiaddr *ifma; 347 uint32_t h = 0, hashes[2] = { 0, 0 }; 348 349 /* Make sure multicast hash table is enabled. */ 350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST); 351 352 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 353 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 354 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 355 return; 356 } 357 358 /* first, zot all the existing hash bits */ 359 CSR_WRITE_4(sc, LGE_MAR0, 0); 360 CSR_WRITE_4(sc, LGE_MAR1, 0); 361 362 /* now program new ones */ 363 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 364 if (ifma->ifma_addr->sa_family != AF_LINK) 365 continue; 366 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 367 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 368 if (h < 32) 369 hashes[0] |= (1 << h); 370 else 371 hashes[1] |= (1 << (h - 32)); 372 } 373 374 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 375 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 376 377 return; 378 } 379 380 static void 381 lge_reset(struct lge_softc *sc) 382 { 383 int i; 384 385 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST); 386 387 for (i = 0; i < LGE_TIMEOUT; i++) { 388 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0) 389 break; 390 } 391 392 if (i == LGE_TIMEOUT) 393 kprintf("lge%d: reset never completed\n", sc->lge_unit); 394 395 /* Wait a little while for the chip to get its brains in order. */ 396 DELAY(1000); 397 } 398 399 /* 400 * Probe for a Level 1 chip. Check the PCI vendor and device 401 * IDs against our list and return a device name if we find a match. 402 */ 403 static int 404 lge_probe(device_t dev) 405 { 406 struct lge_type *t; 407 uint16_t vendor, product; 408 409 vendor = pci_get_vendor(dev); 410 product = pci_get_device(dev); 411 412 for (t = lge_devs; t->lge_name != NULL; t++) { 413 if (vendor == t->lge_vid && product == t->lge_did) { 414 device_set_desc(dev, t->lge_name); 415 return(0); 416 } 417 } 418 419 return(ENXIO); 420 } 421 422 /* 423 * Attach the interface. Allocate softc structures, do ifmedia 424 * setup and ethernet/BPF attach. 425 */ 426 static int 427 lge_attach(device_t dev) 428 { 429 uint8_t eaddr[ETHER_ADDR_LEN]; 430 struct lge_softc *sc; 431 struct ifnet *ifp; 432 int unit, error = 0, rid; 433 434 sc = device_get_softc(dev); 435 unit = device_get_unit(dev); 436 callout_init(&sc->lge_stat_timer); 437 lwkt_serialize_init(&sc->lge_jslot_serializer); 438 439 /* 440 * Handle power management nonsense. 441 */ 442 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 443 uint32_t iobase, membase, irq; 444 445 /* Save important PCI config data. */ 446 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 447 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 448 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 449 450 /* Reset the power state. */ 451 device_printf(dev, "chip is in D%d power mode " 452 "-- setting to D0\n", pci_get_powerstate(dev)); 453 454 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 455 456 /* Restore PCI config data. */ 457 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 458 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 459 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 460 } 461 462 pci_enable_busmaster(dev); 463 464 rid = LGE_RID; 465 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 466 467 if (sc->lge_res == NULL) { 468 kprintf("lge%d: couldn't map ports/memory\n", unit); 469 error = ENXIO; 470 goto fail; 471 } 472 473 sc->lge_btag = rman_get_bustag(sc->lge_res); 474 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 475 476 /* Allocate interrupt */ 477 rid = 0; 478 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 479 RF_SHAREABLE | RF_ACTIVE); 480 481 if (sc->lge_irq == NULL) { 482 kprintf("lge%d: couldn't map interrupt\n", unit); 483 error = ENXIO; 484 goto fail; 485 } 486 487 /* Reset the adapter. */ 488 lge_reset(sc); 489 490 /* 491 * Get station address from the EEPROM. 492 */ 493 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1); 494 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1); 495 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1); 496 497 sc->lge_unit = unit; 498 499 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 500 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 501 502 if (sc->lge_ldata == NULL) { 503 kprintf("lge%d: no memory for list buffers!\n", unit); 504 error = ENXIO; 505 goto fail; 506 } 507 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 508 509 /* Try to allocate memory for jumbo buffers. */ 510 if (lge_alloc_jumbo_mem(sc)) { 511 kprintf("lge%d: jumbo buffer allocation failed\n", 512 sc->lge_unit); 513 error = ENXIO; 514 goto fail; 515 } 516 517 ifp = &sc->arpcom.ac_if; 518 ifp->if_softc = sc; 519 if_initname(ifp, "lge", unit); 520 ifp->if_mtu = ETHERMTU; 521 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 522 ifp->if_ioctl = lge_ioctl; 523 ifp->if_start = lge_start; 524 ifp->if_watchdog = lge_watchdog; 525 ifp->if_init = lge_init; 526 ifp->if_baudrate = 1000000000; 527 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 528 ifq_set_ready(&ifp->if_snd); 529 ifp->if_capabilities = IFCAP_RXCSUM; 530 ifp->if_capenable = ifp->if_capabilities; 531 532 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 533 sc->lge_pcs = 1; 534 else 535 sc->lge_pcs = 0; 536 537 /* 538 * Do MII setup. 539 */ 540 if (mii_phy_probe(dev, &sc->lge_miibus, 541 lge_ifmedia_upd, lge_ifmedia_sts)) { 542 kprintf("lge%d: MII without any PHY!\n", sc->lge_unit); 543 error = ENXIO; 544 goto fail; 545 } 546 547 /* 548 * Call MI attach routine. 549 */ 550 ether_ifattach(ifp, eaddr, NULL); 551 552 error = bus_setup_intr(dev, sc->lge_irq, INTR_NETSAFE, 553 lge_intr, sc, &sc->lge_intrhand, 554 ifp->if_serializer); 555 if (error) { 556 ether_ifdetach(ifp); 557 kprintf("lge%d: couldn't set up irq\n", unit); 558 goto fail; 559 } 560 561 return(0); 562 563 fail: 564 lge_detach(dev); 565 return(error); 566 } 567 568 static int 569 lge_detach(device_t dev) 570 { 571 struct lge_softc *sc= device_get_softc(dev); 572 struct ifnet *ifp = &sc->arpcom.ac_if; 573 574 if (device_is_attached(dev)) { 575 lwkt_serialize_enter(ifp->if_serializer); 576 lge_reset(sc); 577 lge_stop(sc); 578 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 579 lwkt_serialize_exit(ifp->if_serializer); 580 581 ether_ifdetach(ifp); 582 } 583 584 if (sc->lge_miibus) 585 device_delete_child(dev, sc->lge_miibus); 586 bus_generic_detach(dev); 587 588 if (sc->lge_irq) 589 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 590 if (sc->lge_res) 591 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 592 593 if (sc->lge_ldata) 594 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), 595 M_DEVBUF); 596 lge_free_jumbo_mem(sc); 597 598 return(0); 599 } 600 601 /* 602 * Initialize the transmit descriptors. 603 */ 604 static int 605 lge_list_tx_init(struct lge_softc *sc) 606 { 607 struct lge_list_data *ld; 608 struct lge_ring_data *cd; 609 int i; 610 611 cd = &sc->lge_cdata; 612 ld = sc->lge_ldata; 613 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 614 ld->lge_tx_list[i].lge_mbuf = NULL; 615 ld->lge_tx_list[i].lge_ctl = 0; 616 } 617 618 cd->lge_tx_prod = cd->lge_tx_cons = 0; 619 620 return(0); 621 } 622 623 624 /* 625 * Initialize the RX descriptors and allocate mbufs for them. Note that 626 * we arralge the descriptors in a closed ring, so that the last descriptor 627 * points back to the first. 628 */ 629 static int 630 lge_list_rx_init(struct lge_softc *sc) 631 { 632 struct lge_list_data *ld; 633 struct lge_ring_data *cd; 634 int i; 635 636 ld = sc->lge_ldata; 637 cd = &sc->lge_cdata; 638 639 cd->lge_rx_prod = cd->lge_rx_cons = 0; 640 641 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 642 643 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 644 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 645 break; 646 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 647 return(ENOBUFS); 648 } 649 650 /* Clear possible 'rx command queue empty' interrupt. */ 651 CSR_READ_4(sc, LGE_ISR); 652 653 return(0); 654 } 655 656 /* 657 * Initialize an RX descriptor and attach an MBUF cluster. 658 */ 659 static int 660 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 661 { 662 struct mbuf *m_new = NULL; 663 struct lge_jslot *buf; 664 665 if (m == NULL) { 666 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 667 if (m_new == NULL) { 668 kprintf("lge%d: no memory for rx list " 669 "-- packet dropped!\n", sc->lge_unit); 670 return(ENOBUFS); 671 } 672 673 /* Allocate the jumbo buffer */ 674 buf = lge_jalloc(sc); 675 if (buf == NULL) { 676 #ifdef LGE_VERBOSE 677 kprintf("lge%d: jumbo allocation failed " 678 "-- packet dropped!\n", sc->lge_unit); 679 #endif 680 m_freem(m_new); 681 return(ENOBUFS); 682 } 683 /* Attach the buffer to the mbuf */ 684 m_new->m_ext.ext_arg = buf; 685 m_new->m_ext.ext_buf = buf->lge_buf; 686 m_new->m_ext.ext_free = lge_jfree; 687 m_new->m_ext.ext_ref = lge_jref; 688 m_new->m_ext.ext_size = LGE_JUMBO_FRAMELEN; 689 690 m_new->m_data = m_new->m_ext.ext_buf; 691 m_new->m_flags |= M_EXT; 692 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 693 } else { 694 m_new = m; 695 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 696 m_new->m_data = m_new->m_ext.ext_buf; 697 } 698 699 /* 700 * Adjust alignment so packet payload begins on a 701 * longword boundary. Mandatory for Alpha, useful on 702 * x86 too. 703 */ 704 m_adj(m_new, ETHER_ALIGN); 705 706 c->lge_mbuf = m_new; 707 c->lge_fragptr_hi = 0; 708 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 709 c->lge_fraglen = m_new->m_len; 710 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 711 c->lge_sts = 0; 712 713 /* 714 * Put this buffer in the RX command FIFO. To do this, 715 * we just write the physical address of the descriptor 716 * into the RX descriptor address registers. Note that 717 * there are two registers, one high DWORD and one low 718 * DWORD, which lets us specify a 64-bit address if 719 * desired. We only use a 32-bit address for now. 720 * Writing to the low DWORD register is what actually 721 * causes the command to be issued, so we do that 722 * last. 723 */ 724 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 725 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 726 727 return(0); 728 } 729 730 static int 731 lge_alloc_jumbo_mem(struct lge_softc *sc) 732 { 733 struct lge_jslot *entry; 734 caddr_t ptr; 735 int i; 736 737 /* Grab a big chunk o' storage. */ 738 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 739 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 740 741 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 742 kprintf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 743 return(ENOBUFS); 744 } 745 746 SLIST_INIT(&sc->lge_jfree_listhead); 747 748 /* 749 * Now divide it up into 9K pieces and save the addresses 750 * in an array. 751 */ 752 ptr = sc->lge_cdata.lge_jumbo_buf; 753 for (i = 0; i < LGE_JSLOTS; i++) { 754 entry = &sc->lge_cdata.lge_jslots[i]; 755 entry->lge_sc = sc; 756 entry->lge_buf = ptr; 757 entry->lge_inuse = 0; 758 entry->lge_slot = i; 759 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link); 760 ptr += LGE_JLEN; 761 } 762 763 return(0); 764 } 765 766 static void 767 lge_free_jumbo_mem(struct lge_softc *sc) 768 { 769 if (sc->lge_cdata.lge_jumbo_buf) 770 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 771 } 772 773 /* 774 * Allocate a jumbo buffer. 775 */ 776 static struct lge_jslot * 777 lge_jalloc(struct lge_softc *sc) 778 { 779 struct lge_jslot *entry; 780 781 lwkt_serialize_enter(&sc->lge_jslot_serializer); 782 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 783 if (entry) { 784 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jslot_link); 785 entry->lge_inuse = 1; 786 } else { 787 #ifdef LGE_VERBOSE 788 kprintf("lge%d: no free jumbo buffers\n", sc->lge_unit); 789 #endif 790 } 791 lwkt_serialize_exit(&sc->lge_jslot_serializer); 792 return(entry); 793 } 794 795 /* 796 * Adjust usage count on a jumbo buffer. In general this doesn't 797 * get used much because our jumbo buffers don't get passed around 798 * a lot, but it's implemented for correctness. 799 */ 800 static void 801 lge_jref(void *arg) 802 { 803 struct lge_jslot *entry = (struct lge_jslot *)arg; 804 struct lge_softc *sc = entry->lge_sc; 805 806 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) 807 panic("lge_jref: asked to reference buffer " 808 "that we don't manage!"); 809 else if (entry->lge_inuse == 0) 810 panic("lge_jref: buffer already free!"); 811 else 812 atomic_add_int(&entry->lge_inuse, 1); 813 } 814 815 /* 816 * Release a jumbo buffer. 817 */ 818 static void 819 lge_jfree(void *arg) 820 { 821 struct lge_jslot *entry = (struct lge_jslot *)arg; 822 struct lge_softc *sc = entry->lge_sc; 823 824 if (sc == NULL) 825 panic("lge_jfree: can't find softc pointer!"); 826 827 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) { 828 panic("lge_jfree: asked to free buffer that we don't manage!"); 829 } else if (entry->lge_inuse == 0) { 830 panic("lge_jfree: buffer already free!"); 831 } else { 832 lwkt_serialize_enter(&sc->lge_jslot_serializer); 833 atomic_subtract_int(&entry->lge_inuse, 1); 834 if (entry->lge_inuse == 0) { 835 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 836 entry, jslot_link); 837 } 838 lwkt_serialize_exit(&sc->lge_jslot_serializer); 839 } 840 } 841 842 /* 843 * A frame has been uploaded: pass the resulting mbuf chain up to 844 * the higher level protocols. 845 */ 846 static void 847 lge_rxeof(struct lge_softc *sc, int cnt) 848 { 849 struct ifnet *ifp = &sc->arpcom.ac_if; 850 struct mbuf *m; 851 struct lge_rx_desc *cur_rx; 852 int c, i, total_len = 0; 853 uint32_t rxsts, rxctl; 854 855 856 /* Find out how many frames were processed. */ 857 c = cnt; 858 i = sc->lge_cdata.lge_rx_cons; 859 860 /* Suck them in. */ 861 while(c) { 862 struct mbuf *m0 = NULL; 863 864 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 865 rxctl = cur_rx->lge_ctl; 866 rxsts = cur_rx->lge_sts; 867 m = cur_rx->lge_mbuf; 868 cur_rx->lge_mbuf = NULL; 869 total_len = LGE_RXBYTES(cur_rx); 870 LGE_INC(i, LGE_RX_LIST_CNT); 871 c--; 872 873 /* 874 * If an error occurs, update stats, clear the 875 * status word and leave the mbuf cluster in place: 876 * it should simply get re-used next time this descriptor 877 * comes up in the ring. 878 */ 879 if (rxctl & LGE_RXCTL_ERRMASK) { 880 ifp->if_ierrors++; 881 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 882 continue; 883 } 884 885 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 886 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 887 total_len + ETHER_ALIGN, 0, ifp, NULL); 888 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 889 if (m0 == NULL) { 890 kprintf("lge%d: no receive buffers " 891 "available -- packet dropped!\n", 892 sc->lge_unit); 893 ifp->if_ierrors++; 894 continue; 895 } 896 m_adj(m0, ETHER_ALIGN); 897 m = m0; 898 } else { 899 m->m_pkthdr.rcvif = ifp; 900 m->m_pkthdr.len = m->m_len = total_len; 901 } 902 903 ifp->if_ipackets++; 904 905 /* Do IP checksum checking. */ 906 if (rxsts & LGE_RXSTS_ISIP) 907 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 908 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 909 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 910 if ((rxsts & LGE_RXSTS_ISTCP && 911 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 912 (rxsts & LGE_RXSTS_ISUDP && 913 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 914 m->m_pkthdr.csum_flags |= 915 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 916 m->m_pkthdr.csum_data = 0xffff; 917 } 918 919 ifp->if_input(ifp, m); 920 } 921 922 sc->lge_cdata.lge_rx_cons = i; 923 } 924 925 static void 926 lge_rxeoc(struct lge_softc *sc) 927 { 928 struct ifnet *ifp = &sc->arpcom.ac_if; 929 930 ifp->if_flags &= ~IFF_RUNNING; 931 lge_init(sc); 932 } 933 934 /* 935 * A frame was downloaded to the chip. It's safe for us to clean up 936 * the list buffers. 937 */ 938 static void 939 lge_txeof(struct lge_softc *sc) 940 { 941 struct ifnet *ifp = &sc->arpcom.ac_if; 942 struct lge_tx_desc *cur_tx = NULL; 943 uint32_t idx, txdone; 944 945 /* Clear the timeout timer. */ 946 ifp->if_timer = 0; 947 948 /* 949 * Go through our tx list and free mbufs for those 950 * frames that have been transmitted. 951 */ 952 idx = sc->lge_cdata.lge_tx_cons; 953 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 954 955 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 956 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 957 958 ifp->if_opackets++; 959 if (cur_tx->lge_mbuf != NULL) { 960 m_freem(cur_tx->lge_mbuf); 961 cur_tx->lge_mbuf = NULL; 962 } 963 cur_tx->lge_ctl = 0; 964 965 txdone--; 966 LGE_INC(idx, LGE_TX_LIST_CNT); 967 ifp->if_timer = 0; 968 } 969 970 sc->lge_cdata.lge_tx_cons = idx; 971 972 if (cur_tx != NULL) 973 ifp->if_flags &= ~IFF_OACTIVE; 974 } 975 976 static void 977 lge_tick(void *xsc) 978 { 979 struct lge_softc *sc = xsc; 980 struct ifnet *ifp = &sc->arpcom.ac_if; 981 982 lwkt_serialize_enter(ifp->if_serializer); 983 lge_tick_serialized(xsc); 984 lwkt_serialize_exit(ifp->if_serializer); 985 } 986 987 static void 988 lge_tick_serialized(void *xsc) 989 { 990 struct lge_softc *sc = xsc; 991 struct mii_data *mii; 992 struct ifnet *ifp = &sc->arpcom.ac_if; 993 994 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 995 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 996 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 997 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 998 999 if (!sc->lge_link) { 1000 mii = device_get_softc(sc->lge_miibus); 1001 mii_tick(mii); 1002 mii_pollstat(mii); 1003 if (mii->mii_media_status & IFM_ACTIVE && 1004 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1005 sc->lge_link++; 1006 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1007 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1008 kprintf("lge%d: gigabit link up\n", 1009 sc->lge_unit); 1010 if (!ifq_is_empty(&ifp->if_snd)) 1011 (*ifp->if_start)(ifp); 1012 } 1013 } 1014 1015 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1016 } 1017 1018 static void 1019 lge_intr(void *arg) 1020 { 1021 struct lge_softc *sc = arg; 1022 struct ifnet *ifp = &sc->arpcom.ac_if; 1023 uint32_t status; 1024 1025 /* Supress unwanted interrupts */ 1026 if ((ifp->if_flags & IFF_UP) == 0) { 1027 lge_stop(sc); 1028 return; 1029 } 1030 1031 for (;;) { 1032 /* 1033 * Reading the ISR register clears all interrupts, and 1034 * clears the 'interrupts enabled' bit in the IMR 1035 * register. 1036 */ 1037 status = CSR_READ_4(sc, LGE_ISR); 1038 1039 if ((status & LGE_INTRS) == 0) 1040 break; 1041 1042 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1043 lge_txeof(sc); 1044 1045 if (status & LGE_ISR_RXDMA_DONE) 1046 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1047 1048 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1049 lge_rxeoc(sc); 1050 1051 if (status & LGE_ISR_PHY_INTR) { 1052 sc->lge_link = 0; 1053 callout_stop(&sc->lge_stat_timer); 1054 lge_tick_serialized(sc); 1055 } 1056 } 1057 1058 /* Re-enable interrupts. */ 1059 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1060 1061 if (!ifq_is_empty(&ifp->if_snd)) 1062 (*ifp->if_start)(ifp); 1063 } 1064 1065 /* 1066 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1067 * pointers to the fragment pointers. 1068 */ 1069 static int 1070 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1071 { 1072 struct lge_frag *f = NULL; 1073 struct lge_tx_desc *cur_tx; 1074 struct mbuf *m; 1075 int frag = 0, tot_len = 0; 1076 1077 /* 1078 * Start packing the mbufs in this chain into 1079 * the fragment pointers. Stop when we run out 1080 * of fragments or hit the end of the mbuf chain. 1081 */ 1082 m = m_head; 1083 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1084 frag = 0; 1085 1086 for (m = m_head; m != NULL; m = m->m_next) { 1087 if (m->m_len != 0) { 1088 tot_len += m->m_len; 1089 f = &cur_tx->lge_frags[frag]; 1090 f->lge_fraglen = m->m_len; 1091 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1092 f->lge_fragptr_hi = 0; 1093 frag++; 1094 } 1095 } 1096 1097 if (m != NULL) 1098 return(ENOBUFS); 1099 1100 cur_tx->lge_mbuf = m_head; 1101 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1102 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1103 1104 /* Queue for transmit */ 1105 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1106 1107 return(0); 1108 } 1109 1110 /* 1111 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1112 * to the mbuf data regions directly in the transmit lists. We also save a 1113 * copy of the pointers since the transmit list fragment pointers are 1114 * physical addresses. 1115 */ 1116 1117 static void 1118 lge_start(struct ifnet *ifp) 1119 { 1120 struct lge_softc *sc = ifp->if_softc; 1121 struct mbuf *m_head = NULL; 1122 uint32_t idx; 1123 int need_timer; 1124 1125 if (!sc->lge_link) 1126 return; 1127 1128 idx = sc->lge_cdata.lge_tx_prod; 1129 1130 if (ifp->if_flags & IFF_OACTIVE) 1131 return; 1132 1133 need_timer = 0; 1134 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1135 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1136 break; 1137 1138 m_head = ifq_poll(&ifp->if_snd); 1139 if (m_head == NULL) 1140 break; 1141 1142 if (lge_encap(sc, m_head, &idx)) { 1143 ifp->if_flags |= IFF_OACTIVE; 1144 break; 1145 } 1146 ifq_dequeue(&ifp->if_snd, m_head); 1147 need_timer = 1; 1148 1149 BPF_MTAP(ifp, m_head); 1150 } 1151 1152 if (!need_timer) 1153 return; 1154 1155 sc->lge_cdata.lge_tx_prod = idx; 1156 1157 /* 1158 * Set a timeout in case the chip goes out to lunch. 1159 */ 1160 ifp->if_timer = 5; 1161 } 1162 1163 static void 1164 lge_init(void *xsc) 1165 { 1166 struct lge_softc *sc = xsc; 1167 struct ifnet *ifp = &sc->arpcom.ac_if; 1168 struct mii_data *mii; 1169 1170 if (ifp->if_flags & IFF_RUNNING) 1171 return; 1172 1173 /* 1174 * Cancel pending I/O and free all RX/TX buffers. 1175 */ 1176 lge_stop(sc); 1177 lge_reset(sc); 1178 1179 mii = device_get_softc(sc->lge_miibus); 1180 1181 /* Set MAC address */ 1182 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1183 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1184 1185 /* Init circular RX list. */ 1186 if (lge_list_rx_init(sc) == ENOBUFS) { 1187 kprintf("lge%d: initialization failed: no " 1188 "memory for rx buffers\n", sc->lge_unit); 1189 lge_stop(sc); 1190 return; 1191 } 1192 1193 /* 1194 * Init tx descriptors. 1195 */ 1196 lge_list_tx_init(sc); 1197 1198 /* Set initial value for MODE1 register. */ 1199 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST | 1200 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD | 1201 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 | 1202 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2); 1203 1204 /* If we want promiscuous mode, set the allframes bit. */ 1205 if (ifp->if_flags & IFF_PROMISC) { 1206 CSR_WRITE_4(sc, LGE_MODE1, 1207 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC); 1208 } else { 1209 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1210 } 1211 1212 /* 1213 * Set the capture broadcast bit to capture broadcast frames. 1214 */ 1215 if (ifp->if_flags & IFF_BROADCAST) { 1216 CSR_WRITE_4(sc, LGE_MODE1, 1217 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST); 1218 } else { 1219 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1220 } 1221 1222 /* Packet padding workaround? */ 1223 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1224 1225 /* No error frames */ 1226 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1227 1228 /* Receive large frames */ 1229 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS); 1230 1231 /* Workaround: disable RX/TX flow control */ 1232 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1233 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1234 1235 /* Make sure to strip CRC from received frames */ 1236 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1237 1238 /* Turn off magic packet mode */ 1239 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1240 1241 /* Turn off all VLAN stuff */ 1242 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX | 1243 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT); 1244 1245 /* Workarond: FIFO overflow */ 1246 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1247 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1248 1249 /* 1250 * Load the multicast filter. 1251 */ 1252 lge_setmulti(sc); 1253 1254 /* 1255 * Enable hardware checksum validation for all received IPv4 1256 * packets, do not reject packets with bad checksums. 1257 */ 1258 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM | 1259 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM | 1260 LGE_MODE2_RX_ERRCSUM); 1261 1262 /* 1263 * Enable the delivery of PHY interrupts based on 1264 * link/speed/duplex status chalges. 1265 */ 1266 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL); 1267 1268 /* Enable receiver and transmitter. */ 1269 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1270 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB); 1271 1272 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1273 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB); 1274 1275 /* 1276 * Enable interrupts. 1277 */ 1278 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 | 1279 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS); 1280 1281 lge_ifmedia_upd(ifp); 1282 1283 ifp->if_flags |= IFF_RUNNING; 1284 ifp->if_flags &= ~IFF_OACTIVE; 1285 1286 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1287 } 1288 1289 /* 1290 * Set media options. 1291 */ 1292 static int 1293 lge_ifmedia_upd(struct ifnet *ifp) 1294 { 1295 struct lge_softc *sc = ifp->if_softc; 1296 struct mii_data *mii = device_get_softc(sc->lge_miibus); 1297 1298 sc->lge_link = 0; 1299 if (mii->mii_instance) { 1300 struct mii_softc *miisc; 1301 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1302 mii_phy_reset(miisc); 1303 } 1304 mii_mediachg(mii); 1305 1306 return(0); 1307 } 1308 1309 /* 1310 * Report current media status. 1311 */ 1312 static void 1313 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1314 { 1315 struct lge_softc *sc = ifp->if_softc; 1316 struct mii_data *mii; 1317 1318 mii = device_get_softc(sc->lge_miibus); 1319 mii_pollstat(mii); 1320 ifmr->ifm_active = mii->mii_media_active; 1321 ifmr->ifm_status = mii->mii_media_status; 1322 } 1323 1324 static int 1325 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1326 { 1327 struct lge_softc *sc = ifp->if_softc; 1328 struct ifreq *ifr = (struct ifreq *) data; 1329 struct mii_data *mii; 1330 int error = 0; 1331 1332 switch(command) { 1333 case SIOCSIFMTU: 1334 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1335 error = EINVAL; 1336 else 1337 ifp->if_mtu = ifr->ifr_mtu; 1338 break; 1339 case SIOCSIFFLAGS: 1340 if (ifp->if_flags & IFF_UP) { 1341 if (ifp->if_flags & IFF_RUNNING && 1342 ifp->if_flags & IFF_PROMISC && 1343 !(sc->lge_if_flags & IFF_PROMISC)) { 1344 CSR_WRITE_4(sc, LGE_MODE1, 1345 LGE_MODE1_SETRST_CTL1| 1346 LGE_MODE1_RX_PROMISC); 1347 } else if (ifp->if_flags & IFF_RUNNING && 1348 !(ifp->if_flags & IFF_PROMISC) && 1349 sc->lge_if_flags & IFF_PROMISC) { 1350 CSR_WRITE_4(sc, LGE_MODE1, 1351 LGE_MODE1_RX_PROMISC); 1352 } else { 1353 ifp->if_flags &= ~IFF_RUNNING; 1354 lge_init(sc); 1355 } 1356 } else { 1357 if (ifp->if_flags & IFF_RUNNING) 1358 lge_stop(sc); 1359 } 1360 sc->lge_if_flags = ifp->if_flags; 1361 error = 0; 1362 break; 1363 case SIOCADDMULTI: 1364 case SIOCDELMULTI: 1365 lge_setmulti(sc); 1366 error = 0; 1367 break; 1368 case SIOCGIFMEDIA: 1369 case SIOCSIFMEDIA: 1370 mii = device_get_softc(sc->lge_miibus); 1371 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1372 break; 1373 default: 1374 error = ether_ioctl(ifp, command, data); 1375 break; 1376 } 1377 1378 return(error); 1379 } 1380 1381 static void 1382 lge_watchdog(struct ifnet *ifp) 1383 { 1384 struct lge_softc *sc = ifp->if_softc; 1385 1386 ifp->if_oerrors++; 1387 kprintf("lge%d: watchdog timeout\n", sc->lge_unit); 1388 1389 lge_stop(sc); 1390 lge_reset(sc); 1391 ifp->if_flags &= ~IFF_RUNNING; 1392 lge_init(sc); 1393 1394 if (!ifq_is_empty(&ifp->if_snd)) 1395 (*ifp->if_start)(ifp); 1396 } 1397 1398 /* 1399 * Stop the adapter and free any mbufs allocated to the 1400 * RX and TX lists. 1401 */ 1402 static void 1403 lge_stop(struct lge_softc *sc) 1404 { 1405 struct ifnet *ifp = &sc->arpcom.ac_if; 1406 int i; 1407 1408 ifp->if_timer = 0; 1409 callout_stop(&sc->lge_stat_timer); 1410 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1411 1412 /* Disable receiver and transmitter. */ 1413 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1414 sc->lge_link = 0; 1415 1416 /* 1417 * Free data in the RX lists. 1418 */ 1419 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1420 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1421 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1422 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1423 } 1424 } 1425 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list)); 1426 1427 /* 1428 * Free the TX list buffers. 1429 */ 1430 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1431 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1432 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1433 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1434 } 1435 } 1436 1437 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list)); 1438 1439 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1440 } 1441 1442 /* 1443 * Stop all chip I/O so that the kernel's probe routines don't 1444 * get confused by errant DMAs when rebooting. 1445 */ 1446 static void 1447 lge_shutdown(device_t dev) 1448 { 1449 struct lge_softc *sc = device_get_softc(dev); 1450 1451 lge_reset(sc); 1452 lge_stop(sc); 1453 } 1454