1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.15 2004/09/14 23:08:41 joerg Exp $ 35 * 36 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 37 */ 38 39 /* 40 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 41 * documentation not available, but ask me nicely. 42 * 43 * Written by Bill Paul <william.paul@windriver.com> 44 * Wind River Systems 45 */ 46 47 /* 48 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 49 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 50 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 51 * are three supported methods for data transfer between host and 52 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 53 * Propulsion Technology (tm) DMA. The latter mechanism is a form 54 * of double buffer DMA where the packet data is copied to a 55 * pre-allocated DMA buffer who's physical address has been loaded 56 * into a table at device initialization time. The rationale is that 57 * the virtual to physical address translation needed for normal 58 * scatter/gather DMA is more expensive than the data copy needed 59 * for double buffering. This may be true in Windows NT and the like, 60 * but it isn't true for us, at least on the x86 arch. This driver 61 * uses the scatter/gather I/O method for both TX and RX. 62 * 63 * The LXT1001 only supports TCP/IP checksum offload on receive. 64 * Also, the VLAN tagging is done using a 16-entry table which allows 65 * the chip to perform hardware filtering based on VLAN tags. Sadly, 66 * our vlan support doesn't currently play well with this kind of 67 * hardware support. 68 * 69 * Special thanks to: 70 * - Jeff James at Intel, for arranging to have the LXT1001 manual 71 * released (at long last) 72 * - Beny Chen at D-Link, for actually sending it to me 73 * - Brad Short and Keith Alexis at SMC, for sending me sample 74 * SMC9462SX and SMC9462TX adapters for testing 75 * - Paul Saab at Y!, for not killing me (though it remains to be seen 76 * if in fact he did me much of a favor) 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/sockio.h> 82 #include <sys/mbuf.h> 83 #include <sys/malloc.h> 84 #include <sys/kernel.h> 85 #include <sys/socket.h> 86 87 #include <net/if.h> 88 #include <net/if_arp.h> 89 #include <net/ethernet.h> 90 #include <net/if_dl.h> 91 #include <net/if_media.h> 92 93 #include <net/bpf.h> 94 95 #include <vm/vm.h> /* for vtophys */ 96 #include <vm/pmap.h> /* for vtophys */ 97 #include <machine/clock.h> /* for DELAY */ 98 #include <machine/bus_pio.h> 99 #include <machine/bus_memio.h> 100 #include <machine/bus.h> 101 #include <machine/resource.h> 102 #include <sys/bus.h> 103 #include <sys/rman.h> 104 105 #include "../mii_layer/mii.h" 106 #include "../mii_layer/miivar.h" 107 108 #include <bus/pci/pcireg.h> 109 #include <bus/pci/pcivar.h> 110 111 #define LGE_USEIOSPACE 112 113 #include "if_lgereg.h" 114 115 /* "controller miibus0" required. See GENERIC if you get errors here. */ 116 #include "miibus_if.h" 117 118 /* 119 * Various supported device vendors/types and their names. 120 */ 121 static struct lge_type lge_devs[] = { 122 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 123 { 0, 0, NULL } 124 }; 125 126 static int lge_probe (device_t); 127 static int lge_attach (device_t); 128 static int lge_detach (device_t); 129 130 static int lge_alloc_jumbo_mem (struct lge_softc *); 131 static void lge_free_jumbo_mem (struct lge_softc *); 132 static void *lge_jalloc (struct lge_softc *); 133 static void lge_jfree (caddr_t, u_int); 134 static void lge_jref (caddr_t, u_int); 135 136 static int lge_newbuf (struct lge_softc *, 137 struct lge_rx_desc *, 138 struct mbuf *); 139 static int lge_encap (struct lge_softc *, 140 struct mbuf *, u_int32_t *); 141 static void lge_rxeof (struct lge_softc *, int); 142 static void lge_rxeoc (struct lge_softc *); 143 static void lge_txeof (struct lge_softc *); 144 static void lge_intr (void *); 145 static void lge_tick (void *); 146 static void lge_start (struct ifnet *); 147 static int lge_ioctl (struct ifnet *, u_long, caddr_t, 148 struct ucred *); 149 static void lge_init (void *); 150 static void lge_stop (struct lge_softc *); 151 static void lge_watchdog (struct ifnet *); 152 static void lge_shutdown (device_t); 153 static int lge_ifmedia_upd (struct ifnet *); 154 static void lge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 155 156 static void lge_eeprom_getword (struct lge_softc *, int, u_int16_t *); 157 static void lge_read_eeprom (struct lge_softc *, caddr_t, int, 158 int, int); 159 160 static int lge_miibus_readreg (device_t, int, int); 161 static int lge_miibus_writereg (device_t, int, int, int); 162 static void lge_miibus_statchg (device_t); 163 164 static void lge_setmulti (struct lge_softc *); 165 static u_int32_t lge_crc (struct lge_softc *, caddr_t); 166 static void lge_reset (struct lge_softc *); 167 static int lge_list_rx_init (struct lge_softc *); 168 static int lge_list_tx_init (struct lge_softc *); 169 170 #ifdef LGE_USEIOSPACE 171 #define LGE_RES SYS_RES_IOPORT 172 #define LGE_RID LGE_PCI_LOIO 173 #else 174 #define LGE_RES SYS_RES_MEMORY 175 #define LGE_RID LGE_PCI_LOMEM 176 #endif 177 178 static device_method_t lge_methods[] = { 179 /* Device interface */ 180 DEVMETHOD(device_probe, lge_probe), 181 DEVMETHOD(device_attach, lge_attach), 182 DEVMETHOD(device_detach, lge_detach), 183 DEVMETHOD(device_shutdown, lge_shutdown), 184 185 /* bus interface */ 186 DEVMETHOD(bus_print_child, bus_generic_print_child), 187 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 188 189 /* MII interface */ 190 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 191 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 192 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 193 194 { 0, 0 } 195 }; 196 197 static driver_t lge_driver = { 198 "lge", 199 lge_methods, 200 sizeof(struct lge_softc) 201 }; 202 203 static devclass_t lge_devclass; 204 205 DECLARE_DUMMY_MODULE(if_lge); 206 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 207 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 208 209 #define LGE_SETBIT(sc, reg, x) \ 210 CSR_WRITE_4(sc, reg, \ 211 CSR_READ_4(sc, reg) | (x)) 212 213 #define LGE_CLRBIT(sc, reg, x) \ 214 CSR_WRITE_4(sc, reg, \ 215 CSR_READ_4(sc, reg) & ~(x)) 216 217 #define SIO_SET(x) \ 218 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 219 220 #define SIO_CLR(x) \ 221 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 222 223 /* 224 * Read a word of data stored in the EEPROM at address 'addr.' 225 */ 226 static void lge_eeprom_getword(sc, addr, dest) 227 struct lge_softc *sc; 228 int addr; 229 u_int16_t *dest; 230 { 231 int i; 232 u_int32_t val; 233 234 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 235 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 236 237 for (i = 0; i < LGE_TIMEOUT; i++) 238 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 239 break; 240 241 if (i == LGE_TIMEOUT) { 242 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 243 return; 244 } 245 246 val = CSR_READ_4(sc, LGE_EEDATA); 247 248 if (addr & 1) 249 *dest = (val >> 16) & 0xFFFF; 250 else 251 *dest = val & 0xFFFF; 252 253 return; 254 } 255 256 /* 257 * Read a sequence of words from the EEPROM. 258 */ 259 static void lge_read_eeprom(sc, dest, off, cnt, swap) 260 struct lge_softc *sc; 261 caddr_t dest; 262 int off; 263 int cnt; 264 int swap; 265 { 266 int i; 267 u_int16_t word = 0, *ptr; 268 269 for (i = 0; i < cnt; i++) { 270 lge_eeprom_getword(sc, off + i, &word); 271 ptr = (u_int16_t *)(dest + (i * 2)); 272 if (swap) 273 *ptr = ntohs(word); 274 else 275 *ptr = word; 276 } 277 278 return; 279 } 280 281 static int lge_miibus_readreg(dev, phy, reg) 282 device_t dev; 283 int phy, reg; 284 { 285 struct lge_softc *sc; 286 int i; 287 288 sc = device_get_softc(dev); 289 290 /* 291 * If we have a non-PCS PHY, pretend that the internal 292 * autoneg stuff at PHY address 0 isn't there so that 293 * the miibus code will find only the GMII PHY. 294 */ 295 if (sc->lge_pcs == 0 && phy == 0) 296 return(0); 297 298 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 299 300 for (i = 0; i < LGE_TIMEOUT; i++) 301 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 302 break; 303 304 if (i == LGE_TIMEOUT) { 305 printf("lge%d: PHY read timed out\n", sc->lge_unit); 306 return(0); 307 } 308 309 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 310 } 311 312 static int lge_miibus_writereg(dev, phy, reg, data) 313 device_t dev; 314 int phy, reg, data; 315 { 316 struct lge_softc *sc; 317 int i; 318 319 sc = device_get_softc(dev); 320 321 CSR_WRITE_4(sc, LGE_GMIICTL, 322 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 323 324 for (i = 0; i < LGE_TIMEOUT; i++) 325 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 326 break; 327 328 if (i == LGE_TIMEOUT) { 329 printf("lge%d: PHY write timed out\n", sc->lge_unit); 330 return(0); 331 } 332 333 return(0); 334 } 335 336 static void lge_miibus_statchg(dev) 337 device_t dev; 338 { 339 struct lge_softc *sc; 340 struct mii_data *mii; 341 342 sc = device_get_softc(dev); 343 mii = device_get_softc(sc->lge_miibus); 344 345 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 346 switch (IFM_SUBTYPE(mii->mii_media_active)) { 347 case IFM_1000_TX: 348 case IFM_1000_SX: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 350 break; 351 case IFM_100_TX: 352 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 353 break; 354 case IFM_10_T: 355 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 356 break; 357 default: 358 /* 359 * Choose something, even if it's wrong. Clearing 360 * all the bits will hose autoneg on the internal 361 * PHY. 362 */ 363 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 364 break; 365 } 366 367 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 368 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 369 } else { 370 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 371 } 372 373 return; 374 } 375 376 static u_int32_t lge_crc(sc, addr) 377 struct lge_softc *sc; 378 caddr_t addr; 379 { 380 u_int32_t crc, carry; 381 int i, j; 382 u_int8_t c; 383 384 /* Compute CRC for the address value. */ 385 crc = 0xFFFFFFFF; /* initial value */ 386 387 for (i = 0; i < 6; i++) { 388 c = *(addr + i); 389 for (j = 0; j < 8; j++) { 390 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 391 crc <<= 1; 392 c >>= 1; 393 if (carry) 394 crc = (crc ^ 0x04c11db6) | carry; 395 } 396 } 397 398 /* 399 * return the filter bit position 400 */ 401 return((crc >> 26) & 0x0000003F); 402 } 403 404 static void lge_setmulti(sc) 405 struct lge_softc *sc; 406 { 407 struct ifnet *ifp; 408 struct ifmultiaddr *ifma; 409 u_int32_t h = 0, hashes[2] = { 0, 0 }; 410 411 ifp = &sc->arpcom.ac_if; 412 413 /* Make sure multicast hash table is enabled. */ 414 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 415 416 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 417 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 418 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 419 return; 420 } 421 422 /* first, zot all the existing hash bits */ 423 CSR_WRITE_4(sc, LGE_MAR0, 0); 424 CSR_WRITE_4(sc, LGE_MAR1, 0); 425 426 /* now program new ones */ 427 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 428 ifma = ifma->ifma_link.le_next) { 429 if (ifma->ifma_addr->sa_family != AF_LINK) 430 continue; 431 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 432 if (h < 32) 433 hashes[0] |= (1 << h); 434 else 435 hashes[1] |= (1 << (h - 32)); 436 } 437 438 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 439 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 440 441 return; 442 } 443 444 static void lge_reset(sc) 445 struct lge_softc *sc; 446 { 447 int i; 448 449 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 450 451 for (i = 0; i < LGE_TIMEOUT; i++) { 452 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 453 break; 454 } 455 456 if (i == LGE_TIMEOUT) 457 printf("lge%d: reset never completed\n", sc->lge_unit); 458 459 /* Wait a little while for the chip to get its brains in order. */ 460 DELAY(1000); 461 462 return; 463 } 464 465 /* 466 * Probe for a Level 1 chip. Check the PCI vendor and device 467 * IDs against our list and return a device name if we find a match. 468 */ 469 static int lge_probe(dev) 470 device_t dev; 471 { 472 struct lge_type *t; 473 474 t = lge_devs; 475 476 while(t->lge_name != NULL) { 477 if ((pci_get_vendor(dev) == t->lge_vid) && 478 (pci_get_device(dev) == t->lge_did)) { 479 device_set_desc(dev, t->lge_name); 480 return(0); 481 } 482 t++; 483 } 484 485 return(ENXIO); 486 } 487 488 /* 489 * Attach the interface. Allocate softc structures, do ifmedia 490 * setup and ethernet/BPF attach. 491 */ 492 static int lge_attach(dev) 493 device_t dev; 494 { 495 int s; 496 u_char eaddr[ETHER_ADDR_LEN]; 497 u_int32_t command; 498 struct lge_softc *sc; 499 struct ifnet *ifp; 500 int unit, error = 0, rid; 501 502 s = splimp(); 503 504 sc = device_get_softc(dev); 505 unit = device_get_unit(dev); 506 bzero(sc, sizeof(struct lge_softc)); 507 callout_init(&sc->lge_stat_timer); 508 509 /* 510 * Handle power management nonsense. 511 */ 512 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF; 513 if (command == 0x01) { 514 515 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4); 516 if (command & LGE_PSTATE_MASK) { 517 u_int32_t iobase, membase, irq; 518 519 /* Save important PCI config data. */ 520 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 521 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 522 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 523 524 /* Reset the power state. */ 525 printf("lge%d: chip is in D%d power mode " 526 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK); 527 command &= 0xFFFFFFFC; 528 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4); 529 530 /* Restore PCI config data. */ 531 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 532 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 533 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 534 } 535 } 536 537 /* 538 * Map control/status registers. 539 */ 540 command = pci_read_config(dev, PCIR_COMMAND, 4); 541 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 542 pci_write_config(dev, PCIR_COMMAND, command, 4); 543 command = pci_read_config(dev, PCIR_COMMAND, 4); 544 545 #ifdef LGE_USEIOSPACE 546 if (!(command & PCIM_CMD_PORTEN)) { 547 printf("lge%d: failed to enable I/O ports!\n", unit); 548 error = ENXIO;; 549 goto fail; 550 } 551 #else 552 if (!(command & PCIM_CMD_MEMEN)) { 553 printf("lge%d: failed to enable memory mapping!\n", unit); 554 error = ENXIO;; 555 goto fail; 556 } 557 #endif 558 559 rid = LGE_RID; 560 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 561 0, ~0, 1, RF_ACTIVE); 562 563 if (sc->lge_res == NULL) { 564 printf("lge%d: couldn't map ports/memory\n", unit); 565 error = ENXIO; 566 goto fail; 567 } 568 569 sc->lge_btag = rman_get_bustag(sc->lge_res); 570 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 571 572 /* Allocate interrupt */ 573 rid = 0; 574 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 575 RF_SHAREABLE | RF_ACTIVE); 576 577 if (sc->lge_irq == NULL) { 578 printf("lge%d: couldn't map interrupt\n", unit); 579 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 580 error = ENXIO; 581 goto fail; 582 } 583 584 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 585 lge_intr, sc, &sc->lge_intrhand); 586 587 if (error) { 588 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 589 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 590 printf("lge%d: couldn't set up irq\n", unit); 591 goto fail; 592 } 593 594 /* Reset the adapter. */ 595 lge_reset(sc); 596 597 /* 598 * Get station address from the EEPROM. 599 */ 600 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 601 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 602 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 603 604 sc->lge_unit = unit; 605 606 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 607 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 608 609 if (sc->lge_ldata == NULL) { 610 printf("lge%d: no memory for list buffers!\n", unit); 611 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 612 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 613 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 614 error = ENXIO; 615 goto fail; 616 } 617 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 618 619 /* Try to allocate memory for jumbo buffers. */ 620 if (lge_alloc_jumbo_mem(sc)) { 621 printf("lge%d: jumbo buffer allocation failed\n", 622 sc->lge_unit); 623 contigfree(sc->lge_ldata, 624 sizeof(struct lge_list_data), M_DEVBUF); 625 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 626 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 627 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 628 error = ENXIO; 629 goto fail; 630 } 631 632 ifp = &sc->arpcom.ac_if; 633 ifp->if_softc = sc; 634 if_initname(ifp, "lge", unit); 635 ifp->if_mtu = ETHERMTU; 636 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 637 ifp->if_ioctl = lge_ioctl; 638 ifp->if_start = lge_start; 639 ifp->if_watchdog = lge_watchdog; 640 ifp->if_init = lge_init; 641 ifp->if_baudrate = 1000000000; 642 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 643 ifp->if_capabilities = IFCAP_RXCSUM; 644 ifp->if_capenable = ifp->if_capabilities; 645 646 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 647 sc->lge_pcs = 1; 648 else 649 sc->lge_pcs = 0; 650 651 /* 652 * Do MII setup. 653 */ 654 if (mii_phy_probe(dev, &sc->lge_miibus, 655 lge_ifmedia_upd, lge_ifmedia_sts)) { 656 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 657 contigfree(sc->lge_ldata, 658 sizeof(struct lge_list_data), M_DEVBUF); 659 lge_free_jumbo_mem(sc); 660 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 662 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 663 error = ENXIO; 664 goto fail; 665 } 666 667 /* 668 * Call MI attach routine. 669 */ 670 ether_ifattach(ifp, eaddr); 671 672 fail: 673 splx(s); 674 return(error); 675 } 676 677 static int lge_detach(dev) 678 device_t dev; 679 { 680 struct lge_softc *sc; 681 struct ifnet *ifp; 682 int s; 683 684 s = splimp(); 685 686 sc = device_get_softc(dev); 687 ifp = &sc->arpcom.ac_if; 688 689 lge_reset(sc); 690 lge_stop(sc); 691 ether_ifdetach(ifp); 692 693 bus_generic_detach(dev); 694 device_delete_child(dev, sc->lge_miibus); 695 696 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 697 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 698 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 699 700 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 701 lge_free_jumbo_mem(sc); 702 703 splx(s); 704 705 return(0); 706 } 707 708 /* 709 * Initialize the transmit descriptors. 710 */ 711 static int lge_list_tx_init(sc) 712 struct lge_softc *sc; 713 { 714 struct lge_list_data *ld; 715 struct lge_ring_data *cd; 716 int i; 717 718 cd = &sc->lge_cdata; 719 ld = sc->lge_ldata; 720 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 721 ld->lge_tx_list[i].lge_mbuf = NULL; 722 ld->lge_tx_list[i].lge_ctl = 0; 723 } 724 725 cd->lge_tx_prod = cd->lge_tx_cons = 0; 726 727 return(0); 728 } 729 730 731 /* 732 * Initialize the RX descriptors and allocate mbufs for them. Note that 733 * we arralge the descriptors in a closed ring, so that the last descriptor 734 * points back to the first. 735 */ 736 static int lge_list_rx_init(sc) 737 struct lge_softc *sc; 738 { 739 struct lge_list_data *ld; 740 struct lge_ring_data *cd; 741 int i; 742 743 ld = sc->lge_ldata; 744 cd = &sc->lge_cdata; 745 746 cd->lge_rx_prod = cd->lge_rx_cons = 0; 747 748 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 749 750 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 751 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 752 break; 753 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 754 return(ENOBUFS); 755 } 756 757 /* Clear possible 'rx command queue empty' interrupt. */ 758 CSR_READ_4(sc, LGE_ISR); 759 760 return(0); 761 } 762 763 /* 764 * Initialize an RX descriptor and attach an MBUF cluster. 765 */ 766 static int lge_newbuf(sc, c, m) 767 struct lge_softc *sc; 768 struct lge_rx_desc *c; 769 struct mbuf *m; 770 { 771 struct mbuf *m_new = NULL; 772 caddr_t *buf = NULL; 773 774 if (m == NULL) { 775 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 776 if (m_new == NULL) { 777 printf("lge%d: no memory for rx list " 778 "-- packet dropped!\n", sc->lge_unit); 779 return(ENOBUFS); 780 } 781 782 /* Allocate the jumbo buffer */ 783 buf = lge_jalloc(sc); 784 if (buf == NULL) { 785 #ifdef LGE_VERBOSE 786 printf("lge%d: jumbo allocation failed " 787 "-- packet dropped!\n", sc->lge_unit); 788 #endif 789 m_freem(m_new); 790 return(ENOBUFS); 791 } 792 /* Attach the buffer to the mbuf */ 793 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 794 m_new->m_flags |= M_EXT | M_EXT_OLD; 795 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 796 m_new->m_len = LGE_MCLBYTES; 797 m_new->m_ext.ext_nfree.old = lge_jfree; 798 m_new->m_ext.ext_nref.old = lge_jref; 799 } else { 800 m_new = m; 801 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES; 802 m_new->m_data = m_new->m_ext.ext_buf; 803 } 804 805 /* 806 * Adjust alignment so packet payload begins on a 807 * longword boundary. Mandatory for Alpha, useful on 808 * x86 too. 809 */ 810 m_adj(m_new, ETHER_ALIGN); 811 812 c->lge_mbuf = m_new; 813 c->lge_fragptr_hi = 0; 814 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 815 c->lge_fraglen = m_new->m_len; 816 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 817 c->lge_sts = 0; 818 819 /* 820 * Put this buffer in the RX command FIFO. To do this, 821 * we just write the physical address of the descriptor 822 * into the RX descriptor address registers. Note that 823 * there are two registers, one high DWORD and one low 824 * DWORD, which lets us specify a 64-bit address if 825 * desired. We only use a 32-bit address for now. 826 * Writing to the low DWORD register is what actually 827 * causes the command to be issued, so we do that 828 * last. 829 */ 830 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 831 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 832 833 return(0); 834 } 835 836 static int lge_alloc_jumbo_mem(sc) 837 struct lge_softc *sc; 838 { 839 caddr_t ptr; 840 int i; 841 struct lge_jpool_entry *entry; 842 843 /* Grab a big chunk o' storage. */ 844 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 845 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 846 847 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 848 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 849 return(ENOBUFS); 850 } 851 852 SLIST_INIT(&sc->lge_jfree_listhead); 853 SLIST_INIT(&sc->lge_jinuse_listhead); 854 855 /* 856 * Now divide it up into 9K pieces and save the addresses 857 * in an array. 858 */ 859 ptr = sc->lge_cdata.lge_jumbo_buf; 860 for (i = 0; i < LGE_JSLOTS; i++) { 861 u_int64_t **aptr; 862 aptr = (u_int64_t **)ptr; 863 aptr[0] = (u_int64_t *)sc; 864 ptr += sizeof(u_int64_t); 865 sc->lge_cdata.lge_jslots[i].lge_buf = ptr; 866 sc->lge_cdata.lge_jslots[i].lge_inuse = 0; 867 ptr += LGE_MCLBYTES; 868 entry = malloc(sizeof(struct lge_jpool_entry), 869 M_DEVBUF, M_WAITOK); 870 entry->slot = i; 871 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 872 entry, jpool_entries); 873 } 874 875 return(0); 876 } 877 878 static void lge_free_jumbo_mem(sc) 879 struct lge_softc *sc; 880 { 881 int i; 882 struct lge_jpool_entry *entry; 883 884 for (i = 0; i < LGE_JSLOTS; i++) { 885 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 886 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 887 free(entry, M_DEVBUF); 888 } 889 890 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 891 892 return; 893 } 894 895 /* 896 * Allocate a jumbo buffer. 897 */ 898 static void *lge_jalloc(sc) 899 struct lge_softc *sc; 900 { 901 struct lge_jpool_entry *entry; 902 903 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 904 905 if (entry == NULL) { 906 #ifdef LGE_VERBOSE 907 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 908 #endif 909 return(NULL); 910 } 911 912 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 913 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 914 sc->lge_cdata.lge_jslots[entry->slot].lge_inuse = 1; 915 return(sc->lge_cdata.lge_jslots[entry->slot].lge_buf); 916 } 917 918 /* 919 * Adjust usage count on a jumbo buffer. In general this doesn't 920 * get used much because our jumbo buffers don't get passed around 921 * a lot, but it's implemented for correctness. 922 */ 923 static void lge_jref(buf, size) 924 caddr_t buf; 925 u_int size; 926 { 927 struct lge_softc *sc; 928 u_int64_t **aptr; 929 int i; 930 931 /* Extract the softc struct pointer. */ 932 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 933 sc = (struct lge_softc *)(aptr[0]); 934 935 if (sc == NULL) 936 panic("lge_jref: can't find softc pointer!"); 937 938 if (size != LGE_MCLBYTES) 939 panic("lge_jref: adjusting refcount of buf of wrong size!"); 940 941 /* calculate the slot this buffer belongs to */ 942 943 i = ((vm_offset_t)aptr 944 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 945 946 if ((i < 0) || (i >= LGE_JSLOTS)) 947 panic("lge_jref: asked to reference buffer " 948 "that we don't manage!"); 949 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0) 950 panic("lge_jref: buffer already free!"); 951 else 952 sc->lge_cdata.lge_jslots[i].lge_inuse++; 953 954 return; 955 } 956 957 /* 958 * Release a jumbo buffer. 959 */ 960 static void lge_jfree(buf, size) 961 caddr_t buf; 962 u_int size; 963 { 964 struct lge_softc *sc; 965 u_int64_t **aptr; 966 int i; 967 struct lge_jpool_entry *entry; 968 969 /* Extract the softc struct pointer. */ 970 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 971 sc = (struct lge_softc *)(aptr[0]); 972 973 if (sc == NULL) 974 panic("lge_jfree: can't find softc pointer!"); 975 976 if (size != LGE_MCLBYTES) 977 panic("lge_jfree: freeing buffer of wrong size!"); 978 979 /* calculate the slot this buffer belongs to */ 980 i = ((vm_offset_t)aptr 981 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 982 983 if ((i < 0) || (i >= LGE_JSLOTS)) 984 panic("lge_jfree: asked to free buffer that we don't manage!"); 985 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0) 986 panic("lge_jfree: buffer already free!"); 987 else { 988 sc->lge_cdata.lge_jslots[i].lge_inuse--; 989 if(sc->lge_cdata.lge_jslots[i].lge_inuse == 0) { 990 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 991 if (entry == NULL) 992 panic("lge_jfree: buffer not in use!"); 993 entry->slot = i; 994 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, 995 jpool_entries); 996 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 997 entry, jpool_entries); 998 } 999 } 1000 1001 return; 1002 } 1003 1004 /* 1005 * A frame has been uploaded: pass the resulting mbuf chain up to 1006 * the higher level protocols. 1007 */ 1008 static void lge_rxeof(sc, cnt) 1009 struct lge_softc *sc; 1010 int cnt; 1011 { 1012 struct mbuf *m; 1013 struct ifnet *ifp; 1014 struct lge_rx_desc *cur_rx; 1015 int c, i, total_len = 0; 1016 u_int32_t rxsts, rxctl; 1017 1018 ifp = &sc->arpcom.ac_if; 1019 1020 /* Find out how many frames were processed. */ 1021 c = cnt; 1022 i = sc->lge_cdata.lge_rx_cons; 1023 1024 /* Suck them in. */ 1025 while(c) { 1026 struct mbuf *m0 = NULL; 1027 1028 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 1029 rxctl = cur_rx->lge_ctl; 1030 rxsts = cur_rx->lge_sts; 1031 m = cur_rx->lge_mbuf; 1032 cur_rx->lge_mbuf = NULL; 1033 total_len = LGE_RXBYTES(cur_rx); 1034 LGE_INC(i, LGE_RX_LIST_CNT); 1035 c--; 1036 1037 /* 1038 * If an error occurs, update stats, clear the 1039 * status word and leave the mbuf cluster in place: 1040 * it should simply get re-used next time this descriptor 1041 * comes up in the ring. 1042 */ 1043 if (rxctl & LGE_RXCTL_ERRMASK) { 1044 ifp->if_ierrors++; 1045 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 1046 continue; 1047 } 1048 1049 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 1050 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1051 total_len + ETHER_ALIGN, 0, ifp, NULL); 1052 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 1053 if (m0 == NULL) { 1054 printf("lge%d: no receive buffers " 1055 "available -- packet dropped!\n", 1056 sc->lge_unit); 1057 ifp->if_ierrors++; 1058 continue; 1059 } 1060 m_adj(m0, ETHER_ALIGN); 1061 m = m0; 1062 } else { 1063 m->m_pkthdr.rcvif = ifp; 1064 m->m_pkthdr.len = m->m_len = total_len; 1065 } 1066 1067 ifp->if_ipackets++; 1068 1069 /* Do IP checksum checking. */ 1070 if (rxsts & LGE_RXSTS_ISIP) 1071 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1072 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1073 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1074 if ((rxsts & LGE_RXSTS_ISTCP && 1075 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1076 (rxsts & LGE_RXSTS_ISUDP && 1077 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1078 m->m_pkthdr.csum_flags |= 1079 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1080 m->m_pkthdr.csum_data = 0xffff; 1081 } 1082 1083 (*ifp->if_input)(ifp, m); 1084 } 1085 1086 sc->lge_cdata.lge_rx_cons = i; 1087 1088 return; 1089 } 1090 1091 void lge_rxeoc(sc) 1092 struct lge_softc *sc; 1093 { 1094 struct ifnet *ifp; 1095 1096 ifp = &sc->arpcom.ac_if; 1097 ifp->if_flags &= ~IFF_RUNNING; 1098 lge_init(sc); 1099 return; 1100 } 1101 1102 /* 1103 * A frame was downloaded to the chip. It's safe for us to clean up 1104 * the list buffers. 1105 */ 1106 1107 static void lge_txeof(sc) 1108 struct lge_softc *sc; 1109 { 1110 struct lge_tx_desc *cur_tx = NULL; 1111 struct ifnet *ifp; 1112 u_int32_t idx, txdone; 1113 1114 ifp = &sc->arpcom.ac_if; 1115 1116 /* Clear the timeout timer. */ 1117 ifp->if_timer = 0; 1118 1119 /* 1120 * Go through our tx list and free mbufs for those 1121 * frames that have been transmitted. 1122 */ 1123 idx = sc->lge_cdata.lge_tx_cons; 1124 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1125 1126 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1127 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1128 1129 ifp->if_opackets++; 1130 if (cur_tx->lge_mbuf != NULL) { 1131 m_freem(cur_tx->lge_mbuf); 1132 cur_tx->lge_mbuf = NULL; 1133 } 1134 cur_tx->lge_ctl = 0; 1135 1136 txdone--; 1137 LGE_INC(idx, LGE_TX_LIST_CNT); 1138 ifp->if_timer = 0; 1139 } 1140 1141 sc->lge_cdata.lge_tx_cons = idx; 1142 1143 if (cur_tx != NULL) 1144 ifp->if_flags &= ~IFF_OACTIVE; 1145 1146 return; 1147 } 1148 1149 static void lge_tick(xsc) 1150 void *xsc; 1151 { 1152 struct lge_softc *sc; 1153 struct mii_data *mii; 1154 struct ifnet *ifp; 1155 int s; 1156 1157 s = splimp(); 1158 1159 sc = xsc; 1160 ifp = &sc->arpcom.ac_if; 1161 1162 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1163 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1164 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1165 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1166 1167 if (!sc->lge_link) { 1168 mii = device_get_softc(sc->lge_miibus); 1169 mii_tick(mii); 1170 mii_pollstat(mii); 1171 if (mii->mii_media_status & IFM_ACTIVE && 1172 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1173 sc->lge_link++; 1174 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1175 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1176 printf("lge%d: gigabit link up\n", 1177 sc->lge_unit); 1178 if (ifp->if_snd.ifq_head != NULL) 1179 lge_start(ifp); 1180 } 1181 } 1182 1183 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1184 1185 splx(s); 1186 1187 return; 1188 } 1189 1190 static void lge_intr(arg) 1191 void *arg; 1192 { 1193 struct lge_softc *sc; 1194 struct ifnet *ifp; 1195 u_int32_t status; 1196 1197 sc = arg; 1198 ifp = &sc->arpcom.ac_if; 1199 1200 /* Supress unwanted interrupts */ 1201 if (!(ifp->if_flags & IFF_UP)) { 1202 lge_stop(sc); 1203 return; 1204 } 1205 1206 for (;;) { 1207 /* 1208 * Reading the ISR register clears all interrupts, and 1209 * clears the 'interrupts enabled' bit in the IMR 1210 * register. 1211 */ 1212 status = CSR_READ_4(sc, LGE_ISR); 1213 1214 if ((status & LGE_INTRS) == 0) 1215 break; 1216 1217 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1218 lge_txeof(sc); 1219 1220 if (status & LGE_ISR_RXDMA_DONE) 1221 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1222 1223 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1224 lge_rxeoc(sc); 1225 1226 if (status & LGE_ISR_PHY_INTR) { 1227 sc->lge_link = 0; 1228 callout_stop(&sc->lge_stat_timer); 1229 lge_tick(sc); 1230 } 1231 } 1232 1233 /* Re-enable interrupts. */ 1234 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1235 1236 if (ifp->if_snd.ifq_head != NULL) 1237 lge_start(ifp); 1238 1239 return; 1240 } 1241 1242 /* 1243 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1244 * pointers to the fragment pointers. 1245 */ 1246 static int lge_encap(sc, m_head, txidx) 1247 struct lge_softc *sc; 1248 struct mbuf *m_head; 1249 u_int32_t *txidx; 1250 { 1251 struct lge_frag *f = NULL; 1252 struct lge_tx_desc *cur_tx; 1253 struct mbuf *m; 1254 int frag = 0, tot_len = 0; 1255 1256 /* 1257 * Start packing the mbufs in this chain into 1258 * the fragment pointers. Stop when we run out 1259 * of fragments or hit the end of the mbuf chain. 1260 */ 1261 m = m_head; 1262 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1263 frag = 0; 1264 1265 for (m = m_head; m != NULL; m = m->m_next) { 1266 if (m->m_len != 0) { 1267 tot_len += m->m_len; 1268 f = &cur_tx->lge_frags[frag]; 1269 f->lge_fraglen = m->m_len; 1270 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1271 f->lge_fragptr_hi = 0; 1272 frag++; 1273 } 1274 } 1275 1276 if (m != NULL) 1277 return(ENOBUFS); 1278 1279 cur_tx->lge_mbuf = m_head; 1280 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1281 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1282 1283 /* Queue for transmit */ 1284 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1285 1286 return(0); 1287 } 1288 1289 /* 1290 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1291 * to the mbuf data regions directly in the transmit lists. We also save a 1292 * copy of the pointers since the transmit list fragment pointers are 1293 * physical addresses. 1294 */ 1295 1296 static void lge_start(ifp) 1297 struct ifnet *ifp; 1298 { 1299 struct lge_softc *sc; 1300 struct mbuf *m_head = NULL; 1301 u_int32_t idx; 1302 1303 sc = ifp->if_softc; 1304 1305 if (!sc->lge_link) 1306 return; 1307 1308 idx = sc->lge_cdata.lge_tx_prod; 1309 1310 if (ifp->if_flags & IFF_OACTIVE) 1311 return; 1312 1313 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1314 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1315 break; 1316 1317 IF_DEQUEUE(&ifp->if_snd, m_head); 1318 if (m_head == NULL) 1319 break; 1320 1321 if (lge_encap(sc, m_head, &idx)) { 1322 IF_PREPEND(&ifp->if_snd, m_head); 1323 ifp->if_flags |= IFF_OACTIVE; 1324 break; 1325 } 1326 1327 /* 1328 * If there's a BPF listener, bounce a copy of this frame 1329 * to him. 1330 */ 1331 if (ifp->if_bpf) 1332 bpf_mtap(ifp, m_head); 1333 } 1334 1335 sc->lge_cdata.lge_tx_prod = idx; 1336 1337 /* 1338 * Set a timeout in case the chip goes out to lunch. 1339 */ 1340 ifp->if_timer = 5; 1341 1342 return; 1343 } 1344 1345 static void lge_init(xsc) 1346 void *xsc; 1347 { 1348 struct lge_softc *sc = xsc; 1349 struct ifnet *ifp = &sc->arpcom.ac_if; 1350 struct mii_data *mii; 1351 int s; 1352 1353 if (ifp->if_flags & IFF_RUNNING) 1354 return; 1355 1356 s = splimp(); 1357 1358 /* 1359 * Cancel pending I/O and free all RX/TX buffers. 1360 */ 1361 lge_stop(sc); 1362 lge_reset(sc); 1363 1364 mii = device_get_softc(sc->lge_miibus); 1365 1366 /* Set MAC address */ 1367 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1368 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1369 1370 /* Init circular RX list. */ 1371 if (lge_list_rx_init(sc) == ENOBUFS) { 1372 printf("lge%d: initialization failed: no " 1373 "memory for rx buffers\n", sc->lge_unit); 1374 lge_stop(sc); 1375 (void)splx(s); 1376 return; 1377 } 1378 1379 /* 1380 * Init tx descriptors. 1381 */ 1382 lge_list_tx_init(sc); 1383 1384 /* Set initial value for MODE1 register. */ 1385 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1386 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1387 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1388 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1389 1390 /* If we want promiscuous mode, set the allframes bit. */ 1391 if (ifp->if_flags & IFF_PROMISC) { 1392 CSR_WRITE_4(sc, LGE_MODE1, 1393 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1394 } else { 1395 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1396 } 1397 1398 /* 1399 * Set the capture broadcast bit to capture broadcast frames. 1400 */ 1401 if (ifp->if_flags & IFF_BROADCAST) { 1402 CSR_WRITE_4(sc, LGE_MODE1, 1403 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1404 } else { 1405 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1406 } 1407 1408 /* Packet padding workaround? */ 1409 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1410 1411 /* No error frames */ 1412 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1413 1414 /* Receive large frames */ 1415 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1416 1417 /* Workaround: disable RX/TX flow control */ 1418 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1419 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1420 1421 /* Make sure to strip CRC from received frames */ 1422 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1423 1424 /* Turn off magic packet mode */ 1425 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1426 1427 /* Turn off all VLAN stuff */ 1428 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1429 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1430 1431 /* Workarond: FIFO overflow */ 1432 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1433 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1434 1435 /* 1436 * Load the multicast filter. 1437 */ 1438 lge_setmulti(sc); 1439 1440 /* 1441 * Enable hardware checksum validation for all received IPv4 1442 * packets, do not reject packets with bad checksums. 1443 */ 1444 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1445 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1446 LGE_MODE2_RX_ERRCSUM); 1447 1448 /* 1449 * Enable the delivery of PHY interrupts based on 1450 * link/speed/duplex status chalges. 1451 */ 1452 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1453 1454 /* Enable receiver and transmitter. */ 1455 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1456 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1457 1458 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1459 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1460 1461 /* 1462 * Enable interrupts. 1463 */ 1464 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1465 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1466 1467 lge_ifmedia_upd(ifp); 1468 1469 ifp->if_flags |= IFF_RUNNING; 1470 ifp->if_flags &= ~IFF_OACTIVE; 1471 1472 (void)splx(s); 1473 1474 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1475 1476 return; 1477 } 1478 1479 /* 1480 * Set media options. 1481 */ 1482 static int lge_ifmedia_upd(ifp) 1483 struct ifnet *ifp; 1484 { 1485 struct lge_softc *sc; 1486 struct mii_data *mii; 1487 1488 sc = ifp->if_softc; 1489 1490 mii = device_get_softc(sc->lge_miibus); 1491 sc->lge_link = 0; 1492 if (mii->mii_instance) { 1493 struct mii_softc *miisc; 1494 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1495 miisc = LIST_NEXT(miisc, mii_list)) 1496 mii_phy_reset(miisc); 1497 } 1498 mii_mediachg(mii); 1499 1500 return(0); 1501 } 1502 1503 /* 1504 * Report current media status. 1505 */ 1506 static void lge_ifmedia_sts(ifp, ifmr) 1507 struct ifnet *ifp; 1508 struct ifmediareq *ifmr; 1509 { 1510 struct lge_softc *sc; 1511 struct mii_data *mii; 1512 1513 sc = ifp->if_softc; 1514 1515 mii = device_get_softc(sc->lge_miibus); 1516 mii_pollstat(mii); 1517 ifmr->ifm_active = mii->mii_media_active; 1518 ifmr->ifm_status = mii->mii_media_status; 1519 1520 return; 1521 } 1522 1523 static int lge_ioctl(ifp, command, data, cr) 1524 struct ifnet *ifp; 1525 u_long command; 1526 caddr_t data; 1527 struct ucred *cr; 1528 { 1529 struct lge_softc *sc = ifp->if_softc; 1530 struct ifreq *ifr = (struct ifreq *) data; 1531 struct mii_data *mii; 1532 int s, error = 0; 1533 1534 s = splimp(); 1535 1536 switch(command) { 1537 case SIOCSIFADDR: 1538 case SIOCGIFADDR: 1539 error = ether_ioctl(ifp, command, data); 1540 break; 1541 case SIOCSIFMTU: 1542 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1543 error = EINVAL; 1544 else 1545 ifp->if_mtu = ifr->ifr_mtu; 1546 break; 1547 case SIOCSIFFLAGS: 1548 if (ifp->if_flags & IFF_UP) { 1549 if (ifp->if_flags & IFF_RUNNING && 1550 ifp->if_flags & IFF_PROMISC && 1551 !(sc->lge_if_flags & IFF_PROMISC)) { 1552 CSR_WRITE_4(sc, LGE_MODE1, 1553 LGE_MODE1_SETRST_CTL1| 1554 LGE_MODE1_RX_PROMISC); 1555 } else if (ifp->if_flags & IFF_RUNNING && 1556 !(ifp->if_flags & IFF_PROMISC) && 1557 sc->lge_if_flags & IFF_PROMISC) { 1558 CSR_WRITE_4(sc, LGE_MODE1, 1559 LGE_MODE1_RX_PROMISC); 1560 } else { 1561 ifp->if_flags &= ~IFF_RUNNING; 1562 lge_init(sc); 1563 } 1564 } else { 1565 if (ifp->if_flags & IFF_RUNNING) 1566 lge_stop(sc); 1567 } 1568 sc->lge_if_flags = ifp->if_flags; 1569 error = 0; 1570 break; 1571 case SIOCADDMULTI: 1572 case SIOCDELMULTI: 1573 lge_setmulti(sc); 1574 error = 0; 1575 break; 1576 case SIOCGIFMEDIA: 1577 case SIOCSIFMEDIA: 1578 mii = device_get_softc(sc->lge_miibus); 1579 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1580 break; 1581 default: 1582 error = EINVAL; 1583 break; 1584 } 1585 1586 (void)splx(s); 1587 1588 return(error); 1589 } 1590 1591 static void lge_watchdog(ifp) 1592 struct ifnet *ifp; 1593 { 1594 struct lge_softc *sc; 1595 1596 sc = ifp->if_softc; 1597 1598 ifp->if_oerrors++; 1599 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1600 1601 lge_stop(sc); 1602 lge_reset(sc); 1603 ifp->if_flags &= ~IFF_RUNNING; 1604 lge_init(sc); 1605 1606 if (ifp->if_snd.ifq_head != NULL) 1607 lge_start(ifp); 1608 1609 return; 1610 } 1611 1612 /* 1613 * Stop the adapter and free any mbufs allocated to the 1614 * RX and TX lists. 1615 */ 1616 static void lge_stop(sc) 1617 struct lge_softc *sc; 1618 { 1619 int i; 1620 struct ifnet *ifp; 1621 1622 ifp = &sc->arpcom.ac_if; 1623 ifp->if_timer = 0; 1624 callout_stop(&sc->lge_stat_timer); 1625 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1626 1627 /* Disable receiver and transmitter. */ 1628 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1629 sc->lge_link = 0; 1630 1631 /* 1632 * Free data in the RX lists. 1633 */ 1634 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1635 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1636 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1637 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1638 } 1639 } 1640 bzero((char *)&sc->lge_ldata->lge_rx_list, 1641 sizeof(sc->lge_ldata->lge_rx_list)); 1642 1643 /* 1644 * Free the TX list buffers. 1645 */ 1646 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1647 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1648 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1649 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1650 } 1651 } 1652 1653 bzero((char *)&sc->lge_ldata->lge_tx_list, 1654 sizeof(sc->lge_ldata->lge_tx_list)); 1655 1656 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1657 1658 return; 1659 } 1660 1661 /* 1662 * Stop all chip I/O so that the kernel's probe routines don't 1663 * get confused by errant DMAs when rebooting. 1664 */ 1665 static void lge_shutdown(dev) 1666 device_t dev; 1667 { 1668 struct lge_softc *sc; 1669 1670 sc = device_get_softc(dev); 1671 1672 lge_reset(sc); 1673 lge_stop(sc); 1674 1675 return; 1676 } 1677