1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.36 2006/08/01 18:05:02 swildner Exp $ 35 */ 36 37 /* 38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 39 * documentation not available, but ask me nicely. 40 * 41 * Written by Bill Paul <william.paul@windriver.com> 42 * Wind River Systems 43 */ 44 45 /* 46 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 47 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 48 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 49 * are three supported methods for data transfer between host and 50 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 51 * Propulsion Technology (tm) DMA. The latter mechanism is a form 52 * of double buffer DMA where the packet data is copied to a 53 * pre-allocated DMA buffer who's physical address has been loaded 54 * into a table at device initialization time. The rationale is that 55 * the virtual to physical address translation needed for normal 56 * scatter/gather DMA is more expensive than the data copy needed 57 * for double buffering. This may be true in Windows NT and the like, 58 * but it isn't true for us, at least on the x86 arch. This driver 59 * uses the scatter/gather I/O method for both TX and RX. 60 * 61 * The LXT1001 only supports TCP/IP checksum offload on receive. 62 * Also, the VLAN tagging is done using a 16-entry table which allows 63 * the chip to perform hardware filtering based on VLAN tags. Sadly, 64 * our vlan support doesn't currently play well with this kind of 65 * hardware support. 66 * 67 * Special thanks to: 68 * - Jeff James at Intel, for arranging to have the LXT1001 manual 69 * released (at long last) 70 * - Beny Chen at D-Link, for actually sending it to me 71 * - Brad Short and Keith Alexis at SMC, for sending me sample 72 * SMC9462SX and SMC9462TX adapters for testing 73 * - Paul Saab at Y!, for not killing me (though it remains to be seen 74 * if in fact he did me much of a favor) 75 */ 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/sockio.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/socket.h> 84 #include <sys/serialize.h> 85 #include <sys/thread2.h> 86 87 #include <net/if.h> 88 #include <net/ifq_var.h> 89 #include <net/if_arp.h> 90 #include <net/ethernet.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 94 #include <net/bpf.h> 95 96 #include <vm/vm.h> /* for vtophys */ 97 #include <vm/pmap.h> /* for vtophys */ 98 #include <machine/bus.h> 99 #include <machine/resource.h> 100 #include <sys/bus.h> 101 #include <sys/rman.h> 102 103 #include <dev/netif/mii_layer/mii.h> 104 #include <dev/netif/mii_layer/miivar.h> 105 106 #include <bus/pci/pcidevs.h> 107 #include <bus/pci/pcireg.h> 108 #include <bus/pci/pcivar.h> 109 110 #define LGE_USEIOSPACE 111 112 #include "if_lgereg.h" 113 114 /* "controller miibus0" required. See GENERIC if you get errors here. */ 115 #include "miibus_if.h" 116 117 /* 118 * Various supported device vendors/types and their names. 119 */ 120 static struct lge_type lge_devs[] = { 121 { PCI_VENDOR_LEVELONE, PCI_PRODUCT_LEVELONE_LXT1001, 122 "Level 1 Gigabit Ethernet" }, 123 { 0, 0, NULL } 124 }; 125 126 static int lge_probe(device_t); 127 static int lge_attach(device_t); 128 static int lge_detach(device_t); 129 130 static int lge_alloc_jumbo_mem(struct lge_softc *); 131 static void lge_free_jumbo_mem(struct lge_softc *); 132 static struct lge_jslot 133 *lge_jalloc(struct lge_softc *); 134 static void lge_jfree(void *); 135 static void lge_jref(void *); 136 137 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 138 struct mbuf *); 139 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *); 140 static void lge_rxeof(struct lge_softc *, int); 141 static void lge_rxeoc(struct lge_softc *); 142 static void lge_txeof(struct lge_softc *); 143 static void lge_intr(void *); 144 static void lge_tick(void *); 145 static void lge_tick_serialized(void *); 146 static void lge_start(struct ifnet *); 147 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 148 static void lge_init(void *); 149 static void lge_stop(struct lge_softc *); 150 static void lge_watchdog(struct ifnet *); 151 static void lge_shutdown(device_t); 152 static int lge_ifmedia_upd(struct ifnet *); 153 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 154 155 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *); 156 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int); 157 158 static int lge_miibus_readreg(device_t, int, int); 159 static int lge_miibus_writereg(device_t, int, int, int); 160 static void lge_miibus_statchg(device_t); 161 162 static void lge_setmulti(struct lge_softc *); 163 static void lge_reset(struct lge_softc *); 164 static int lge_list_rx_init(struct lge_softc *); 165 static int lge_list_tx_init(struct lge_softc *); 166 167 #ifdef LGE_USEIOSPACE 168 #define LGE_RES SYS_RES_IOPORT 169 #define LGE_RID LGE_PCI_LOIO 170 #else 171 #define LGE_RES SYS_RES_MEMORY 172 #define LGE_RID LGE_PCI_LOMEM 173 #endif 174 175 static device_method_t lge_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, lge_probe), 178 DEVMETHOD(device_attach, lge_attach), 179 DEVMETHOD(device_detach, lge_detach), 180 DEVMETHOD(device_shutdown, lge_shutdown), 181 182 /* bus interface */ 183 DEVMETHOD(bus_print_child, bus_generic_print_child), 184 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 185 186 /* MII interface */ 187 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 188 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 189 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 190 191 { 0, 0 } 192 }; 193 194 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc)); 195 static devclass_t lge_devclass; 196 197 DECLARE_DUMMY_MODULE(if_lge); 198 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0); 199 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 200 201 #define LGE_SETBIT(sc, reg, x) \ 202 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 203 204 #define LGE_CLRBIT(sc, reg, x) \ 205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 206 207 #define SIO_SET(x) \ 208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x)) 209 210 #define SIO_CLR(x) \ 211 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x)) 212 213 /* 214 * Read a word of data stored in the EEPROM at address 'addr.' 215 */ 216 static void 217 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest) 218 { 219 int i; 220 uint32_t val; 221 222 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 223 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8)); 224 225 for (i = 0; i < LGE_TIMEOUT; i++) { 226 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0) 227 break; 228 } 229 230 if (i == LGE_TIMEOUT) { 231 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 232 return; 233 } 234 235 val = CSR_READ_4(sc, LGE_EEDATA); 236 237 if (addr & 1) 238 *dest = (val >> 16) & 0xFFFF; 239 else 240 *dest = val & 0xFFFF; 241 } 242 243 /* 244 * Read a sequence of words from the EEPROM. 245 */ 246 static void 247 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt) 248 { 249 int i; 250 uint16_t word = 0, *ptr; 251 252 for (i = 0; i < cnt; i++) { 253 lge_eeprom_getword(sc, off + i, &word); 254 ptr = (uint16_t *)(dest + (i * 2)); 255 *ptr = ntohs(word); 256 } 257 } 258 259 static int 260 lge_miibus_readreg(device_t dev, int phy, int reg) 261 { 262 struct lge_softc *sc = device_get_softc(dev); 263 int i; 264 265 /* 266 * If we have a non-PCS PHY, pretend that the internal 267 * autoneg stuff at PHY address 0 isn't there so that 268 * the miibus code will find only the GMII PHY. 269 */ 270 if (sc->lge_pcs == 0 && phy == 0) 271 return(0); 272 273 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 274 275 for (i = 0; i < LGE_TIMEOUT; i++) { 276 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 277 break; 278 } 279 280 if (i == LGE_TIMEOUT) { 281 printf("lge%d: PHY read timed out\n", sc->lge_unit); 282 return(0); 283 } 284 285 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 286 } 287 288 static int 289 lge_miibus_writereg(device_t dev, int phy, int reg, int data) 290 { 291 struct lge_softc *sc = device_get_softc(dev); 292 int i; 293 294 CSR_WRITE_4(sc, LGE_GMIICTL, 295 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 296 297 for (i = 0; i < LGE_TIMEOUT; i++) { 298 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 299 break; 300 } 301 302 if (i == LGE_TIMEOUT) { 303 printf("lge%d: PHY write timed out\n", sc->lge_unit); 304 return(0); 305 } 306 307 return(0); 308 } 309 310 static void 311 lge_miibus_statchg(device_t dev) 312 { 313 struct lge_softc *sc = device_get_softc(dev); 314 struct mii_data *mii = device_get_softc(sc->lge_miibus); 315 316 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 317 switch (IFM_SUBTYPE(mii->mii_media_active)) { 318 case IFM_1000_T: 319 case IFM_1000_SX: 320 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 321 break; 322 case IFM_100_TX: 323 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 324 break; 325 case IFM_10_T: 326 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 327 break; 328 default: 329 /* 330 * Choose something, even if it's wrong. Clearing 331 * all the bits will hose autoneg on the internal 332 * PHY. 333 */ 334 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 335 break; 336 } 337 338 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 339 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 340 else 341 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 342 } 343 344 static void 345 lge_setmulti(struct lge_softc *sc) 346 { 347 struct ifnet *ifp = &sc->arpcom.ac_if; 348 struct ifmultiaddr *ifma; 349 uint32_t h = 0, hashes[2] = { 0, 0 }; 350 351 /* Make sure multicast hash table is enabled. */ 352 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST); 353 354 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 355 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 356 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 357 return; 358 } 359 360 /* first, zot all the existing hash bits */ 361 CSR_WRITE_4(sc, LGE_MAR0, 0); 362 CSR_WRITE_4(sc, LGE_MAR1, 0); 363 364 /* now program new ones */ 365 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 366 if (ifma->ifma_addr->sa_family != AF_LINK) 367 continue; 368 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 369 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 370 if (h < 32) 371 hashes[0] |= (1 << h); 372 else 373 hashes[1] |= (1 << (h - 32)); 374 } 375 376 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 377 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 378 379 return; 380 } 381 382 static void 383 lge_reset(struct lge_softc *sc) 384 { 385 int i; 386 387 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST); 388 389 for (i = 0; i < LGE_TIMEOUT; i++) { 390 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0) 391 break; 392 } 393 394 if (i == LGE_TIMEOUT) 395 printf("lge%d: reset never completed\n", sc->lge_unit); 396 397 /* Wait a little while for the chip to get its brains in order. */ 398 DELAY(1000); 399 } 400 401 /* 402 * Probe for a Level 1 chip. Check the PCI vendor and device 403 * IDs against our list and return a device name if we find a match. 404 */ 405 static int 406 lge_probe(device_t dev) 407 { 408 struct lge_type *t; 409 uint16_t vendor, product; 410 411 vendor = pci_get_vendor(dev); 412 product = pci_get_device(dev); 413 414 for (t = lge_devs; t->lge_name != NULL; t++) { 415 if (vendor == t->lge_vid && product == t->lge_did) { 416 device_set_desc(dev, t->lge_name); 417 return(0); 418 } 419 } 420 421 return(ENXIO); 422 } 423 424 /* 425 * Attach the interface. Allocate softc structures, do ifmedia 426 * setup and ethernet/BPF attach. 427 */ 428 static int 429 lge_attach(device_t dev) 430 { 431 uint8_t eaddr[ETHER_ADDR_LEN]; 432 struct lge_softc *sc; 433 struct ifnet *ifp; 434 int unit, error = 0, rid; 435 436 sc = device_get_softc(dev); 437 unit = device_get_unit(dev); 438 callout_init(&sc->lge_stat_timer); 439 lwkt_serialize_init(&sc->lge_jslot_serializer); 440 441 /* 442 * Handle power management nonsense. 443 */ 444 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 445 uint32_t iobase, membase, irq; 446 447 /* Save important PCI config data. */ 448 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 449 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 450 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 451 452 /* Reset the power state. */ 453 device_printf(dev, "chip is in D%d power mode " 454 "-- setting to D0\n", pci_get_powerstate(dev)); 455 456 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 457 458 /* Restore PCI config data. */ 459 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 460 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 461 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 462 } 463 464 pci_enable_busmaster(dev); 465 466 rid = LGE_RID; 467 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 468 469 if (sc->lge_res == NULL) { 470 printf("lge%d: couldn't map ports/memory\n", unit); 471 error = ENXIO; 472 goto fail; 473 } 474 475 sc->lge_btag = rman_get_bustag(sc->lge_res); 476 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 477 478 /* Allocate interrupt */ 479 rid = 0; 480 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 481 RF_SHAREABLE | RF_ACTIVE); 482 483 if (sc->lge_irq == NULL) { 484 printf("lge%d: couldn't map interrupt\n", unit); 485 error = ENXIO; 486 goto fail; 487 } 488 489 /* Reset the adapter. */ 490 lge_reset(sc); 491 492 /* 493 * Get station address from the EEPROM. 494 */ 495 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1); 496 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1); 497 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1); 498 499 sc->lge_unit = unit; 500 501 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 502 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 503 504 if (sc->lge_ldata == NULL) { 505 printf("lge%d: no memory for list buffers!\n", unit); 506 error = ENXIO; 507 goto fail; 508 } 509 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 510 511 /* Try to allocate memory for jumbo buffers. */ 512 if (lge_alloc_jumbo_mem(sc)) { 513 printf("lge%d: jumbo buffer allocation failed\n", 514 sc->lge_unit); 515 error = ENXIO; 516 goto fail; 517 } 518 519 ifp = &sc->arpcom.ac_if; 520 ifp->if_softc = sc; 521 if_initname(ifp, "lge", unit); 522 ifp->if_mtu = ETHERMTU; 523 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 524 ifp->if_ioctl = lge_ioctl; 525 ifp->if_start = lge_start; 526 ifp->if_watchdog = lge_watchdog; 527 ifp->if_init = lge_init; 528 ifp->if_baudrate = 1000000000; 529 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 530 ifq_set_ready(&ifp->if_snd); 531 ifp->if_capabilities = IFCAP_RXCSUM; 532 ifp->if_capenable = ifp->if_capabilities; 533 534 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 535 sc->lge_pcs = 1; 536 else 537 sc->lge_pcs = 0; 538 539 /* 540 * Do MII setup. 541 */ 542 if (mii_phy_probe(dev, &sc->lge_miibus, 543 lge_ifmedia_upd, lge_ifmedia_sts)) { 544 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 545 error = ENXIO; 546 goto fail; 547 } 548 549 /* 550 * Call MI attach routine. 551 */ 552 ether_ifattach(ifp, eaddr, NULL); 553 554 error = bus_setup_intr(dev, sc->lge_irq, INTR_NETSAFE, 555 lge_intr, sc, &sc->lge_intrhand, 556 ifp->if_serializer); 557 if (error) { 558 ether_ifdetach(ifp); 559 printf("lge%d: couldn't set up irq\n", unit); 560 goto fail; 561 } 562 563 return(0); 564 565 fail: 566 lge_detach(dev); 567 return(error); 568 } 569 570 static int 571 lge_detach(device_t dev) 572 { 573 struct lge_softc *sc= device_get_softc(dev); 574 struct ifnet *ifp = &sc->arpcom.ac_if; 575 576 if (device_is_attached(dev)) { 577 lwkt_serialize_enter(ifp->if_serializer); 578 lge_reset(sc); 579 lge_stop(sc); 580 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 581 lwkt_serialize_exit(ifp->if_serializer); 582 583 ether_ifdetach(ifp); 584 } 585 586 if (sc->lge_miibus) 587 device_delete_child(dev, sc->lge_miibus); 588 bus_generic_detach(dev); 589 590 if (sc->lge_irq) 591 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 592 if (sc->lge_res) 593 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 594 595 if (sc->lge_ldata) 596 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), 597 M_DEVBUF); 598 lge_free_jumbo_mem(sc); 599 600 return(0); 601 } 602 603 /* 604 * Initialize the transmit descriptors. 605 */ 606 static int 607 lge_list_tx_init(struct lge_softc *sc) 608 { 609 struct lge_list_data *ld; 610 struct lge_ring_data *cd; 611 int i; 612 613 cd = &sc->lge_cdata; 614 ld = sc->lge_ldata; 615 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 616 ld->lge_tx_list[i].lge_mbuf = NULL; 617 ld->lge_tx_list[i].lge_ctl = 0; 618 } 619 620 cd->lge_tx_prod = cd->lge_tx_cons = 0; 621 622 return(0); 623 } 624 625 626 /* 627 * Initialize the RX descriptors and allocate mbufs for them. Note that 628 * we arralge the descriptors in a closed ring, so that the last descriptor 629 * points back to the first. 630 */ 631 static int 632 lge_list_rx_init(struct lge_softc *sc) 633 { 634 struct lge_list_data *ld; 635 struct lge_ring_data *cd; 636 int i; 637 638 ld = sc->lge_ldata; 639 cd = &sc->lge_cdata; 640 641 cd->lge_rx_prod = cd->lge_rx_cons = 0; 642 643 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 644 645 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 646 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 647 break; 648 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 649 return(ENOBUFS); 650 } 651 652 /* Clear possible 'rx command queue empty' interrupt. */ 653 CSR_READ_4(sc, LGE_ISR); 654 655 return(0); 656 } 657 658 /* 659 * Initialize an RX descriptor and attach an MBUF cluster. 660 */ 661 static int 662 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 663 { 664 struct mbuf *m_new = NULL; 665 struct lge_jslot *buf; 666 667 if (m == NULL) { 668 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 669 if (m_new == NULL) { 670 printf("lge%d: no memory for rx list " 671 "-- packet dropped!\n", sc->lge_unit); 672 return(ENOBUFS); 673 } 674 675 /* Allocate the jumbo buffer */ 676 buf = lge_jalloc(sc); 677 if (buf == NULL) { 678 #ifdef LGE_VERBOSE 679 printf("lge%d: jumbo allocation failed " 680 "-- packet dropped!\n", sc->lge_unit); 681 #endif 682 m_freem(m_new); 683 return(ENOBUFS); 684 } 685 /* Attach the buffer to the mbuf */ 686 m_new->m_ext.ext_arg = buf; 687 m_new->m_ext.ext_buf = buf->lge_buf; 688 m_new->m_ext.ext_free = lge_jfree; 689 m_new->m_ext.ext_ref = lge_jref; 690 m_new->m_ext.ext_size = LGE_JUMBO_FRAMELEN; 691 692 m_new->m_data = m_new->m_ext.ext_buf; 693 m_new->m_flags |= M_EXT; 694 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 695 } else { 696 m_new = m; 697 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 698 m_new->m_data = m_new->m_ext.ext_buf; 699 } 700 701 /* 702 * Adjust alignment so packet payload begins on a 703 * longword boundary. Mandatory for Alpha, useful on 704 * x86 too. 705 */ 706 m_adj(m_new, ETHER_ALIGN); 707 708 c->lge_mbuf = m_new; 709 c->lge_fragptr_hi = 0; 710 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 711 c->lge_fraglen = m_new->m_len; 712 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 713 c->lge_sts = 0; 714 715 /* 716 * Put this buffer in the RX command FIFO. To do this, 717 * we just write the physical address of the descriptor 718 * into the RX descriptor address registers. Note that 719 * there are two registers, one high DWORD and one low 720 * DWORD, which lets us specify a 64-bit address if 721 * desired. We only use a 32-bit address for now. 722 * Writing to the low DWORD register is what actually 723 * causes the command to be issued, so we do that 724 * last. 725 */ 726 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 727 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 728 729 return(0); 730 } 731 732 static int 733 lge_alloc_jumbo_mem(struct lge_softc *sc) 734 { 735 struct lge_jslot *entry; 736 caddr_t ptr; 737 int i; 738 739 /* Grab a big chunk o' storage. */ 740 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 741 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 742 743 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 744 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 745 return(ENOBUFS); 746 } 747 748 SLIST_INIT(&sc->lge_jfree_listhead); 749 750 /* 751 * Now divide it up into 9K pieces and save the addresses 752 * in an array. 753 */ 754 ptr = sc->lge_cdata.lge_jumbo_buf; 755 for (i = 0; i < LGE_JSLOTS; i++) { 756 entry = &sc->lge_cdata.lge_jslots[i]; 757 entry->lge_sc = sc; 758 entry->lge_buf = ptr; 759 entry->lge_inuse = 0; 760 entry->lge_slot = i; 761 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link); 762 ptr += LGE_JLEN; 763 } 764 765 return(0); 766 } 767 768 static void 769 lge_free_jumbo_mem(struct lge_softc *sc) 770 { 771 if (sc->lge_cdata.lge_jumbo_buf) 772 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 773 } 774 775 /* 776 * Allocate a jumbo buffer. 777 */ 778 static struct lge_jslot * 779 lge_jalloc(struct lge_softc *sc) 780 { 781 struct lge_jslot *entry; 782 783 lwkt_serialize_enter(&sc->lge_jslot_serializer); 784 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 785 if (entry) { 786 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jslot_link); 787 entry->lge_inuse = 1; 788 } else { 789 #ifdef LGE_VERBOSE 790 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 791 #endif 792 } 793 lwkt_serialize_exit(&sc->lge_jslot_serializer); 794 return(entry); 795 } 796 797 /* 798 * Adjust usage count on a jumbo buffer. In general this doesn't 799 * get used much because our jumbo buffers don't get passed around 800 * a lot, but it's implemented for correctness. 801 */ 802 static void 803 lge_jref(void *arg) 804 { 805 struct lge_jslot *entry = (struct lge_jslot *)arg; 806 struct lge_softc *sc = entry->lge_sc; 807 808 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) 809 panic("lge_jref: asked to reference buffer " 810 "that we don't manage!"); 811 else if (entry->lge_inuse == 0) 812 panic("lge_jref: buffer already free!"); 813 else 814 atomic_add_int(&entry->lge_inuse, 1); 815 } 816 817 /* 818 * Release a jumbo buffer. 819 */ 820 static void 821 lge_jfree(void *arg) 822 { 823 struct lge_jslot *entry = (struct lge_jslot *)arg; 824 struct lge_softc *sc = entry->lge_sc; 825 826 if (sc == NULL) 827 panic("lge_jfree: can't find softc pointer!"); 828 829 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) { 830 panic("lge_jfree: asked to free buffer that we don't manage!"); 831 } else if (entry->lge_inuse == 0) { 832 panic("lge_jfree: buffer already free!"); 833 } else { 834 lwkt_serialize_enter(&sc->lge_jslot_serializer); 835 atomic_subtract_int(&entry->lge_inuse, 1); 836 if (entry->lge_inuse == 0) { 837 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 838 entry, jslot_link); 839 } 840 lwkt_serialize_exit(&sc->lge_jslot_serializer); 841 } 842 } 843 844 /* 845 * A frame has been uploaded: pass the resulting mbuf chain up to 846 * the higher level protocols. 847 */ 848 static void 849 lge_rxeof(struct lge_softc *sc, int cnt) 850 { 851 struct ifnet *ifp = &sc->arpcom.ac_if; 852 struct mbuf *m; 853 struct lge_rx_desc *cur_rx; 854 int c, i, total_len = 0; 855 uint32_t rxsts, rxctl; 856 857 858 /* Find out how many frames were processed. */ 859 c = cnt; 860 i = sc->lge_cdata.lge_rx_cons; 861 862 /* Suck them in. */ 863 while(c) { 864 struct mbuf *m0 = NULL; 865 866 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 867 rxctl = cur_rx->lge_ctl; 868 rxsts = cur_rx->lge_sts; 869 m = cur_rx->lge_mbuf; 870 cur_rx->lge_mbuf = NULL; 871 total_len = LGE_RXBYTES(cur_rx); 872 LGE_INC(i, LGE_RX_LIST_CNT); 873 c--; 874 875 /* 876 * If an error occurs, update stats, clear the 877 * status word and leave the mbuf cluster in place: 878 * it should simply get re-used next time this descriptor 879 * comes up in the ring. 880 */ 881 if (rxctl & LGE_RXCTL_ERRMASK) { 882 ifp->if_ierrors++; 883 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 884 continue; 885 } 886 887 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 888 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 889 total_len + ETHER_ALIGN, 0, ifp, NULL); 890 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 891 if (m0 == NULL) { 892 printf("lge%d: no receive buffers " 893 "available -- packet dropped!\n", 894 sc->lge_unit); 895 ifp->if_ierrors++; 896 continue; 897 } 898 m_adj(m0, ETHER_ALIGN); 899 m = m0; 900 } else { 901 m->m_pkthdr.rcvif = ifp; 902 m->m_pkthdr.len = m->m_len = total_len; 903 } 904 905 ifp->if_ipackets++; 906 907 /* Do IP checksum checking. */ 908 if (rxsts & LGE_RXSTS_ISIP) 909 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 910 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 911 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 912 if ((rxsts & LGE_RXSTS_ISTCP && 913 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 914 (rxsts & LGE_RXSTS_ISUDP && 915 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 916 m->m_pkthdr.csum_flags |= 917 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 918 m->m_pkthdr.csum_data = 0xffff; 919 } 920 921 ifp->if_input(ifp, m); 922 } 923 924 sc->lge_cdata.lge_rx_cons = i; 925 } 926 927 static void 928 lge_rxeoc(struct lge_softc *sc) 929 { 930 struct ifnet *ifp = &sc->arpcom.ac_if; 931 932 ifp->if_flags &= ~IFF_RUNNING; 933 lge_init(sc); 934 } 935 936 /* 937 * A frame was downloaded to the chip. It's safe for us to clean up 938 * the list buffers. 939 */ 940 static void 941 lge_txeof(struct lge_softc *sc) 942 { 943 struct ifnet *ifp = &sc->arpcom.ac_if; 944 struct lge_tx_desc *cur_tx = NULL; 945 uint32_t idx, txdone; 946 947 /* Clear the timeout timer. */ 948 ifp->if_timer = 0; 949 950 /* 951 * Go through our tx list and free mbufs for those 952 * frames that have been transmitted. 953 */ 954 idx = sc->lge_cdata.lge_tx_cons; 955 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 956 957 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 958 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 959 960 ifp->if_opackets++; 961 if (cur_tx->lge_mbuf != NULL) { 962 m_freem(cur_tx->lge_mbuf); 963 cur_tx->lge_mbuf = NULL; 964 } 965 cur_tx->lge_ctl = 0; 966 967 txdone--; 968 LGE_INC(idx, LGE_TX_LIST_CNT); 969 ifp->if_timer = 0; 970 } 971 972 sc->lge_cdata.lge_tx_cons = idx; 973 974 if (cur_tx != NULL) 975 ifp->if_flags &= ~IFF_OACTIVE; 976 } 977 978 static void 979 lge_tick(void *xsc) 980 { 981 struct lge_softc *sc = xsc; 982 struct ifnet *ifp = &sc->arpcom.ac_if; 983 984 lwkt_serialize_enter(ifp->if_serializer); 985 lge_tick_serialized(xsc); 986 lwkt_serialize_exit(ifp->if_serializer); 987 } 988 989 static void 990 lge_tick_serialized(void *xsc) 991 { 992 struct lge_softc *sc = xsc; 993 struct mii_data *mii; 994 struct ifnet *ifp = &sc->arpcom.ac_if; 995 996 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 997 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 998 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 999 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1000 1001 if (!sc->lge_link) { 1002 mii = device_get_softc(sc->lge_miibus); 1003 mii_tick(mii); 1004 mii_pollstat(mii); 1005 if (mii->mii_media_status & IFM_ACTIVE && 1006 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1007 sc->lge_link++; 1008 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1009 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1010 printf("lge%d: gigabit link up\n", 1011 sc->lge_unit); 1012 if (!ifq_is_empty(&ifp->if_snd)) 1013 (*ifp->if_start)(ifp); 1014 } 1015 } 1016 1017 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1018 } 1019 1020 static void 1021 lge_intr(void *arg) 1022 { 1023 struct lge_softc *sc = arg; 1024 struct ifnet *ifp = &sc->arpcom.ac_if; 1025 uint32_t status; 1026 1027 /* Supress unwanted interrupts */ 1028 if ((ifp->if_flags & IFF_UP) == 0) { 1029 lge_stop(sc); 1030 return; 1031 } 1032 1033 for (;;) { 1034 /* 1035 * Reading the ISR register clears all interrupts, and 1036 * clears the 'interrupts enabled' bit in the IMR 1037 * register. 1038 */ 1039 status = CSR_READ_4(sc, LGE_ISR); 1040 1041 if ((status & LGE_INTRS) == 0) 1042 break; 1043 1044 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1045 lge_txeof(sc); 1046 1047 if (status & LGE_ISR_RXDMA_DONE) 1048 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1049 1050 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1051 lge_rxeoc(sc); 1052 1053 if (status & LGE_ISR_PHY_INTR) { 1054 sc->lge_link = 0; 1055 callout_stop(&sc->lge_stat_timer); 1056 lge_tick_serialized(sc); 1057 } 1058 } 1059 1060 /* Re-enable interrupts. */ 1061 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1062 1063 if (!ifq_is_empty(&ifp->if_snd)) 1064 (*ifp->if_start)(ifp); 1065 } 1066 1067 /* 1068 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1069 * pointers to the fragment pointers. 1070 */ 1071 static int 1072 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1073 { 1074 struct lge_frag *f = NULL; 1075 struct lge_tx_desc *cur_tx; 1076 struct mbuf *m; 1077 int frag = 0, tot_len = 0; 1078 1079 /* 1080 * Start packing the mbufs in this chain into 1081 * the fragment pointers. Stop when we run out 1082 * of fragments or hit the end of the mbuf chain. 1083 */ 1084 m = m_head; 1085 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1086 frag = 0; 1087 1088 for (m = m_head; m != NULL; m = m->m_next) { 1089 if (m->m_len != 0) { 1090 tot_len += m->m_len; 1091 f = &cur_tx->lge_frags[frag]; 1092 f->lge_fraglen = m->m_len; 1093 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1094 f->lge_fragptr_hi = 0; 1095 frag++; 1096 } 1097 } 1098 1099 if (m != NULL) 1100 return(ENOBUFS); 1101 1102 cur_tx->lge_mbuf = m_head; 1103 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1104 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1105 1106 /* Queue for transmit */ 1107 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1108 1109 return(0); 1110 } 1111 1112 /* 1113 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1114 * to the mbuf data regions directly in the transmit lists. We also save a 1115 * copy of the pointers since the transmit list fragment pointers are 1116 * physical addresses. 1117 */ 1118 1119 static void 1120 lge_start(struct ifnet *ifp) 1121 { 1122 struct lge_softc *sc = ifp->if_softc; 1123 struct mbuf *m_head = NULL; 1124 uint32_t idx; 1125 int need_timer; 1126 1127 if (!sc->lge_link) 1128 return; 1129 1130 idx = sc->lge_cdata.lge_tx_prod; 1131 1132 if (ifp->if_flags & IFF_OACTIVE) 1133 return; 1134 1135 need_timer = 0; 1136 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1137 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1138 break; 1139 1140 m_head = ifq_poll(&ifp->if_snd); 1141 if (m_head == NULL) 1142 break; 1143 1144 if (lge_encap(sc, m_head, &idx)) { 1145 ifp->if_flags |= IFF_OACTIVE; 1146 break; 1147 } 1148 ifq_dequeue(&ifp->if_snd, m_head); 1149 need_timer = 1; 1150 1151 BPF_MTAP(ifp, m_head); 1152 } 1153 1154 if (!need_timer) 1155 return; 1156 1157 sc->lge_cdata.lge_tx_prod = idx; 1158 1159 /* 1160 * Set a timeout in case the chip goes out to lunch. 1161 */ 1162 ifp->if_timer = 5; 1163 } 1164 1165 static void 1166 lge_init(void *xsc) 1167 { 1168 struct lge_softc *sc = xsc; 1169 struct ifnet *ifp = &sc->arpcom.ac_if; 1170 struct mii_data *mii; 1171 1172 if (ifp->if_flags & IFF_RUNNING) 1173 return; 1174 1175 /* 1176 * Cancel pending I/O and free all RX/TX buffers. 1177 */ 1178 lge_stop(sc); 1179 lge_reset(sc); 1180 1181 mii = device_get_softc(sc->lge_miibus); 1182 1183 /* Set MAC address */ 1184 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1185 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1186 1187 /* Init circular RX list. */ 1188 if (lge_list_rx_init(sc) == ENOBUFS) { 1189 printf("lge%d: initialization failed: no " 1190 "memory for rx buffers\n", sc->lge_unit); 1191 lge_stop(sc); 1192 return; 1193 } 1194 1195 /* 1196 * Init tx descriptors. 1197 */ 1198 lge_list_tx_init(sc); 1199 1200 /* Set initial value for MODE1 register. */ 1201 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST | 1202 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD | 1203 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 | 1204 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2); 1205 1206 /* If we want promiscuous mode, set the allframes bit. */ 1207 if (ifp->if_flags & IFF_PROMISC) { 1208 CSR_WRITE_4(sc, LGE_MODE1, 1209 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC); 1210 } else { 1211 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1212 } 1213 1214 /* 1215 * Set the capture broadcast bit to capture broadcast frames. 1216 */ 1217 if (ifp->if_flags & IFF_BROADCAST) { 1218 CSR_WRITE_4(sc, LGE_MODE1, 1219 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST); 1220 } else { 1221 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1222 } 1223 1224 /* Packet padding workaround? */ 1225 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1226 1227 /* No error frames */ 1228 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1229 1230 /* Receive large frames */ 1231 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS); 1232 1233 /* Workaround: disable RX/TX flow control */ 1234 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1235 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1236 1237 /* Make sure to strip CRC from received frames */ 1238 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1239 1240 /* Turn off magic packet mode */ 1241 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1242 1243 /* Turn off all VLAN stuff */ 1244 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX | 1245 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT); 1246 1247 /* Workarond: FIFO overflow */ 1248 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1249 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1250 1251 /* 1252 * Load the multicast filter. 1253 */ 1254 lge_setmulti(sc); 1255 1256 /* 1257 * Enable hardware checksum validation for all received IPv4 1258 * packets, do not reject packets with bad checksums. 1259 */ 1260 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM | 1261 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM | 1262 LGE_MODE2_RX_ERRCSUM); 1263 1264 /* 1265 * Enable the delivery of PHY interrupts based on 1266 * link/speed/duplex status chalges. 1267 */ 1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL); 1269 1270 /* Enable receiver and transmitter. */ 1271 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1272 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB); 1273 1274 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1275 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB); 1276 1277 /* 1278 * Enable interrupts. 1279 */ 1280 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 | 1281 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS); 1282 1283 lge_ifmedia_upd(ifp); 1284 1285 ifp->if_flags |= IFF_RUNNING; 1286 ifp->if_flags &= ~IFF_OACTIVE; 1287 1288 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1289 } 1290 1291 /* 1292 * Set media options. 1293 */ 1294 static int 1295 lge_ifmedia_upd(struct ifnet *ifp) 1296 { 1297 struct lge_softc *sc = ifp->if_softc; 1298 struct mii_data *mii = device_get_softc(sc->lge_miibus); 1299 1300 sc->lge_link = 0; 1301 if (mii->mii_instance) { 1302 struct mii_softc *miisc; 1303 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1304 mii_phy_reset(miisc); 1305 } 1306 mii_mediachg(mii); 1307 1308 return(0); 1309 } 1310 1311 /* 1312 * Report current media status. 1313 */ 1314 static void 1315 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1316 { 1317 struct lge_softc *sc = ifp->if_softc; 1318 struct mii_data *mii; 1319 1320 mii = device_get_softc(sc->lge_miibus); 1321 mii_pollstat(mii); 1322 ifmr->ifm_active = mii->mii_media_active; 1323 ifmr->ifm_status = mii->mii_media_status; 1324 } 1325 1326 static int 1327 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1328 { 1329 struct lge_softc *sc = ifp->if_softc; 1330 struct ifreq *ifr = (struct ifreq *) data; 1331 struct mii_data *mii; 1332 int error = 0; 1333 1334 switch(command) { 1335 case SIOCSIFMTU: 1336 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1337 error = EINVAL; 1338 else 1339 ifp->if_mtu = ifr->ifr_mtu; 1340 break; 1341 case SIOCSIFFLAGS: 1342 if (ifp->if_flags & IFF_UP) { 1343 if (ifp->if_flags & IFF_RUNNING && 1344 ifp->if_flags & IFF_PROMISC && 1345 !(sc->lge_if_flags & IFF_PROMISC)) { 1346 CSR_WRITE_4(sc, LGE_MODE1, 1347 LGE_MODE1_SETRST_CTL1| 1348 LGE_MODE1_RX_PROMISC); 1349 } else if (ifp->if_flags & IFF_RUNNING && 1350 !(ifp->if_flags & IFF_PROMISC) && 1351 sc->lge_if_flags & IFF_PROMISC) { 1352 CSR_WRITE_4(sc, LGE_MODE1, 1353 LGE_MODE1_RX_PROMISC); 1354 } else { 1355 ifp->if_flags &= ~IFF_RUNNING; 1356 lge_init(sc); 1357 } 1358 } else { 1359 if (ifp->if_flags & IFF_RUNNING) 1360 lge_stop(sc); 1361 } 1362 sc->lge_if_flags = ifp->if_flags; 1363 error = 0; 1364 break; 1365 case SIOCADDMULTI: 1366 case SIOCDELMULTI: 1367 lge_setmulti(sc); 1368 error = 0; 1369 break; 1370 case SIOCGIFMEDIA: 1371 case SIOCSIFMEDIA: 1372 mii = device_get_softc(sc->lge_miibus); 1373 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1374 break; 1375 default: 1376 error = ether_ioctl(ifp, command, data); 1377 break; 1378 } 1379 1380 return(error); 1381 } 1382 1383 static void 1384 lge_watchdog(struct ifnet *ifp) 1385 { 1386 struct lge_softc *sc = ifp->if_softc; 1387 1388 ifp->if_oerrors++; 1389 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1390 1391 lge_stop(sc); 1392 lge_reset(sc); 1393 ifp->if_flags &= ~IFF_RUNNING; 1394 lge_init(sc); 1395 1396 if (!ifq_is_empty(&ifp->if_snd)) 1397 (*ifp->if_start)(ifp); 1398 } 1399 1400 /* 1401 * Stop the adapter and free any mbufs allocated to the 1402 * RX and TX lists. 1403 */ 1404 static void 1405 lge_stop(struct lge_softc *sc) 1406 { 1407 struct ifnet *ifp = &sc->arpcom.ac_if; 1408 int i; 1409 1410 ifp->if_timer = 0; 1411 callout_stop(&sc->lge_stat_timer); 1412 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1413 1414 /* Disable receiver and transmitter. */ 1415 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1416 sc->lge_link = 0; 1417 1418 /* 1419 * Free data in the RX lists. 1420 */ 1421 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1422 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1423 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1424 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1425 } 1426 } 1427 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list)); 1428 1429 /* 1430 * Free the TX list buffers. 1431 */ 1432 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1433 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1434 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1435 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1436 } 1437 } 1438 1439 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list)); 1440 1441 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1442 } 1443 1444 /* 1445 * Stop all chip I/O so that the kernel's probe routines don't 1446 * get confused by errant DMAs when rebooting. 1447 */ 1448 static void 1449 lge_shutdown(device_t dev) 1450 { 1451 struct lge_softc *sc = device_get_softc(dev); 1452 1453 lge_reset(sc); 1454 lge_stop(sc); 1455 } 1456