1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 34 */ 35 36 /* 37 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 38 * documentation not available, but ask me nicely. 39 * 40 * Written by Bill Paul <william.paul@windriver.com> 41 * Wind River Systems 42 */ 43 44 /* 45 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 46 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 47 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 48 * are three supported methods for data transfer between host and 49 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 50 * Propulsion Technology (tm) DMA. The latter mechanism is a form 51 * of double buffer DMA where the packet data is copied to a 52 * pre-allocated DMA buffer who's physical address has been loaded 53 * into a table at device initialization time. The rationale is that 54 * the virtual to physical address translation needed for normal 55 * scatter/gather DMA is more expensive than the data copy needed 56 * for double buffering. This may be true in Windows NT and the like, 57 * but it isn't true for us, at least on the x86 arch. This driver 58 * uses the scatter/gather I/O method for both TX and RX. 59 * 60 * The LXT1001 only supports TCP/IP checksum offload on receive. 61 * Also, the VLAN tagging is done using a 16-entry table which allows 62 * the chip to perform hardware filtering based on VLAN tags. Sadly, 63 * our vlan support doesn't currently play well with this kind of 64 * hardware support. 65 * 66 * Special thanks to: 67 * - Jeff James at Intel, for arranging to have the LXT1001 manual 68 * released (at long last) 69 * - Beny Chen at D-Link, for actually sending it to me 70 * - Brad Short and Keith Alexis at SMC, for sending me sample 71 * SMC9462SX and SMC9462TX adapters for testing 72 * - Paul Saab at Y!, for not killing me (though it remains to be seen 73 * if in fact he did me much of a favor) 74 */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/sockio.h> 79 #include <sys/mbuf.h> 80 #include <sys/malloc.h> 81 #include <sys/kernel.h> 82 #include <sys/interrupt.h> 83 #include <sys/socket.h> 84 #include <sys/serialize.h> 85 #include <sys/thread2.h> 86 87 #include <net/if.h> 88 #include <net/ifq_var.h> 89 #include <net/if_arp.h> 90 #include <net/ethernet.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 94 #include <net/bpf.h> 95 96 #include <vm/vm.h> /* for vtophys */ 97 #include <vm/pmap.h> /* for vtophys */ 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 101 #include <dev/netif/mii_layer/mii.h> 102 #include <dev/netif/mii_layer/miivar.h> 103 104 #include "pcidevs.h" 105 #include <bus/pci/pcireg.h> 106 #include <bus/pci/pcivar.h> 107 108 #define LGE_USEIOSPACE 109 110 #include "if_lgereg.h" 111 112 /* "controller miibus0" required. See GENERIC if you get errors here. */ 113 #include "miibus_if.h" 114 115 /* 116 * Various supported device vendors/types and their names. 117 */ 118 static struct lge_type lge_devs[] = { 119 { PCI_VENDOR_LEVELONE, PCI_PRODUCT_LEVELONE_LXT1001, 120 "Level 1 Gigabit Ethernet" }, 121 { 0, 0, NULL } 122 }; 123 124 static int lge_probe(device_t); 125 static int lge_attach(device_t); 126 static int lge_detach(device_t); 127 128 static int lge_alloc_jumbo_mem(struct lge_softc *); 129 static void lge_free_jumbo_mem(struct lge_softc *); 130 static struct lge_jslot 131 *lge_jalloc(struct lge_softc *); 132 static void lge_jfree(void *); 133 static void lge_jref(void *); 134 135 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 136 struct mbuf *); 137 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *); 138 static void lge_rxeof(struct lge_softc *, int); 139 static void lge_rxeoc(struct lge_softc *); 140 static void lge_txeof(struct lge_softc *); 141 static void lge_intr(void *); 142 static void lge_tick(void *); 143 static void lge_tick_serialized(void *); 144 static void lge_start(struct ifnet *, struct ifaltq_subque *); 145 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 146 static void lge_init(void *); 147 static void lge_stop(struct lge_softc *); 148 static void lge_watchdog(struct ifnet *); 149 static void lge_shutdown(device_t); 150 static int lge_ifmedia_upd(struct ifnet *); 151 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 152 153 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *); 154 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int); 155 156 static int lge_miibus_readreg(device_t, int, int); 157 static int lge_miibus_writereg(device_t, int, int, int); 158 static void lge_miibus_statchg(device_t); 159 160 static void lge_setmulti(struct lge_softc *); 161 static void lge_reset(struct lge_softc *); 162 static int lge_list_rx_init(struct lge_softc *); 163 static int lge_list_tx_init(struct lge_softc *); 164 165 #ifdef LGE_USEIOSPACE 166 #define LGE_RES SYS_RES_IOPORT 167 #define LGE_RID LGE_PCI_LOIO 168 #else 169 #define LGE_RES SYS_RES_MEMORY 170 #define LGE_RID LGE_PCI_LOMEM 171 #endif 172 173 static device_method_t lge_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, lge_probe), 176 DEVMETHOD(device_attach, lge_attach), 177 DEVMETHOD(device_detach, lge_detach), 178 DEVMETHOD(device_shutdown, lge_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 186 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 187 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 188 189 DEVMETHOD_END 190 }; 191 192 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc)); 193 static devclass_t lge_devclass; 194 195 DECLARE_DUMMY_MODULE(if_lge); 196 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, NULL, NULL); 197 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, NULL, NULL); 198 199 #define LGE_SETBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 201 202 #define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 204 205 #define SIO_SET(x) \ 206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x)) 207 208 #define SIO_CLR(x) \ 209 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x)) 210 211 /* 212 * Read a word of data stored in the EEPROM at address 'addr.' 213 */ 214 static void 215 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest) 216 { 217 int i; 218 uint32_t val; 219 220 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 221 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8)); 222 223 for (i = 0; i < LGE_TIMEOUT; i++) { 224 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0) 225 break; 226 } 227 228 if (i == LGE_TIMEOUT) { 229 kprintf("lge%d: EEPROM read timed out\n", sc->lge_unit); 230 return; 231 } 232 233 val = CSR_READ_4(sc, LGE_EEDATA); 234 235 if (addr & 1) 236 *dest = (val >> 16) & 0xFFFF; 237 else 238 *dest = val & 0xFFFF; 239 } 240 241 /* 242 * Read a sequence of words from the EEPROM. 243 */ 244 static void 245 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt) 246 { 247 int i; 248 uint16_t word = 0, *ptr; 249 250 for (i = 0; i < cnt; i++) { 251 lge_eeprom_getword(sc, off + i, &word); 252 ptr = (uint16_t *)(dest + (i * 2)); 253 *ptr = ntohs(word); 254 } 255 } 256 257 static int 258 lge_miibus_readreg(device_t dev, int phy, int reg) 259 { 260 struct lge_softc *sc = device_get_softc(dev); 261 int i; 262 263 /* 264 * If we have a non-PCS PHY, pretend that the internal 265 * autoneg stuff at PHY address 0 isn't there so that 266 * the miibus code will find only the GMII PHY. 267 */ 268 if (sc->lge_pcs == 0 && phy == 0) 269 return(0); 270 271 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 272 273 for (i = 0; i < LGE_TIMEOUT; i++) { 274 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 275 break; 276 } 277 278 if (i == LGE_TIMEOUT) { 279 kprintf("lge%d: PHY read timed out\n", sc->lge_unit); 280 return(0); 281 } 282 283 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 284 } 285 286 static int 287 lge_miibus_writereg(device_t dev, int phy, int reg, int data) 288 { 289 struct lge_softc *sc = device_get_softc(dev); 290 int i; 291 292 CSR_WRITE_4(sc, LGE_GMIICTL, 293 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 294 295 for (i = 0; i < LGE_TIMEOUT; i++) { 296 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 297 break; 298 } 299 300 if (i == LGE_TIMEOUT) { 301 kprintf("lge%d: PHY write timed out\n", sc->lge_unit); 302 return(0); 303 } 304 305 return(0); 306 } 307 308 static void 309 lge_miibus_statchg(device_t dev) 310 { 311 struct lge_softc *sc = device_get_softc(dev); 312 struct mii_data *mii = device_get_softc(sc->lge_miibus); 313 314 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_1000_T: 317 case IFM_1000_SX: 318 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 319 break; 320 case IFM_100_TX: 321 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 322 break; 323 case IFM_10_T: 324 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 325 break; 326 default: 327 /* 328 * Choose something, even if it's wrong. Clearing 329 * all the bits will hose autoneg on the internal 330 * PHY. 331 */ 332 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 333 break; 334 } 335 336 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 337 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 338 else 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 340 } 341 342 static void 343 lge_setmulti(struct lge_softc *sc) 344 { 345 struct ifnet *ifp = &sc->arpcom.ac_if; 346 struct ifmultiaddr *ifma; 347 uint32_t h = 0, hashes[2] = { 0, 0 }; 348 349 /* Make sure multicast hash table is enabled. */ 350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST); 351 352 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 353 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 354 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 355 return; 356 } 357 358 /* first, zot all the existing hash bits */ 359 CSR_WRITE_4(sc, LGE_MAR0, 0); 360 CSR_WRITE_4(sc, LGE_MAR1, 0); 361 362 /* now program new ones */ 363 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 364 if (ifma->ifma_addr->sa_family != AF_LINK) 365 continue; 366 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 367 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 368 if (h < 32) 369 hashes[0] |= (1 << h); 370 else 371 hashes[1] |= (1 << (h - 32)); 372 } 373 374 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 375 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 376 377 return; 378 } 379 380 static void 381 lge_reset(struct lge_softc *sc) 382 { 383 int i; 384 385 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST); 386 387 for (i = 0; i < LGE_TIMEOUT; i++) { 388 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0) 389 break; 390 } 391 392 if (i == LGE_TIMEOUT) 393 kprintf("lge%d: reset never completed\n", sc->lge_unit); 394 395 /* Wait a little while for the chip to get its brains in order. */ 396 DELAY(1000); 397 } 398 399 /* 400 * Probe for a Level 1 chip. Check the PCI vendor and device 401 * IDs against our list and return a device name if we find a match. 402 */ 403 static int 404 lge_probe(device_t dev) 405 { 406 struct lge_type *t; 407 uint16_t vendor, product; 408 409 vendor = pci_get_vendor(dev); 410 product = pci_get_device(dev); 411 412 for (t = lge_devs; t->lge_name != NULL; t++) { 413 if (vendor == t->lge_vid && product == t->lge_did) { 414 device_set_desc(dev, t->lge_name); 415 return(0); 416 } 417 } 418 419 return(ENXIO); 420 } 421 422 /* 423 * Attach the interface. Allocate softc structures, do ifmedia 424 * setup and ethernet/BPF attach. 425 */ 426 static int 427 lge_attach(device_t dev) 428 { 429 uint8_t eaddr[ETHER_ADDR_LEN]; 430 struct lge_softc *sc; 431 struct ifnet *ifp; 432 int unit, error = 0, rid; 433 434 sc = device_get_softc(dev); 435 unit = device_get_unit(dev); 436 callout_init(&sc->lge_stat_timer); 437 lwkt_serialize_init(&sc->lge_jslot_serializer); 438 439 /* 440 * Handle power management nonsense. 441 */ 442 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 443 uint32_t iobase, membase, irq; 444 445 /* Save important PCI config data. */ 446 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 447 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 448 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 449 450 /* Reset the power state. */ 451 device_printf(dev, "chip is in D%d power mode " 452 "-- setting to D0\n", pci_get_powerstate(dev)); 453 454 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 455 456 /* Restore PCI config data. */ 457 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 458 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 459 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 460 } 461 462 pci_enable_busmaster(dev); 463 464 rid = LGE_RID; 465 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 466 467 if (sc->lge_res == NULL) { 468 kprintf("lge%d: couldn't map ports/memory\n", unit); 469 error = ENXIO; 470 goto fail; 471 } 472 473 sc->lge_btag = rman_get_bustag(sc->lge_res); 474 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 475 476 /* Allocate interrupt */ 477 rid = 0; 478 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 479 RF_SHAREABLE | RF_ACTIVE); 480 481 if (sc->lge_irq == NULL) { 482 kprintf("lge%d: couldn't map interrupt\n", unit); 483 error = ENXIO; 484 goto fail; 485 } 486 487 /* Reset the adapter. */ 488 lge_reset(sc); 489 490 /* 491 * Get station address from the EEPROM. 492 */ 493 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1); 494 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1); 495 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1); 496 497 sc->lge_unit = unit; 498 499 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 500 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 501 502 if (sc->lge_ldata == NULL) { 503 kprintf("lge%d: no memory for list buffers!\n", unit); 504 error = ENXIO; 505 goto fail; 506 } 507 508 /* Try to allocate memory for jumbo buffers. */ 509 if (lge_alloc_jumbo_mem(sc)) { 510 kprintf("lge%d: jumbo buffer allocation failed\n", 511 sc->lge_unit); 512 error = ENXIO; 513 goto fail; 514 } 515 516 ifp = &sc->arpcom.ac_if; 517 ifp->if_softc = sc; 518 if_initname(ifp, "lge", unit); 519 ifp->if_mtu = ETHERMTU; 520 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 521 ifp->if_ioctl = lge_ioctl; 522 ifp->if_start = lge_start; 523 ifp->if_watchdog = lge_watchdog; 524 ifp->if_init = lge_init; 525 ifp->if_baudrate = 1000000000; 526 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 527 ifq_set_ready(&ifp->if_snd); 528 ifp->if_capabilities = IFCAP_RXCSUM; 529 ifp->if_capenable = ifp->if_capabilities; 530 531 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 532 sc->lge_pcs = 1; 533 else 534 sc->lge_pcs = 0; 535 536 /* 537 * Do MII setup. 538 */ 539 if (mii_phy_probe(dev, &sc->lge_miibus, 540 lge_ifmedia_upd, lge_ifmedia_sts)) { 541 kprintf("lge%d: MII without any PHY!\n", sc->lge_unit); 542 error = ENXIO; 543 goto fail; 544 } 545 546 /* 547 * Call MI attach routine. 548 */ 549 ether_ifattach(ifp, eaddr, NULL); 550 551 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->lge_irq)); 552 553 error = bus_setup_intr(dev, sc->lge_irq, INTR_MPSAFE, 554 lge_intr, sc, &sc->lge_intrhand, 555 ifp->if_serializer); 556 if (error) { 557 ether_ifdetach(ifp); 558 kprintf("lge%d: couldn't set up irq\n", unit); 559 goto fail; 560 } 561 562 return(0); 563 564 fail: 565 lge_detach(dev); 566 return(error); 567 } 568 569 static int 570 lge_detach(device_t dev) 571 { 572 struct lge_softc *sc= device_get_softc(dev); 573 struct ifnet *ifp = &sc->arpcom.ac_if; 574 575 if (device_is_attached(dev)) { 576 lwkt_serialize_enter(ifp->if_serializer); 577 lge_reset(sc); 578 lge_stop(sc); 579 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 580 lwkt_serialize_exit(ifp->if_serializer); 581 582 ether_ifdetach(ifp); 583 } 584 585 if (sc->lge_miibus) 586 device_delete_child(dev, sc->lge_miibus); 587 bus_generic_detach(dev); 588 589 if (sc->lge_irq) 590 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 591 if (sc->lge_res) 592 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 593 594 if (sc->lge_ldata) 595 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), 596 M_DEVBUF); 597 lge_free_jumbo_mem(sc); 598 599 return(0); 600 } 601 602 /* 603 * Initialize the transmit descriptors. 604 */ 605 static int 606 lge_list_tx_init(struct lge_softc *sc) 607 { 608 struct lge_list_data *ld; 609 struct lge_ring_data *cd; 610 int i; 611 612 cd = &sc->lge_cdata; 613 ld = sc->lge_ldata; 614 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 615 ld->lge_tx_list[i].lge_mbuf = NULL; 616 ld->lge_tx_list[i].lge_ctl = 0; 617 } 618 619 cd->lge_tx_prod = cd->lge_tx_cons = 0; 620 621 return(0); 622 } 623 624 625 /* 626 * Initialize the RX descriptors and allocate mbufs for them. Note that 627 * we arralge the descriptors in a closed ring, so that the last descriptor 628 * points back to the first. 629 */ 630 static int 631 lge_list_rx_init(struct lge_softc *sc) 632 { 633 struct lge_list_data *ld; 634 struct lge_ring_data *cd; 635 int i; 636 637 ld = sc->lge_ldata; 638 cd = &sc->lge_cdata; 639 640 cd->lge_rx_prod = cd->lge_rx_cons = 0; 641 642 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 643 644 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 645 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 646 break; 647 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 648 return(ENOBUFS); 649 } 650 651 /* Clear possible 'rx command queue empty' interrupt. */ 652 CSR_READ_4(sc, LGE_ISR); 653 654 return(0); 655 } 656 657 /* 658 * Initialize an RX descriptor and attach an MBUF cluster. 659 */ 660 static int 661 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 662 { 663 struct mbuf *m_new = NULL; 664 struct lge_jslot *buf; 665 666 if (m == NULL) { 667 MGETHDR(m_new, M_NOWAIT, MT_DATA); 668 if (m_new == NULL) { 669 kprintf("lge%d: no memory for rx list " 670 "-- packet dropped!\n", sc->lge_unit); 671 return(ENOBUFS); 672 } 673 674 /* Allocate the jumbo buffer */ 675 buf = lge_jalloc(sc); 676 if (buf == NULL) { 677 #ifdef LGE_VERBOSE 678 kprintf("lge%d: jumbo allocation failed " 679 "-- packet dropped!\n", sc->lge_unit); 680 #endif 681 m_freem(m_new); 682 return(ENOBUFS); 683 } 684 /* Attach the buffer to the mbuf */ 685 m_new->m_ext.ext_arg = buf; 686 m_new->m_ext.ext_buf = buf->lge_buf; 687 m_new->m_ext.ext_free = lge_jfree; 688 m_new->m_ext.ext_ref = lge_jref; 689 m_new->m_ext.ext_size = LGE_JUMBO_FRAMELEN; 690 691 m_new->m_data = m_new->m_ext.ext_buf; 692 m_new->m_flags |= M_EXT; 693 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 694 } else { 695 m_new = m; 696 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 697 m_new->m_data = m_new->m_ext.ext_buf; 698 } 699 700 /* 701 * Adjust alignment so packet payload begins on a 702 * longword boundary. Mandatory for Alpha, useful on 703 * x86 too. 704 */ 705 m_adj(m_new, ETHER_ALIGN); 706 707 c->lge_mbuf = m_new; 708 c->lge_fragptr_hi = 0; 709 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 710 c->lge_fraglen = m_new->m_len; 711 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 712 c->lge_sts = 0; 713 714 /* 715 * Put this buffer in the RX command FIFO. To do this, 716 * we just write the physical address of the descriptor 717 * into the RX descriptor address registers. Note that 718 * there are two registers, one high DWORD and one low 719 * DWORD, which lets us specify a 64-bit address if 720 * desired. We only use a 32-bit address for now. 721 * Writing to the low DWORD register is what actually 722 * causes the command to be issued, so we do that 723 * last. 724 */ 725 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 726 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 727 728 return(0); 729 } 730 731 static int 732 lge_alloc_jumbo_mem(struct lge_softc *sc) 733 { 734 struct lge_jslot *entry; 735 caddr_t ptr; 736 int i; 737 738 /* Grab a big chunk o' storage. */ 739 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 740 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 741 742 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 743 kprintf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 744 return(ENOBUFS); 745 } 746 747 SLIST_INIT(&sc->lge_jfree_listhead); 748 749 /* 750 * Now divide it up into 9K pieces and save the addresses 751 * in an array. 752 */ 753 ptr = sc->lge_cdata.lge_jumbo_buf; 754 for (i = 0; i < LGE_JSLOTS; i++) { 755 entry = &sc->lge_cdata.lge_jslots[i]; 756 entry->lge_sc = sc; 757 entry->lge_buf = ptr; 758 entry->lge_inuse = 0; 759 entry->lge_slot = i; 760 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link); 761 ptr += LGE_JLEN; 762 } 763 764 return(0); 765 } 766 767 static void 768 lge_free_jumbo_mem(struct lge_softc *sc) 769 { 770 if (sc->lge_cdata.lge_jumbo_buf) 771 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 772 } 773 774 /* 775 * Allocate a jumbo buffer. 776 */ 777 static struct lge_jslot * 778 lge_jalloc(struct lge_softc *sc) 779 { 780 struct lge_jslot *entry; 781 782 lwkt_serialize_enter(&sc->lge_jslot_serializer); 783 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 784 if (entry) { 785 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jslot_link); 786 entry->lge_inuse = 1; 787 } else { 788 #ifdef LGE_VERBOSE 789 kprintf("lge%d: no free jumbo buffers\n", sc->lge_unit); 790 #endif 791 } 792 lwkt_serialize_exit(&sc->lge_jslot_serializer); 793 return(entry); 794 } 795 796 /* 797 * Adjust usage count on a jumbo buffer. In general this doesn't 798 * get used much because our jumbo buffers don't get passed around 799 * a lot, but it's implemented for correctness. 800 */ 801 static void 802 lge_jref(void *arg) 803 { 804 struct lge_jslot *entry = (struct lge_jslot *)arg; 805 struct lge_softc *sc = entry->lge_sc; 806 807 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) 808 panic("lge_jref: asked to reference buffer " 809 "that we don't manage!"); 810 else if (entry->lge_inuse == 0) 811 panic("lge_jref: buffer already free!"); 812 else 813 atomic_add_int(&entry->lge_inuse, 1); 814 } 815 816 /* 817 * Release a jumbo buffer. 818 */ 819 static void 820 lge_jfree(void *arg) 821 { 822 struct lge_jslot *entry = (struct lge_jslot *)arg; 823 struct lge_softc *sc = entry->lge_sc; 824 825 if (sc == NULL) 826 panic("lge_jfree: can't find softc pointer!"); 827 828 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) { 829 panic("lge_jfree: asked to free buffer that we don't manage!"); 830 } else if (entry->lge_inuse == 0) { 831 panic("lge_jfree: buffer already free!"); 832 } else { 833 lwkt_serialize_enter(&sc->lge_jslot_serializer); 834 atomic_subtract_int(&entry->lge_inuse, 1); 835 if (entry->lge_inuse == 0) { 836 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 837 entry, jslot_link); 838 } 839 lwkt_serialize_exit(&sc->lge_jslot_serializer); 840 } 841 } 842 843 /* 844 * A frame has been uploaded: pass the resulting mbuf chain up to 845 * the higher level protocols. 846 */ 847 static void 848 lge_rxeof(struct lge_softc *sc, int cnt) 849 { 850 struct ifnet *ifp = &sc->arpcom.ac_if; 851 struct mbuf *m; 852 struct lge_rx_desc *cur_rx; 853 int c, i, total_len = 0; 854 uint32_t rxsts, rxctl; 855 856 857 /* Find out how many frames were processed. */ 858 c = cnt; 859 i = sc->lge_cdata.lge_rx_cons; 860 861 /* Suck them in. */ 862 while(c) { 863 struct mbuf *m0 = NULL; 864 865 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 866 rxctl = cur_rx->lge_ctl; 867 rxsts = cur_rx->lge_sts; 868 m = cur_rx->lge_mbuf; 869 cur_rx->lge_mbuf = NULL; 870 total_len = LGE_RXBYTES(cur_rx); 871 LGE_INC(i, LGE_RX_LIST_CNT); 872 c--; 873 874 /* 875 * If an error occurs, update stats, clear the 876 * status word and leave the mbuf cluster in place: 877 * it should simply get re-used next time this descriptor 878 * comes up in the ring. 879 */ 880 if (rxctl & LGE_RXCTL_ERRMASK) { 881 IFNET_STAT_INC(ifp, ierrors, 1); 882 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 883 continue; 884 } 885 886 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 887 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 888 total_len + ETHER_ALIGN, 0, ifp); 889 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 890 if (m0 == NULL) { 891 kprintf("lge%d: no receive buffers " 892 "available -- packet dropped!\n", 893 sc->lge_unit); 894 IFNET_STAT_INC(ifp, ierrors, 1); 895 continue; 896 } 897 m_adj(m0, ETHER_ALIGN); 898 m = m0; 899 } else { 900 m->m_pkthdr.rcvif = ifp; 901 m->m_pkthdr.len = m->m_len = total_len; 902 } 903 904 IFNET_STAT_INC(ifp, ipackets, 1); 905 906 /* Do IP checksum checking. */ 907 if (rxsts & LGE_RXSTS_ISIP) 908 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 909 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 910 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 911 if ((rxsts & LGE_RXSTS_ISTCP && 912 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 913 (rxsts & LGE_RXSTS_ISUDP && 914 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 915 m->m_pkthdr.csum_flags |= 916 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 917 CSUM_FRAG_NOT_CHECKED; 918 m->m_pkthdr.csum_data = 0xffff; 919 } 920 921 ifp->if_input(ifp, m, NULL, -1); 922 } 923 924 sc->lge_cdata.lge_rx_cons = i; 925 } 926 927 static void 928 lge_rxeoc(struct lge_softc *sc) 929 { 930 struct ifnet *ifp = &sc->arpcom.ac_if; 931 932 ifp->if_flags &= ~IFF_RUNNING; 933 lge_init(sc); 934 } 935 936 /* 937 * A frame was downloaded to the chip. It's safe for us to clean up 938 * the list buffers. 939 */ 940 static void 941 lge_txeof(struct lge_softc *sc) 942 { 943 struct ifnet *ifp = &sc->arpcom.ac_if; 944 struct lge_tx_desc *cur_tx = NULL; 945 uint32_t idx, txdone; 946 947 /* Clear the timeout timer. */ 948 ifp->if_timer = 0; 949 950 /* 951 * Go through our tx list and free mbufs for those 952 * frames that have been transmitted. 953 */ 954 idx = sc->lge_cdata.lge_tx_cons; 955 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 956 957 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 958 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 959 960 IFNET_STAT_INC(ifp, opackets, 1); 961 if (cur_tx->lge_mbuf != NULL) { 962 m_freem(cur_tx->lge_mbuf); 963 cur_tx->lge_mbuf = NULL; 964 } 965 cur_tx->lge_ctl = 0; 966 967 txdone--; 968 LGE_INC(idx, LGE_TX_LIST_CNT); 969 ifp->if_timer = 0; 970 } 971 972 sc->lge_cdata.lge_tx_cons = idx; 973 974 if (cur_tx != NULL) 975 ifq_clr_oactive(&ifp->if_snd); 976 } 977 978 static void 979 lge_tick(void *xsc) 980 { 981 struct lge_softc *sc = xsc; 982 struct ifnet *ifp = &sc->arpcom.ac_if; 983 984 lwkt_serialize_enter(ifp->if_serializer); 985 lge_tick_serialized(xsc); 986 lwkt_serialize_exit(ifp->if_serializer); 987 } 988 989 static void 990 lge_tick_serialized(void *xsc) 991 { 992 struct lge_softc *sc = xsc; 993 struct mii_data *mii; 994 struct ifnet *ifp = &sc->arpcom.ac_if; 995 996 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 997 IFNET_STAT_INC(ifp, collisions, CSR_READ_4(sc, LGE_STATSVAL)); 998 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 999 IFNET_STAT_INC(ifp, collisions, CSR_READ_4(sc, LGE_STATSVAL)); 1000 1001 if (!sc->lge_link) { 1002 mii = device_get_softc(sc->lge_miibus); 1003 mii_tick(mii); 1004 mii_pollstat(mii); 1005 if (mii->mii_media_status & IFM_ACTIVE && 1006 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1007 sc->lge_link++; 1008 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1009 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1010 kprintf("lge%d: gigabit link up\n", 1011 sc->lge_unit); 1012 if (!ifq_is_empty(&ifp->if_snd)) 1013 if_devstart(ifp); 1014 } 1015 } 1016 1017 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1018 } 1019 1020 static void 1021 lge_intr(void *arg) 1022 { 1023 struct lge_softc *sc = arg; 1024 struct ifnet *ifp = &sc->arpcom.ac_if; 1025 uint32_t status; 1026 1027 /* Supress unwanted interrupts */ 1028 if ((ifp->if_flags & IFF_UP) == 0) { 1029 lge_stop(sc); 1030 return; 1031 } 1032 1033 for (;;) { 1034 /* 1035 * Reading the ISR register clears all interrupts, and 1036 * clears the 'interrupts enabled' bit in the IMR 1037 * register. 1038 */ 1039 status = CSR_READ_4(sc, LGE_ISR); 1040 1041 if ((status & LGE_INTRS) == 0) 1042 break; 1043 1044 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1045 lge_txeof(sc); 1046 1047 if (status & LGE_ISR_RXDMA_DONE) 1048 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1049 1050 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1051 lge_rxeoc(sc); 1052 1053 if (status & LGE_ISR_PHY_INTR) { 1054 sc->lge_link = 0; 1055 callout_stop(&sc->lge_stat_timer); 1056 lge_tick_serialized(sc); 1057 } 1058 } 1059 1060 /* Re-enable interrupts. */ 1061 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1062 1063 if (!ifq_is_empty(&ifp->if_snd)) 1064 if_devstart(ifp); 1065 } 1066 1067 /* 1068 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1069 * pointers to the fragment pointers. 1070 */ 1071 static int 1072 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1073 { 1074 struct lge_frag *f = NULL; 1075 struct lge_tx_desc *cur_tx; 1076 struct mbuf *m; 1077 int frag = 0, tot_len = 0; 1078 1079 /* 1080 * Start packing the mbufs in this chain into 1081 * the fragment pointers. Stop when we run out 1082 * of fragments or hit the end of the mbuf chain. 1083 */ 1084 m = m_head; 1085 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1086 frag = 0; 1087 1088 for (m = m_head; m != NULL; m = m->m_next) { 1089 if (m->m_len != 0) { 1090 if (frag == LGE_FRAG_CNT) 1091 break; 1092 1093 tot_len += m->m_len; 1094 f = &cur_tx->lge_frags[frag]; 1095 f->lge_fraglen = m->m_len; 1096 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1097 f->lge_fragptr_hi = 0; 1098 frag++; 1099 } 1100 } 1101 /* Caller should make sure that 'm_head' is not excessive fragmented */ 1102 KASSERT(m == NULL, ("too many fragments")); 1103 1104 cur_tx->lge_mbuf = m_head; 1105 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1106 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1107 1108 /* Queue for transmit */ 1109 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1110 1111 return(0); 1112 } 1113 1114 /* 1115 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1116 * to the mbuf data regions directly in the transmit lists. We also save a 1117 * copy of the pointers since the transmit list fragment pointers are 1118 * physical addresses. 1119 */ 1120 1121 static void 1122 lge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1123 { 1124 struct lge_softc *sc = ifp->if_softc; 1125 struct mbuf *m_head = NULL, *m_defragged; 1126 uint32_t idx; 1127 int need_timer; 1128 1129 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1130 1131 if (!sc->lge_link) { 1132 ifq_purge(&ifp->if_snd); 1133 return; 1134 } 1135 1136 idx = sc->lge_cdata.lge_tx_prod; 1137 1138 if (ifq_is_oactive(&ifp->if_snd)) 1139 return; 1140 1141 need_timer = 0; 1142 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1143 struct mbuf *m; 1144 int frags; 1145 1146 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) { 1147 ifq_set_oactive(&ifp->if_snd); 1148 break; 1149 } 1150 1151 m_defragged = NULL; 1152 m_head = ifq_dequeue(&ifp->if_snd); 1153 if (m_head == NULL) 1154 break; 1155 1156 again: 1157 frags = 0; 1158 for (m = m_head; m != NULL; m = m->m_next) 1159 ++frags; 1160 if (frags > LGE_FRAG_CNT) { 1161 if (m_defragged != NULL) { 1162 /* 1163 * Even after defragmentation, there 1164 * are still too many fragments, so 1165 * drop this packet. 1166 */ 1167 m_freem(m_head); 1168 continue; 1169 } 1170 1171 m_defragged = m_defrag(m_head, M_NOWAIT); 1172 if (m_defragged == NULL) { 1173 m_freem(m_head); 1174 continue; 1175 } 1176 m_head = m_defragged; 1177 1178 /* Recount # of fragments */ 1179 goto again; 1180 } 1181 1182 lge_encap(sc, m_head, &idx); 1183 need_timer = 1; 1184 1185 BPF_MTAP(ifp, m_head); 1186 } 1187 1188 if (!need_timer) 1189 return; 1190 1191 sc->lge_cdata.lge_tx_prod = idx; 1192 1193 /* 1194 * Set a timeout in case the chip goes out to lunch. 1195 */ 1196 ifp->if_timer = 5; 1197 } 1198 1199 static void 1200 lge_init(void *xsc) 1201 { 1202 struct lge_softc *sc = xsc; 1203 struct ifnet *ifp = &sc->arpcom.ac_if; 1204 1205 if (ifp->if_flags & IFF_RUNNING) 1206 return; 1207 1208 /* 1209 * Cancel pending I/O and free all RX/TX buffers. 1210 */ 1211 lge_stop(sc); 1212 lge_reset(sc); 1213 1214 /* Set MAC address */ 1215 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1216 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1217 1218 /* Init circular RX list. */ 1219 if (lge_list_rx_init(sc) == ENOBUFS) { 1220 kprintf("lge%d: initialization failed: no " 1221 "memory for rx buffers\n", sc->lge_unit); 1222 lge_stop(sc); 1223 return; 1224 } 1225 1226 /* 1227 * Init tx descriptors. 1228 */ 1229 lge_list_tx_init(sc); 1230 1231 /* Set initial value for MODE1 register. */ 1232 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST | 1233 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD | 1234 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 | 1235 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2); 1236 1237 /* If we want promiscuous mode, set the allframes bit. */ 1238 if (ifp->if_flags & IFF_PROMISC) { 1239 CSR_WRITE_4(sc, LGE_MODE1, 1240 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC); 1241 } else { 1242 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1243 } 1244 1245 /* 1246 * Set the capture broadcast bit to capture broadcast frames. 1247 */ 1248 if (ifp->if_flags & IFF_BROADCAST) { 1249 CSR_WRITE_4(sc, LGE_MODE1, 1250 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST); 1251 } else { 1252 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1253 } 1254 1255 /* Packet padding workaround? */ 1256 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1257 1258 /* No error frames */ 1259 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1260 1261 /* Receive large frames */ 1262 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS); 1263 1264 /* Workaround: disable RX/TX flow control */ 1265 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1266 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1267 1268 /* Make sure to strip CRC from received frames */ 1269 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1270 1271 /* Turn off magic packet mode */ 1272 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1273 1274 /* Turn off all VLAN stuff */ 1275 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX | 1276 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT); 1277 1278 /* Workarond: FIFO overflow */ 1279 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1280 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1281 1282 /* 1283 * Load the multicast filter. 1284 */ 1285 lge_setmulti(sc); 1286 1287 /* 1288 * Enable hardware checksum validation for all received IPv4 1289 * packets, do not reject packets with bad checksums. 1290 */ 1291 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM | 1292 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM | 1293 LGE_MODE2_RX_ERRCSUM); 1294 1295 /* 1296 * Enable the delivery of PHY interrupts based on 1297 * link/speed/duplex status chalges. 1298 */ 1299 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL); 1300 1301 /* Enable receiver and transmitter. */ 1302 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1303 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB); 1304 1305 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1306 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB); 1307 1308 /* 1309 * Enable interrupts. 1310 */ 1311 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 | 1312 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS); 1313 1314 lge_ifmedia_upd(ifp); 1315 1316 ifp->if_flags |= IFF_RUNNING; 1317 ifq_clr_oactive(&ifp->if_snd); 1318 1319 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1320 } 1321 1322 /* 1323 * Set media options. 1324 */ 1325 static int 1326 lge_ifmedia_upd(struct ifnet *ifp) 1327 { 1328 struct lge_softc *sc = ifp->if_softc; 1329 struct mii_data *mii = device_get_softc(sc->lge_miibus); 1330 1331 sc->lge_link = 0; 1332 if (mii->mii_instance) { 1333 struct mii_softc *miisc; 1334 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1335 mii_phy_reset(miisc); 1336 } 1337 mii_mediachg(mii); 1338 1339 return(0); 1340 } 1341 1342 /* 1343 * Report current media status. 1344 */ 1345 static void 1346 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1347 { 1348 struct lge_softc *sc = ifp->if_softc; 1349 struct mii_data *mii; 1350 1351 mii = device_get_softc(sc->lge_miibus); 1352 mii_pollstat(mii); 1353 ifmr->ifm_active = mii->mii_media_active; 1354 ifmr->ifm_status = mii->mii_media_status; 1355 } 1356 1357 static int 1358 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1359 { 1360 struct lge_softc *sc = ifp->if_softc; 1361 struct ifreq *ifr = (struct ifreq *) data; 1362 struct mii_data *mii; 1363 int error = 0; 1364 1365 switch(command) { 1366 case SIOCSIFMTU: 1367 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1368 error = EINVAL; 1369 else 1370 ifp->if_mtu = ifr->ifr_mtu; 1371 break; 1372 case SIOCSIFFLAGS: 1373 if (ifp->if_flags & IFF_UP) { 1374 if (ifp->if_flags & IFF_RUNNING && 1375 ifp->if_flags & IFF_PROMISC && 1376 !(sc->lge_if_flags & IFF_PROMISC)) { 1377 CSR_WRITE_4(sc, LGE_MODE1, 1378 LGE_MODE1_SETRST_CTL1| 1379 LGE_MODE1_RX_PROMISC); 1380 } else if (ifp->if_flags & IFF_RUNNING && 1381 !(ifp->if_flags & IFF_PROMISC) && 1382 sc->lge_if_flags & IFF_PROMISC) { 1383 CSR_WRITE_4(sc, LGE_MODE1, 1384 LGE_MODE1_RX_PROMISC); 1385 } else { 1386 ifp->if_flags &= ~IFF_RUNNING; 1387 lge_init(sc); 1388 } 1389 } else { 1390 if (ifp->if_flags & IFF_RUNNING) 1391 lge_stop(sc); 1392 } 1393 sc->lge_if_flags = ifp->if_flags; 1394 error = 0; 1395 break; 1396 case SIOCADDMULTI: 1397 case SIOCDELMULTI: 1398 lge_setmulti(sc); 1399 error = 0; 1400 break; 1401 case SIOCGIFMEDIA: 1402 case SIOCSIFMEDIA: 1403 mii = device_get_softc(sc->lge_miibus); 1404 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1405 break; 1406 default: 1407 error = ether_ioctl(ifp, command, data); 1408 break; 1409 } 1410 1411 return(error); 1412 } 1413 1414 static void 1415 lge_watchdog(struct ifnet *ifp) 1416 { 1417 struct lge_softc *sc = ifp->if_softc; 1418 1419 IFNET_STAT_INC(ifp, oerrors, 1); 1420 kprintf("lge%d: watchdog timeout\n", sc->lge_unit); 1421 1422 lge_stop(sc); 1423 lge_reset(sc); 1424 ifp->if_flags &= ~IFF_RUNNING; 1425 lge_init(sc); 1426 1427 if (!ifq_is_empty(&ifp->if_snd)) 1428 if_devstart(ifp); 1429 } 1430 1431 /* 1432 * Stop the adapter and free any mbufs allocated to the 1433 * RX and TX lists. 1434 */ 1435 static void 1436 lge_stop(struct lge_softc *sc) 1437 { 1438 struct ifnet *ifp = &sc->arpcom.ac_if; 1439 int i; 1440 1441 ifp->if_timer = 0; 1442 callout_stop(&sc->lge_stat_timer); 1443 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1444 1445 /* Disable receiver and transmitter. */ 1446 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1447 sc->lge_link = 0; 1448 1449 /* 1450 * Free data in the RX lists. 1451 */ 1452 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1453 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1454 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1455 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1456 } 1457 } 1458 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list)); 1459 1460 /* 1461 * Free the TX list buffers. 1462 */ 1463 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1464 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1465 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1466 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1467 } 1468 } 1469 1470 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list)); 1471 1472 ifp->if_flags &= ~IFF_RUNNING; 1473 ifq_clr_oactive(&ifp->if_snd); 1474 } 1475 1476 /* 1477 * Stop all chip I/O so that the kernel's probe routines don't 1478 * get confused by errant DMAs when rebooting. 1479 */ 1480 static void 1481 lge_shutdown(device_t dev) 1482 { 1483 struct lge_softc *sc = device_get_softc(dev); 1484 1485 lge_reset(sc); 1486 lge_stop(sc); 1487 } 1488