1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $ 34 */ 35 36 /* 37 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 38 * documentation not available, but ask me nicely. 39 * 40 * Written by Bill Paul <william.paul@windriver.com> 41 * Wind River Systems 42 */ 43 44 /* 45 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 46 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 47 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 48 * are three supported methods for data transfer between host and 49 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 50 * Propulsion Technology (tm) DMA. The latter mechanism is a form 51 * of double buffer DMA where the packet data is copied to a 52 * pre-allocated DMA buffer who's physical address has been loaded 53 * into a table at device initialization time. The rationale is that 54 * the virtual to physical address translation needed for normal 55 * scatter/gather DMA is more expensive than the data copy needed 56 * for double buffering. This may be true in Windows NT and the like, 57 * but it isn't true for us, at least on the x86 arch. This driver 58 * uses the scatter/gather I/O method for both TX and RX. 59 * 60 * The LXT1001 only supports TCP/IP checksum offload on receive. 61 * Also, the VLAN tagging is done using a 16-entry table which allows 62 * the chip to perform hardware filtering based on VLAN tags. Sadly, 63 * our vlan support doesn't currently play well with this kind of 64 * hardware support. 65 * 66 * Special thanks to: 67 * - Jeff James at Intel, for arranging to have the LXT1001 manual 68 * released (at long last) 69 * - Beny Chen at D-Link, for actually sending it to me 70 * - Brad Short and Keith Alexis at SMC, for sending me sample 71 * SMC9462SX and SMC9462TX adapters for testing 72 * - Paul Saab at Y!, for not killing me (though it remains to be seen 73 * if in fact he did me much of a favor) 74 */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/sockio.h> 79 #include <sys/mbuf.h> 80 #include <sys/malloc.h> 81 #include <sys/kernel.h> 82 #include <sys/interrupt.h> 83 #include <sys/socket.h> 84 #include <sys/serialize.h> 85 #include <sys/thread2.h> 86 87 #include <net/if.h> 88 #include <net/ifq_var.h> 89 #include <net/if_arp.h> 90 #include <net/ethernet.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 94 #include <net/bpf.h> 95 96 #include <vm/vm.h> /* for vtophys */ 97 #include <vm/pmap.h> /* for vtophys */ 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 101 #include <dev/netif/mii_layer/mii.h> 102 #include <dev/netif/mii_layer/miivar.h> 103 104 #include <bus/pci/pcidevs.h> 105 #include <bus/pci/pcireg.h> 106 #include <bus/pci/pcivar.h> 107 108 #define LGE_USEIOSPACE 109 110 #include "if_lgereg.h" 111 112 /* "controller miibus0" required. See GENERIC if you get errors here. */ 113 #include "miibus_if.h" 114 115 /* 116 * Various supported device vendors/types and their names. 117 */ 118 static struct lge_type lge_devs[] = { 119 { PCI_VENDOR_LEVELONE, PCI_PRODUCT_LEVELONE_LXT1001, 120 "Level 1 Gigabit Ethernet" }, 121 { 0, 0, NULL } 122 }; 123 124 static int lge_probe(device_t); 125 static int lge_attach(device_t); 126 static int lge_detach(device_t); 127 128 static int lge_alloc_jumbo_mem(struct lge_softc *); 129 static void lge_free_jumbo_mem(struct lge_softc *); 130 static struct lge_jslot 131 *lge_jalloc(struct lge_softc *); 132 static void lge_jfree(void *); 133 static void lge_jref(void *); 134 135 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, 136 struct mbuf *); 137 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *); 138 static void lge_rxeof(struct lge_softc *, int); 139 static void lge_rxeoc(struct lge_softc *); 140 static void lge_txeof(struct lge_softc *); 141 static void lge_intr(void *); 142 static void lge_tick(void *); 143 static void lge_tick_serialized(void *); 144 static void lge_start(struct ifnet *); 145 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 146 static void lge_init(void *); 147 static void lge_stop(struct lge_softc *); 148 static void lge_watchdog(struct ifnet *); 149 static void lge_shutdown(device_t); 150 static int lge_ifmedia_upd(struct ifnet *); 151 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 152 153 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *); 154 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int); 155 156 static int lge_miibus_readreg(device_t, int, int); 157 static int lge_miibus_writereg(device_t, int, int, int); 158 static void lge_miibus_statchg(device_t); 159 160 static void lge_setmulti(struct lge_softc *); 161 static void lge_reset(struct lge_softc *); 162 static int lge_list_rx_init(struct lge_softc *); 163 static int lge_list_tx_init(struct lge_softc *); 164 165 #ifdef LGE_USEIOSPACE 166 #define LGE_RES SYS_RES_IOPORT 167 #define LGE_RID LGE_PCI_LOIO 168 #else 169 #define LGE_RES SYS_RES_MEMORY 170 #define LGE_RID LGE_PCI_LOMEM 171 #endif 172 173 static device_method_t lge_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, lge_probe), 176 DEVMETHOD(device_attach, lge_attach), 177 DEVMETHOD(device_detach, lge_detach), 178 DEVMETHOD(device_shutdown, lge_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 186 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 187 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 188 189 { 0, 0 } 190 }; 191 192 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc)); 193 static devclass_t lge_devclass; 194 195 DECLARE_DUMMY_MODULE(if_lge); 196 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, NULL, NULL); 197 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, NULL, NULL); 198 199 #define LGE_SETBIT(sc, reg, x) \ 200 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 201 202 #define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 204 205 #define SIO_SET(x) \ 206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x)) 207 208 #define SIO_CLR(x) \ 209 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x)) 210 211 /* 212 * Read a word of data stored in the EEPROM at address 'addr.' 213 */ 214 static void 215 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest) 216 { 217 int i; 218 uint32_t val; 219 220 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 221 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8)); 222 223 for (i = 0; i < LGE_TIMEOUT; i++) { 224 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0) 225 break; 226 } 227 228 if (i == LGE_TIMEOUT) { 229 kprintf("lge%d: EEPROM read timed out\n", sc->lge_unit); 230 return; 231 } 232 233 val = CSR_READ_4(sc, LGE_EEDATA); 234 235 if (addr & 1) 236 *dest = (val >> 16) & 0xFFFF; 237 else 238 *dest = val & 0xFFFF; 239 } 240 241 /* 242 * Read a sequence of words from the EEPROM. 243 */ 244 static void 245 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt) 246 { 247 int i; 248 uint16_t word = 0, *ptr; 249 250 for (i = 0; i < cnt; i++) { 251 lge_eeprom_getword(sc, off + i, &word); 252 ptr = (uint16_t *)(dest + (i * 2)); 253 *ptr = ntohs(word); 254 } 255 } 256 257 static int 258 lge_miibus_readreg(device_t dev, int phy, int reg) 259 { 260 struct lge_softc *sc = device_get_softc(dev); 261 int i; 262 263 /* 264 * If we have a non-PCS PHY, pretend that the internal 265 * autoneg stuff at PHY address 0 isn't there so that 266 * the miibus code will find only the GMII PHY. 267 */ 268 if (sc->lge_pcs == 0 && phy == 0) 269 return(0); 270 271 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 272 273 for (i = 0; i < LGE_TIMEOUT; i++) { 274 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 275 break; 276 } 277 278 if (i == LGE_TIMEOUT) { 279 kprintf("lge%d: PHY read timed out\n", sc->lge_unit); 280 return(0); 281 } 282 283 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 284 } 285 286 static int 287 lge_miibus_writereg(device_t dev, int phy, int reg, int data) 288 { 289 struct lge_softc *sc = device_get_softc(dev); 290 int i; 291 292 CSR_WRITE_4(sc, LGE_GMIICTL, 293 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 294 295 for (i = 0; i < LGE_TIMEOUT; i++) { 296 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0) 297 break; 298 } 299 300 if (i == LGE_TIMEOUT) { 301 kprintf("lge%d: PHY write timed out\n", sc->lge_unit); 302 return(0); 303 } 304 305 return(0); 306 } 307 308 static void 309 lge_miibus_statchg(device_t dev) 310 { 311 struct lge_softc *sc = device_get_softc(dev); 312 struct mii_data *mii = device_get_softc(sc->lge_miibus); 313 314 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 315 switch (IFM_SUBTYPE(mii->mii_media_active)) { 316 case IFM_1000_T: 317 case IFM_1000_SX: 318 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 319 break; 320 case IFM_100_TX: 321 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 322 break; 323 case IFM_10_T: 324 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 325 break; 326 default: 327 /* 328 * Choose something, even if it's wrong. Clearing 329 * all the bits will hose autoneg on the internal 330 * PHY. 331 */ 332 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 333 break; 334 } 335 336 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 337 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 338 else 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 340 } 341 342 static void 343 lge_setmulti(struct lge_softc *sc) 344 { 345 struct ifnet *ifp = &sc->arpcom.ac_if; 346 struct ifmultiaddr *ifma; 347 uint32_t h = 0, hashes[2] = { 0, 0 }; 348 349 /* Make sure multicast hash table is enabled. */ 350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST); 351 352 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 353 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 354 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 355 return; 356 } 357 358 /* first, zot all the existing hash bits */ 359 CSR_WRITE_4(sc, LGE_MAR0, 0); 360 CSR_WRITE_4(sc, LGE_MAR1, 0); 361 362 /* now program new ones */ 363 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 364 if (ifma->ifma_addr->sa_family != AF_LINK) 365 continue; 366 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 367 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 368 if (h < 32) 369 hashes[0] |= (1 << h); 370 else 371 hashes[1] |= (1 << (h - 32)); 372 } 373 374 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 375 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 376 377 return; 378 } 379 380 static void 381 lge_reset(struct lge_softc *sc) 382 { 383 int i; 384 385 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST); 386 387 for (i = 0; i < LGE_TIMEOUT; i++) { 388 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0) 389 break; 390 } 391 392 if (i == LGE_TIMEOUT) 393 kprintf("lge%d: reset never completed\n", sc->lge_unit); 394 395 /* Wait a little while for the chip to get its brains in order. */ 396 DELAY(1000); 397 } 398 399 /* 400 * Probe for a Level 1 chip. Check the PCI vendor and device 401 * IDs against our list and return a device name if we find a match. 402 */ 403 static int 404 lge_probe(device_t dev) 405 { 406 struct lge_type *t; 407 uint16_t vendor, product; 408 409 vendor = pci_get_vendor(dev); 410 product = pci_get_device(dev); 411 412 for (t = lge_devs; t->lge_name != NULL; t++) { 413 if (vendor == t->lge_vid && product == t->lge_did) { 414 device_set_desc(dev, t->lge_name); 415 return(0); 416 } 417 } 418 419 return(ENXIO); 420 } 421 422 /* 423 * Attach the interface. Allocate softc structures, do ifmedia 424 * setup and ethernet/BPF attach. 425 */ 426 static int 427 lge_attach(device_t dev) 428 { 429 uint8_t eaddr[ETHER_ADDR_LEN]; 430 struct lge_softc *sc; 431 struct ifnet *ifp; 432 int unit, error = 0, rid; 433 434 sc = device_get_softc(dev); 435 unit = device_get_unit(dev); 436 callout_init(&sc->lge_stat_timer); 437 lwkt_serialize_init(&sc->lge_jslot_serializer); 438 439 /* 440 * Handle power management nonsense. 441 */ 442 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 443 uint32_t iobase, membase, irq; 444 445 /* Save important PCI config data. */ 446 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 447 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 448 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 449 450 /* Reset the power state. */ 451 device_printf(dev, "chip is in D%d power mode " 452 "-- setting to D0\n", pci_get_powerstate(dev)); 453 454 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 455 456 /* Restore PCI config data. */ 457 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 458 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 459 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 460 } 461 462 pci_enable_busmaster(dev); 463 464 rid = LGE_RID; 465 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE); 466 467 if (sc->lge_res == NULL) { 468 kprintf("lge%d: couldn't map ports/memory\n", unit); 469 error = ENXIO; 470 goto fail; 471 } 472 473 sc->lge_btag = rman_get_bustag(sc->lge_res); 474 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 475 476 /* Allocate interrupt */ 477 rid = 0; 478 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 479 RF_SHAREABLE | RF_ACTIVE); 480 481 if (sc->lge_irq == NULL) { 482 kprintf("lge%d: couldn't map interrupt\n", unit); 483 error = ENXIO; 484 goto fail; 485 } 486 487 /* Reset the adapter. */ 488 lge_reset(sc); 489 490 /* 491 * Get station address from the EEPROM. 492 */ 493 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1); 494 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1); 495 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1); 496 497 sc->lge_unit = unit; 498 499 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 500 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 501 502 if (sc->lge_ldata == NULL) { 503 kprintf("lge%d: no memory for list buffers!\n", unit); 504 error = ENXIO; 505 goto fail; 506 } 507 508 /* Try to allocate memory for jumbo buffers. */ 509 if (lge_alloc_jumbo_mem(sc)) { 510 kprintf("lge%d: jumbo buffer allocation failed\n", 511 sc->lge_unit); 512 error = ENXIO; 513 goto fail; 514 } 515 516 ifp = &sc->arpcom.ac_if; 517 ifp->if_softc = sc; 518 if_initname(ifp, "lge", unit); 519 ifp->if_mtu = ETHERMTU; 520 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 521 ifp->if_ioctl = lge_ioctl; 522 ifp->if_start = lge_start; 523 ifp->if_watchdog = lge_watchdog; 524 ifp->if_init = lge_init; 525 ifp->if_baudrate = 1000000000; 526 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1); 527 ifq_set_ready(&ifp->if_snd); 528 ifp->if_capabilities = IFCAP_RXCSUM; 529 ifp->if_capenable = ifp->if_capabilities; 530 531 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 532 sc->lge_pcs = 1; 533 else 534 sc->lge_pcs = 0; 535 536 /* 537 * Do MII setup. 538 */ 539 if (mii_phy_probe(dev, &sc->lge_miibus, 540 lge_ifmedia_upd, lge_ifmedia_sts)) { 541 kprintf("lge%d: MII without any PHY!\n", sc->lge_unit); 542 error = ENXIO; 543 goto fail; 544 } 545 546 /* 547 * Call MI attach routine. 548 */ 549 ether_ifattach(ifp, eaddr, NULL); 550 551 error = bus_setup_intr(dev, sc->lge_irq, INTR_MPSAFE, 552 lge_intr, sc, &sc->lge_intrhand, 553 ifp->if_serializer); 554 if (error) { 555 ether_ifdetach(ifp); 556 kprintf("lge%d: couldn't set up irq\n", unit); 557 goto fail; 558 } 559 560 ifp->if_cpuid = rman_get_cpuid(sc->lge_irq); 561 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus); 562 563 return(0); 564 565 fail: 566 lge_detach(dev); 567 return(error); 568 } 569 570 static int 571 lge_detach(device_t dev) 572 { 573 struct lge_softc *sc= device_get_softc(dev); 574 struct ifnet *ifp = &sc->arpcom.ac_if; 575 576 if (device_is_attached(dev)) { 577 lwkt_serialize_enter(ifp->if_serializer); 578 lge_reset(sc); 579 lge_stop(sc); 580 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 581 lwkt_serialize_exit(ifp->if_serializer); 582 583 ether_ifdetach(ifp); 584 } 585 586 if (sc->lge_miibus) 587 device_delete_child(dev, sc->lge_miibus); 588 bus_generic_detach(dev); 589 590 if (sc->lge_irq) 591 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 592 if (sc->lge_res) 593 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 594 595 if (sc->lge_ldata) 596 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), 597 M_DEVBUF); 598 lge_free_jumbo_mem(sc); 599 600 return(0); 601 } 602 603 /* 604 * Initialize the transmit descriptors. 605 */ 606 static int 607 lge_list_tx_init(struct lge_softc *sc) 608 { 609 struct lge_list_data *ld; 610 struct lge_ring_data *cd; 611 int i; 612 613 cd = &sc->lge_cdata; 614 ld = sc->lge_ldata; 615 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 616 ld->lge_tx_list[i].lge_mbuf = NULL; 617 ld->lge_tx_list[i].lge_ctl = 0; 618 } 619 620 cd->lge_tx_prod = cd->lge_tx_cons = 0; 621 622 return(0); 623 } 624 625 626 /* 627 * Initialize the RX descriptors and allocate mbufs for them. Note that 628 * we arralge the descriptors in a closed ring, so that the last descriptor 629 * points back to the first. 630 */ 631 static int 632 lge_list_rx_init(struct lge_softc *sc) 633 { 634 struct lge_list_data *ld; 635 struct lge_ring_data *cd; 636 int i; 637 638 ld = sc->lge_ldata; 639 cd = &sc->lge_cdata; 640 641 cd->lge_rx_prod = cd->lge_rx_cons = 0; 642 643 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 644 645 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 646 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 647 break; 648 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 649 return(ENOBUFS); 650 } 651 652 /* Clear possible 'rx command queue empty' interrupt. */ 653 CSR_READ_4(sc, LGE_ISR); 654 655 return(0); 656 } 657 658 /* 659 * Initialize an RX descriptor and attach an MBUF cluster. 660 */ 661 static int 662 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m) 663 { 664 struct mbuf *m_new = NULL; 665 struct lge_jslot *buf; 666 667 if (m == NULL) { 668 MGETHDR(m_new, MB_DONTWAIT, MT_DATA); 669 if (m_new == NULL) { 670 kprintf("lge%d: no memory for rx list " 671 "-- packet dropped!\n", sc->lge_unit); 672 return(ENOBUFS); 673 } 674 675 /* Allocate the jumbo buffer */ 676 buf = lge_jalloc(sc); 677 if (buf == NULL) { 678 #ifdef LGE_VERBOSE 679 kprintf("lge%d: jumbo allocation failed " 680 "-- packet dropped!\n", sc->lge_unit); 681 #endif 682 m_freem(m_new); 683 return(ENOBUFS); 684 } 685 /* Attach the buffer to the mbuf */ 686 m_new->m_ext.ext_arg = buf; 687 m_new->m_ext.ext_buf = buf->lge_buf; 688 m_new->m_ext.ext_free = lge_jfree; 689 m_new->m_ext.ext_ref = lge_jref; 690 m_new->m_ext.ext_size = LGE_JUMBO_FRAMELEN; 691 692 m_new->m_data = m_new->m_ext.ext_buf; 693 m_new->m_flags |= M_EXT; 694 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size; 695 } else { 696 m_new = m; 697 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN; 698 m_new->m_data = m_new->m_ext.ext_buf; 699 } 700 701 /* 702 * Adjust alignment so packet payload begins on a 703 * longword boundary. Mandatory for Alpha, useful on 704 * x86 too. 705 */ 706 m_adj(m_new, ETHER_ALIGN); 707 708 c->lge_mbuf = m_new; 709 c->lge_fragptr_hi = 0; 710 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 711 c->lge_fraglen = m_new->m_len; 712 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 713 c->lge_sts = 0; 714 715 /* 716 * Put this buffer in the RX command FIFO. To do this, 717 * we just write the physical address of the descriptor 718 * into the RX descriptor address registers. Note that 719 * there are two registers, one high DWORD and one low 720 * DWORD, which lets us specify a 64-bit address if 721 * desired. We only use a 32-bit address for now. 722 * Writing to the low DWORD register is what actually 723 * causes the command to be issued, so we do that 724 * last. 725 */ 726 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 727 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 728 729 return(0); 730 } 731 732 static int 733 lge_alloc_jumbo_mem(struct lge_softc *sc) 734 { 735 struct lge_jslot *entry; 736 caddr_t ptr; 737 int i; 738 739 /* Grab a big chunk o' storage. */ 740 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 741 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0); 742 743 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 744 kprintf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 745 return(ENOBUFS); 746 } 747 748 SLIST_INIT(&sc->lge_jfree_listhead); 749 750 /* 751 * Now divide it up into 9K pieces and save the addresses 752 * in an array. 753 */ 754 ptr = sc->lge_cdata.lge_jumbo_buf; 755 for (i = 0; i < LGE_JSLOTS; i++) { 756 entry = &sc->lge_cdata.lge_jslots[i]; 757 entry->lge_sc = sc; 758 entry->lge_buf = ptr; 759 entry->lge_inuse = 0; 760 entry->lge_slot = i; 761 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link); 762 ptr += LGE_JLEN; 763 } 764 765 return(0); 766 } 767 768 static void 769 lge_free_jumbo_mem(struct lge_softc *sc) 770 { 771 if (sc->lge_cdata.lge_jumbo_buf) 772 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 773 } 774 775 /* 776 * Allocate a jumbo buffer. 777 */ 778 static struct lge_jslot * 779 lge_jalloc(struct lge_softc *sc) 780 { 781 struct lge_jslot *entry; 782 783 lwkt_serialize_enter(&sc->lge_jslot_serializer); 784 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 785 if (entry) { 786 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jslot_link); 787 entry->lge_inuse = 1; 788 } else { 789 #ifdef LGE_VERBOSE 790 kprintf("lge%d: no free jumbo buffers\n", sc->lge_unit); 791 #endif 792 } 793 lwkt_serialize_exit(&sc->lge_jslot_serializer); 794 return(entry); 795 } 796 797 /* 798 * Adjust usage count on a jumbo buffer. In general this doesn't 799 * get used much because our jumbo buffers don't get passed around 800 * a lot, but it's implemented for correctness. 801 */ 802 static void 803 lge_jref(void *arg) 804 { 805 struct lge_jslot *entry = (struct lge_jslot *)arg; 806 struct lge_softc *sc = entry->lge_sc; 807 808 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) 809 panic("lge_jref: asked to reference buffer " 810 "that we don't manage!"); 811 else if (entry->lge_inuse == 0) 812 panic("lge_jref: buffer already free!"); 813 else 814 atomic_add_int(&entry->lge_inuse, 1); 815 } 816 817 /* 818 * Release a jumbo buffer. 819 */ 820 static void 821 lge_jfree(void *arg) 822 { 823 struct lge_jslot *entry = (struct lge_jslot *)arg; 824 struct lge_softc *sc = entry->lge_sc; 825 826 if (sc == NULL) 827 panic("lge_jfree: can't find softc pointer!"); 828 829 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) { 830 panic("lge_jfree: asked to free buffer that we don't manage!"); 831 } else if (entry->lge_inuse == 0) { 832 panic("lge_jfree: buffer already free!"); 833 } else { 834 lwkt_serialize_enter(&sc->lge_jslot_serializer); 835 atomic_subtract_int(&entry->lge_inuse, 1); 836 if (entry->lge_inuse == 0) { 837 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 838 entry, jslot_link); 839 } 840 lwkt_serialize_exit(&sc->lge_jslot_serializer); 841 } 842 } 843 844 /* 845 * A frame has been uploaded: pass the resulting mbuf chain up to 846 * the higher level protocols. 847 */ 848 static void 849 lge_rxeof(struct lge_softc *sc, int cnt) 850 { 851 struct ifnet *ifp = &sc->arpcom.ac_if; 852 struct mbuf *m; 853 struct lge_rx_desc *cur_rx; 854 int c, i, total_len = 0; 855 uint32_t rxsts, rxctl; 856 857 858 /* Find out how many frames were processed. */ 859 c = cnt; 860 i = sc->lge_cdata.lge_rx_cons; 861 862 /* Suck them in. */ 863 while(c) { 864 struct mbuf *m0 = NULL; 865 866 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 867 rxctl = cur_rx->lge_ctl; 868 rxsts = cur_rx->lge_sts; 869 m = cur_rx->lge_mbuf; 870 cur_rx->lge_mbuf = NULL; 871 total_len = LGE_RXBYTES(cur_rx); 872 LGE_INC(i, LGE_RX_LIST_CNT); 873 c--; 874 875 /* 876 * If an error occurs, update stats, clear the 877 * status word and leave the mbuf cluster in place: 878 * it should simply get re-used next time this descriptor 879 * comes up in the ring. 880 */ 881 if (rxctl & LGE_RXCTL_ERRMASK) { 882 ifp->if_ierrors++; 883 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 884 continue; 885 } 886 887 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 888 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 889 total_len + ETHER_ALIGN, 0, ifp, NULL); 890 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 891 if (m0 == NULL) { 892 kprintf("lge%d: no receive buffers " 893 "available -- packet dropped!\n", 894 sc->lge_unit); 895 ifp->if_ierrors++; 896 continue; 897 } 898 m_adj(m0, ETHER_ALIGN); 899 m = m0; 900 } else { 901 m->m_pkthdr.rcvif = ifp; 902 m->m_pkthdr.len = m->m_len = total_len; 903 } 904 905 ifp->if_ipackets++; 906 907 /* Do IP checksum checking. */ 908 if (rxsts & LGE_RXSTS_ISIP) 909 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 910 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 911 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 912 if ((rxsts & LGE_RXSTS_ISTCP && 913 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 914 (rxsts & LGE_RXSTS_ISUDP && 915 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 916 m->m_pkthdr.csum_flags |= 917 CSUM_DATA_VALID|CSUM_PSEUDO_HDR| 918 CSUM_FRAG_NOT_CHECKED; 919 m->m_pkthdr.csum_data = 0xffff; 920 } 921 922 ifp->if_input(ifp, m); 923 } 924 925 sc->lge_cdata.lge_rx_cons = i; 926 } 927 928 static void 929 lge_rxeoc(struct lge_softc *sc) 930 { 931 struct ifnet *ifp = &sc->arpcom.ac_if; 932 933 ifp->if_flags &= ~IFF_RUNNING; 934 lge_init(sc); 935 } 936 937 /* 938 * A frame was downloaded to the chip. It's safe for us to clean up 939 * the list buffers. 940 */ 941 static void 942 lge_txeof(struct lge_softc *sc) 943 { 944 struct ifnet *ifp = &sc->arpcom.ac_if; 945 struct lge_tx_desc *cur_tx = NULL; 946 uint32_t idx, txdone; 947 948 /* Clear the timeout timer. */ 949 ifp->if_timer = 0; 950 951 /* 952 * Go through our tx list and free mbufs for those 953 * frames that have been transmitted. 954 */ 955 idx = sc->lge_cdata.lge_tx_cons; 956 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 957 958 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 959 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 960 961 ifp->if_opackets++; 962 if (cur_tx->lge_mbuf != NULL) { 963 m_freem(cur_tx->lge_mbuf); 964 cur_tx->lge_mbuf = NULL; 965 } 966 cur_tx->lge_ctl = 0; 967 968 txdone--; 969 LGE_INC(idx, LGE_TX_LIST_CNT); 970 ifp->if_timer = 0; 971 } 972 973 sc->lge_cdata.lge_tx_cons = idx; 974 975 if (cur_tx != NULL) 976 ifp->if_flags &= ~IFF_OACTIVE; 977 } 978 979 static void 980 lge_tick(void *xsc) 981 { 982 struct lge_softc *sc = xsc; 983 struct ifnet *ifp = &sc->arpcom.ac_if; 984 985 lwkt_serialize_enter(ifp->if_serializer); 986 lge_tick_serialized(xsc); 987 lwkt_serialize_exit(ifp->if_serializer); 988 } 989 990 static void 991 lge_tick_serialized(void *xsc) 992 { 993 struct lge_softc *sc = xsc; 994 struct mii_data *mii; 995 struct ifnet *ifp = &sc->arpcom.ac_if; 996 997 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 998 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 999 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1000 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1001 1002 if (!sc->lge_link) { 1003 mii = device_get_softc(sc->lge_miibus); 1004 mii_tick(mii); 1005 mii_pollstat(mii); 1006 if (mii->mii_media_status & IFM_ACTIVE && 1007 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1008 sc->lge_link++; 1009 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1010 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1011 kprintf("lge%d: gigabit link up\n", 1012 sc->lge_unit); 1013 if (!ifq_is_empty(&ifp->if_snd)) 1014 if_devstart(ifp); 1015 } 1016 } 1017 1018 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1019 } 1020 1021 static void 1022 lge_intr(void *arg) 1023 { 1024 struct lge_softc *sc = arg; 1025 struct ifnet *ifp = &sc->arpcom.ac_if; 1026 uint32_t status; 1027 1028 /* Supress unwanted interrupts */ 1029 if ((ifp->if_flags & IFF_UP) == 0) { 1030 lge_stop(sc); 1031 return; 1032 } 1033 1034 for (;;) { 1035 /* 1036 * Reading the ISR register clears all interrupts, and 1037 * clears the 'interrupts enabled' bit in the IMR 1038 * register. 1039 */ 1040 status = CSR_READ_4(sc, LGE_ISR); 1041 1042 if ((status & LGE_INTRS) == 0) 1043 break; 1044 1045 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1046 lge_txeof(sc); 1047 1048 if (status & LGE_ISR_RXDMA_DONE) 1049 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1050 1051 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1052 lge_rxeoc(sc); 1053 1054 if (status & LGE_ISR_PHY_INTR) { 1055 sc->lge_link = 0; 1056 callout_stop(&sc->lge_stat_timer); 1057 lge_tick_serialized(sc); 1058 } 1059 } 1060 1061 /* Re-enable interrupts. */ 1062 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1063 1064 if (!ifq_is_empty(&ifp->if_snd)) 1065 if_devstart(ifp); 1066 } 1067 1068 /* 1069 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1070 * pointers to the fragment pointers. 1071 */ 1072 static int 1073 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx) 1074 { 1075 struct lge_frag *f = NULL; 1076 struct lge_tx_desc *cur_tx; 1077 struct mbuf *m; 1078 int frag = 0, tot_len = 0; 1079 1080 /* 1081 * Start packing the mbufs in this chain into 1082 * the fragment pointers. Stop when we run out 1083 * of fragments or hit the end of the mbuf chain. 1084 */ 1085 m = m_head; 1086 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1087 frag = 0; 1088 1089 for (m = m_head; m != NULL; m = m->m_next) { 1090 if (m->m_len != 0) { 1091 if (frag == LGE_FRAG_CNT) 1092 break; 1093 1094 tot_len += m->m_len; 1095 f = &cur_tx->lge_frags[frag]; 1096 f->lge_fraglen = m->m_len; 1097 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1098 f->lge_fragptr_hi = 0; 1099 frag++; 1100 } 1101 } 1102 /* Caller should make sure that 'm_head' is not excessive fragmented */ 1103 KASSERT(m == NULL, ("too many fragments\n")); 1104 1105 cur_tx->lge_mbuf = m_head; 1106 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1107 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1108 1109 /* Queue for transmit */ 1110 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1111 1112 return(0); 1113 } 1114 1115 /* 1116 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1117 * to the mbuf data regions directly in the transmit lists. We also save a 1118 * copy of the pointers since the transmit list fragment pointers are 1119 * physical addresses. 1120 */ 1121 1122 static void 1123 lge_start(struct ifnet *ifp) 1124 { 1125 struct lge_softc *sc = ifp->if_softc; 1126 struct mbuf *m_head = NULL, *m_defragged; 1127 uint32_t idx; 1128 int need_timer; 1129 1130 if (!sc->lge_link) { 1131 ifq_purge(&ifp->if_snd); 1132 return; 1133 } 1134 1135 idx = sc->lge_cdata.lge_tx_prod; 1136 1137 if (ifp->if_flags & IFF_OACTIVE) 1138 return; 1139 1140 need_timer = 0; 1141 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1142 struct mbuf *m; 1143 int frags; 1144 1145 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) { 1146 ifp->if_flags |= IFF_OACTIVE; 1147 break; 1148 } 1149 1150 m_defragged = NULL; 1151 m_head = ifq_dequeue(&ifp->if_snd, NULL); 1152 if (m_head == NULL) 1153 break; 1154 1155 again: 1156 frags = 0; 1157 for (m = m_head; m != NULL; m = m->m_next) 1158 ++frags; 1159 if (frags > LGE_FRAG_CNT) { 1160 if (m_defragged != NULL) { 1161 /* 1162 * Even after defragmentation, there 1163 * are still too many fragments, so 1164 * drop this packet. 1165 */ 1166 m_freem(m_head); 1167 continue; 1168 } 1169 1170 m_defragged = m_defrag(m_head, MB_DONTWAIT); 1171 if (m_defragged == NULL) { 1172 m_freem(m_head); 1173 continue; 1174 } 1175 m_head = m_defragged; 1176 1177 /* Recount # of fragments */ 1178 goto again; 1179 } 1180 1181 lge_encap(sc, m_head, &idx); 1182 need_timer = 1; 1183 1184 BPF_MTAP(ifp, m_head); 1185 } 1186 1187 if (!need_timer) 1188 return; 1189 1190 sc->lge_cdata.lge_tx_prod = idx; 1191 1192 /* 1193 * Set a timeout in case the chip goes out to lunch. 1194 */ 1195 ifp->if_timer = 5; 1196 } 1197 1198 static void 1199 lge_init(void *xsc) 1200 { 1201 struct lge_softc *sc = xsc; 1202 struct ifnet *ifp = &sc->arpcom.ac_if; 1203 struct mii_data *mii; 1204 1205 if (ifp->if_flags & IFF_RUNNING) 1206 return; 1207 1208 /* 1209 * Cancel pending I/O and free all RX/TX buffers. 1210 */ 1211 lge_stop(sc); 1212 lge_reset(sc); 1213 1214 mii = device_get_softc(sc->lge_miibus); 1215 1216 /* Set MAC address */ 1217 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0])); 1218 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4])); 1219 1220 /* Init circular RX list. */ 1221 if (lge_list_rx_init(sc) == ENOBUFS) { 1222 kprintf("lge%d: initialization failed: no " 1223 "memory for rx buffers\n", sc->lge_unit); 1224 lge_stop(sc); 1225 return; 1226 } 1227 1228 /* 1229 * Init tx descriptors. 1230 */ 1231 lge_list_tx_init(sc); 1232 1233 /* Set initial value for MODE1 register. */ 1234 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST | 1235 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD | 1236 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 | 1237 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2); 1238 1239 /* If we want promiscuous mode, set the allframes bit. */ 1240 if (ifp->if_flags & IFF_PROMISC) { 1241 CSR_WRITE_4(sc, LGE_MODE1, 1242 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC); 1243 } else { 1244 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1245 } 1246 1247 /* 1248 * Set the capture broadcast bit to capture broadcast frames. 1249 */ 1250 if (ifp->if_flags & IFF_BROADCAST) { 1251 CSR_WRITE_4(sc, LGE_MODE1, 1252 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST); 1253 } else { 1254 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1255 } 1256 1257 /* Packet padding workaround? */ 1258 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1259 1260 /* No error frames */ 1261 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1262 1263 /* Receive large frames */ 1264 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS); 1265 1266 /* Workaround: disable RX/TX flow control */ 1267 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1269 1270 /* Make sure to strip CRC from received frames */ 1271 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1272 1273 /* Turn off magic packet mode */ 1274 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1275 1276 /* Turn off all VLAN stuff */ 1277 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX | 1278 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT); 1279 1280 /* Workarond: FIFO overflow */ 1281 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1282 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1283 1284 /* 1285 * Load the multicast filter. 1286 */ 1287 lge_setmulti(sc); 1288 1289 /* 1290 * Enable hardware checksum validation for all received IPv4 1291 * packets, do not reject packets with bad checksums. 1292 */ 1293 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM | 1294 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM | 1295 LGE_MODE2_RX_ERRCSUM); 1296 1297 /* 1298 * Enable the delivery of PHY interrupts based on 1299 * link/speed/duplex status chalges. 1300 */ 1301 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL); 1302 1303 /* Enable receiver and transmitter. */ 1304 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1305 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB); 1306 1307 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB); 1309 1310 /* 1311 * Enable interrupts. 1312 */ 1313 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 | 1314 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS); 1315 1316 lge_ifmedia_upd(ifp); 1317 1318 ifp->if_flags |= IFF_RUNNING; 1319 ifp->if_flags &= ~IFF_OACTIVE; 1320 1321 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc); 1322 } 1323 1324 /* 1325 * Set media options. 1326 */ 1327 static int 1328 lge_ifmedia_upd(struct ifnet *ifp) 1329 { 1330 struct lge_softc *sc = ifp->if_softc; 1331 struct mii_data *mii = device_get_softc(sc->lge_miibus); 1332 1333 sc->lge_link = 0; 1334 if (mii->mii_instance) { 1335 struct mii_softc *miisc; 1336 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1337 mii_phy_reset(miisc); 1338 } 1339 mii_mediachg(mii); 1340 1341 return(0); 1342 } 1343 1344 /* 1345 * Report current media status. 1346 */ 1347 static void 1348 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1349 { 1350 struct lge_softc *sc = ifp->if_softc; 1351 struct mii_data *mii; 1352 1353 mii = device_get_softc(sc->lge_miibus); 1354 mii_pollstat(mii); 1355 ifmr->ifm_active = mii->mii_media_active; 1356 ifmr->ifm_status = mii->mii_media_status; 1357 } 1358 1359 static int 1360 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 1361 { 1362 struct lge_softc *sc = ifp->if_softc; 1363 struct ifreq *ifr = (struct ifreq *) data; 1364 struct mii_data *mii; 1365 int error = 0; 1366 1367 switch(command) { 1368 case SIOCSIFMTU: 1369 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1370 error = EINVAL; 1371 else 1372 ifp->if_mtu = ifr->ifr_mtu; 1373 break; 1374 case SIOCSIFFLAGS: 1375 if (ifp->if_flags & IFF_UP) { 1376 if (ifp->if_flags & IFF_RUNNING && 1377 ifp->if_flags & IFF_PROMISC && 1378 !(sc->lge_if_flags & IFF_PROMISC)) { 1379 CSR_WRITE_4(sc, LGE_MODE1, 1380 LGE_MODE1_SETRST_CTL1| 1381 LGE_MODE1_RX_PROMISC); 1382 } else if (ifp->if_flags & IFF_RUNNING && 1383 !(ifp->if_flags & IFF_PROMISC) && 1384 sc->lge_if_flags & IFF_PROMISC) { 1385 CSR_WRITE_4(sc, LGE_MODE1, 1386 LGE_MODE1_RX_PROMISC); 1387 } else { 1388 ifp->if_flags &= ~IFF_RUNNING; 1389 lge_init(sc); 1390 } 1391 } else { 1392 if (ifp->if_flags & IFF_RUNNING) 1393 lge_stop(sc); 1394 } 1395 sc->lge_if_flags = ifp->if_flags; 1396 error = 0; 1397 break; 1398 case SIOCADDMULTI: 1399 case SIOCDELMULTI: 1400 lge_setmulti(sc); 1401 error = 0; 1402 break; 1403 case SIOCGIFMEDIA: 1404 case SIOCSIFMEDIA: 1405 mii = device_get_softc(sc->lge_miibus); 1406 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1407 break; 1408 default: 1409 error = ether_ioctl(ifp, command, data); 1410 break; 1411 } 1412 1413 return(error); 1414 } 1415 1416 static void 1417 lge_watchdog(struct ifnet *ifp) 1418 { 1419 struct lge_softc *sc = ifp->if_softc; 1420 1421 ifp->if_oerrors++; 1422 kprintf("lge%d: watchdog timeout\n", sc->lge_unit); 1423 1424 lge_stop(sc); 1425 lge_reset(sc); 1426 ifp->if_flags &= ~IFF_RUNNING; 1427 lge_init(sc); 1428 1429 if (!ifq_is_empty(&ifp->if_snd)) 1430 if_devstart(ifp); 1431 } 1432 1433 /* 1434 * Stop the adapter and free any mbufs allocated to the 1435 * RX and TX lists. 1436 */ 1437 static void 1438 lge_stop(struct lge_softc *sc) 1439 { 1440 struct ifnet *ifp = &sc->arpcom.ac_if; 1441 int i; 1442 1443 ifp->if_timer = 0; 1444 callout_stop(&sc->lge_stat_timer); 1445 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1446 1447 /* Disable receiver and transmitter. */ 1448 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1449 sc->lge_link = 0; 1450 1451 /* 1452 * Free data in the RX lists. 1453 */ 1454 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1455 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1456 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1457 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1458 } 1459 } 1460 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list)); 1461 1462 /* 1463 * Free the TX list buffers. 1464 */ 1465 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1466 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1467 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1468 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1469 } 1470 } 1471 1472 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list)); 1473 1474 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1475 } 1476 1477 /* 1478 * Stop all chip I/O so that the kernel's probe routines don't 1479 * get confused by errant DMAs when rebooting. 1480 */ 1481 static void 1482 lge_shutdown(device_t dev) 1483 { 1484 struct lge_softc *sc = device_get_softc(dev); 1485 1486 lge_reset(sc); 1487 lge_stop(sc); 1488 } 1489