1 /*- 2 * Copyright (c) 2001 Semen Ustimenko (semenu@FreeBSD.org) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: src/sys/dev/mii/acphyreg.h,v 1.1.2.1 2001/06/08 19:58:33 semenu Exp $ 27 * $DragonFly: src/sys/dev/netif/mii_layer/acphyreg.h,v 1.2 2003/06/17 04:28:28 dillon Exp $ 28 */ 29 30 #ifndef _DEV_MII_ACPHYREG_H_ 31 #define _DEV_MII_ACPHYREG_H_ 32 33 /* 34 * Register definitions for the Altima Communications AC101 35 */ 36 37 #define MII_ACPHY_POL 0x10 /* Polarity int level */ 38 39 /* High byte is interrupt mask register */ 40 #define MII_ACPHY_INT 0x11 /* Interrupt control/status */ 41 #define AC_INT_ACOMP 0x0001 /* Autoneg complete */ 42 #define AC_INT_REM_FLT 0x0002 /* Remote fault */ 43 #define AC_INT_LINK_DOWN 0x0004 /* Link not OK */ 44 #define AC_INT_LP_ACK 0x0008 /* FLP ack recved */ 45 #define AC_INT_PD_FLT 0x0010 /* Parallel detect fault */ 46 #define AC_INT_PAGE_RECV 0x0020 /* New page recved */ 47 #define AC_INT_RX_ER 0x0040 /* RX_ER transitions high */ 48 #define AC_INT_JAB 0x0080 /* Jabber detected */ 49 50 #define MII_ACPHY_DIAG 0x12 /* Diagnostic */ 51 #define AC_DIAG_RX_LOCK 0x0100 52 #define AC_DIAG_RX_PASS 0x0200 53 #define AC_DIAG_SPEED 0x0400 /* Aneg speed result */ 54 #define AC_DIAG_DUPLEX 0x0800 /* Aneg duplex result */ 55 56 #define MII_ACPHY_PWRLOOP 0x13 /* Power/Loopback */ 57 #define MII_ACPHY_CBLMEAS 0x14 /* Cable meas. */ 58 59 #define MII_ACPHY_MCTL 0x15 /* Mode control */ 60 #define AC_MCTL_FX_SEL 0x0001 /* FX mode */ 61 #define AC_MCTL_BYP_PCS 0x0001 /* Bypass PCS */ 62 #define AC_MCTL_SCRMBL 0x0004 /* Data scrambling */ 63 #define AC_MCTL_REM_LOOP 0x0008 /* Remote loopback */ 64 #define AC_MCTL_DIS_WDT 0x0010 /* Disable watchdog timer */ 65 #define AC_MCTL_DIS_REC 0x0020 /* Disable recv error counter */ 66 #define AC_MCTL_REC_FULL 0x0040 /* Recv error counter full */ 67 #define AC_MCTL_FRC_FEF 0x0080 /* Force Far End Fault Insert. */ 68 #define AC_MCTL_DIS_FEF 0x0100 /* Disable FEF Insertion */ 69 #define AC_MCTL_LED_SEL 0x0200 /* Compat LED config */ 70 #define AC_MCTL_ALED_SEL 0x0400 /* ActLED RX&TX - RX only */ 71 #define AC_MCTL_10BT_SEL 0x0800 /* Enable 7-wire interface */ 72 #define AC_MCTL_DIS_JAB 0x1000 /* Disable jabber */ 73 #define AC_MCTL_FRC_LINK 0x2000 /* Force TX link up */ 74 #define AC_MCTL_DIS_NLP 0x4000 /* Disable NLP check */ 75 76 #define MII_ACPHY_REC 0x18 /* Recv error counter */ 77 78 #endif /* _DEV_MII_ACPHYREG_H_ */ 79