1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Driver for the Attansic/Atheros F1 10/100/1000 PHY. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/socket.h> 38 #include <sys/bus.h> 39 40 #include <net/if.h> 41 #include <net/if_media.h> 42 43 #include <dev/netif/mii_layer/mii.h> 44 #include <dev/netif/mii_layer/miivar.h> 45 #include <dev/netif/mii_layer/atphyreg.h> 46 47 #include "miibus_if.h" 48 #include "miidevs.h" 49 50 static int atphy_probe(device_t); 51 static int atphy_attach(device_t); 52 static int atphy_service(struct mii_softc *, struct mii_data *, int); 53 static void atphy_status(struct mii_softc *); 54 static void atphy_reset(struct mii_softc *); 55 static uint16_t atphy_anar(struct ifmedia_entry *); 56 static int atphy_setmedia(struct mii_softc *sc, int media); 57 58 static device_method_t atphy_methods[] = { 59 /* Device interface. */ 60 DEVMETHOD(device_probe, atphy_probe), 61 DEVMETHOD(device_attach, atphy_attach), 62 DEVMETHOD(device_detach, ukphy_detach), 63 DEVMETHOD(device_shutdown, bus_generic_shutdown), 64 DEVMETHOD_END 65 }; 66 67 static devclass_t atphy_devclass; 68 static driver_t atphy_driver = { 69 "atphy", 70 atphy_methods, 71 sizeof(struct mii_softc) 72 }; 73 74 DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, NULL, NULL); 75 76 static const struct mii_phydesc atphys[] = { 77 #if 0 78 MII_PHYDESC(xxATHEROS, F1), 79 MII_PHYDESC(xxATHEROS, F1_7), 80 MII_PHYDESC(xxATHEROS, AR8021), 81 MII_PHYDESC(xxATHEROS, F2), 82 #endif 83 MII_PHYDESC(ATHEROS, F1), 84 MII_PHYDESC(ATHEROS, F1_7), 85 MII_PHYDESC(ATHEROS, F2), 86 MII_PHYDESC_NULL 87 }; 88 89 #if 0 90 static const struct mii_phy_funcs atphy_funcs = { 91 atphy_service, 92 atphy_status, 93 atphy_reset 94 }; 95 #endif 96 97 static int 98 atphy_probe(device_t dev) 99 { 100 /*return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT));*/ 101 struct mii_attach_args *ma = device_get_ivars(dev); 102 const struct mii_phydesc *mpd; 103 104 mpd = mii_phy_match(ma, atphys); 105 if (mpd != NULL) { 106 device_set_desc(dev, mpd->mpd_name); 107 return 0; 108 } 109 return ENXIO; 110 } 111 112 static int 113 atphy_attach(device_t dev) 114 { 115 /*mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &atphy_funcs, 1);*/ 116 117 struct mii_softc *sc; 118 struct mii_attach_args *ma; 119 struct mii_data *mii; 120 121 sc = device_get_softc(dev); 122 ma = device_get_ivars(dev); 123 124 mii_softc_init(sc, ma); 125 sc->mii_dev = device_get_parent(dev); 126 mii = device_get_softc(sc->mii_dev); 127 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 128 129 sc->mii_inst = mii->mii_instance; 130 sc->mii_service = atphy_service; 131 sc->mii_pdata = mii; 132 sc->mii_anegticks = MII_ANEGTICKS_GIGE; 133 134 mii->mii_instance++; 135 136 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 137 if (sc->mii_capabilities & BMSR_EXTSTAT) 138 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 139 140 device_printf(dev, " "); 141 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 142 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 143 kprintf("no media present"); 144 else 145 mii_phy_add_media(sc); 146 kprintf("\n"); 147 148 atphy_reset(sc); 149 150 MIIBUS_MEDIAINIT(sc->mii_dev); 151 return (0); 152 } 153 154 static int 155 atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 156 { 157 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 158 uint16_t anar, bmcr, bmsr; 159 160 switch (cmd) { 161 case MII_POLLSTAT: 162 break; 163 164 case MII_MEDIACHG: 165 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO || 166 IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 167 atphy_setmedia(sc, ife->ifm_media); 168 break; 169 } 170 171 bmcr = 0; 172 switch (IFM_SUBTYPE(ife->ifm_media)) { 173 case IFM_100_TX: 174 bmcr = BMCR_S100; 175 break; 176 case IFM_10_T: 177 bmcr = BMCR_S10; 178 break; 179 case IFM_NONE: 180 bmcr = PHY_READ(sc, MII_BMCR); 181 /* 182 * XXX 183 * Due to an unknown reason powering down PHY resulted 184 * in unexpected results such as inaccessibility of 185 * hardware of freshly rebooted system. Disable 186 * powering down PHY until I got more information for 187 * Attansic/Atheros PHY hardwares. 188 */ 189 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO); 190 goto done; 191 default: 192 return (EINVAL); 193 } 194 195 anar = atphy_anar(ife); 196 if ((ife->ifm_media & IFM_FDX) != 0) { 197 bmcr |= BMCR_FDX; 198 #if defined(__FreeBSD__) 199 if ((ife->ifm_media & IFM_FLOW) != 0 || 200 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 201 anar |= ANAR_PAUSE_TOWARDS; 202 #else 203 if ((ife->ifm_media & IFM_FLOW) != 0) 204 anar |= ANAR_PAUSE_TOWARDS; 205 #endif 206 } 207 208 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | 209 EXTSR_1000THDX)) != 0) 210 PHY_WRITE(sc, MII_100T2CR, 0); 211 PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA); 212 213 /* 214 * Reset the PHY so all changes take effect. 215 */ 216 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN | 217 BMCR_STARTNEG); 218 done: 219 break; 220 221 case MII_TICK: 222 /* 223 * Only used for autonegotiation. 224 */ 225 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 226 sc->mii_ticks = 0; 227 break; 228 } 229 230 /* 231 * Check for link. 232 * Read the status register twice; BMSR_LINK is latch-low. 233 */ 234 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 235 if (bmsr & BMSR_LINK) { 236 sc->mii_ticks = 0; 237 break; 238 } 239 240 /* Announce link loss right after it happens. */ 241 if (sc->mii_ticks++ == 0) 242 break; 243 if (sc->mii_ticks <= sc->mii_anegticks) 244 return (0); 245 246 sc->mii_ticks = 0; 247 atphy_setmedia(sc, ife->ifm_media); 248 break; 249 } 250 251 /* Update the media status. */ 252 atphy_status(sc); 253 254 /* Callback if something changed. */ 255 mii_phy_update(sc, cmd); 256 return (0); 257 } 258 259 static void 260 atphy_status(struct mii_softc *sc) 261 { 262 struct mii_data *mii = sc->mii_pdata; 263 uint32_t bmsr, bmcr, ssr; 264 265 mii->mii_media_status = IFM_AVALID; 266 mii->mii_media_active = IFM_ETHER; 267 268 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 269 if ((bmsr & BMSR_LINK) != 0) 270 mii->mii_media_status |= IFM_ACTIVE; 271 272 bmcr = PHY_READ(sc, MII_BMCR); 273 if ((bmcr & BMCR_ISO) != 0) { 274 mii->mii_media_active |= IFM_NONE; 275 mii->mii_media_status = 0; 276 return; 277 } 278 279 if ((bmcr & BMCR_LOOP) != 0) 280 mii->mii_media_active |= IFM_LOOP; 281 282 ssr = PHY_READ(sc, ATPHY_SSR); 283 if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) { 284 /* Erg, still trying, I guess... */ 285 mii->mii_media_active |= IFM_NONE; 286 return; 287 } 288 289 switch (ssr & ATPHY_SSR_SPEED_MASK) { 290 case ATPHY_SSR_1000MBS: 291 mii->mii_media_active |= IFM_1000_T; 292 /* 293 * atphy(4) has a valid link so reset mii_ticks. 294 * Resetting mii_ticks is needed in order to 295 * detect link loss after auto-negotiation. 296 */ 297 sc->mii_ticks = 0; 298 break; 299 case ATPHY_SSR_100MBS: 300 mii->mii_media_active |= IFM_100_TX; 301 sc->mii_ticks = 0; 302 break; 303 case ATPHY_SSR_10MBS: 304 mii->mii_media_active |= IFM_10_T; 305 sc->mii_ticks = 0; 306 break; 307 default: 308 mii->mii_media_active |= IFM_NONE; 309 return; 310 } 311 312 if ((ssr & ATPHY_SSR_DUPLEX) != 0) 313 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 314 else 315 mii->mii_media_active |= IFM_HDX; 316 317 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 318 (PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0) 319 mii->mii_media_active |= IFM_ETH_MASTER; 320 } 321 322 static void 323 atphy_reset(struct mii_softc *sc) 324 { 325 struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur; 326 uint32_t reg; 327 int i; 328 329 /* Take PHY out of power down mode. */ 330 PHY_WRITE(sc, 29, 0x29); 331 PHY_WRITE(sc, 30, 0); 332 333 reg = PHY_READ(sc, ATPHY_SCR); 334 /* Enable automatic crossover. */ 335 reg |= ATPHY_SCR_AUTO_X_MODE; 336 /* Disable power down. */ 337 reg &= ~ATPHY_SCR_MAC_PDOWN; 338 /* Enable CRS on Tx. */ 339 reg |= ATPHY_SCR_ASSERT_CRS_ON_TX; 340 /* Auto correction for reversed cable polarity. */ 341 reg |= ATPHY_SCR_POLARITY_REVERSAL; 342 PHY_WRITE(sc, ATPHY_SCR, reg); 343 344 /* Workaround F1 bug to reset phy. */ 345 atphy_setmedia(sc, ife == NULL ? IFM_AUTO : ife->ifm_media); 346 347 for (i = 0; i < 1000; i++) { 348 DELAY(1); 349 if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0) 350 break; 351 } 352 } 353 354 static uint16_t 355 atphy_anar(struct ifmedia_entry *ife) 356 { 357 uint16_t anar; 358 359 anar = 0; 360 switch (IFM_SUBTYPE(ife->ifm_media)) { 361 case IFM_AUTO: 362 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 363 return (anar); 364 case IFM_1000_T: 365 return (anar); 366 case IFM_100_TX: 367 anar |= ANAR_TX; 368 break; 369 case IFM_10_T: 370 anar |= ANAR_10; 371 break; 372 default: 373 return (0); 374 } 375 376 if ((ife->ifm_media & IFM_FDX) != 0) { 377 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 378 anar |= ANAR_TX_FD; 379 else 380 anar |= ANAR_10_FD; 381 } 382 383 return (anar); 384 } 385 386 static int 387 atphy_setmedia(struct mii_softc *sc, int media) 388 { 389 uint16_t anar; 390 391 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 392 #if defined(__FreeBSD__) 393 if ((IFM_SUBTYPE(media) == IFM_AUTO || (media & IFM_FDX) != 0) && 394 ((media & IFM_FLOW) != 0 || 395 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)) 396 anar |= ANAR_PAUSE_TOWARDS; 397 #else 398 if ((IFM_SUBTYPE(media) == IFM_AUTO || (media & IFM_FDX) != 0) && 399 ((media & IFM_FLOW) != 0)) 400 anar |= ANAR_PAUSE_TOWARDS; 401 #endif 402 PHY_WRITE(sc, MII_ANAR, anar); 403 if ((sc->mii_extcapabilities & 404 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 405 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX | 406 GTCR_ADV_1000THDX); 407 else if (sc->mii_model == MII_MODEL_ATHEROS_F1) { 408 /* 409 * AR8132 has 10/100 PHY and the PHY uses the same 410 * model number of F1 gigabit PHY. The PHY has no 411 * ability to establish gigabit link so explicitly 412 * disable 1000baseT configuration for the PHY. 413 * Otherwise, there is a case that atphy(4) could 414 * not establish a link against gigabit link partner 415 * unless the link partner supports down-shifting. 416 */ 417 PHY_WRITE(sc, MII_100T2CR, 0); 418 } 419 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 420 421 return (EJUSTRETURN); 422 } 423