1 /* 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $ 33 * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.5 2004/09/18 19:32:59 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $ 36 */ 37 38 /* 39 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 40 * 1000mbps; all we need to negotiate here is full or half duplex. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/bus.h> 48 49 #include <machine/bus.h> 50 #include <machine/clock.h> 51 52 #include <net/if.h> 53 #include <net/if_media.h> 54 #include <net/if_arp.h> 55 56 #include "mii.h" 57 #include "miivar.h" 58 #include "miidevs.h" 59 60 #include "brgphyreg.h" 61 #include <dev/netif/bge/if_bgereg.h> 62 63 #include "miibus_if.h" 64 65 static int brgphy_probe(device_t); 66 static int brgphy_attach(device_t); 67 static int brgphy_detach(device_t); 68 69 static device_method_t brgphy_methods[] = { 70 /* device interface */ 71 DEVMETHOD(device_probe, brgphy_probe), 72 DEVMETHOD(device_attach, brgphy_attach), 73 DEVMETHOD(device_detach, brgphy_detach), 74 DEVMETHOD(device_shutdown, bus_generic_shutdown), 75 { 0, 0 } 76 }; 77 78 static devclass_t brgphy_devclass; 79 80 static driver_t brgphy_driver = { 81 "brgphy", 82 brgphy_methods, 83 sizeof(struct mii_softc) 84 }; 85 86 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 87 88 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 89 static void brgphy_status(struct mii_softc *); 90 static int brgphy_mii_phy_auto(struct mii_softc *); 91 static void brgphy_reset(struct mii_softc *); 92 static void brgphy_loop(struct mii_softc *); 93 static void bcm5401_load_dspcode(struct mii_softc *); 94 static void bcm5411_load_dspcode(struct mii_softc *); 95 static void bcm5703_load_dspcode(struct mii_softc *); 96 static int brgphy_mii_model; 97 98 static int brgphy_probe(dev) 99 device_t dev; 100 { 101 struct mii_attach_args *ma; 102 103 ma = device_get_ivars(dev); 104 105 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 106 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 107 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 108 return(0); 109 } 110 111 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 112 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 113 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 114 return(0); 115 } 116 117 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 118 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 119 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 120 return(0); 121 } 122 123 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 124 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 125 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 126 return(0); 127 } 128 129 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 130 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 131 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 132 return(0); 133 } 134 135 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 136 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 137 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 138 return(0); 139 } 140 141 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 142 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5705) { 143 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5705); 144 return(0); 145 } 146 147 return(ENXIO); 148 } 149 150 static int 151 brgphy_attach(dev) 152 device_t dev; 153 { 154 struct mii_softc *sc; 155 struct mii_attach_args *ma; 156 struct mii_data *mii; 157 const char *sep = ""; 158 159 sc = device_get_softc(dev); 160 ma = device_get_ivars(dev); 161 mii_softc_init(sc); 162 sc->mii_dev = device_get_parent(dev); 163 mii = device_get_softc(sc->mii_dev); 164 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 165 166 sc->mii_inst = mii->mii_instance; 167 sc->mii_phy = ma->mii_phyno; 168 sc->mii_service = brgphy_service; 169 sc->mii_pdata = mii; 170 171 sc->mii_flags |= MIIF_NOISOLATE; 172 mii->mii_instance++; 173 174 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 175 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 176 177 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 178 BMCR_ISO); 179 #if 0 180 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 181 BMCR_LOOP|BMCR_S100); 182 #endif 183 184 brgphy_mii_model = MII_MODEL(ma->mii_id2); 185 brgphy_reset(sc); 186 187 sc->mii_capabilities = 188 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 189 device_printf(dev, " "); 190 if (sc->mii_capabilities & BMSR_MEDIAMASK) 191 mii_add_media(mii, (sc->mii_capabilities & ~BMSR_ANEG), 192 sc->mii_inst); 193 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, 0, sc->mii_inst), 194 BRGPHY_BMCR_FDX); 195 PRINT(", 1000baseTX"); 196 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, IFM_FDX, sc->mii_inst), 0); 197 PRINT("1000baseTX-FDX"); 198 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 199 PRINT("auto"); 200 201 printf("\n"); 202 #undef ADD 203 #undef PRINT 204 205 MIIBUS_MEDIAINIT(sc->mii_dev); 206 return(0); 207 } 208 209 static int 210 brgphy_detach(dev) 211 device_t dev; 212 { 213 struct mii_softc *sc; 214 struct mii_data *mii; 215 216 sc = device_get_softc(dev); 217 mii = device_get_softc(device_get_parent(dev)); 218 sc->mii_dev = NULL; 219 LIST_REMOVE(sc, mii_list); 220 221 return(0); 222 } 223 224 static int 225 brgphy_service(sc, mii, cmd) 226 struct mii_softc *sc; 227 struct mii_data *mii; 228 int cmd; 229 { 230 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 231 int reg, speed, gig; 232 233 switch (cmd) { 234 case MII_POLLSTAT: 235 /* 236 * If we're not polling our PHY instance, just return. 237 */ 238 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 239 return (0); 240 break; 241 242 case MII_MEDIACHG: 243 /* 244 * If the media indicates a different PHY instance, 245 * isolate ourselves. 246 */ 247 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 248 reg = PHY_READ(sc, MII_BMCR); 249 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 250 return (0); 251 } 252 253 /* 254 * If the interface is not up, don't do anything. 255 */ 256 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 257 break; 258 259 brgphy_reset(sc); /* XXX hardware bug work-around */ 260 261 switch (IFM_SUBTYPE(ife->ifm_media)) { 262 case IFM_AUTO: 263 #ifdef foo 264 /* 265 * If we're already in auto mode, just return. 266 */ 267 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 268 return (0); 269 #endif 270 (void) brgphy_mii_phy_auto(sc); 271 break; 272 case IFM_1000_TX: 273 speed = BRGPHY_S1000; 274 goto setit; 275 case IFM_100_TX: 276 speed = BRGPHY_S100; 277 goto setit; 278 case IFM_10_T: 279 speed = BRGPHY_S10; 280 setit: 281 brgphy_loop(sc); 282 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 283 speed |= BRGPHY_BMCR_FDX; 284 gig = BRGPHY_1000CTL_AFD; 285 } else { 286 gig = BRGPHY_1000CTL_AHD; 287 } 288 289 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 290 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 291 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 292 293 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_TX) 294 break; 295 296 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 297 PHY_WRITE(sc, BRGPHY_MII_BMCR, 298 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 299 300 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 301 break; 302 303 /* 304 * When settning the link manually, one side must 305 * be the master and the other the slave. However 306 * ifmedia doesn't give us a good way to specify 307 * this, so we fake it by using one of the LINK 308 * flags. If LINK0 is set, we program the PHY to 309 * be a master, otherwise it's a slave. 310 */ 311 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 312 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 313 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 314 } else { 315 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 316 gig|BRGPHY_1000CTL_MSE); 317 } 318 break; 319 #ifdef foo 320 case IFM_NONE: 321 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 322 break; 323 #endif 324 case IFM_100_T4: 325 default: 326 return (EINVAL); 327 } 328 break; 329 330 case MII_TICK: 331 /* 332 * If we're not currently selected, just return. 333 */ 334 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 335 return (0); 336 337 /* 338 * Only used for autonegotiation. 339 */ 340 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 341 return (0); 342 343 /* 344 * Is the interface even up? 345 */ 346 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 347 return (0); 348 349 /* 350 * Check to see if we have link. If we do, we don't 351 * need to restart the autonegotiation process. Read 352 * the BMSR twice in case it's latched. 353 */ 354 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 355 if (reg & BRGPHY_AUXSTS_LINK) 356 break; 357 358 /* 359 * Only retry autonegotiation every 5 seconds. 360 */ 361 if (++sc->mii_ticks != 5) 362 return (0); 363 364 sc->mii_ticks = 0; 365 brgphy_mii_phy_auto(sc); 366 return (0); 367 } 368 369 /* Update the media status. */ 370 brgphy_status(sc); 371 372 /* 373 * Callback if something changed. Note that we need to poke 374 * the DSP on the Broadcom PHYs if the media changes. 375 */ 376 if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 377 MIIBUS_STATCHG(sc->mii_dev); 378 sc->mii_active = mii->mii_media_active; 379 switch (brgphy_mii_model) { 380 case MII_MODEL_xxBROADCOM_BCM5401: 381 bcm5401_load_dspcode(sc); 382 break; 383 case MII_MODEL_xxBROADCOM_BCM5411: 384 bcm5411_load_dspcode(sc); 385 break; 386 } 387 } 388 return (0); 389 } 390 391 void 392 brgphy_status(sc) 393 struct mii_softc *sc; 394 { 395 struct mii_data *mii = sc->mii_pdata; 396 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 397 int bmsr, bmcr; 398 399 mii->mii_media_status = IFM_AVALID; 400 mii->mii_media_active = IFM_ETHER; 401 402 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 403 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 404 mii->mii_media_status |= IFM_ACTIVE; 405 406 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 407 408 if (bmcr & BRGPHY_BMCR_LOOP) 409 mii->mii_media_active |= IFM_LOOP; 410 411 if (bmcr & BRGPHY_BMCR_AUTOEN) { 412 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 413 /* Erg, still trying, I guess... */ 414 mii->mii_media_active |= IFM_NONE; 415 return; 416 } 417 418 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 419 BRGPHY_AUXSTS_AN_RES) { 420 case BRGPHY_RES_1000FD: 421 mii->mii_media_active |= IFM_1000_TX | IFM_FDX; 422 break; 423 case BRGPHY_RES_1000HD: 424 mii->mii_media_active |= IFM_1000_TX | IFM_HDX; 425 break; 426 case BRGPHY_RES_100FD: 427 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 428 break; 429 case BRGPHY_RES_100T4: 430 mii->mii_media_active |= IFM_100_T4; 431 break; 432 case BRGPHY_RES_100HD: 433 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 434 break; 435 case BRGPHY_RES_10FD: 436 mii->mii_media_active |= IFM_10_T | IFM_FDX; 437 break; 438 case BRGPHY_RES_10HD: 439 mii->mii_media_active |= IFM_10_T | IFM_HDX; 440 break; 441 default: 442 mii->mii_media_active |= IFM_NONE; 443 break; 444 } 445 return; 446 } 447 448 mii->mii_media_active = ife->ifm_media; 449 450 return; 451 } 452 453 454 static int 455 brgphy_mii_phy_auto(mii) 456 struct mii_softc *mii; 457 { 458 int ktcr = 0; 459 460 brgphy_loop(mii); 461 brgphy_reset(mii); 462 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 463 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 464 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 465 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 466 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 467 DELAY(1000); 468 PHY_WRITE(mii, BRGPHY_MII_ANAR, 469 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 470 DELAY(1000); 471 PHY_WRITE(mii, BRGPHY_MII_BMCR, 472 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 473 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 474 return (EJUSTRETURN); 475 } 476 477 static void 478 brgphy_loop(struct mii_softc *sc) 479 { 480 u_int32_t bmsr; 481 int i; 482 483 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 484 for (i = 0; i < 15000; i++) { 485 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 486 if (!(bmsr & BRGPHY_BMSR_LINK)) { 487 #if 0 488 device_printf(sc->mii_dev, "looped %d\n", i); 489 #endif 490 break; 491 } 492 DELAY(10); 493 } 494 } 495 496 /* Turn off tap power management on 5401. */ 497 static void 498 bcm5401_load_dspcode(struct mii_softc *sc) 499 { 500 static const struct { 501 int reg; 502 uint16_t val; 503 } dspcode[] = { 504 { BRGPHY_MII_AUXCTL, 0x0c20 }, 505 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 506 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 507 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 508 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 509 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 510 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 511 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 512 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 513 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 514 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 515 { 0, 0 }, 516 }; 517 int i; 518 519 for (i = 0; dspcode[i].reg != 0; i++) 520 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 521 DELAY(40); 522 } 523 524 static void 525 bcm5411_load_dspcode(struct mii_softc *sc) 526 { 527 static const struct { 528 int reg; 529 uint16_t val; 530 } dspcode[] = { 531 { 0x1c, 0x8c23 }, 532 { 0x1c, 0x8ca3 }, 533 { 0x1c, 0x8c23 }, 534 { 0, 0 }, 535 }; 536 int i; 537 538 for (i = 0; dspcode[i].reg != 0; i++) 539 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 540 } 541 542 static void 543 bcm5703_load_dspcode(struct mii_softc *sc) 544 { 545 static const struct { 546 int reg; 547 uint16_t val; 548 } dspcode[] = { 549 { BRGPHY_MII_AUXCTL, 0x0c00 }, 550 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 551 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 552 { 0, 0 }, 553 }; 554 int i; 555 556 for (i = 0; dspcode[i].reg != 0; i++) 557 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 558 } 559 560 static void 561 bcm5704_load_dspcode(struct mii_softc *sc) 562 { 563 static const struct { 564 int reg; 565 u_int16_t val; 566 } dspcode[] = { 567 { 0x1c, 0x8d68 }, 568 { 0x1c, 0x8d68 }, 569 { 0, 0 }, 570 }; 571 int i; 572 573 for (i = 0; dspcode[i].reg != 0; i++) 574 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 575 } 576 577 static void 578 brgphy_reset(struct mii_softc *sc) 579 { 580 u_int32_t val; 581 struct ifnet *ifp; 582 struct bge_softc *bge_sc; 583 584 mii_phy_reset(sc); 585 586 switch (brgphy_mii_model) { 587 case MII_MODEL_xxBROADCOM_BCM5401: 588 bcm5401_load_dspcode(sc); 589 break; 590 case MII_MODEL_xxBROADCOM_BCM5411: 591 bcm5411_load_dspcode(sc); 592 break; 593 case MII_MODEL_xxBROADCOM_BCM5703: 594 bcm5703_load_dspcode(sc); 595 break; 596 case MII_MODEL_xxBROADCOM_BCM5704: 597 bcm5704_load_dspcode(sc); 598 break; 599 } 600 601 ifp = sc->mii_pdata->mii_ifp; 602 bge_sc = ifp->if_softc; 603 604 /* 605 * Don't enable Ethernet@WireSpeed for the 5700 or the 606 * 5705 A1 and A2 chips. Make sure we only do this test 607 * on "bge" NICs, since other drivers may use this same 608 * PHY subdriver. 609 */ 610 if (strcmp(ifp->if_dname, "bge") == 0 && 611 (bge_sc->bge_asicrev == BGE_ASICREV_BCM5700 || 612 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 || 613 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2)) 614 return; 615 616 /* Enable Ethernet@WireSpeed. */ 617 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 618 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 619 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4)); 620 621 /* Enable Link LED on Dell boxes */ 622 if (bge_sc->bge_no_3_led) { 623 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 624 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 625 & ~BRGPHY_PHY_EXTCTL_3_LED); 626 } 627 } 628