1 /* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2000 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $ 35 */ 36 37 /* 38 * Driver for the Broadcom BCR5400 1000baseT PHY. Speed is always 39 * 1000mbps; all we need to negotiate here is full or half duplex. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 #include <sys/sysctl.h> 48 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_media.h> 52 #include <net/if_arp.h> 53 54 #include "mii.h" 55 #include "miivar.h" 56 #include "miidevs.h" 57 58 #include "brgphyreg.h" 59 #include <dev/netif/bge/if_bgereg.h> 60 #include <dev/netif/bce/if_bcereg.h> 61 62 #include "miibus_if.h" 63 64 static int brgphy_probe(device_t); 65 static int brgphy_attach(device_t); 66 67 static const struct mii_phydesc brgphys[] = { 68 MII_PHYDESC(xxBROADCOM, BCM5400), 69 MII_PHYDESC(xxBROADCOM, BCM5401), 70 MII_PHYDESC(xxBROADCOM, BCM5411), 71 MII_PHYDESC(xxBROADCOM, BCM5421), 72 MII_PHYDESC(xxBROADCOM, BCM54K2), 73 MII_PHYDESC(xxBROADCOM, BCM5461), 74 MII_PHYDESC(xxBROADCOM, BCM5462), 75 MII_PHYDESC(xxBROADCOM, BCM5464), 76 77 MII_PHYDESC(xxBROADCOM, BCM5701), 78 MII_PHYDESC(xxBROADCOM, BCM5703), 79 MII_PHYDESC(xxBROADCOM, BCM5704), 80 MII_PHYDESC(xxBROADCOM, BCM5705), 81 MII_PHYDESC(xxBROADCOM, BCM5714), 82 MII_PHYDESC(xxBROADCOM, BCM5750), 83 MII_PHYDESC(xxBROADCOM, BCM5752), 84 MII_PHYDESC(xxBROADCOM, BCM5780), 85 86 MII_PHYDESC(xxBROADCOM2,BCM54XX), 87 MII_PHYDESC(xxBROADCOM2,BCM5481), 88 MII_PHYDESC(xxBROADCOM2,BCM5482), 89 MII_PHYDESC(xxBROADCOM2,BCM5722), 90 MII_PHYDESC(xxBROADCOM2,BCM5755), 91 MII_PHYDESC(xxBROADCOM2,BCM5761), 92 MII_PHYDESC(xxBROADCOM2,BCM5784), 93 MII_PHYDESC(xxBROADCOM2,BCM5787), 94 95 MII_PHYDESC(xxBROADCOM, BCM5706C), 96 MII_PHYDESC(xxBROADCOM, BCM5708C), 97 MII_PHYDESC(xxBROADCOM2, BCM5709CAX), 98 MII_PHYDESC(xxBROADCOM2, BCM5709C), 99 100 MII_PHYDESC(xxBROADCOM3, BCM5717C), 101 MII_PHYDESC(xxBROADCOM3, BCM5719C), 102 MII_PHYDESC(xxBROADCOM3, BCM57765), 103 MII_PHYDESC(xxBROADCOM3, BCM57780), 104 105 MII_PHYDESC(BROADCOM2, BCM5906), 106 107 MII_PHYDESC_NULL 108 }; 109 110 static device_method_t brgphy_methods[] = { 111 /* device interface */ 112 DEVMETHOD(device_probe, brgphy_probe), 113 DEVMETHOD(device_attach, brgphy_attach), 114 DEVMETHOD(device_detach, ukphy_detach), 115 DEVMETHOD(device_shutdown, bus_generic_shutdown), 116 { 0, 0 } 117 }; 118 119 static devclass_t brgphy_devclass; 120 121 static driver_t brgphy_driver = { 122 "brgphy", 123 brgphy_methods, 124 sizeof(struct mii_softc) 125 }; 126 127 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, NULL, NULL); 128 129 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 130 static void brgphy_status(struct mii_softc *); 131 static void brgphy_mii_phy_auto(struct mii_softc *); 132 static void brgphy_reset(struct mii_softc *); 133 static void brgphy_loop(struct mii_softc *); 134 135 static void brgphy_bcm5401_dspcode(struct mii_softc *); 136 static void brgphy_bcm5411_dspcode(struct mii_softc *); 137 static void brgphy_bcm5421_dspcode(struct mii_softc *); 138 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 139 140 static void brgphy_adc_bug(struct mii_softc *); 141 static void brgphy_5704_a0_bug(struct mii_softc *); 142 static void brgphy_ber_bug(struct mii_softc *); 143 static void brgphy_crc_bug(struct mii_softc *); 144 145 static void brgphy_disable_early_dac(struct mii_softc *); 146 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 147 static void brgphy_eth_wirespeed(struct mii_softc *); 148 149 static int 150 brgphy_probe(device_t dev) 151 { 152 struct mii_attach_args *ma = device_get_ivars(dev); 153 const struct mii_phydesc *mpd; 154 155 mpd = mii_phy_match(ma, brgphys); 156 if (mpd != NULL) { 157 device_set_desc(dev, mpd->mpd_name); 158 return (0); 159 } 160 return(ENXIO); 161 } 162 163 static int 164 brgphy_attach(device_t dev) 165 { 166 struct mii_softc *sc; 167 struct mii_attach_args *ma; 168 struct mii_data *mii; 169 170 sc = device_get_softc(dev); 171 ma = device_get_ivars(dev); 172 mii_softc_init(sc, ma); 173 sc->mii_dev = device_get_parent(dev); 174 mii = device_get_softc(sc->mii_dev); 175 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 176 177 sc->mii_inst = mii->mii_instance; 178 sc->mii_service = brgphy_service; 179 sc->mii_reset = brgphy_reset; 180 sc->mii_pdata = mii; 181 182 sc->mii_flags |= MIIF_NOISOLATE; 183 mii->mii_instance++; 184 185 brgphy_reset(sc); 186 187 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 188 189 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 190 MII_MEDIA_NONE); 191 #if 0 192 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 193 MII_MEDIA_100_TX); 194 #endif 195 196 #undef ADD 197 198 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 199 if (sc->mii_capabilities & BMSR_EXTSTAT) 200 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 201 202 device_printf(dev, " "); 203 if ((sc->mii_capabilities & BMSR_MEDIAMASK) || 204 (sc->mii_extcapabilities & EXTSR_MEDIAMASK)) 205 mii_phy_add_media(sc); 206 else 207 kprintf("no media present"); 208 kprintf("\n"); 209 210 MIIBUS_MEDIAINIT(sc->mii_dev); 211 return(0); 212 } 213 214 static int 215 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 216 { 217 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 218 int reg, speed, gig; 219 220 switch (cmd) { 221 case MII_POLLSTAT: 222 /* 223 * If we're not polling our PHY instance, just return. 224 */ 225 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 226 return (0); 227 break; 228 229 case MII_MEDIACHG: 230 /* 231 * If the media indicates a different PHY instance, 232 * isolate ourselves. 233 */ 234 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 235 reg = PHY_READ(sc, MII_BMCR); 236 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 237 return (0); 238 } 239 240 /* 241 * If the interface is not up, don't do anything. 242 */ 243 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 244 break; 245 246 brgphy_reset(sc); /* XXX hardware bug work-around */ 247 248 switch (IFM_SUBTYPE(ife->ifm_media)) { 249 case IFM_AUTO: 250 #ifdef foo 251 /* 252 * If we're already in auto mode, just return. 253 */ 254 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 255 return (0); 256 #endif 257 brgphy_mii_phy_auto(sc); 258 break; 259 case IFM_1000_T: 260 speed = BRGPHY_S1000; 261 goto setit; 262 case IFM_100_TX: 263 speed = BRGPHY_S100; 264 goto setit; 265 case IFM_10_T: 266 speed = BRGPHY_S10; 267 setit: 268 brgphy_loop(sc); 269 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 270 speed |= BRGPHY_BMCR_FDX; 271 gig = BRGPHY_1000CTL_AFD; 272 } else { 273 gig = BRGPHY_1000CTL_AHD; 274 } 275 276 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 277 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 278 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 279 280 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 281 break; 282 283 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 284 PHY_WRITE(sc, BRGPHY_MII_BMCR, 285 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 286 287 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 288 break; 289 290 /* 291 * When settning the link manually, one side must 292 * be the master and the other the slave. However 293 * ifmedia doesn't give us a good way to specify 294 * this, so we fake it by using one of the LINK 295 * flags. If LINK0 is set, we program the PHY to 296 * be a master, otherwise it's a slave. 297 */ 298 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 299 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 300 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 301 } else { 302 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 303 gig|BRGPHY_1000CTL_MSE); 304 } 305 break; 306 #ifdef foo 307 case IFM_NONE: 308 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 309 break; 310 #endif 311 case IFM_100_T4: 312 default: 313 return (EINVAL); 314 } 315 break; 316 317 case MII_TICK: 318 /* 319 * If we're not currently selected, just return. 320 */ 321 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 322 return (0); 323 324 /* 325 * Is the interface even up? 326 */ 327 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 328 return (0); 329 330 /* 331 * Only used for autonegotiation. 332 */ 333 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 334 break; 335 336 /* 337 * Check to see if we have link. If we do, we don't 338 * need to restart the autonegotiation process. Read 339 * the BMSR twice in case it's latched. 340 */ 341 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 342 if (reg & BMSR_LINK) { 343 sc->mii_ticks = 0; 344 break; 345 } 346 347 /* 348 * Only retry autonegotiation every 5 seconds. 349 */ 350 if (++sc->mii_ticks <= sc->mii_anegticks) 351 break; 352 353 sc->mii_ticks = 0; 354 brgphy_mii_phy_auto(sc); 355 break; 356 } 357 358 /* Update the media status. */ 359 brgphy_status(sc); 360 361 /* 362 * Callback if something changed. Note that we need to poke 363 * the DSP on the Broadcom PHYs if the media changes. 364 */ 365 if (sc->mii_media_active != mii->mii_media_active || 366 sc->mii_media_status != mii->mii_media_status || 367 cmd == MII_MEDIACHG) { 368 switch (sc->mii_model) { 369 case MII_MODEL_xxBROADCOM_BCM5400: 370 brgphy_bcm5401_dspcode(sc); 371 break; 372 case MII_MODEL_xxBROADCOM_BCM5401: 373 if (sc->mii_rev == 1 || sc->mii_rev == 3) 374 brgphy_bcm5401_dspcode(sc); 375 break; 376 case MII_MODEL_xxBROADCOM_BCM5411: 377 brgphy_bcm5411_dspcode(sc); 378 break; 379 } 380 } 381 mii_phy_update(sc, cmd); 382 return (0); 383 } 384 385 static void 386 brgphy_status(struct mii_softc *sc) 387 { 388 struct mii_data *mii = sc->mii_pdata; 389 int bmcr, bmsr; 390 391 mii->mii_media_status = IFM_AVALID; 392 mii->mii_media_active = IFM_ETHER; 393 394 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 395 if (bmsr & BRGPHY_BMSR_LINK) 396 mii->mii_media_status |= IFM_ACTIVE; 397 398 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 399 if (bmcr & BRGPHY_BMCR_LOOP) 400 mii->mii_media_active |= IFM_LOOP; 401 402 if (bmcr & BRGPHY_BMCR_AUTOEN) { 403 int auxsts; 404 405 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 406 /* Erg, still trying, I guess... */ 407 mii->mii_media_active |= IFM_NONE; 408 return; 409 } 410 411 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 412 413 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 414 case BRGPHY_RES_1000FD: 415 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 416 break; 417 case BRGPHY_RES_1000HD: 418 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 419 break; 420 case BRGPHY_RES_100FD: 421 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 422 break; 423 case BRGPHY_RES_100T4: 424 mii->mii_media_active |= IFM_100_T4; 425 break; 426 case BRGPHY_RES_100HD: 427 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 428 break; 429 case BRGPHY_RES_10FD: 430 mii->mii_media_active |= IFM_10_T | IFM_FDX; 431 break; 432 case BRGPHY_RES_10HD: 433 mii->mii_media_active |= IFM_10_T | IFM_HDX; 434 break; 435 default: 436 if (sc->mii_model == MII_MODEL_BROADCOM2_BCM5906) { 437 mii->mii_media_active |= (auxsts & 438 BRGPHY_RES_100) ? IFM_100_TX : IFM_10_T; 439 mii->mii_media_active |= (auxsts & 440 BRGPHY_RES_FULL) ? IFM_FDX : IFM_HDX; 441 break; 442 } 443 mii->mii_media_active |= IFM_NONE; 444 break; 445 } 446 } else { 447 mii->mii_media_active = mii->mii_media.ifm_cur->ifm_media; 448 } 449 } 450 451 452 static void 453 brgphy_mii_phy_auto(struct mii_softc *sc) 454 { 455 int ktcr; 456 457 brgphy_reset(sc); 458 459 PHY_WRITE(sc, BRGPHY_MII_ANAR, 460 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); 461 DELAY(1000); 462 463 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 464 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 465 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 466 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 467 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 468 DELAY(1000); 469 470 PHY_WRITE(sc, BRGPHY_MII_BMCR, 471 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 472 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 473 } 474 475 static void 476 brgphy_loop(struct mii_softc *sc) 477 { 478 uint32_t bmsr; 479 int i; 480 481 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 482 for (i = 0; i < 15000; i++) { 483 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 484 if (!(bmsr & BRGPHY_BMSR_LINK)) 485 break; 486 DELAY(10); 487 } 488 } 489 490 static void 491 brgphy_reset(struct mii_softc *sc) 492 { 493 struct ifnet *ifp; 494 495 mii_phy_reset(sc); 496 497 switch (sc->mii_model) { 498 case MII_MODEL_xxBROADCOM_BCM5400: 499 brgphy_bcm5401_dspcode(sc); 500 break; 501 case MII_MODEL_xxBROADCOM_BCM5401: 502 if (sc->mii_rev == 1 || sc->mii_rev == 3) 503 brgphy_bcm5401_dspcode(sc); 504 break; 505 case MII_MODEL_xxBROADCOM_BCM5411: 506 brgphy_bcm5411_dspcode(sc); 507 break; 508 case MII_MODEL_xxBROADCOM_BCM5421: 509 brgphy_bcm5421_dspcode(sc); 510 break; 511 case MII_MODEL_xxBROADCOM_BCM54K2: 512 brgphy_bcm54k2_dspcode(sc); 513 break; 514 } 515 516 ifp = sc->mii_pdata->mii_ifp; 517 if (strncmp(ifp->if_xname, "bge", 3) == 0) { 518 struct bge_softc *bge_sc = ifp->if_softc; 519 520 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) 521 brgphy_adc_bug(sc); 522 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) 523 brgphy_5704_a0_bug(sc); 524 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) { 525 brgphy_ber_bug(sc); 526 } else if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) { 527 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 528 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 529 530 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) { 531 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b); 532 PHY_WRITE(sc, BRGPHY_TEST1, 533 BRGPHY_TEST1_TRIM_EN | 0x4); 534 } else { 535 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b); 536 } 537 538 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 539 } 540 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) 541 brgphy_crc_bug(sc); 542 543 /* Set Jumbo frame settings in the PHY. */ 544 brgphy_jumbo_settings(sc, ifp->if_mtu); 545 546 /* Adjust output voltage */ 547 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 548 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 549 550 /* Enable Ethernet@Wirespeed */ 551 if (bge_sc->bge_flags & BGE_FLAG_ETH_WIRESPEED) 552 brgphy_eth_wirespeed(sc); 553 554 /* Enable Link LED on Dell boxes */ 555 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { 556 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 557 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 558 & ~BRGPHY_PHY_EXTCTL_3_LED); 559 } 560 } else if (strncmp(ifp->if_xname, "bce", 3) == 0) { 561 struct bce_softc *bce_sc = ifp->if_softc; 562 563 if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) { 564 if (BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax || 565 BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx) 566 brgphy_disable_early_dac(sc); 567 brgphy_jumbo_settings(sc, ifp->if_mtu); 568 brgphy_eth_wirespeed(sc); 569 } else { 570 brgphy_ber_bug(sc); 571 brgphy_jumbo_settings(sc, ifp->if_mtu); 572 brgphy_eth_wirespeed(sc); 573 } 574 } 575 } 576 577 /* Turn off tap power management on 5401. */ 578 static void 579 brgphy_bcm5401_dspcode(struct mii_softc *sc) 580 { 581 static const struct { 582 int reg; 583 uint16_t val; 584 } dspcode[] = { 585 { BRGPHY_MII_AUXCTL, 0x0c20 }, 586 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 587 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 588 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 589 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 590 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 591 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 592 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 593 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 594 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 595 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 596 { 0, 0 }, 597 }; 598 int i; 599 600 for (i = 0; dspcode[i].reg != 0; i++) 601 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 602 DELAY(40); 603 } 604 605 /* Setting some undocumented voltage */ 606 static void 607 brgphy_bcm5411_dspcode(struct mii_softc *sc) 608 { 609 static const struct { 610 int reg; 611 uint16_t val; 612 } dspcode[] = { 613 { 0x1c, 0x8c23 }, 614 { 0x1c, 0x8ca3 }, 615 { 0x1c, 0x8c23 }, 616 { 0, 0 }, 617 }; 618 int i; 619 620 for (i = 0; dspcode[i].reg != 0; i++) 621 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 622 } 623 624 static void 625 brgphy_bcm5421_dspcode(struct mii_softc *sc) 626 { 627 uint16_t data; 628 629 /* Set Class A mode */ 630 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 631 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 632 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 633 634 /* Set FFE gamma override to -0.125 */ 635 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 636 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 637 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 638 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 639 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 640 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 641 } 642 643 static void 644 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 645 { 646 static const struct { 647 int reg; 648 uint16_t val; 649 } dspcode[] = { 650 { 4, 0x01e1 }, 651 { 9, 0x0300 }, 652 { 0, 0 }, 653 }; 654 int i; 655 656 for (i = 0; dspcode[i].reg != 0; i++) 657 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 658 } 659 660 static void 661 brgphy_adc_bug(struct mii_softc *sc) 662 { 663 static const struct { 664 int reg; 665 uint16_t val; 666 } dspcode[] = { 667 { BRGPHY_MII_AUXCTL, 0x0c00 }, 668 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 669 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 670 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 671 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 672 { BRGPHY_MII_AUXCTL, 0x0400 }, 673 { 0, 0 }, 674 }; 675 int i; 676 677 for (i = 0; dspcode[i].reg != 0; i++) 678 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 679 } 680 681 static void 682 brgphy_5704_a0_bug(struct mii_softc *sc) 683 { 684 static const struct { 685 int reg; 686 u_int16_t val; 687 } dspcode[] = { 688 { 0x1c, 0x8d68 }, 689 { 0x1c, 0x8d68 }, 690 { 0, 0 }, 691 }; 692 int i; 693 694 for (i = 0; dspcode[i].reg != 0; i++) 695 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 696 } 697 698 static void 699 brgphy_ber_bug(struct mii_softc *sc) 700 { 701 static const struct { 702 int reg; 703 uint16_t val; 704 } dspcode[] = { 705 { BRGPHY_MII_AUXCTL, 0x0c00 }, 706 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 707 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 708 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 709 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 710 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 711 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 712 { BRGPHY_MII_AUXCTL, 0x0400 }, 713 { 0, 0 }, 714 }; 715 int i; 716 717 for (i = 0; dspcode[i].reg != 0; i++) 718 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 719 } 720 721 static void 722 brgphy_crc_bug(struct mii_softc *sc) 723 { 724 static const struct { 725 int reg; 726 uint16_t val; 727 } dspcode[] = { 728 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 729 { 0x1c, 0x8c68 }, 730 { 0x1c, 0x8d68 }, 731 { 0x1c, 0x8c68 }, 732 { 0, 0 }, 733 }; 734 int i; 735 736 for (i = 0; dspcode[i].reg != 0; i++) 737 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 738 } 739 740 static void 741 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 742 { 743 uint32_t val; 744 745 /* Set or clear jumbo frame settings in the PHY. */ 746 if (mtu > ETHER_MAX_LEN) { 747 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 748 /* BCM5401 PHY cannot read-modify-write. */ 749 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 750 } else { 751 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 752 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 753 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 754 val | BRGPHY_AUXCTL_LONG_PKT); 755 } 756 757 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 758 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 759 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 760 } else { 761 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 762 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 763 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 764 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 765 766 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 767 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 768 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 769 } 770 } 771 772 static void 773 brgphy_eth_wirespeed(struct mii_softc *sc) 774 { 775 u_int32_t val; 776 777 /* Enable Ethernet@Wirespeed */ 778 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 779 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 780 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4))); 781 } 782 783 static void 784 brgphy_disable_early_dac(struct mii_softc *sc) 785 { 786 uint32_t val; 787 788 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 789 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 790 val &= ~(1 << 8); 791 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 792 } 793