1 /* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2000 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $ 35 * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.22 2008/10/22 14:24:24 sephe Exp $ 36 */ 37 38 /* 39 * Driver for the Broadcom BCR5400 1000baseT PHY. Speed is always 40 * 1000mbps; all we need to negotiate here is full or half duplex. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/bus.h> 48 #include <sys/sysctl.h> 49 50 #include <net/ethernet.h> 51 #include <net/if.h> 52 #include <net/if_media.h> 53 #include <net/if_arp.h> 54 55 #include "mii.h" 56 #include "miivar.h" 57 #include "miidevs.h" 58 59 #include "brgphyreg.h" 60 #include <dev/netif/bge/if_bgereg.h> 61 62 #include "miibus_if.h" 63 64 static int brgphy_probe(device_t); 65 static int brgphy_attach(device_t); 66 67 static const struct mii_phydesc brgphys[] = { 68 MII_PHYDESC(xxBROADCOM, BCM5400), 69 MII_PHYDESC(xxBROADCOM, BCM5401), 70 MII_PHYDESC(xxBROADCOM, BCM5411), 71 MII_PHYDESC(xxBROADCOM, BCM5421), 72 MII_PHYDESC(xxBROADCOM, BCM54K2), 73 MII_PHYDESC(xxBROADCOM, BCM5462), 74 75 MII_PHYDESC(xxBROADCOM, BCM5701), 76 MII_PHYDESC(xxBROADCOM, BCM5703), 77 MII_PHYDESC(xxBROADCOM, BCM5704), 78 MII_PHYDESC(xxBROADCOM, BCM5705), 79 80 MII_PHYDESC(xxBROADCOM, BCM5714), 81 MII_PHYDESC(xxBROADCOM2,BCM5722), 82 MII_PHYDESC(xxBROADCOM, BCM5750), 83 MII_PHYDESC(xxBROADCOM, BCM5752), 84 MII_PHYDESC(xxBROADCOM2,BCM5755), 85 MII_PHYDESC(xxBROADCOM, BCM5780), 86 MII_PHYDESC(xxBROADCOM2,BCM5787), 87 88 MII_PHYDESC(xxBROADCOM, BCM5706C), 89 MII_PHYDESC(xxBROADCOM, BCM5708C), 90 91 MII_PHYDESC(BROADCOM2, BCM5906), 92 93 MII_PHYDESC_NULL 94 }; 95 96 static device_method_t brgphy_methods[] = { 97 /* device interface */ 98 DEVMETHOD(device_probe, brgphy_probe), 99 DEVMETHOD(device_attach, brgphy_attach), 100 DEVMETHOD(device_detach, ukphy_detach), 101 DEVMETHOD(device_shutdown, bus_generic_shutdown), 102 { 0, 0 } 103 }; 104 105 static devclass_t brgphy_devclass; 106 107 static driver_t brgphy_driver = { 108 "brgphy", 109 brgphy_methods, 110 sizeof(struct mii_softc) 111 }; 112 113 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 114 115 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 116 static void brgphy_status(struct mii_softc *); 117 static void brgphy_mii_phy_auto(struct mii_softc *); 118 static void brgphy_reset(struct mii_softc *); 119 static void brgphy_loop(struct mii_softc *); 120 121 static void brgphy_bcm5401_dspcode(struct mii_softc *); 122 static void brgphy_bcm5411_dspcode(struct mii_softc *); 123 static void brgphy_bcm5421_dspcode(struct mii_softc *); 124 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 125 126 static void brgphy_adc_bug(struct mii_softc *); 127 static void brgphy_5704_a0_bug(struct mii_softc *); 128 static void brgphy_ber_bug(struct mii_softc *); 129 static void brgphy_crc_bug(struct mii_softc *); 130 131 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 132 static void brgphy_eth_wirespeed(struct mii_softc *); 133 134 static int 135 brgphy_probe(device_t dev) 136 { 137 struct mii_attach_args *ma = device_get_ivars(dev); 138 const struct mii_phydesc *mpd; 139 140 mpd = mii_phy_match(ma, brgphys); 141 if (mpd != NULL) { 142 device_set_desc(dev, mpd->mpd_name); 143 return (0); 144 } 145 return(ENXIO); 146 } 147 148 static int 149 brgphy_attach(device_t dev) 150 { 151 struct mii_softc *sc; 152 struct mii_attach_args *ma; 153 struct mii_data *mii; 154 155 sc = device_get_softc(dev); 156 ma = device_get_ivars(dev); 157 mii_softc_init(sc, ma); 158 sc->mii_dev = device_get_parent(dev); 159 mii = device_get_softc(sc->mii_dev); 160 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 161 162 sc->mii_inst = mii->mii_instance; 163 sc->mii_service = brgphy_service; 164 sc->mii_reset = brgphy_reset; 165 sc->mii_pdata = mii; 166 167 sc->mii_flags |= MIIF_NOISOLATE; 168 mii->mii_instance++; 169 170 brgphy_reset(sc); 171 172 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 173 174 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 175 MII_MEDIA_NONE); 176 #if 0 177 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 178 MII_MEDIA_100_TX); 179 #endif 180 181 #undef ADD 182 183 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 184 if (sc->mii_capabilities & BMSR_EXTSTAT) 185 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 186 187 device_printf(dev, " "); 188 if ((sc->mii_capabilities & BMSR_MEDIAMASK) || 189 (sc->mii_extcapabilities & EXTSR_MEDIAMASK)) 190 mii_phy_add_media(sc); 191 else 192 kprintf("no media present"); 193 kprintf("\n"); 194 195 MIIBUS_MEDIAINIT(sc->mii_dev); 196 return(0); 197 } 198 199 static int 200 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 201 { 202 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 203 int reg, speed, gig; 204 205 switch (cmd) { 206 case MII_POLLSTAT: 207 /* 208 * If we're not polling our PHY instance, just return. 209 */ 210 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 211 return (0); 212 break; 213 214 case MII_MEDIACHG: 215 /* 216 * If the media indicates a different PHY instance, 217 * isolate ourselves. 218 */ 219 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 220 reg = PHY_READ(sc, MII_BMCR); 221 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 222 return (0); 223 } 224 225 /* 226 * If the interface is not up, don't do anything. 227 */ 228 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 229 break; 230 231 brgphy_reset(sc); /* XXX hardware bug work-around */ 232 233 switch (IFM_SUBTYPE(ife->ifm_media)) { 234 case IFM_AUTO: 235 #ifdef foo 236 /* 237 * If we're already in auto mode, just return. 238 */ 239 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 240 return (0); 241 #endif 242 brgphy_mii_phy_auto(sc); 243 break; 244 case IFM_1000_T: 245 speed = BRGPHY_S1000; 246 goto setit; 247 case IFM_100_TX: 248 speed = BRGPHY_S100; 249 goto setit; 250 case IFM_10_T: 251 speed = BRGPHY_S10; 252 setit: 253 brgphy_loop(sc); 254 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 255 speed |= BRGPHY_BMCR_FDX; 256 gig = BRGPHY_1000CTL_AFD; 257 } else { 258 gig = BRGPHY_1000CTL_AHD; 259 } 260 261 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 262 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 263 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 264 265 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 266 break; 267 268 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 269 PHY_WRITE(sc, BRGPHY_MII_BMCR, 270 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 271 272 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 273 break; 274 275 /* 276 * When settning the link manually, one side must 277 * be the master and the other the slave. However 278 * ifmedia doesn't give us a good way to specify 279 * this, so we fake it by using one of the LINK 280 * flags. If LINK0 is set, we program the PHY to 281 * be a master, otherwise it's a slave. 282 */ 283 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 284 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 285 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 286 } else { 287 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 288 gig|BRGPHY_1000CTL_MSE); 289 } 290 break; 291 #ifdef foo 292 case IFM_NONE: 293 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 294 break; 295 #endif 296 case IFM_100_T4: 297 default: 298 return (EINVAL); 299 } 300 break; 301 302 case MII_TICK: 303 /* 304 * If we're not currently selected, just return. 305 */ 306 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 307 return (0); 308 309 /* 310 * Is the interface even up? 311 */ 312 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 313 return (0); 314 315 /* 316 * Only used for autonegotiation. 317 */ 318 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 319 break; 320 321 /* 322 * Check to see if we have link. If we do, we don't 323 * need to restart the autonegotiation process. 324 */ 325 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 326 if (reg & BRGPHY_AUXSTS_LINK) { 327 sc->mii_ticks = 0; 328 break; 329 } 330 331 /* 332 * Only retry autonegotiation every 5 seconds. 333 */ 334 if (++sc->mii_ticks <= sc->mii_anegticks) 335 break; 336 337 sc->mii_ticks = 0; 338 brgphy_mii_phy_auto(sc); 339 break; 340 } 341 342 /* Update the media status. */ 343 brgphy_status(sc); 344 345 /* 346 * Callback if something changed. Note that we need to poke 347 * the DSP on the Broadcom PHYs if the media changes. 348 */ 349 if (sc->mii_media_active != mii->mii_media_active || 350 sc->mii_media_status != mii->mii_media_status || 351 cmd == MII_MEDIACHG) { 352 switch (sc->mii_model) { 353 case MII_MODEL_xxBROADCOM_BCM5400: 354 brgphy_bcm5401_dspcode(sc); 355 break; 356 case MII_MODEL_xxBROADCOM_BCM5401: 357 if (sc->mii_rev == 1 || sc->mii_rev == 3) 358 brgphy_bcm5401_dspcode(sc); 359 break; 360 case MII_MODEL_xxBROADCOM_BCM5411: 361 brgphy_bcm5411_dspcode(sc); 362 break; 363 } 364 } 365 mii_phy_update(sc, cmd); 366 return (0); 367 } 368 369 static void 370 brgphy_status(struct mii_softc *sc) 371 { 372 struct mii_data *mii = sc->mii_pdata; 373 int bmcr, aux; 374 375 mii->mii_media_status = IFM_AVALID; 376 mii->mii_media_active = IFM_ETHER; 377 378 aux = PHY_READ(sc, BRGPHY_MII_AUXSTS); 379 if (aux & BRGPHY_AUXSTS_LINK) 380 mii->mii_media_status |= IFM_ACTIVE; 381 382 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 383 if (bmcr & BRGPHY_BMCR_LOOP) 384 mii->mii_media_active |= IFM_LOOP; 385 386 if (bmcr & BRGPHY_BMCR_AUTOEN) { 387 if ((PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_ACOMP) == 0) { 388 /* Erg, still trying, I guess... */ 389 mii->mii_media_active |= IFM_NONE; 390 return; 391 } 392 393 switch (aux & BRGPHY_AUXSTS_AN_RES) { 394 case BRGPHY_RES_1000FD: 395 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 396 break; 397 case BRGPHY_RES_1000HD: 398 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 399 break; 400 case BRGPHY_RES_100FD: 401 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 402 break; 403 case BRGPHY_RES_100T4: 404 mii->mii_media_active |= IFM_100_T4; 405 break; 406 case BRGPHY_RES_100HD: 407 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 408 break; 409 case BRGPHY_RES_10FD: 410 mii->mii_media_active |= IFM_10_T | IFM_FDX; 411 break; 412 case BRGPHY_RES_10HD: 413 mii->mii_media_active |= IFM_10_T | IFM_HDX; 414 break; 415 default: 416 mii->mii_media_active |= IFM_NONE; 417 break; 418 } 419 } else { 420 mii->mii_media_active = mii->mii_media.ifm_cur->ifm_media; 421 } 422 } 423 424 425 static void 426 brgphy_mii_phy_auto(struct mii_softc *sc) 427 { 428 int ktcr = 0; 429 430 brgphy_loop(sc); 431 brgphy_reset(sc); 432 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 433 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 434 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 435 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 436 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 437 DELAY(1000); 438 PHY_WRITE(sc, BRGPHY_MII_ANAR, 439 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); 440 DELAY(1000); 441 PHY_WRITE(sc, BRGPHY_MII_BMCR, 442 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 443 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 444 } 445 446 static void 447 brgphy_loop(struct mii_softc *sc) 448 { 449 uint32_t bmsr; 450 int i; 451 452 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 453 for (i = 0; i < 15000; i++) { 454 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 455 if (!(bmsr & BRGPHY_BMSR_LINK)) 456 break; 457 DELAY(10); 458 } 459 } 460 461 static void 462 brgphy_reset(struct mii_softc *sc) 463 { 464 struct ifnet *ifp; 465 466 mii_phy_reset(sc); 467 468 switch (sc->mii_model) { 469 case MII_MODEL_xxBROADCOM_BCM5400: 470 brgphy_bcm5401_dspcode(sc); 471 break; 472 case MII_MODEL_xxBROADCOM_BCM5401: 473 if (sc->mii_rev == 1 || sc->mii_rev == 3) 474 brgphy_bcm5401_dspcode(sc); 475 break; 476 case MII_MODEL_xxBROADCOM_BCM5411: 477 brgphy_bcm5411_dspcode(sc); 478 break; 479 case MII_MODEL_xxBROADCOM_BCM5421: 480 brgphy_bcm5421_dspcode(sc); 481 break; 482 case MII_MODEL_xxBROADCOM_BCM54K2: 483 brgphy_bcm54k2_dspcode(sc); 484 break; 485 } 486 487 ifp = sc->mii_pdata->mii_ifp; 488 if (strncmp(ifp->if_xname, "bge", 3) == 0) { 489 struct bge_softc *bge_sc = ifp->if_softc; 490 491 if (bge_sc->bge_flags & BGE_FLAG_ADC_BUG) 492 brgphy_adc_bug(sc); 493 if (bge_sc->bge_flags & BGE_FLAG_5704_A0_BUG) 494 brgphy_5704_a0_bug(sc); 495 if (bge_sc->bge_flags & BGE_FLAG_BER_BUG) { 496 brgphy_ber_bug(sc); 497 } else if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG) { 498 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 499 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 500 501 if (bge_sc->bge_flags & BGE_FLAG_ADJUST_TRIM) { 502 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b); 503 PHY_WRITE(sc, BRGPHY_TEST1, 504 BRGPHY_TEST1_TRIM_EN | 0x4); 505 } else { 506 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b); 507 } 508 509 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 510 } 511 if (bge_sc->bge_flags & BGE_FLAG_CRC_BUG) 512 brgphy_crc_bug(sc); 513 514 /* Set Jumbo frame settings in the PHY. */ 515 brgphy_jumbo_settings(sc, ifp->if_mtu); 516 517 /* Enable Ethernet@Wirespeed */ 518 if (bge_sc->bge_flags & BGE_FLAG_ETH_WIRESPEED) 519 brgphy_eth_wirespeed(sc); 520 521 /* Enable Link LED on Dell boxes */ 522 if (bge_sc->bge_flags & BGE_FLAG_NO_3LED) { 523 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 524 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) 525 & ~BRGPHY_PHY_EXTCTL_3_LED); 526 } 527 528 /* Adjust output voltage (From Linux driver) */ 529 if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906) 530 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 531 } else if (strncmp(ifp->if_xname, "bce", 3) == 0) { 532 brgphy_ber_bug(sc); 533 brgphy_jumbo_settings(sc, ifp->if_mtu); 534 brgphy_eth_wirespeed(sc); 535 } 536 } 537 538 /* Turn off tap power management on 5401. */ 539 static void 540 brgphy_bcm5401_dspcode(struct mii_softc *sc) 541 { 542 static const struct { 543 int reg; 544 uint16_t val; 545 } dspcode[] = { 546 { BRGPHY_MII_AUXCTL, 0x0c20 }, 547 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 548 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 549 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 550 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 551 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 552 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 553 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 554 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 555 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 556 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 557 { 0, 0 }, 558 }; 559 int i; 560 561 for (i = 0; dspcode[i].reg != 0; i++) 562 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 563 DELAY(40); 564 } 565 566 /* Setting some undocumented voltage */ 567 static void 568 brgphy_bcm5411_dspcode(struct mii_softc *sc) 569 { 570 static const struct { 571 int reg; 572 uint16_t val; 573 } dspcode[] = { 574 { 0x1c, 0x8c23 }, 575 { 0x1c, 0x8ca3 }, 576 { 0x1c, 0x8c23 }, 577 { 0, 0 }, 578 }; 579 int i; 580 581 for (i = 0; dspcode[i].reg != 0; i++) 582 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 583 } 584 585 static void 586 brgphy_bcm5421_dspcode(struct mii_softc *sc) 587 { 588 uint16_t data; 589 590 /* Set Class A mode */ 591 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 592 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 593 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 594 595 /* Set FFE gamma override to -0.125 */ 596 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 597 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 598 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 599 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 600 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 601 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 602 } 603 604 static void 605 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 606 { 607 static const struct { 608 int reg; 609 uint16_t val; 610 } dspcode[] = { 611 { 4, 0x01e1 }, 612 { 9, 0x0300 }, 613 { 0, 0 }, 614 }; 615 int i; 616 617 for (i = 0; dspcode[i].reg != 0; i++) 618 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 619 } 620 621 static void 622 brgphy_adc_bug(struct mii_softc *sc) 623 { 624 static const struct { 625 int reg; 626 uint16_t val; 627 } dspcode[] = { 628 { BRGPHY_MII_AUXCTL, 0x0c00 }, 629 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 630 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 631 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 632 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 633 { BRGPHY_MII_AUXCTL, 0x0400 }, 634 { 0, 0 }, 635 }; 636 int i; 637 638 for (i = 0; dspcode[i].reg != 0; i++) 639 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 640 } 641 642 static void 643 brgphy_5704_a0_bug(struct mii_softc *sc) 644 { 645 static const struct { 646 int reg; 647 u_int16_t val; 648 } dspcode[] = { 649 { 0x1c, 0x8d68 }, 650 { 0x1c, 0x8d68 }, 651 { 0, 0 }, 652 }; 653 int i; 654 655 for (i = 0; dspcode[i].reg != 0; i++) 656 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 657 } 658 659 static void 660 brgphy_ber_bug(struct mii_softc *sc) 661 { 662 static const struct { 663 int reg; 664 uint16_t val; 665 } dspcode[] = { 666 { BRGPHY_MII_AUXCTL, 0x0c00 }, 667 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 668 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 669 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 670 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 671 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 672 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 673 { BRGPHY_MII_AUXCTL, 0x0400 }, 674 { 0, 0 }, 675 }; 676 int i; 677 678 for (i = 0; dspcode[i].reg != 0; i++) 679 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 680 } 681 682 static void 683 brgphy_crc_bug(struct mii_softc *sc) 684 { 685 static const struct { 686 int reg; 687 uint16_t val; 688 } dspcode[] = { 689 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 690 { 0x1c, 0x8c68 }, 691 { 0x1c, 0x8d68 }, 692 { 0x1c, 0x8c68 }, 693 { 0, 0 }, 694 }; 695 int i; 696 697 for (i = 0; dspcode[i].reg != 0; i++) 698 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 699 } 700 701 static void 702 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 703 { 704 uint32_t val; 705 706 /* Set or clear jumbo frame settings in the PHY. */ 707 if (mtu > ETHER_MAX_LEN) { 708 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 709 /* BCM5401 PHY cannot read-modify-write. */ 710 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 711 } else { 712 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 713 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 714 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 715 val | BRGPHY_AUXCTL_LONG_PKT); 716 } 717 718 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 719 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 720 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 721 } else { 722 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 723 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 724 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 725 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 726 727 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 728 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 729 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 730 } 731 } 732 733 static void 734 brgphy_eth_wirespeed(struct mii_softc *sc) 735 { 736 u_int32_t val; 737 738 /* Enable Ethernet@Wirespeed */ 739 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 740 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 741 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4))); 742 } 743