1 /* 2 * Copyright (c) 2000 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $ 33 * $DragonFly: src/sys/dev/netif/mii_layer/brgphy.c,v 1.3 2003/08/07 21:17:03 dillon Exp $ 34 * 35 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $ 36 */ 37 38 /* 39 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always 40 * 1000mbps; all we need to negotiate here is full or half duplex. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/bus.h> 48 49 #include <machine/clock.h> 50 51 #include <net/if.h> 52 #include <net/if_media.h> 53 54 #include "mii.h" 55 #include "miivar.h" 56 #include "miidevs.h" 57 58 #include "brgphyreg.h" 59 60 #include "miibus_if.h" 61 62 static int brgphy_probe(device_t); 63 static int brgphy_attach(device_t); 64 static int brgphy_detach(device_t); 65 66 static device_method_t brgphy_methods[] = { 67 /* device interface */ 68 DEVMETHOD(device_probe, brgphy_probe), 69 DEVMETHOD(device_attach, brgphy_attach), 70 DEVMETHOD(device_detach, brgphy_detach), 71 DEVMETHOD(device_shutdown, bus_generic_shutdown), 72 { 0, 0 } 73 }; 74 75 static devclass_t brgphy_devclass; 76 77 static driver_t brgphy_driver = { 78 "brgphy", 79 brgphy_methods, 80 sizeof(struct mii_softc) 81 }; 82 83 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, 0, 0); 84 85 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 86 static void brgphy_status(struct mii_softc *); 87 static int brgphy_mii_phy_auto(struct mii_softc *); 88 static void brgphy_reset(struct mii_softc *); 89 static void brgphy_loop(struct mii_softc *); 90 static void bcm5401_load_dspcode(struct mii_softc *); 91 static void bcm5411_load_dspcode(struct mii_softc *); 92 static void bcm5703_load_dspcode(struct mii_softc *); 93 static int brgphy_mii_model; 94 95 static int brgphy_probe(dev) 96 device_t dev; 97 { 98 struct mii_attach_args *ma; 99 100 ma = device_get_ivars(dev); 101 102 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 103 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5400) { 104 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5400); 105 return(0); 106 } 107 108 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 109 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5401) { 110 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5401); 111 return(0); 112 } 113 114 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 115 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5411) { 116 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5411); 117 return(0); 118 } 119 120 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 121 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5701) { 122 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5701); 123 return(0); 124 } 125 126 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 127 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5703) { 128 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5703); 129 return(0); 130 } 131 132 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxBROADCOM && 133 MII_MODEL(ma->mii_id2) == MII_MODEL_xxBROADCOM_BCM5704) { 134 device_set_desc(dev, MII_STR_xxBROADCOM_BCM5704); 135 return(0); 136 } 137 138 return(ENXIO); 139 } 140 141 static int 142 brgphy_attach(dev) 143 device_t dev; 144 { 145 struct mii_softc *sc; 146 struct mii_attach_args *ma; 147 struct mii_data *mii; 148 const char *sep = ""; 149 150 sc = device_get_softc(dev); 151 ma = device_get_ivars(dev); 152 sc->mii_dev = device_get_parent(dev); 153 mii = device_get_softc(sc->mii_dev); 154 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 155 156 sc->mii_inst = mii->mii_instance; 157 sc->mii_phy = ma->mii_phyno; 158 sc->mii_service = brgphy_service; 159 sc->mii_pdata = mii; 160 161 sc->mii_flags |= MIIF_NOISOLATE; 162 mii->mii_instance++; 163 164 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 165 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 166 167 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 168 BMCR_ISO); 169 #if 0 170 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 171 BMCR_LOOP|BMCR_S100); 172 #endif 173 174 brgphy_mii_model = MII_MODEL(ma->mii_id2); 175 brgphy_reset(sc); 176 177 sc->mii_capabilities = 178 PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 179 device_printf(dev, " "); 180 if (sc->mii_capabilities & BMSR_MEDIAMASK) 181 mii_add_media(mii, (sc->mii_capabilities & ~BMSR_ANEG), 182 sc->mii_inst); 183 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, 0, sc->mii_inst), 184 BRGPHY_BMCR_FDX); 185 PRINT(", 1000baseTX"); 186 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, IFM_FDX, sc->mii_inst), 0); 187 PRINT("1000baseTX-FDX"); 188 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 189 PRINT("auto"); 190 191 printf("\n"); 192 #undef ADD 193 #undef PRINT 194 195 MIIBUS_MEDIAINIT(sc->mii_dev); 196 return(0); 197 } 198 199 static int 200 brgphy_detach(dev) 201 device_t dev; 202 { 203 struct mii_softc *sc; 204 struct mii_data *mii; 205 206 sc = device_get_softc(dev); 207 mii = device_get_softc(device_get_parent(dev)); 208 sc->mii_dev = NULL; 209 LIST_REMOVE(sc, mii_list); 210 211 return(0); 212 } 213 214 static int 215 brgphy_service(sc, mii, cmd) 216 struct mii_softc *sc; 217 struct mii_data *mii; 218 int cmd; 219 { 220 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 221 int reg, speed, gig; 222 223 switch (cmd) { 224 case MII_POLLSTAT: 225 /* 226 * If we're not polling our PHY instance, just return. 227 */ 228 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 229 return (0); 230 break; 231 232 case MII_MEDIACHG: 233 /* 234 * If the media indicates a different PHY instance, 235 * isolate ourselves. 236 */ 237 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 238 reg = PHY_READ(sc, MII_BMCR); 239 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 240 return (0); 241 } 242 243 /* 244 * If the interface is not up, don't do anything. 245 */ 246 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 247 break; 248 249 brgphy_reset(sc); /* XXX hardware bug work-around */ 250 251 switch (IFM_SUBTYPE(ife->ifm_media)) { 252 case IFM_AUTO: 253 #ifdef foo 254 /* 255 * If we're already in auto mode, just return. 256 */ 257 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 258 return (0); 259 #endif 260 (void) brgphy_mii_phy_auto(sc); 261 break; 262 case IFM_1000_TX: 263 speed = BRGPHY_S1000; 264 goto setit; 265 case IFM_100_TX: 266 speed = BRGPHY_S100; 267 goto setit; 268 case IFM_10_T: 269 speed = BRGPHY_S10; 270 setit: 271 brgphy_loop(sc); 272 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 273 speed |= BRGPHY_BMCR_FDX; 274 gig = BRGPHY_1000CTL_AFD; 275 } else { 276 gig = BRGPHY_1000CTL_AHD; 277 } 278 279 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 280 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 281 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 282 283 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_TX) 284 break; 285 286 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 287 PHY_WRITE(sc, BRGPHY_MII_BMCR, 288 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 289 290 if (brgphy_mii_model != MII_MODEL_xxBROADCOM_BCM5701) 291 break; 292 293 /* 294 * When settning the link manually, one side must 295 * be the master and the other the slave. However 296 * ifmedia doesn't give us a good way to specify 297 * this, so we fake it by using one of the LINK 298 * flags. If LINK0 is set, we program the PHY to 299 * be a master, otherwise it's a slave. 300 */ 301 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 302 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 303 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 304 } else { 305 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 306 gig|BRGPHY_1000CTL_MSE); 307 } 308 break; 309 #ifdef foo 310 case IFM_NONE: 311 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 312 break; 313 #endif 314 case IFM_100_T4: 315 default: 316 return (EINVAL); 317 } 318 break; 319 320 case MII_TICK: 321 /* 322 * If we're not currently selected, just return. 323 */ 324 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 325 return (0); 326 327 /* 328 * Only used for autonegotiation. 329 */ 330 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 331 return (0); 332 333 /* 334 * Is the interface even up? 335 */ 336 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 337 return (0); 338 339 /* 340 * Check to see if we have link. If we do, we don't 341 * need to restart the autonegotiation process. Read 342 * the BMSR twice in case it's latched. 343 */ 344 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS); 345 if (reg & BRGPHY_AUXSTS_LINK) 346 break; 347 348 /* 349 * Only retry autonegotiation every 5 seconds. 350 */ 351 if (++sc->mii_ticks != 5) 352 return (0); 353 354 sc->mii_ticks = 0; 355 brgphy_mii_phy_auto(sc); 356 return (0); 357 } 358 359 /* Update the media status. */ 360 brgphy_status(sc); 361 362 /* 363 * Callback if something changed. Note that we need to poke 364 * the DSP on the Broadcom PHYs if the media changes. 365 */ 366 if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 367 MIIBUS_STATCHG(sc->mii_dev); 368 sc->mii_active = mii->mii_media_active; 369 switch (brgphy_mii_model) { 370 case MII_MODEL_xxBROADCOM_BCM5401: 371 bcm5401_load_dspcode(sc); 372 break; 373 case MII_MODEL_xxBROADCOM_BCM5411: 374 bcm5411_load_dspcode(sc); 375 break; 376 } 377 } 378 return (0); 379 } 380 381 void 382 brgphy_status(sc) 383 struct mii_softc *sc; 384 { 385 struct mii_data *mii = sc->mii_pdata; 386 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 387 int bmsr, bmcr; 388 389 mii->mii_media_status = IFM_AVALID; 390 mii->mii_media_active = IFM_ETHER; 391 392 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 393 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK) 394 mii->mii_media_status |= IFM_ACTIVE; 395 396 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 397 398 if (bmcr & BRGPHY_BMCR_LOOP) 399 mii->mii_media_active |= IFM_LOOP; 400 401 if (bmcr & BRGPHY_BMCR_AUTOEN) { 402 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 403 /* Erg, still trying, I guess... */ 404 mii->mii_media_active |= IFM_NONE; 405 return; 406 } 407 408 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) & 409 BRGPHY_AUXSTS_AN_RES) { 410 case BRGPHY_RES_1000FD: 411 mii->mii_media_active |= IFM_1000_TX | IFM_FDX; 412 break; 413 case BRGPHY_RES_1000HD: 414 mii->mii_media_active |= IFM_1000_TX | IFM_HDX; 415 break; 416 case BRGPHY_RES_100FD: 417 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 418 break; 419 case BRGPHY_RES_100T4: 420 mii->mii_media_active |= IFM_100_T4; 421 break; 422 case BRGPHY_RES_100HD: 423 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 424 break; 425 case BRGPHY_RES_10FD: 426 mii->mii_media_active |= IFM_10_T | IFM_FDX; 427 break; 428 case BRGPHY_RES_10HD: 429 mii->mii_media_active |= IFM_10_T | IFM_HDX; 430 break; 431 default: 432 mii->mii_media_active |= IFM_NONE; 433 break; 434 } 435 return; 436 } 437 438 mii->mii_media_active = ife->ifm_media; 439 440 return; 441 } 442 443 444 static int 445 brgphy_mii_phy_auto(mii) 446 struct mii_softc *mii; 447 { 448 int ktcr = 0; 449 450 brgphy_loop(mii); 451 brgphy_reset(mii); 452 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 453 if (brgphy_mii_model == MII_MODEL_xxBROADCOM_BCM5701) 454 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 455 PHY_WRITE(mii, BRGPHY_MII_1000CTL, ktcr); 456 ktcr = PHY_READ(mii, BRGPHY_MII_1000CTL); 457 DELAY(1000); 458 PHY_WRITE(mii, BRGPHY_MII_ANAR, 459 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA); 460 DELAY(1000); 461 PHY_WRITE(mii, BRGPHY_MII_BMCR, 462 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 463 PHY_WRITE(mii, BRGPHY_MII_IMR, 0xFF00); 464 return (EJUSTRETURN); 465 } 466 467 static void 468 brgphy_loop(struct mii_softc *sc) 469 { 470 u_int32_t bmsr; 471 int i; 472 473 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 474 for (i = 0; i < 15000; i++) { 475 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 476 if (!(bmsr & BRGPHY_BMSR_LINK)) { 477 #if 0 478 device_printf(sc->mii_dev, "looped %d\n", i); 479 #endif 480 break; 481 } 482 DELAY(10); 483 } 484 } 485 486 /* Turn off tap power management on 5401. */ 487 static void 488 bcm5401_load_dspcode(struct mii_softc *sc) 489 { 490 static const struct { 491 int reg; 492 uint16_t val; 493 } dspcode[] = { 494 { BRGPHY_MII_AUXCTL, 0x0c20 }, 495 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 496 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 497 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 498 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 499 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 500 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 501 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 502 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 503 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 504 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 505 { 0, 0 }, 506 }; 507 int i; 508 509 for (i = 0; dspcode[i].reg != 0; i++) 510 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 511 DELAY(40); 512 } 513 514 static void 515 bcm5411_load_dspcode(struct mii_softc *sc) 516 { 517 static const struct { 518 int reg; 519 uint16_t val; 520 } dspcode[] = { 521 { 0x1c, 0x8c23 }, 522 { 0x1c, 0x8ca3 }, 523 { 0x1c, 0x8c23 }, 524 { 0, 0 }, 525 }; 526 int i; 527 528 for (i = 0; dspcode[i].reg != 0; i++) 529 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 530 } 531 532 static void 533 bcm5703_load_dspcode(struct mii_softc *sc) 534 { 535 static const struct { 536 int reg; 537 uint16_t val; 538 } dspcode[] = { 539 { BRGPHY_MII_AUXCTL, 0x0c00 }, 540 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 541 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 542 { 0, 0 }, 543 }; 544 int i; 545 546 for (i = 0; dspcode[i].reg != 0; i++) 547 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 548 } 549 550 static void 551 bcm5704_load_dspcode(struct mii_softc *sc) 552 { 553 static const struct { 554 int reg; 555 u_int16_t val; 556 } dspcode[] = { 557 { 0x1c, 0x8d68 }, 558 { 0x1c, 0x8d68 }, 559 { 0, 0 }, 560 }; 561 int i; 562 563 for (i = 0; dspcode[i].reg != 0; i++) 564 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 565 } 566 567 static void 568 brgphy_reset(struct mii_softc *sc) 569 { 570 u_int32_t val; 571 572 mii_phy_reset(sc); 573 574 switch (brgphy_mii_model) { 575 case MII_MODEL_xxBROADCOM_BCM5401: 576 bcm5401_load_dspcode(sc); 577 break; 578 case MII_MODEL_xxBROADCOM_BCM5411: 579 bcm5411_load_dspcode(sc); 580 break; 581 case MII_MODEL_xxBROADCOM_BCM5703: 582 bcm5703_load_dspcode(sc); 583 break; 584 case MII_MODEL_xxBROADCOM_BCM5704: 585 bcm5704_load_dspcode(sc); 586 break; 587 } 588 589 /* Enable Ethernet@WireSpeed. */ 590 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 591 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 592 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) || (1 << 4)); 593 } 594