1 /* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */ 2 3 /* 4 * Copyright (c) 2000 5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $ 35 */ 36 37 /* 38 * Driver for the Broadcom BCR5400 1000baseT PHY. Speed is always 39 * 1000mbps; all we need to negotiate here is full or half duplex. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/bus.h> 47 #include <sys/sysctl.h> 48 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_media.h> 52 #include <net/if_arp.h> 53 54 #include "mii.h" 55 #include "miivar.h" 56 #include "miidevs.h" 57 #include "brgphyreg.h" 58 59 #include "miibus_if.h" 60 61 static int brgphy_probe(device_t); 62 static int brgphy_attach(device_t); 63 64 static const struct mii_phydesc brgphys[] = { 65 MII_PHYDESC(xxBROADCOM, BCM5400), 66 MII_PHYDESC(xxBROADCOM, BCM5401), 67 MII_PHYDESC(xxBROADCOM, BCM5411), 68 MII_PHYDESC(xxBROADCOM, BCM5421), 69 MII_PHYDESC(xxBROADCOM, BCM54K2), 70 MII_PHYDESC(xxBROADCOM, BCM5461), 71 MII_PHYDESC(xxBROADCOM, BCM5462), 72 MII_PHYDESC(xxBROADCOM, BCM5464), 73 74 MII_PHYDESC(xxBROADCOM, BCM5701), 75 MII_PHYDESC(xxBROADCOM, BCM5703), 76 MII_PHYDESC(xxBROADCOM, BCM5704), 77 MII_PHYDESC(xxBROADCOM, BCM5705), 78 MII_PHYDESC(xxBROADCOM, BCM5714), 79 MII_PHYDESC(xxBROADCOM, BCM5750), 80 MII_PHYDESC(xxBROADCOM, BCM5752), 81 MII_PHYDESC(xxBROADCOM, BCM5780), 82 83 MII_PHYDESC(xxBROADCOM2,BCM54XX), 84 MII_PHYDESC(xxBROADCOM2,BCM5481), 85 MII_PHYDESC(xxBROADCOM2,BCM5482), 86 MII_PHYDESC(xxBROADCOM2,BCM5722), 87 MII_PHYDESC(xxBROADCOM2,BCM5755), 88 MII_PHYDESC(xxBROADCOM2,BCM5761), 89 MII_PHYDESC(xxBROADCOM2,BCM5784), 90 MII_PHYDESC(xxBROADCOM2,BCM5787), 91 92 MII_PHYDESC(xxBROADCOM, BCM5706C), 93 MII_PHYDESC(xxBROADCOM, BCM5708C), 94 MII_PHYDESC(xxBROADCOM2, BCM5709CAX), 95 MII_PHYDESC(xxBROADCOM2, BCM5709C), 96 97 MII_PHYDESC(xxBROADCOM3, BCM54640), 98 MII_PHYDESC(xxBROADCOM3, BCM54680), 99 MII_PHYDESC(xxBROADCOM3, BCM54685), 100 MII_PHYDESC(xxBROADCOM3, BCM54880), 101 MII_PHYDESC(xxBROADCOM3, BCM54881), 102 MII_PHYDESC(xxBROADCOM3, BCM5719C), 103 MII_PHYDESC(xxBROADCOM3, BCM5718C), 104 MII_PHYDESC(xxBROADCOM3, BCM5720C), 105 MII_PHYDESC(xxBROADCOM3, BCM57765), 106 MII_PHYDESC(xxBROADCOM3, BCM57780), 107 108 MII_PHYDESC(BROADCOM2, BCM5906), 109 110 MII_PHYDESC_NULL 111 }; 112 113 static device_method_t brgphy_methods[] = { 114 /* device interface */ 115 DEVMETHOD(device_probe, brgphy_probe), 116 DEVMETHOD(device_attach, brgphy_attach), 117 DEVMETHOD(device_detach, ukphy_detach), 118 DEVMETHOD(device_shutdown, bus_generic_shutdown), 119 { 0, 0 } 120 }; 121 122 static devclass_t brgphy_devclass; 123 124 static driver_t brgphy_driver = { 125 "brgphy", 126 brgphy_methods, 127 sizeof(struct mii_softc) 128 }; 129 130 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, NULL, NULL); 131 132 static int brgphy_service(struct mii_softc *, struct mii_data *, int); 133 static void brgphy_status(struct mii_softc *); 134 static void brgphy_mii_phy_auto(struct mii_softc *); 135 static void brgphy_reset(struct mii_softc *); 136 static void brgphy_loop(struct mii_softc *); 137 138 static void brgphy_bcm5401_dspcode(struct mii_softc *); 139 static void brgphy_bcm5411_dspcode(struct mii_softc *); 140 static void brgphy_bcm5421_dspcode(struct mii_softc *); 141 static void brgphy_bcm54k2_dspcode(struct mii_softc *); 142 143 static void brgphy_adc_bug(struct mii_softc *); 144 static void brgphy_5704_a0_bug(struct mii_softc *); 145 static void brgphy_ber_bug(struct mii_softc *); 146 static void brgphy_crc_bug(struct mii_softc *); 147 148 static void brgphy_disable_early_dac(struct mii_softc *); 149 static void brgphy_jumbo_settings(struct mii_softc *, u_long); 150 static void brgphy_eth_wirespeed(struct mii_softc *); 151 152 static int 153 brgphy_probe(device_t dev) 154 { 155 struct mii_attach_args *ma = device_get_ivars(dev); 156 const struct mii_phydesc *mpd; 157 158 mpd = mii_phy_match(ma, brgphys); 159 if (mpd != NULL) { 160 device_set_desc(dev, mpd->mpd_name); 161 return (0); 162 } 163 return(ENXIO); 164 } 165 166 static int 167 brgphy_attach(device_t dev) 168 { 169 struct mii_softc *sc; 170 struct mii_attach_args *ma; 171 struct mii_data *mii; 172 173 sc = device_get_softc(dev); 174 ma = device_get_ivars(dev); 175 mii_softc_init(sc, ma); 176 sc->mii_dev = device_get_parent(dev); 177 mii = device_get_softc(sc->mii_dev); 178 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 179 180 sc->mii_inst = mii->mii_instance; 181 sc->mii_service = brgphy_service; 182 sc->mii_reset = brgphy_reset; 183 sc->mii_pdata = mii; 184 185 sc->mii_flags |= MIIF_NOISOLATE; 186 mii->mii_instance++; 187 188 brgphy_reset(sc); 189 190 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 191 192 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 193 MII_MEDIA_NONE); 194 #if 0 195 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst), 196 MII_MEDIA_100_TX); 197 #endif 198 199 #undef ADD 200 201 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 202 if (sc->mii_capabilities & BMSR_EXTSTAT) 203 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 204 205 device_printf(dev, " "); 206 if ((sc->mii_capabilities & BMSR_MEDIAMASK) || 207 (sc->mii_extcapabilities & EXTSR_MEDIAMASK)) 208 mii_phy_add_media(sc); 209 else 210 kprintf("no media present"); 211 kprintf("\n"); 212 213 MIIBUS_MEDIAINIT(sc->mii_dev); 214 return(0); 215 } 216 217 static int 218 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 219 { 220 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 221 int reg, speed, gig; 222 223 switch (cmd) { 224 case MII_POLLSTAT: 225 /* 226 * If we're not polling our PHY instance, just return. 227 */ 228 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 229 return (0); 230 break; 231 232 case MII_MEDIACHG: 233 /* 234 * If the media indicates a different PHY instance, 235 * isolate ourselves. 236 */ 237 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 238 reg = PHY_READ(sc, MII_BMCR); 239 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 240 return (0); 241 } 242 243 /* 244 * If the interface is not up, don't do anything. 245 */ 246 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 247 break; 248 249 brgphy_reset(sc); /* XXX hardware bug work-around */ 250 251 switch (IFM_SUBTYPE(ife->ifm_media)) { 252 case IFM_AUTO: 253 #ifdef foo 254 /* 255 * If we're already in auto mode, just return. 256 */ 257 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN) 258 return (0); 259 #endif 260 brgphy_mii_phy_auto(sc); 261 break; 262 case IFM_1000_T: 263 speed = BRGPHY_S1000; 264 goto setit; 265 case IFM_100_TX: 266 speed = BRGPHY_S100; 267 goto setit; 268 case IFM_10_T: 269 speed = BRGPHY_S10; 270 setit: 271 brgphy_loop(sc); 272 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 273 speed |= BRGPHY_BMCR_FDX; 274 gig = BRGPHY_1000CTL_AFD; 275 } else { 276 gig = BRGPHY_1000CTL_AHD; 277 } 278 279 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0); 280 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE); 281 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed); 282 283 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 284 break; 285 286 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig); 287 PHY_WRITE(sc, BRGPHY_MII_BMCR, 288 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG); 289 290 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701) 291 break; 292 293 /* 294 * When settning the link manually, one side must 295 * be the master and the other the slave. However 296 * ifmedia doesn't give us a good way to specify 297 * this, so we fake it by using one of the LINK 298 * flags. If LINK0 is set, we program the PHY to 299 * be a master, otherwise it's a slave. 300 */ 301 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 302 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 303 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC); 304 } else { 305 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 306 gig|BRGPHY_1000CTL_MSE); 307 } 308 break; 309 #ifdef foo 310 case IFM_NONE: 311 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 312 break; 313 #endif 314 case IFM_100_T4: 315 default: 316 return (EINVAL); 317 } 318 break; 319 320 case MII_TICK: 321 /* 322 * If we're not currently selected, just return. 323 */ 324 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 325 return (0); 326 327 /* 328 * Is the interface even up? 329 */ 330 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 331 return (0); 332 333 /* 334 * Only used for autonegotiation. 335 */ 336 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 337 break; 338 339 /* 340 * Check to see if we have link. If we do, we don't 341 * need to restart the autonegotiation process. Read 342 * the BMSR twice in case it's latched. 343 */ 344 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 345 if (reg & BMSR_LINK) { 346 sc->mii_ticks = 0; 347 break; 348 } 349 350 /* 351 * Only retry autonegotiation every 5 seconds. 352 */ 353 if (++sc->mii_ticks <= sc->mii_anegticks) 354 break; 355 356 sc->mii_ticks = 0; 357 brgphy_mii_phy_auto(sc); 358 break; 359 } 360 361 /* Update the media status. */ 362 brgphy_status(sc); 363 364 /* 365 * Callback if something changed. Note that we need to poke 366 * the DSP on the Broadcom PHYs if the media changes. 367 */ 368 if (sc->mii_media_active != mii->mii_media_active || 369 sc->mii_media_status != mii->mii_media_status || 370 cmd == MII_MEDIACHG) { 371 switch (sc->mii_model) { 372 case MII_MODEL_xxBROADCOM_BCM5400: 373 brgphy_bcm5401_dspcode(sc); 374 break; 375 case MII_MODEL_xxBROADCOM_BCM5401: 376 if (sc->mii_rev == 1 || sc->mii_rev == 3) 377 brgphy_bcm5401_dspcode(sc); 378 break; 379 case MII_MODEL_xxBROADCOM_BCM5411: 380 brgphy_bcm5411_dspcode(sc); 381 break; 382 } 383 } 384 mii_phy_update(sc, cmd); 385 return (0); 386 } 387 388 static void 389 brgphy_status(struct mii_softc *sc) 390 { 391 struct mii_data *mii = sc->mii_pdata; 392 int bmcr, bmsr; 393 394 mii->mii_media_status = IFM_AVALID; 395 mii->mii_media_active = IFM_ETHER; 396 397 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR); 398 if (bmsr & BRGPHY_BMSR_LINK) 399 mii->mii_media_status |= IFM_ACTIVE; 400 401 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR); 402 if (bmcr & BRGPHY_BMCR_LOOP) 403 mii->mii_media_active |= IFM_LOOP; 404 405 if (bmcr & BRGPHY_BMCR_AUTOEN) { 406 int auxsts; 407 408 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) { 409 /* Erg, still trying, I guess... */ 410 mii->mii_media_active |= IFM_NONE; 411 return; 412 } 413 414 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS); 415 416 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 417 case BRGPHY_RES_1000FD: 418 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 419 break; 420 case BRGPHY_RES_1000HD: 421 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 422 break; 423 case BRGPHY_RES_100FD: 424 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 425 break; 426 case BRGPHY_RES_100T4: 427 mii->mii_media_active |= IFM_100_T4; 428 break; 429 case BRGPHY_RES_100HD: 430 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 431 break; 432 case BRGPHY_RES_10FD: 433 mii->mii_media_active |= IFM_10_T | IFM_FDX; 434 break; 435 case BRGPHY_RES_10HD: 436 mii->mii_media_active |= IFM_10_T | IFM_HDX; 437 break; 438 default: 439 if (sc->mii_model == MII_MODEL_BROADCOM2_BCM5906) { 440 mii->mii_media_active |= (auxsts & 441 BRGPHY_RES_100) ? IFM_100_TX : IFM_10_T; 442 mii->mii_media_active |= (auxsts & 443 BRGPHY_RES_FULL) ? IFM_FDX : IFM_HDX; 444 break; 445 } 446 mii->mii_media_active |= IFM_NONE; 447 break; 448 } 449 } else { 450 mii->mii_media_active = mii->mii_media.ifm_cur->ifm_media; 451 } 452 } 453 454 455 static void 456 brgphy_mii_phy_auto(struct mii_softc *sc) 457 { 458 int ktcr; 459 460 brgphy_reset(sc); 461 462 PHY_WRITE(sc, BRGPHY_MII_ANAR, 463 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA); 464 DELAY(1000); 465 466 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD; 467 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701) 468 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC; 469 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr); 470 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL); 471 DELAY(1000); 472 473 PHY_WRITE(sc, BRGPHY_MII_BMCR, 474 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG); 475 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 476 } 477 478 static void 479 brgphy_loop(struct mii_softc *sc) 480 { 481 uint32_t bmsr; 482 int i; 483 484 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP); 485 for (i = 0; i < 15000; i++) { 486 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR); 487 if (!(bmsr & BRGPHY_BMSR_LINK)) 488 break; 489 DELAY(10); 490 } 491 } 492 493 static void 494 brgphy_reset(struct mii_softc *sc) 495 { 496 mii_phy_reset(sc); 497 498 switch (sc->mii_model) { 499 case MII_MODEL_xxBROADCOM_BCM5400: 500 brgphy_bcm5401_dspcode(sc); 501 break; 502 case MII_MODEL_xxBROADCOM_BCM5401: 503 if (sc->mii_rev == 1 || sc->mii_rev == 3) 504 brgphy_bcm5401_dspcode(sc); 505 break; 506 case MII_MODEL_xxBROADCOM_BCM5411: 507 brgphy_bcm5411_dspcode(sc); 508 break; 509 case MII_MODEL_xxBROADCOM_BCM5421: 510 brgphy_bcm5421_dspcode(sc); 511 break; 512 case MII_MODEL_xxBROADCOM_BCM54K2: 513 brgphy_bcm54k2_dspcode(sc); 514 break; 515 } 516 517 if (sc->mii_privtag != MII_PRIVTAG_BRGPHY) 518 return; 519 520 if (sc->mii_priv & BRGPHY_FLAG_ADC_BUG) 521 brgphy_adc_bug(sc); 522 if (sc->mii_priv & BRGPHY_FLAG_5704_A0) 523 brgphy_5704_a0_bug(sc); 524 if (sc->mii_priv & BRGPHY_FLAG_BER_BUG) { 525 brgphy_ber_bug(sc); 526 } else if (sc->mii_priv & BRGPHY_FLAG_JITTER_BUG) { 527 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 528 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 529 530 if (sc->mii_priv & BRGPHY_FLAG_ADJUST_TRIM) { 531 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b); 532 PHY_WRITE(sc, BRGPHY_TEST1, 533 BRGPHY_TEST1_TRIM_EN | 0x4); 534 } else { 535 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b); 536 } 537 538 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 539 } 540 if (sc->mii_priv & BRGPHY_FLAG_CRC_BUG) 541 brgphy_crc_bug(sc); 542 if (sc->mii_priv & BRGPHY_FLAG_NO_EARLYDAC) 543 brgphy_disable_early_dac(sc); 544 545 /* Set Jumbo frame settings in the PHY. */ 546 brgphy_jumbo_settings(sc, sc->mii_pdata->mii_ifp->if_mtu); 547 548 /* Adjust output voltage */ 549 if (sc->mii_priv & BRGPHY_FLAG_5906) 550 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 551 552 /* Enable Ethernet@Wirespeed */ 553 if (sc->mii_priv & BRGPHY_FLAG_WIRESPEED) 554 brgphy_eth_wirespeed(sc); 555 556 /* Enable Link LED on Dell boxes */ 557 if (sc->mii_priv & BRGPHY_FLAG_NO_3LED) { 558 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 559 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) & 560 ~BRGPHY_PHY_EXTCTL_3_LED); 561 } 562 } 563 564 /* Turn off tap power management on 5401. */ 565 static void 566 brgphy_bcm5401_dspcode(struct mii_softc *sc) 567 { 568 static const struct { 569 int reg; 570 uint16_t val; 571 } dspcode[] = { 572 { BRGPHY_MII_AUXCTL, 0x0c20 }, 573 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 574 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 575 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 576 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 577 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 578 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 579 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 580 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 581 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 582 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 583 { 0, 0 }, 584 }; 585 int i; 586 587 for (i = 0; dspcode[i].reg != 0; i++) 588 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 589 DELAY(40); 590 } 591 592 /* Setting some undocumented voltage */ 593 static void 594 brgphy_bcm5411_dspcode(struct mii_softc *sc) 595 { 596 static const struct { 597 int reg; 598 uint16_t val; 599 } dspcode[] = { 600 { 0x1c, 0x8c23 }, 601 { 0x1c, 0x8ca3 }, 602 { 0x1c, 0x8c23 }, 603 { 0, 0 }, 604 }; 605 int i; 606 607 for (i = 0; dspcode[i].reg != 0; i++) 608 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 609 } 610 611 static void 612 brgphy_bcm5421_dspcode(struct mii_softc *sc) 613 { 614 uint16_t data; 615 616 /* Set Class A mode */ 617 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 618 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 619 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 620 621 /* Set FFE gamma override to -0.125 */ 622 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 623 data = PHY_READ(sc, BRGPHY_MII_AUXCTL); 624 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 625 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 626 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 627 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 628 } 629 630 static void 631 brgphy_bcm54k2_dspcode(struct mii_softc *sc) 632 { 633 static const struct { 634 int reg; 635 uint16_t val; 636 } dspcode[] = { 637 { 4, 0x01e1 }, 638 { 9, 0x0300 }, 639 { 0, 0 }, 640 }; 641 int i; 642 643 for (i = 0; dspcode[i].reg != 0; i++) 644 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 645 } 646 647 static void 648 brgphy_adc_bug(struct mii_softc *sc) 649 { 650 static const struct { 651 int reg; 652 uint16_t val; 653 } dspcode[] = { 654 { BRGPHY_MII_AUXCTL, 0x0c00 }, 655 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 656 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 657 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 658 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 659 { BRGPHY_MII_AUXCTL, 0x0400 }, 660 { 0, 0 }, 661 }; 662 int i; 663 664 for (i = 0; dspcode[i].reg != 0; i++) 665 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 666 } 667 668 static void 669 brgphy_5704_a0_bug(struct mii_softc *sc) 670 { 671 static const struct { 672 int reg; 673 u_int16_t val; 674 } dspcode[] = { 675 { 0x1c, 0x8d68 }, 676 { 0x1c, 0x8d68 }, 677 { 0, 0 }, 678 }; 679 int i; 680 681 for (i = 0; dspcode[i].reg != 0; i++) 682 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 683 } 684 685 static void 686 brgphy_ber_bug(struct mii_softc *sc) 687 { 688 static const struct { 689 int reg; 690 uint16_t val; 691 } dspcode[] = { 692 { BRGPHY_MII_AUXCTL, 0x0c00 }, 693 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 694 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 695 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 696 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 697 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 698 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 699 { BRGPHY_MII_AUXCTL, 0x0400 }, 700 { 0, 0 }, 701 }; 702 int i; 703 704 for (i = 0; dspcode[i].reg != 0; i++) 705 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 706 } 707 708 static void 709 brgphy_crc_bug(struct mii_softc *sc) 710 { 711 static const struct { 712 int reg; 713 uint16_t val; 714 } dspcode[] = { 715 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 716 { 0x1c, 0x8c68 }, 717 { 0x1c, 0x8d68 }, 718 { 0x1c, 0x8c68 }, 719 { 0, 0 }, 720 }; 721 int i; 722 723 for (i = 0; dspcode[i].reg != 0; i++) 724 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 725 } 726 727 static void 728 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu) 729 { 730 uint32_t val; 731 732 /* Set or clear jumbo frame settings in the PHY. */ 733 if (mtu > ETHER_MAX_LEN) { 734 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) { 735 /* BCM5401 PHY cannot read-modify-write. */ 736 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20); 737 } else { 738 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 739 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 740 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 741 val | BRGPHY_AUXCTL_LONG_PKT); 742 } 743 744 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 745 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 746 val | BRGPHY_PHY_EXTCTL_HIGH_LA); 747 } else { 748 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7); 749 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 750 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 751 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7)); 752 753 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL); 754 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 755 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA); 756 } 757 } 758 759 static void 760 brgphy_eth_wirespeed(struct mii_softc *sc) 761 { 762 u_int32_t val; 763 764 /* Enable Ethernet@Wirespeed */ 765 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007); 766 val = PHY_READ(sc, BRGPHY_MII_AUXCTL); 767 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4))); 768 } 769 770 static void 771 brgphy_disable_early_dac(struct mii_softc *sc) 772 { 773 uint32_t val; 774 775 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08); 776 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT); 777 val &= ~(1 << 8); 778 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val); 779 } 780