1 /* $OpenBSD: ciphy.c,v 1.13 2006/03/10 09:53:16 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/mii/ciphy.c,v 1.3 2005/09/30 19:39:27 imp Exp $ 35 * $DragonFly: src/sys/dev/netif/mii_layer/ciphy.c,v 1.5 2007/09/17 11:29:36 hasso Exp $ 36 */ 37 38 /* 39 * Driver for the Cicada CS8201 10/100/1000 copper PHY. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/if_media.h> 52 53 #include <dev/netif/mii_layer/mii.h> 54 #include <dev/netif/mii_layer/miivar.h> 55 56 #include "miidevs.h" 57 #include "miibus_if.h" 58 59 #include <dev/netif/mii_layer/ciphyreg.h> 60 61 static int ciphy_probe(device_t); 62 static int ciphy_attach(device_t); 63 64 static device_method_t ciphy_methods[] = { 65 /* device interface */ 66 DEVMETHOD(device_probe, ciphy_probe), 67 DEVMETHOD(device_attach, ciphy_attach), 68 DEVMETHOD(device_detach, ukphy_detach), 69 DEVMETHOD(device_shutdown, bus_generic_shutdown), 70 { 0, 0 } 71 }; 72 73 static const struct mii_phydesc ciphys[] = { 74 MII_PHYDESC(CICADA, CS8201), 75 MII_PHYDESC(CICADA, CS8201A), 76 MII_PHYDESC(CICADA, CS8201B), 77 MII_PHYDESC(xxCICADA, CS8201), 78 MII_PHYDESC(xxCICADA, CS8201A), 79 MII_PHYDESC(xxCICADA, CS8201B), 80 MII_PHYDESC(VITESSE, VSC8601), 81 MII_PHYDESC_NULL 82 }; 83 84 static devclass_t ciphy_devclass; 85 86 static driver_t ciphy_driver = { 87 "ciphy", 88 ciphy_methods, 89 sizeof(struct mii_softc) 90 }; 91 92 DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0); 93 94 static int ciphy_service(struct mii_softc *, struct mii_data *, int); 95 static void ciphy_status(struct mii_softc *); 96 static void ciphy_reset(struct mii_softc *); 97 static void ciphy_fixup(struct mii_softc *); 98 99 static int 100 ciphy_probe(device_t dev) 101 { 102 struct mii_attach_args *ma = device_get_ivars(dev); 103 const struct mii_phydesc *mpd; 104 105 mpd = mii_phy_match(ma, ciphys); 106 if (mpd != NULL) { 107 device_set_desc(dev, mpd->mpd_name); 108 return (0); 109 } 110 return (ENXIO); 111 } 112 113 static int 114 ciphy_attach(device_t dev) 115 { 116 struct mii_softc *sc; 117 struct mii_attach_args *ma; 118 struct mii_data *mii; 119 120 sc = device_get_softc(dev); 121 ma = device_get_ivars(dev); 122 mii_softc_init(sc, ma); 123 124 sc->mii_dev = device_get_parent(dev); 125 mii = device_get_softc(sc->mii_dev); 126 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 127 128 sc->mii_inst = mii->mii_instance; 129 sc->mii_service = ciphy_service; 130 sc->mii_reset = ciphy_reset; 131 sc->mii_pdata = mii; 132 133 sc->mii_flags |= MIIF_NOISOLATE; 134 mii->mii_instance++; 135 136 ciphy_reset(sc); 137 138 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 139 if (sc->mii_capabilities & BMSR_EXTSTAT) 140 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 141 142 device_printf(dev, " "); 143 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 && 144 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) 145 kprintf("no media present"); 146 else 147 mii_phy_add_media(sc); 148 kprintf("\n"); 149 150 MIIBUS_MEDIAINIT(sc->mii_dev); 151 return(0); 152 } 153 154 static int 155 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 156 { 157 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 158 int reg, speed, gig; 159 160 switch (cmd) { 161 case MII_POLLSTAT: 162 /* 163 * If we're not polling our PHY instance, just return. 164 */ 165 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 166 return (0); 167 break; 168 169 case MII_MEDIACHG: 170 /* 171 * If the media indicates a different PHY instance, 172 * isolate ourselves. 173 */ 174 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 175 reg = PHY_READ(sc, MII_BMCR); 176 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 177 return (0); 178 } 179 180 /* 181 * If the interface is not up, don't do anything. 182 */ 183 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 184 break; 185 186 ciphy_fixup(sc); /* XXX hardware bug work-around */ 187 188 switch (IFM_SUBTYPE(ife->ifm_media)) { 189 case IFM_AUTO: 190 #ifdef foo 191 /* 192 * If we're already in auto mode, just return. 193 */ 194 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN) 195 return (0); 196 #endif 197 if (mii_phy_auto(sc, 0) == EJUSTRETURN) 198 return (0); 199 break; 200 case IFM_1000_T: 201 speed = CIPHY_S1000; 202 goto setit; 203 case IFM_100_TX: 204 speed = CIPHY_S100; 205 goto setit; 206 case IFM_10_T: 207 speed = CIPHY_S10; 208 setit: 209 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 210 speed |= CIPHY_BMCR_FDX; 211 gig = CIPHY_1000CTL_AFD; 212 } else { 213 gig = CIPHY_1000CTL_AHD; 214 } 215 216 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0); 217 PHY_WRITE(sc, CIPHY_MII_BMCR, speed); 218 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE); 219 220 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 221 break; 222 223 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig); 224 PHY_WRITE(sc, CIPHY_MII_BMCR, 225 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG); 226 227 /* 228 * When setting the link manually, one side must 229 * be the master and the other the slave. However 230 * ifmedia doesn't give us a good way to specify 231 * this, so we fake it by using one of the LINK 232 * flags. If LINK0 is set, we program the PHY to 233 * be a master, otherwise it's a slave. 234 */ 235 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 236 PHY_WRITE(sc, CIPHY_MII_1000CTL, 237 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC); 238 } else { 239 PHY_WRITE(sc, CIPHY_MII_1000CTL, 240 gig|CIPHY_1000CTL_MSE); 241 } 242 break; 243 case IFM_NONE: 244 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 245 break; 246 case IFM_100_T4: 247 default: 248 return (EINVAL); 249 } 250 break; 251 252 case MII_TICK: 253 /* 254 * If we're not currently selected, just return. 255 */ 256 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 257 return (0); 258 259 if (mii_phy_tick(sc) == EJUSTRETURN) 260 return (0); 261 break; 262 } 263 264 /* Update the media status. */ 265 ciphy_status(sc); 266 267 /* 268 * Callback if something changed. Note that we need to poke 269 * apply fixups for certain PHY revs. 270 */ 271 if (sc->mii_media_active != mii->mii_media_active || 272 sc->mii_media_status != mii->mii_media_status || 273 cmd == MII_MEDIACHG) 274 ciphy_fixup(sc); 275 mii_phy_update(sc, cmd); 276 return (0); 277 } 278 279 static void 280 ciphy_status(struct mii_softc *sc) 281 { 282 struct mii_data *mii = sc->mii_pdata; 283 int bmsr, bmcr; 284 285 mii->mii_media_status = IFM_AVALID; 286 mii->mii_media_active = IFM_ETHER; 287 288 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 289 290 if (bmsr & BMSR_LINK) 291 mii->mii_media_status |= IFM_ACTIVE; 292 293 bmcr = PHY_READ(sc, CIPHY_MII_BMCR); 294 295 if (bmcr & CIPHY_BMCR_LOOP) 296 mii->mii_media_active |= IFM_LOOP; 297 298 if (bmcr & CIPHY_BMCR_AUTOEN) { 299 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) { 300 /* Erg, still trying, I guess... */ 301 mii->mii_media_active |= IFM_NONE; 302 return; 303 } 304 } 305 306 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR); 307 switch (bmsr & CIPHY_AUXCSR_SPEED) { 308 case CIPHY_SPEED10: 309 mii->mii_media_active |= IFM_10_T; 310 break; 311 case CIPHY_SPEED100: 312 mii->mii_media_active |= IFM_100_TX; 313 break; 314 case CIPHY_SPEED1000: 315 mii->mii_media_active |= IFM_1000_T; 316 break; 317 default: 318 device_printf(sc->mii_dev, "unknown PHY speed %x\n", 319 bmsr & CIPHY_AUXCSR_SPEED); 320 break; 321 } 322 323 if (bmsr & CIPHY_AUXCSR_FDX) 324 mii->mii_media_active |= IFM_FDX; 325 } 326 327 static void 328 ciphy_reset(struct mii_softc *sc) 329 { 330 mii_phy_reset(sc); 331 DELAY(1000); 332 } 333 334 #define PHY_SETBIT(x, y, z) \ 335 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 336 #define PHY_CLRBIT(x, y, z) \ 337 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 338 339 static void 340 ciphy_fixup(struct mii_softc *sc) 341 { 342 uint16_t model, status, speed; 343 device_t parent; 344 345 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2)); 346 status = PHY_READ(sc, CIPHY_MII_AUXCSR); 347 speed = status & CIPHY_AUXCSR_SPEED; 348 349 parent = device_get_parent(sc->mii_dev); 350 if (strncmp(device_get_name(parent), "nfe", 3) == 0) { 351 /* Need to set for 2.5V RGMII for NVIDIA adapters */ 352 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_INTSEL_RGMII); 353 PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_IOVOL_2500MV); 354 } 355 356 switch (model) { 357 case MII_MODEL_CICADA_CS8201: /* MII_MODEL_xxCICADA_CS8201 */ 358 /* Turn off "aux mode" (whatever that means) */ 359 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); 360 361 /* 362 * Work around speed polling bug in VT3119/VT3216 363 * when using MII in full duplex mode. 364 */ 365 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 366 (status & CIPHY_AUXCSR_FDX)) { 367 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 368 } else { 369 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 370 } 371 372 /* Enable link/activity LED blink. */ 373 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); 374 break; 375 376 case MII_MODEL_CICADA_CS8201A: /* MII_MODEL_xxCICADA_CS8201A */ 377 case MII_MODEL_CICADA_CS8201B: /* MII_MODEL_xxCICADA_CS8201B */ 378 /* 379 * Work around speed polling bug in VT3119/VT3216 380 * when using MII in full duplex mode. 381 */ 382 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 383 (status & CIPHY_AUXCSR_FDX)) { 384 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 385 } else { 386 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 387 } 388 break; 389 390 case MII_MODEL_VITESSE_VSC8601: 391 break; 392 393 default: 394 device_printf(sc->mii_dev, 395 "unknown CICADA PHY model %x\n", model); 396 break; 397 } 398 } 399