1 /* 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/dev/mii/ciphy.c,v 1.3 2005/09/30 19:39:27 imp Exp $ 33 * $DragonFly: src/sys/dev/netif/mii_layer/ciphy.c,v 1.1 2006/05/20 07:15:17 sephe Exp $ 34 */ 35 36 /* 37 * Driver for the Cicada CS8201 10/100/1000 copper PHY. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/bus.h> 46 47 #include <machine/bus.h> 48 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/if_media.h> 52 53 #include <dev/netif/mii_layer/mii.h> 54 #include <dev/netif/mii_layer/miivar.h> 55 56 #include "miidevs.h" 57 #include "miibus_if.h" 58 59 #include <dev/netif/mii_layer/ciphyreg.h> 60 61 static int ciphy_probe(device_t); 62 static int ciphy_attach(device_t); 63 64 static device_method_t ciphy_methods[] = { 65 /* device interface */ 66 DEVMETHOD(device_probe, ciphy_probe), 67 DEVMETHOD(device_attach, ciphy_attach), 68 DEVMETHOD(device_detach, ukphy_detach), 69 DEVMETHOD(device_shutdown, bus_generic_shutdown), 70 { 0, 0 } 71 }; 72 73 static devclass_t ciphy_devclass; 74 75 static driver_t ciphy_driver = { 76 "ciphy", 77 ciphy_methods, 78 sizeof(struct mii_softc) 79 }; 80 81 DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0); 82 83 static int ciphy_service(struct mii_softc *, struct mii_data *, int); 84 static void ciphy_status(struct mii_softc *); 85 static void ciphy_reset(struct mii_softc *); 86 static void ciphy_fixup(struct mii_softc *); 87 static void ciphy_mii_phy_auto(struct mii_softc *); 88 89 static int 90 ciphy_probe(device_t dev) 91 { 92 struct mii_attach_args *ma; 93 94 ma = device_get_ivars(dev); 95 96 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA && 97 MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201) { 98 device_set_desc(dev, MII_STR_CICADA_CS8201); 99 return(0); 100 } 101 102 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA && 103 MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201A) { 104 device_set_desc(dev, MII_STR_CICADA_CS8201A); 105 return(0); 106 } 107 108 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA && 109 MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201B) { 110 device_set_desc(dev, MII_STR_CICADA_CS8201B); 111 return(0); 112 } 113 114 return(ENXIO); 115 } 116 117 static int 118 ciphy_attach(device_t dev) 119 { 120 struct mii_softc *sc; 121 struct mii_attach_args *ma; 122 struct mii_data *mii; 123 const char *sep = ""; 124 125 sc = device_get_softc(dev); 126 ma = device_get_ivars(dev); 127 mii_softc_init(sc, ma); 128 129 sc->mii_dev = device_get_parent(dev); 130 mii = device_get_softc(sc->mii_dev); 131 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 132 133 sc->mii_inst = mii->mii_instance; 134 sc->mii_service = ciphy_service; 135 sc->mii_pdata = mii; 136 137 sc->mii_flags |= MIIF_NOISOLATE; 138 mii->mii_instance++; 139 140 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 141 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 142 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst), 143 BMCR_ISO); 144 145 ciphy_reset(sc); 146 147 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 148 #ifdef notyet 149 if (sc->mii_capabilities & BMSR_EXTSTAT) 150 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 151 #endif 152 153 device_printf(dev, " "); 154 mii_add_media(sc, sc->mii_capabilities & ~BMSR_ANEG); 155 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst), 156 CIPHY_BMCR_FDX); 157 PRINT(", 1000baseTX"); 158 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0); 159 PRINT("1000baseTX-FDX"); 160 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0); 161 PRINT("auto"); 162 163 printf("\n"); 164 165 ma->mii_flags |= MIIF_IS_1000X; 166 MIIBUS_MEDIAINIT(sc->mii_dev); 167 168 return(0); 169 } 170 171 static int 172 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 173 { 174 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 175 int reg, speed, gig; 176 177 switch (cmd) { 178 case MII_POLLSTAT: 179 /* 180 * If we're not polling our PHY instance, just return. 181 */ 182 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 183 return (0); 184 break; 185 186 case MII_MEDIACHG: 187 /* 188 * If the media indicates a different PHY instance, 189 * isolate ourselves. 190 */ 191 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 192 reg = PHY_READ(sc, MII_BMCR); 193 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 194 return (0); 195 } 196 197 /* 198 * If the interface is not up, don't do anything. 199 */ 200 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 201 break; 202 203 ciphy_fixup(sc); /* XXX hardware bug work-around */ 204 205 switch (IFM_SUBTYPE(ife->ifm_media)) { 206 case IFM_AUTO: 207 #ifdef foo 208 /* 209 * If we're already in auto mode, just return. 210 */ 211 if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN) 212 return (0); 213 #endif 214 ciphy_mii_phy_auto(sc); 215 break; 216 case IFM_1000_T: 217 speed = CIPHY_S1000; 218 goto setit; 219 case IFM_100_TX: 220 speed = CIPHY_S100; 221 goto setit; 222 case IFM_10_T: 223 speed = CIPHY_S10; 224 setit: 225 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 226 speed |= CIPHY_BMCR_FDX; 227 gig = CIPHY_1000CTL_AFD; 228 } else { 229 gig = CIPHY_1000CTL_AHD; 230 } 231 232 PHY_WRITE(sc, CIPHY_MII_1000CTL, 0); 233 PHY_WRITE(sc, CIPHY_MII_BMCR, speed); 234 PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE); 235 236 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) 237 break; 238 239 PHY_WRITE(sc, CIPHY_MII_1000CTL, gig); 240 PHY_WRITE(sc, CIPHY_MII_BMCR, 241 speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG); 242 243 /* 244 * When setting the link manually, one side must 245 * be the master and the other the slave. However 246 * ifmedia doesn't give us a good way to specify 247 * this, so we fake it by using one of the LINK 248 * flags. If LINK0 is set, we program the PHY to 249 * be a master, otherwise it's a slave. 250 */ 251 if ((mii->mii_ifp->if_flags & IFF_LINK0)) { 252 PHY_WRITE(sc, CIPHY_MII_1000CTL, 253 gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC); 254 } else { 255 PHY_WRITE(sc, CIPHY_MII_1000CTL, 256 gig|CIPHY_1000CTL_MSE); 257 } 258 break; 259 case IFM_NONE: 260 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); 261 break; 262 case IFM_100_T4: 263 default: 264 return (EINVAL); 265 } 266 break; 267 268 case MII_TICK: 269 /* 270 * If we're not currently selected, just return. 271 */ 272 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 273 return (0); 274 275 /* 276 * Is the interface even up? 277 */ 278 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 279 return (0); 280 281 /* 282 * Only used for autonegotiation. 283 */ 284 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 285 break; 286 287 /* 288 * Check to see if we have link. If we do, we don't 289 * need to restart the autonegotiation process. Read 290 * the BMSR twice in case it's latched. 291 */ 292 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 293 if (reg & BMSR_LINK) 294 break; 295 296 /* 297 * Only retry autonegotiation every 5 seconds. 298 */ 299 if (++sc->mii_ticks <= 5/*10*/) 300 break; 301 302 sc->mii_ticks = 0; 303 ciphy_mii_phy_auto(sc); 304 return (0); 305 } 306 307 /* Update the media status. */ 308 ciphy_status(sc); 309 310 /* 311 * Callback if something changed. Note that we need to poke 312 * apply fixups for certain PHY revs. 313 */ 314 if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 315 ciphy_fixup(sc); 316 MIIBUS_STATCHG(sc->mii_dev); 317 sc->mii_active = mii->mii_media_active; 318 } 319 return (0); 320 } 321 322 static void 323 ciphy_status(struct mii_softc *sc) 324 { 325 struct mii_data *mii = sc->mii_pdata; 326 int bmsr, bmcr; 327 328 mii->mii_media_status = IFM_AVALID; 329 mii->mii_media_active = IFM_ETHER; 330 331 bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 332 333 if (bmsr & BMSR_LINK) 334 mii->mii_media_status |= IFM_ACTIVE; 335 336 bmcr = PHY_READ(sc, CIPHY_MII_BMCR); 337 338 if (bmcr & CIPHY_BMCR_LOOP) 339 mii->mii_media_active |= IFM_LOOP; 340 341 if (bmcr & CIPHY_BMCR_AUTOEN) { 342 if ((bmsr & CIPHY_BMSR_ACOMP) == 0) { 343 /* Erg, still trying, I guess... */ 344 mii->mii_media_active |= IFM_NONE; 345 return; 346 } 347 } 348 349 bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR); 350 switch (bmsr & CIPHY_AUXCSR_SPEED) { 351 case CIPHY_SPEED10: 352 mii->mii_media_active |= IFM_10_T; 353 break; 354 case CIPHY_SPEED100: 355 mii->mii_media_active |= IFM_100_TX; 356 break; 357 case CIPHY_SPEED1000: 358 mii->mii_media_active |= IFM_1000_T; 359 break; 360 default: 361 device_printf(sc->mii_dev, "unknown PHY speed %x\n", 362 bmsr & CIPHY_AUXCSR_SPEED); 363 break; 364 } 365 366 if (bmsr & CIPHY_AUXCSR_FDX) 367 mii->mii_media_active |= IFM_FDX; 368 } 369 370 static void 371 ciphy_reset(struct mii_softc *sc) 372 { 373 mii_phy_reset(sc); 374 DELAY(1000); 375 } 376 377 #define PHY_SETBIT(x, y, z) \ 378 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 379 #define PHY_CLRBIT(x, y, z) \ 380 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 381 382 static void 383 ciphy_fixup(struct mii_softc *sc) 384 { 385 uint16_t model; 386 uint16_t status, speed; 387 388 model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2)); 389 status = PHY_READ(sc, CIPHY_MII_AUXCSR); 390 speed = status & CIPHY_AUXCSR_SPEED; 391 392 switch (model) { 393 case MII_MODEL_CICADA_CS8201: 394 395 /* Turn off "aux mode" (whatever that means) */ 396 PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); 397 398 /* 399 * Work around speed polling bug in VT3119/VT3216 400 * when using MII in full duplex mode. 401 */ 402 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 403 (status & CIPHY_AUXCSR_FDX)) { 404 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 405 } else { 406 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 407 } 408 409 /* Enable link/activity LED blink. */ 410 PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); 411 412 break; 413 414 case MII_MODEL_CICADA_CS8201A: 415 case MII_MODEL_CICADA_CS8201B: 416 417 /* 418 * Work around speed polling bug in VT3119/VT3216 419 * when using MII in full duplex mode. 420 */ 421 if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && 422 (status & CIPHY_AUXCSR_FDX)) { 423 PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 424 } else { 425 PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); 426 } 427 428 break; 429 default: 430 device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n", 431 model); 432 break; 433 } 434 } 435 436 static void 437 ciphy_mii_phy_auto(struct mii_softc *sc) 438 { 439 PHY_WRITE(sc, CIPHY_MII_ANAR, mii_bmsr_media_to_anar(sc)); 440 PHY_WRITE(sc, CIPHY_MII_1000CTL, CIPHY_1000CTL_AFD); 441 PHY_WRITE(sc, CIPHY_MII_BMCR, CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG); 442 } 443